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Lab 11 (To Construct and Test Encoder and Decoder.)

This document outlines experiments to construct and test an encoder and decoder. The objectives are to design and implement a 3-8 line decoder and an 8-3 line encoder using integrated circuits and logic gates. The decoder will take 3 input lines and decode them to 8 output lines, while the encoder will take 8 input lines and encode them to 3 output lines. Equipment used includes decoder, encoder, and logic gate ICs. Tasks involve verifying the function of the decoder and encoder by comparing their outputs to truth tables.

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Daniyal Nisar
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© © All Rights Reserved
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Download as PDF, TXT or read online on Scribd
271 views

Lab 11 (To Construct and Test Encoder and Decoder.)

This document outlines experiments to construct and test an encoder and decoder. The objectives are to design and implement a 3-8 line decoder and an 8-3 line encoder using integrated circuits and logic gates. The decoder will take 3 input lines and decode them to 8 output lines, while the encoder will take 8 input lines and encode them to 3 output lines. Equipment used includes decoder, encoder, and logic gate ICs. Tasks involve verifying the function of the decoder and encoder by comparing their outputs to truth tables.

Uploaded by

Daniyal Nisar
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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TITLE : To Construct and Test Encoder and


Decoder

DATE OF
: 21th April, 2021
EXPERIMENT

Lab Number : 11

NAME : ___________________

ROLL NO : ___________________

Mechanical DLD Lab Page 1


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Objective:
 Design and Implementation of 3-8-line Decoder.
 Design and Implementation of 8-3-line Encoder.

Equipment:
 Decoder IC (74138).
 Encoder IC (74148).
 Logic gates.
 Connecting Wire.

Theory:
3X8 Line Decoder:
A decoder is a device which does the reverse of an encoder, undoing the encoding
so that the original information can be retrieved. The same method used to encode is usually
just reversed in order to decode.
A decoder provides the 2n minterms of n input variables. The procedure for implementing
a combinational circuit by means of a decoder and OR gates requires that the Boolean
function for the circuit be expressed as a sum of minterms. A decoder is then chosen that
generate all the minterms of the input variables. In this way, any combinational circuit
with n inputs and m outputs can be implemented with an n-to-2n line decoder and m OR
gates.

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Here E is the Enable Switch you can use to turn on and off the entire decoder
function. If you set enable to 0 it passes nothing to outputs, but if you set E=1 then you can
get the desired output which you want to turn on and off.

4X16 Line Decoder:


A decoder circuit of the higher combination is obtained by adding two or more lower
combinational circuits. 4 to 16 decoder circuit is obtained from two 3 to 8 decoder circuits
or three 2 to 4 decoder circuits.
When two 3 to 8 Decoder circuits are combined the enable pin acts as the input for both
the decoders. When enable pin is high at one 3 to 8 decoder circuits then it is low at another
3 to 8 decoder circuit.

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Encoder:
An encoder has 2n input lines and n output lines. The output lines generate a binary
code corresponding to the input value. For example, a single bit 4 to 2 encoder takes in 4
bits and outputs 2 bits. It is assumed that there are only 4 types of input signals these are :
0001, 0010, 0100, 1000.

Its opposite in function of decoder, here you can encode the larger output in some smaller
code.

We don’t have IC for encoder operation in lab so you have to design this by yourself.

Priority Encoder:
Why We Need:
One of the main disadvantages of standard digital encoders is that they can generate
the wrong output code when there is more than one input present at logic level “1”. For
example, if we make inputs D1 and D2 HIGH at logic “1” both at the same time, the
resulting output is neither at “01” or at “10” but will be at “11” which is an output binary
number that is different to the actual input present. Also, an output code of all logic “0”s
can be generated when all of its inputs are at “0” OR when input D0 is equal to one.

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One simple way to overcome this problem is to “Priorities” the level of each input pin. So
if there is more than one input at logic level “1” at the same time, the actual output code
would only correspond to the input with the highest designated priority. Then this type of
digital encoder is known commonly as a Priority Encoder or P-encoder for short.

How we Overcome this issue:


The Priority Encoder solves the problems mentioned above by allocating a priority
level to each input. The priority encoders output corresponds to the currently active input
which has the highest priority. So when an input with a higher priority is present, all other
inputs with a lower priority will be ignored.

The priority encoder comes in many different forms with an example of an 8-input
priority encoder along with its truth table shown below.

Lab Tasks
Task 1:
1. See the function table of 3*8 Line Decoder.
2. Verify Results with function table

Task 2:
1. Using function table from data sheet of 8x3 priority Encoder IC.
2. Verify Results with function table.

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