Sumit Gangwar

Roll No. 2K20/VLS/21

Experiment: 1a
Aim:- To characterize the n- channel MOSFET by measuring the device parameters:

i).Output characteristics and Transfer characteristics

ii).Threshold Voltage (Vto, Vth)

iii).Channel length modulation coefficient((λ)

iv).Transconductance parameter(Kn)

Theory:- Metal Oxide Semiconductor Field Effect transistor (MOSFET) is a four terminal
device. It is also known as insulated Gate Field- Effect Transistor (IGFET). n-MOS devices are
formed in a p-type substrate of moderate doping level. The source and drain regions are formed
by diffusing n-type impurities. In this device the channel current is controlled by a voltage
applied at a gate electrode that is isolated from the channel by an insulator.The MOS transistor is
the most widely used switching device in LSI and VLSI circuits because of its some
technological advantage over BJT.

Fig1.1: Physical structure of n-channel enhancement type MOSFET

MOSFET can be operated in three mode:

i). Cut-Off mode(Vgs<Vt), ii). Linear Mode(Triode region)(Vds<Vgs-Vt), iii). Saturation
Region(Vds>Vgs-Vt)
Threshold Voltage (Vt) is the minimum gate voltage required to induce the channel. Thus the
voltage required to create strong inversion must be large enough to first achieve the flat band
condition (ɸms and Qi/Ci terms), then accommodate the charge in the depletion region (Qd/Ci),
and finally to induce the inverted region (2ɸf).

Vt = ɸms –Qi/Ci-Qd/Ci+ 2ɸf

Channel Length Modulation occurs because of the shortening the length of the channel with
increase in drain bias voltage. The result of channel length modulation is an increase in current
with drain bias and reduction of output resistance.
Sumit Gangwar
Roll No. 2K20/VLS/21

Observation:-

Figure 1.2: Circuit schematic of n MOS with body connected to ground

Figure1.3:Output Characteristics of n MOS (Plot Id v/s Vds)

Sumit Gangwar
Roll No. 2K20/VLS/21

Figure1.4:Transfer Characteristics of n MOS (Plot Id v/s Vgs)

Figure1.5:Graph between Sqrt(Id) and Vgs of n MOS when body connected to ground
Sumit Gangwar
Roll No. 2K20/VLS/21

Figure 2.6: Circuit schematic of n MOS with body connected to negative potential

Figure1.7:Graph between Sqrt(Id) and Vgs of n MOS when body connected to negative potential
Sumit Gangwar
Roll No. 2K20/VLS/21
Sumit Gangwar
Roll No. 2K20/VLS/21
Sumit Gangwar
Roll No. 2K20/VLS/21

Result:- Output and Transfer characteristics have been plotted successfully and all the
parameters are observed.

Value of threshold voltage Vt when body is grounded=0.7.

Value of Threshold voltage when body is connected to negative potential= 0.9

Process transconductance Kn’=1.624 mA/V^2

Device Transconductance Parameter Kn=3.248 mA/V^2

Channel length modulation Coefficient=0.106 V^-1

Sumit Gangwar
2K20/VLS/21

Experiment No. 1(b)

Objective:- To characterize the p-channel MOSFET by measuring the device parameters:

i).Output characteristics and transfer characteristics

ii).Threshold Voltage (Vto, Vth)

iii).Channel length modulation coefficient((λ)

iv).Transconductance parameter(Kn)

Theory:- Metal Oxide Semiconductor Field Effect transistor (MOSFET) is a four terminal
device. It is also known as insulated Gate Field- Effect Transistor (IGFET). p-MOS devices are
formed in a n-type substrate of moderate doping level. The source and drain regions are formed
by diffusing p-type impurities. In this device the channel current is controlled by a voltage
applied at a gate electrode that is isolated from the channel by an insulator.The MOS transistor is
the most widely used switching device in LSI and VLSI circuits because of its some
technological advantage over BJT.

Figure1.1: PMOS Structural diagram

When we applied negative potential at Gate terminal, holes are attracted to the surface. At a
particular voltage level, which we will define as the threshold voltage, the hole density at the
surface exceeds the electron density. At this voltage, the surface has inverted from the n-type
polarity of the substrate to a p-type inversion layer. This inversion region is an extremely
shallow layer, existing as a charge sheet directly below the gate. In the MOS capacitor, the high
density of holes in the inversion layer is supplied by the electron–hole generation process within
the depletion layer. The negative charge on the gate is balanced by the combination of positive
charge in the inversion layer plus positive ionic donor charge in the depletion layer. The voltage
at which the surface inversion layer just forms plays an extremely important role in field-effect
transistors and is called the threshold voltage V tp . The region of output characteristics where
V GS tp and no current flows is called the cutt-off region. When the channel forms in the pMOS
transistor, a negative drain voltage with respect to the source creates a horizontal electric field
moving the holes toward the drain forming a negative drain current coming into the transistor.
Sumit Gangwar
2K20/VLS/21

If the channel horizontal electric field is of the same order or smaller than the vertical thin oxide
field, then the inversion channel remains almost uniform along the device length. This
continuous carrier profile from drain to source puts the transistor in a bias state that is
equivalently called either the non-saturated, linear, or ohmic bias state. The drain and source are
effectively short-circuited. This happens when V GS < V DS +V tp . Drain current is linearly related
to drain-source voltage over small intervals in the linear bias state.

Figure 1.2: Structural diagram of PMOS when pinch off condition occurs

If the source drain voltage rises while the gate voltage remains the same, then VGD can go
below the threshold voltage in the drain region. There can be no carrier inversion at the drain-
gate oxide region, so the inverted portion of the channel retracts from the drain, and no longer
“touches” this terminal. The pinched-off portion of the channel forms a depletion region with a
high electric field. The n-drain and p-bulk form a pn junction. When this happens the inversion
channel is said to be “pinched-off” and the device is in the saturation region.
Channel Length Modulation occurs because of the shortening the length of the channel with
increase in source drain bias voltage. The result of channel length modulation is an increase in
current with source drain bias and reduction of output resistance.

Observations:-

Figure1.3: Circuit Schematic of PMOS

Sumit Gangwar
2K20/VLS/21

Figure1.4:Graph between sqrt Id V/S Vgs

Figure1.5:Graph between Id V/S Vgs for different values of Vds

Sumit Gangwar
2K20/VLS/21

Figure1.6:Graph between Id V/S Vds for different values of Vgs

Figure1.7:Cicuit schematic of PMOS when body is connected at positive potential

Figure1.8:Graph between sqrt Id V/S Vgs when body is connected to positive potenetial
Sumit Gangwar
2K20/VLS/21

Calculations:-
Sumit Gangwar
2K20/VLS/21
Sumit Gangwar
2K20/VLS/21

Result:- Output and Transfer characteristics have been plotted successfully and all the
parameters are observed.
Value of threshold voltage Vt when body is grounded= -0.7.
Value of Threshold voltage when body is connected to negative potential= -0.8
Process transconductance Kp’=51.9841 mA/V2
Device Transconductance Parameter Kp=103.9682 mA/V2
Channel length modulation Coefficient=0.139 V-1
Sumit Gangwar
2K20/VLS/21

Experiment No. 2

Objective:- To plot the voltage transfer curve and findng out the noise margin. Find the effect of
resistance on noise margin.

ii). To plot the transient waveforms and calculate the delay of the inverter. What is the effect of
load capacitor on delay value

Theory:- A NOT gate is a one-input, one-output logic circuit whose output is always the
complement of the input. That is, a LOW input produces a HIGH output, and vice versa. When
interpreted for a positive logic system, a logic ‘0’ at the input produces a logic ‘1’ at the output,
and vice versa. It is also known as a complementing circuit or an inverting circuit.

Figure 2.1:Symbol of NOT gate

Table 2.1: Truth table of NOT gate

Voltage transfer characteristics of ideal inverter circuit is shown. Here Vth is the threshold
voltage of the inverter. For any input voltage between 0 and Vth = VDD/2 , the output voltage is
equal to VDD (logic 1 ). The output switches from VDD to 0 when the input is equal to Vth. For
any input voltage between Vth and VDD, the output voltage assumes a value of 0 (logic 0).
Thus, an input voltage 0 < Vi. < Vth is interpreted by this ideal inverter as a logic 0 while an
input voltage Vth <Vin < VDD is interpreted as a logic 1.

Figure 2.2: Voltage transfer characteristics of ideal inverter circuit

Sumit Gangwar
2K20/VLS/21

The typical Voltage transfer characteristics of MOS transistor is as shown in fig

Figure 2.3:Voltage transfer characteristics of a genral MOS inverter circuit

VOH: Maximum output voltage when the output level is logic 1

VOL: Minimum output voltage when the output level is logic 0
VOL: Maximum input voltage which can be interpreted as logic 0
VIL: Minimum input voltage which can be interpreted as logic 1

The basic structure of the resistive-load inverter circuit is shown in Fig. Enhancement-type
nMOS transistor acts as the driver device. The load consists of a simple linear resistor, RL. The
power supply voltage of this circuit is VDD.

Figure 2.4:Resistive Load inverter circuit diagram

Table 2.2: Transistor operation mode table for given input values
Sumit Gangwar
2K20/VLS/21

The definition of noise tolerances for digital circuits, called noise margins and denoted by NM.
The noise immunity of the circuit increases with NM. Two noise margins will be defined: the
noise margin for low signal levels (NML) and the noise margin for high signal levels (NMH).

Figure 2.5: Schematic diagram Noise margin definition

Observations:-
Sumit Gangwar
2K20/VLS/21

Figure 2.6: Cicuit Schematic of resistive load inverter

Figure 2.7: VTC response of resistive load inverter

Figure 2.8:Graph between differential of Vout V/s Vin

Sumit Gangwar
2K20/VLS/21

Figure 2.9: Cicuit Schematic of resistive load inverter for different values of resistance

Figure 2.10:Graph of VTC at different values of resistances

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2K20/VLS/21

Figure 2.11: Cicuit Schematic of resistive load inverter with capacitor connected
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2K20/VLS/21

Figure 2.12:Graph between differential of Vout V/s Vin at different values of capacitances

Figure 2.13: Cicuit Schematic of resistive load inverter with pulse input
Sumit Gangwar
2K20/VLS/21

Table 2.3: Delay response observed from the different values of capacitances

Calculations:-
Sumit Gangwar
2K20/VLS/21
Sumit Gangwar
2K20/VLS/21
Sumit Gangwar
2K20/VLS/21

Results:- We have been successfully observe the voltage transfer characteristics at different
different values of resistance and calculated the noise margin. From the noise margin calculation
we observe that as load resistance value increases nois margin also increases.

We aslo calculated the delay at different values of the capacitor and concluded that as capacitor
value increases delay also increases.
Sumit Gangwar
2K20/VLS/21

Experiment No. 3
Aim:- i). Plot the VTC for pseudo NMOS inverter. Calculate the Noise margin value and what
is the affect of Kn on NM.

ii). Plot the transient characteristic for pseudo NMOS inverter and calculate the delay value.
Find the effect of capacitor on delay value.

Theory:- The inverter that uses a p-device pull-up or load that has its gate permanently ground.
An n-device pull-down or driver is driven with the input signal. This roughly equivalent to use of
a depletion load is Nmos technology and is thus called ‘Pseudo-NMOS’. The circuit is used in a
variety of CMOS logic circuits. In this, PMOS for most of the time will be linear region. So
resistance is low and hence RC time constant is low. When the driver is turned on a constant DC
current flows in the circuit. Pseudo nMOS inverter provides sharp VTC transition and better
noise margin, it requires single power supply and it require small layout area.

Figure 3.1: Circuit diagram of Pseudo nMOS inverter

In pseudo nMOS inverter the gain ratio of p-transistor load to n-transistor driver has to be
selected to yield sufficient gain to generate consistent logic levels. The design of this style of
gate involve ratioed transistor sizes to ensure correct switching. The main problem with pseudo
nMOS type design is static power dissipation that occurs whenever the pull-down is turned on.
As the load is always turned on, when the n pull-down is on, current flows in the gate structure.
If we design logic gates with the help of pseudo nMOS inverter it requires n+1 transistors. In this
type gate the minimum load can be one unit gate load, as a result of using only one transistor for
each term of the input function. However if minimum sized driver transistor for each term are
used, the pull-up gain has to be decreased to provide adequate noise margins. This inturn slows
the rise time of the gate. One possible advantage of the pMOS load is that it does not suffer from
body effect as the nMOS depletion load does. A gate so implemented may have a density
advantage over a fully complementary gate.
Sumit Gangwar
2K20/VLS/21

Observations:-

Figure3.2: Circuit schematic of Pseudo nMOS inverter

Figure 3.3: Voltage transfer characteristic (VTC) of Pseudo nMOS inverter

Sumit Gangwar
2K20/VLS/21

Figure 3.4: Plot of Derivative of output voltage

Figure3.5: Circuit schematic of Pseudo nMOS inverter for different value of aspect ratio of load transistor
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2K20/VLS/21

Figure 3.6: Plot of Voltage transfer characteristics for different value of aspect ratio of load transistor

Figure 3.7: Plot of Voltage transfer characteristics for different value of aspect ratio of load transistor.
Sumit Gangwar
2K20/VLS/21

Figure 3.8: Plot of derivative of output voltage for different value of aspect ratio of load transistor

Figure 3.9: Circuit schematic of Pseudo nMOS inverter for transient response
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2K20/VLS/21

Figure 3.10: Transient response of Pseudo nMOS inverter for different value of capacitance

Figure 3.11: Calculated delay (Rise to fall) for different value of capacitance
Sumit Gangwar
2K20/VLS/21

Figure 3.11: Calculated delay (Fall to rise) for different value of capacitance
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2K20/VLS/21

Calculations:-
Sumit Gangwar
2K20/VLS/21
Sumit Gangwar
2K20/VLS/21

Result:- i). From the above calculations , it can be observed that by increasing the W/L ratio ,
the VTC curve shifts towards right side and correspondingly the noise margin decreases
ii). It can also be observed that as the value of capacitance increases the delay of the circuit also
increases.
Sumit Gangwar
2K20/VLS/21

Experiment No. 4

Aim:- i). Plot the VTC for CMOS inverter. Calculate the NM value and what is the affect of
Kn on NM.

ii). Plot the transient characteristic CMOS inverter and calculate the delay value. Find the
effect of capacitor on delay value.

Theory:- A complementary CMOS inverter is realized by the series connection of a p- and n-

device.The circuit topology is complementary push-pull in the sense that for high input, the
nMOS transistor drives (pulls down) the output node while the pMOS transistor acts as the load,
and for low input the pMOS transistor drives (pulls up) the output node while the nMOS
transistor acts as the load. When Vin is high and equal to VDD, the NMOS transistor is on, while
the PMOS is off. It implies that a direct path exists between Vout and the ground node, resulting
in a steady-state value of 0 V. On the other hand, when the input voltage is low (0 V), NMOS
and PMOS transistors are off and on, respectively. It shows that a path exists between VDD and
Vout, yielding a high output voltage. The gate clearly functions as an inverter.

Figure 4.1: a) Circuit diagram of CMOS inverter b)Simplified view of CMOS inverter
Properties of static CMOS inverter:
• In CMOS transistor high and low output levels equal to VDD and GND, respectively; in other
words, the voltage swing is equal to the supply voltage. This results in high noise margins.
• In steady state, there always exists a path with finite resistance between the output and either
VDD or GND. CMOS inverter therefore, has a low output impedance, which makes it less
sensitive to noise and disturbances.
• The input resistance of the CMOS inverter is extremely high, as the gate of an MOS transistor
is a virtually perfect insulator and draws no dc input current. Since the input node of the inverter
only connects to transistor gates, the steady-state input current is nearly zero. A single inverter
can theoretically drive an infinite number of gates (or have an infinite fan-out) and still be
functionally operational; however, increasing the fan-out also increases the propagation delay.
So, although fan-out does not have any effect on the steady-state behavior, it degrades the
transient response.
Sumit Gangwar
2K20/VLS/21

• No direct path exists between the supply and ground rails under steady-state operating
conditions. The absence of current flow means that the gate does not consume any static power
A fast gate is built either by keeping the output capacitance small or by decreasing the on-
resistance of the transistor.
If we want to change ᵝn / ᵝp, we need to change the chsnnel dimensions, i.e., channel length L and
channel width W. As the ratio ᵝn / ᵝp is decreased the transition region shifts from left to right;
however, the output voltage transition remain sharp and hence the switching performance is not
affected. This behavior should be contrasted with the nMOS inverter, where the transition gain
depends critically on the ᵝ ratio of the load(pull up) and driver(pull down) transistors.
For the CMOS inverter a ratio of

ᵝn / ᵝp=1

May be desirable since it allows a capacitance load to charge and discharge in equal times by
providing equal current source and sink capabilities.

Figure 4.2: Voltage transfer characteristics of CMOS inverter

Table 4.1: Operating moade of transistors for different input

Sumit Gangwar
2K20/VLS/21

Figure 4.3: Circuit schematic of CMOS inverter

Figure 4.4: Voltage transfer characteristics of CMOS inverter

Sumit Gangwar
2K20/VLS/21

Figure 4.5: Plot of Derivative of output voltage

Figure 4.6: Cicuit schematic of CMOS inverter for different value of aspect ratio at load transistor
Sumit Gangwar
2K20/VLS/21

Figure 4.7: Voltage transfer characteristics of CMOS inverter for different value of aspect ratio of load transistor

Figure 4.8: Voltage transfer characteristics and input voltage plot for different value of aspect ratio of load transistor
Sumit Gangwar
2K20/VLS/21

Figure 4.9: Plot of Derivative of output voltage for different value of aspect ratio of load transistor

Figure 4.10:Circuit schematic of CMOS inverter for transient response

Sumit Gangwar
2K20/VLS/21

Figure 4.11: Transient response of CMOS inverter at different value of capacitor

Figure 4.12: Delay(Rise to fall) at different values of capacitor

Sumit Gangwar
2K20/VLS/21

Figure 4.12: Delay(fall to rise) at different values of capacitor

Sumit Gangwar
2K20/VLS/21

Calculations:-
Sumit Gangwar
2K20/VLS/21
Sumit Gangwar
2K20/VLS/21

Result:- i). From the above calculations , it can be observed that CMOS logic has a high value of
noise margin .
ii). It can also be observed that as the value of capacitance increases the delay of the circuit also
increases.
Sumit Gangwar (2K20/VLS/21)

Experiment No. 5
Aim:- Design the NAND, NOR and XOR gate. Calculate the delay value for each input
transition. Find the threshold (Vth) value for NAND and NOR gate.

1).NAND GATE:-
The NAND (Not – AND) gate has an output that is normally at logic level “1” and only goes
“LOW” to logic level “0” when all of its inputs are at logic level “1”. The Logic NAND Gate is
the reverse or “Complementary” form of the AND gate. The logic or Boolean expression given
for a logic NAND gate is that for Logical Addition, which is the opposite to the AND gate, and it
performs on the complements of the inputs. The Boolean expression for a logic NAND gate is
denoted by a single dot or full stop symbol, ( . ) with a line or Over line, ( ‾‾ ) over the expression
to signify the NOT or logical negation of the NAND gate.

Figure 5.1: Circuit diagram of NAND gate using MOSFET

The circuit shows the realization of CMOS NAND gate which consists of two PMOS and two
NMOS gates. Here in this circuit when input A and B are high i.e. at 5V then the two PMOS
will be open circuited and two NMOS will be Short circuited. The output Vout will be shorted to
ground and produces zero output. If any of the input is low (0 V) corresponding PMOS will be
shorted and NMOS will opened the Vout is shorted to Vdd which provides high output.
2). NOR GATE
The NOR (Not – OR) gate has an output that is normally at logic level “1” and only goes
“LOW” to logic level “0” when any of its inputs are at logic level “1”. The Logic NOR Gate is
the reverse or “Complementary” form of the OR gate.The logic or Boolean expression given for
a logic NOR gate is that for logical multiplication which it performs on the complements of the
Sumit Gangwar (2K20/VLS/21)

inputs. The Boolean expression for a logic NOR gate is denoted by a plus sign, ( + ) with a line
or Overline, ( ‾‾ ) over the expression to signify the NOT or logical negation of the NOR gate.
Table 5.1: Truth table of NOR Gate

Figure 5.2: Logical symbol of NOR gate

Figure 5.3: Circuit diagram of NOR gate using MOSFET

3).EX – OR GATE
The Exclusive-OR Gate The output of an Exclusive-OR gate only goes “HIGH” when its two
input terminals are at “DIFFERENT” logic levels with respect to each other. An odd number of
logic “1’s” on its inputs gives a logic “1” at the output. These two inputs can be at logic level “1”
or at logic level “0” giving us the Boolean expression of: Q = (A^B) = A’.B + A.B’.
Table 5.2: Truth table of XOR gate

Figure 5.4: Logical symbol of XOR gate

Figure 5.5: Circuit diagram of XOR gate using MOSFET

Sumit Gangwar (2K20/VLS/21)

Observations:-

i). NAND Gate:-

Figure 5.6: Circuit schematic of NAND gate

Figure 5.7: Voltage transfer characteristics of NAND gate

Sumit Gangwar (2K20/VLS/21)

Figure 5.8: Circuit schematic of NAND gate for transient response

Figure 5.9: Transient response of NAND gate

Sumit Gangwar (2K20/VLS/21)

Figure 5.10: Delay in 00 to 11 transition for NAND gate

Figure 5.11: Delay in 01 to 11 transition for NAND gate

Sumit Gangwar (2K20/VLS/21)

Figure 5.12: Delay in 11 to 10 transition for NAND gate

Figure 5.13: Delay in 10 to 11 transition for NAND gate

Sumit Gangwar (2K20/VLS/21)

Figure 5.14: Delay in 11 to 01 transition for NAND gate

Figure 5.15: Delay in 11 to 00 transition for NAND gate

Sumit Gangwar (2K20/VLS/21)

ii). NOR Gate:-

Figure 5.16: Circuit schematic of NOR gate

Figure 5.17: Voltage transfer characteristics plot of NOR gate

Sumit Gangwar (2K20/VLS/21)

Figure 5.18: Circuit schematc of NOR gate for transient response

Figure 5.19: Transient response of NOR gate

Sumit Gangwar (2K20/VLS/21)

Figure 5.20: Delay in 00 to 11 transition for NOR gate

Figure 5.21: Delay in 01 to 00 transition for NOR gate

Sumit Gangwar (2K20/VLS/21)

Figure 5.22: Delay in 00 to 10 transition for NOR gate

Figure 5.23: Delay in 10 to 00 transition for NOR gate

Sumit Gangwar (2K20/VLS/21)

Figure 5.24: Delay in 00 to 01 transition for NOR gate

Figure 5.25: Delay in 11 to 00 transition for NOR gate

Sumit Gangwar (2K20/VLS/21)

ii). XOR Gate:-

Figure 5.26: Circuit schematic of XOR gate for transient response

Figure 5.27: Delay in XOR gate for 11 to 10 transition

Sumit Gangwar (2K20/VLS/21)

Figure 5.28: Delay in XOR gate for 11 to 10 transition.

Figure 5.29: Delay in XOR gate for 10 to 00 transition

Sumit Gangwar (2K20/VLS/21)

Figure 5.30: Delay in XOR gate for 00 to 01 transition

Figure 5.31: Delay in XOR gate for 01 to 00 transition

Sumit Gangwar (2K20/VLS/21)

Figure 5.32: Delay in XOR gate for 00 to 10 transition

Figure 5.33: Delay in XOR gate for 10 to 11 transition

Sumit Gangwar (2K20/VLS/21)

Delay Calculations:-

T= (THL +TLH)/2

NAND Gate
Transition Delay Type Delay in transition Total Delay
00 to 11 THL 232.59 586.74
11 to 00 TLH 940.90
11 to 10 TLH 460.47 414.42
10 to 11 THL 368.38
11 to 01 TLH 478.89 308.86
01 to 11 THL 277.66

NOR Gate
Transition Delay Type Delay in transition Total Delay
00 to 11 THL 274.59 460.93
11 to 00 TLH 647.28
00 to 01 THL 295.40 416.38
01 to 00 TLH 537.37
00 to 10 THL 433.00 565.55
10 to 00 TLH 698.10

XOR Gate
Transition Delay Type Delay in transition Total Delay
10 to 00 THL 218.82 309.25
00 to 10 TLH 399.68
01 to 00 THL 239.447 288.98
00 to 01 TLH 338.52
10 to 11 THL 179.58 272.84
11 to 10 TLH 366.10

Result:- Implementation of NAND, NOR and XOR Gate has been done successfully. The
transient waveforms and static characteristics is also determined for each gate using the CMOS
technology.
Sumit Gangwar
2K20/VLS/21

Experiment No.6
Aim:- To implement 4*1 MUX using CMOS 2*1 MUX and calculate the delay.

Theory:- A multiplexer or MUX, also called a data selector, is a combinational circuit with more
than one input line, one output line and one or more than one selection line. A multiplexer
selects binary information present on any one of the input lines, depending upon the logic status
of the selection inputs, and routes it to the output line. If there are n selection lines, then the
number of maximum possible input lines is 2 n and the multiplexer is referred to as a 2n-to-1
multiplexer or 2n ×1 multiplexer.
For 2*1 MUX :
For S = 0, the Boolean expression for the output becomes Y = I0.
For S = 1, the Boolean expression for the output becomes Y = I1.

For 4*1 MUX:

For S1S0= 00, the Boolean expression for the output becomes Y = I0.
For S1S0= 01, the Boolean expression for the output becomes Y = I1.
For S1S0= 10, the Boolean expression for the output becomes Y = I2.
For S1S0= 11, the Boolean expression for the output becomes Y = I3.

Figure 6.1: Logic diagram and block diagram of 2*1 MUX

Figure 6.2: Logic diagram and Block diagram of 4*1 MUX and corresponding response table
Sumit Gangwar
2K20/VLS/21
Observations:-

Figure 6.3: Circuit schematic of 2*1 MUX using CMOS circuit design technique

Figure 6.4: 2*1 MUX Circuit used in making hierarchy symbol

Sumit Gangwar
2K20/VLS/21

Figure 6.5:Plot of input and corresponding output response of 2*1 MUX

Figure 6.6:Plot of Delay in 00 to 11 transition for 2*1 MUX

Sumit Gangwar
2K20/VLS/21

Figure 6.7:Plot of Delay in 01 to 00 transition for 2*1 MUX

Figure 6.8:Plot of Delay in 11 to 10 transition for 2*1 MUX

Sumit Gangwar
2K20/VLS/21

Figure 6.9:Plot of Delay in 10 to 11 transition for 2*1 MUX

Figure 6.10:Plot of Delay in 11 to 00 transition for 2*1 MUX

Sumit Gangwar
2K20/VLS/21

Figure 6.11:Plot of Delay in 00 to 01 transition for 2*1 MUX

Figure 6.12: Block diagram of 4*1 MUX using 2*1 MUX

Sumit Gangwar
2K20/VLS/21

Figure 6.13:Plot of input and corresponding output response of 4*1 MUX

Delay Calculation:-

2*1 MUX
Transition Delay Type Delay in transition Total Delay
00 to 11 TLH 645.90 455.47
11 to 00 THL 265.04
01 to 00 THL 370.22 506.52
00 to 01 TLH 642.82
10 to 11 TLH 629.77 522.55
11 to 10 THL 415.34

Result:- We have successfully implemented the 2*1 MUX using CMOS technique and
calculated the delay and with the help of 2*1 MUX we implemented 4*1 MUX and observe the
result.
Sumit Gangwar
2K20/VLS/21

EXPERIMENT NO.7

Aim:-
i). To implement AND, OR and 2*1 MUX gate using Transmission gate and calculate delay
of each transition.
ii). Implement 4*1 mux using 2*1 mux with transmission gate logic.
Theory:- The transmission gate is a bilateral switch consisting of NMOS and PMOS transistors
controlled by externally applied logic levels. The CMOS transmission gate consists of one
NMOS and one PMOS transistor which connected in parallel. The gate voltages applied to these
two transistors are also set to be complementary signals The open and closed operations of the
switch positions are usually controlled by some digital logic network The switching and routing
of digital and analogue signals (both voltage and current) can easily be done using mechanical
relays and their contacts, but these can be slow and costly. The obvious choice is to use much
faster acting solid state electronic switches which use metal oxide semiconductor (MOS)
analogue gates to route the signal currents from their input to their output.

As shown if the control signal C is logic-high, i.e., equal to VDD, then both transistors are turned
on and provide a low-resistance current path between the nodes A and B. If, on the other hand,
the control signal C is low, then both transistors will be off, and the path between the nodes A
and B will be an open circuit and this condition is also called the high-impedance state
The substrate terminal of the NMOS transistor is connected to ground and the substrate terminal
of the PMOS transistor is connected to VDD. Thus, we must take into account the substrate-bias
effect for both transistors, depending on the bias conditions.

Figure 7.1: Circuit diagram and different symbol reperesentation of transmission gate

The implementation of CMOS transmission gates in logic circuit design usually results in
compact circuit structures which may even require a smaller number of transistors than their
standard CMOS counterparts. The control signal and its complement must be available
simultaneously for TG applications. The total equivalent resistance of the CMOS TG will then
be the parallel equivalent of these two resistances Reqn and Resqp
Sumit Gangwar
2K20/VLS/21

Figure 7.2: Different region of operation of transmission gate

Figure 7.3: Circuit diagram of AND logic using transmission gate

Figure 7.4: Gate level schematic 2*1 MUX using transmission gate

Figure 7.5: Circuit diagram of 4*1 MUX using transmission gate

Figure 7.6: Gate level schematic of OR logic using transmission gate

Sumit Gangwar
2K20/VLS/21

Observations:-

For NMOS W=360nm, L=180nm, and For PMOS W=720nm, L=180nm

Figure 7.7: Circuit diagram of AND logic using transmission gate logic

Figure 7.8: Transient response of AND gate

Sumit Gangwar
2K20/VLS/21

Figure 7.9: Delay in transition from 10 to 11

Figure 7.10: Delay in transition from 11 to 01

Sumit Gangwar
2K20/VLS/21

Figure 7.11: Delay in transition from 01 to 11

Figure 7.12: Delay in transition from 11 to 10

Sumit Gangwar
2K20/VLS/21

Figure 7.13: Delay in transition from 00 to 11

Figure 7.14: Delay in transition from 11 to 00

Sumit Gangwar
2K20/VLS/21

Figure 7.15: Circuit diagram of OR logic using transmission gate logic

Figure 7.16: Transient response of OR gate

Sumit Gangwar
2K20/VLS/21

Figure 7.17: Delay in transition from 11 to 00

Figure 7.18: Delay in transition from 00 to 11

Sumit Gangwar
2K20/VLS/21

Figure 7.19: Delay in transition from 00 to 01

Figure 7.20: Delay in transition from 10 to 00

Sumit Gangwar
2K20/VLS/21

Figure 7.21: Delay in transition from 01 to 00

Figure 7.22: Delay in transition from 00 to 10

Sumit Gangwar
2K20/VLS/21

Figure 7.23: Circuit diagram of 2*1 MUX using transmission gate logic

Figure 7.24: Transient response of 2*1 MUX

Sumit Gangwar
2K20/VLS/21

Figure 7.25: Delay in transition from 00 to 01

Figure 7.26: Delay in transition from 01 to 00

Sumit Gangwar
2K20/VLS/21

Figure 7.27: Delay in transition from 10 to 11

Figure 7.28: Delay in transition from 11 to 10

Sumit Gangwar
2K20/VLS/21

Figure 7.29: Block diagram of 4*1 MUX using transmission gate logic

Figure 7.30: Transient response of 4*1 MUX

Delay Calculation:-

AND LOGIC
Transition Delay Type Delay in Total Delay(pS)
transition(pS)
10 to 11 TLH 241.66 204.40
11 to 10 THL 167.15
11 to 01 THL 213.46 275.26
01 to 11 TLH 337.06
11 to 00 THL 232.07 255.55
00 to 11 TLH 279.04
Sumit Gangwar
2K20/VLS/21

OR LOGIC
Transition Delay Type Delay in Total Delay(pS)
transition(pS)
00 to 11 TLH 222.17 215.90
11 to 00 THL 209.64
00 to 01 TLH 230.85 230.19
01 to 00 THL 229.53
10 to 00 THL 212.73 204.21
00 to 10 TLH 195.70

2*1 MUX
Transition Delay Type Delay in Total Delay(pS)
transition(pS)
00 to 01 TLH 452.26 277.86
01 to 00 THL 103.47
10 to 11 TLH 411.53 265.01
11 to 10 THL 118.49

Result:- We have successfully implemented AND, OR and 2*1 MUX gate using
Transmission gate and calculated the delay of each transition. We have successfully
implemented 4*1 MUX using 2*1 MUX with transmission logic.
Sumit Gangwar
2K20/VLS/21

Experiment No. 8

Aim:- To implement the CMOS full-adder, verify its functionality and calculate the delay.

Theory:- A full adder circuit is an arithmetic circuit block that can be used to add three bits to
produce a SUM and a CARRY output. Such a building block becomes a necessity when it comes
to adding binary numbers with a large number of bits. The full adder circuit overcomes the
limitation of the half-adder, which can be used to add two bits only. truth table of a full adder
circuit showing all possible input combinations and corresponding outputs. In order to arrive at
the logic circuit for hardware implementation of a full adder, we will firstly write the Boolean
expressions for the two output variables, that is, the SUM and CARRY outputs, in terms of input
variables. These expressions are then simplified by using any of the simplification techniques.

Figure 8.1: Block diagram and truth table of the full adder
Boolean expression can be implemented with a two-input EX-OR gate provided that one of the
inputs is Cin and the other input is the output of another two-input EX-OR gate with A and B as
its inputs. Similarly, Boolean expression can be implemented by ORing two minterms. One of
them is the AND output of A and B. The other is also the output of an AND gate whose inputs
are Cin and the output of an EX-OR operation on A and B. The full adder of the type described
above forms the basic building block of binary adders. However, a single full adder circuit can
be used to add one-bit binary numbers only. A cascade arrangement of these adders can be used
to construct adders capable of adding binary numbers with a larger number of bits.

Figure 8.2: Gate level schematic of sum and carry

Sumit Gangwar
2K20/VLS/21

Observations:-
For NMOS w=360nm, L=180nm and for PMOS W=720nm, L= 180nm

Figure 8.3: Circuit schematic of full adder

Figure 8.4: Waveform response of Full adder

Sumit Gangwar
2K20/VLS/21

Figure8.5: Delay in 111 to 110 transition

Figure8.6: Delay in 100 to 011 transition

Sumit Gangwar
2K20/VLS/21

Figure8.7: Delay in 011 to 010 transition

Figure8.8: Delay in 001 to 111 transition

Sumit Gangwar
2K20/VLS/21

Figure8.9: Delay in 000 to 111 transition

Figure8.10: Delay in 101 to 100 transition

Sumit Gangwar
2K20/VLS/21

Figure8.11: Delay in 110 to 111 transition

Figure8.12: Delay in 100 to 101 transition

Sumit Gangwar
2K20/VLS/21

Figure8.13: Delay in 010 to 011 transition

Figure8.14: Delay in 000 to 001 transition

Sumit Gangwar
2K20/VLS/21

Figure8.15: Delay in 111 to 000 transition

Figure8.16: Delay in 011 to 100 transition

Sumit Gangwar
2K20/VLS/21

Table 8.1: Delay calculation

Transition Delay type Delay in transition Total Delay

111 to 110 TPHL 55.54 72.59
110 to 111 TPLH 89.65
101 to 100 TPLH 102.80 71.66
100 to 101 TPHL 40.52
100 to 011 TPHL 30.8 60.71
011 to 100 TPLH 90.62
001 to 000 TPHL 34.52 54.49
000 to 001 TPLH 74.46
000 to 111 TPLH 71.07 47.07
111 to 000 TPHL 23.07
011 to 010 TPLH 77.53 60.22
010 to 011 TPHL 42.92

Conclusion:- We have successfully design and verify the functionality of the full adder and also
calculated the delay.