Microprocessor

Term paper
ECE 212

Submitted to: Submitted by:

Ms. Preet Kanwal Deependra Dabas
RB1801B24
B.Tech CSE(150)

ACKNOWLEDGEMENT
History of all great works in to witness that no great work was ever done without
either active or passive support of a person ‘surrounding and one’s close quarters.
Thus is it not hard to conclude how active assistance from senior could positively
impact the execution of a project . I am highly thankful to our learned faculty Ms.
Preet Kanwal for his active guidance throughout the completion of project.

Last but not least, I would also want to extend my appreciation to

those who could not be mentioned here but have well played their role to inspire
me behind the certain.

DEEPENDRA DABAS

Brief Introduction
8255 is a widely used programmable parallel I/O device. This is also named as programmable
peripheral input output port. 8255 is designed to use with 8 bit, 16 bit and higher capability
microprocessor. This 8255 has 24 input/output lines, which can be individually programmed.
These I/O lines can be grouped as Group A and Group B. Group A contains an 8-bit port A along
with a 4-bit port C upper. Group B contains an 8-bit port B along with a 4-bit port, c lower. The
C upper and C lower ports can be combined be use as an 8-bit port. Thus for on 8255 we can
have either three 8 bit I/O ports or two 8 bit and two 4 bit ports. All these ports can function
independently either as input or as output ports. This can be achieved by programming the bits of
an internal register called as Control Word Register (CWR). The internal block diagram is shown
in the fig.

The read/write control logic controls the 8-bit data bus buffer. The read/write control
logic manages all the internal and external transfers of both the data and control words. RD, WR,
A1, A0 and RESET ate the input provided by the microprocessor to read/write control logic of
8255.

The bidirectional 8-bit data buffer is used to interface the 8255’s internal data bus with the
external system data bus. This buffer receives or transmits data up on the execution of input or
output instructions by the microprocessor. The control word or the status information is also
transferred through the buffer.

Signal Descriptions of 8255

 The Read/write control logic is having six signal lines. Which are RD, WR, RESET, CS,
A0 and A1

RD [READ] :- This control signal enables the read operation. When the signal is low, the
microprocessor reads data from a selected I/O port of 8255

WR [WRITE] :- This control signal enables the write operation. When the signal goes low the
MPU (microprocessor) writes into a selected I/O port or the control register.

RESET :- This is an active high signal, A logic high on this line clears the control word register
and set all ports in the input mode. (that is , set as input port by default after reset)

CS [CHIP SELECT] :- This is a Chip Select line. If the line goes low it enables the 8255 to
respond to RD and WR signals.

A1 – A0 :- These are address lines driven by the microprocessor. These address lines are used for
selecting any one of the three ports or a control word.

CS A1 A0 Selected

0 0 0 Port A

0 0 1 Port B

0 1 0 Port C

0 1 1 Control Register

1 X X 8255 is not selected.

PA7 – PA0 :- These are eight port A lines that act either as input or output lines depending up on
the control word loaded into the control word register.

PC7 – PC4 :- These are four Port C upper lines that can act as input or output lines. This port can
be used for the generation of handshake lines.

PC3 – PCo : - These are four port C lower lines that can act as input or output lines. This port
can also be used for the generation of handshake lines.

PB0 – PB7 :- These are 8 port B lines which can be input or output lines in the same way as port
A
D0 – D7 :- These are the data bus lines that carry data or control word to/from the
microprocessor.

This 8255 is a widely used, flexible and economical I/O device that can be used with almost all
microprocessors when multiple I/O ports are required. 8255 is a 40 pin IC.

MODES OF OPERATION OF 8255

All the functions of 8255 A is classified according to two modes: the Bit Set/Reset (BSR) mode
and the I/O mode. The BSR mode is used to set or reset the bits in port C. The I/O mode is
further divided into three modes: Mode 0, Mode 1 and Mode 2. In Mode 0, all ports function as
simple as I/O ports. Mode 1 is a handshake mode whereby port A and port B use bits from port C
as handshake signals. In the handshake mode, two types of I/O data transfer can be implemented:
status checks and interrupt. In Mode 2 port A can be set up for bidirectional data transfer using
handshaking signals from port C and port B can be set up either in Mode 0 or Mode 1.

1. I/O MODE

In this mode all 8255 ports will be function as programmable I/O ports. It can be again classified
into three as follows:

Mode 0 : Simple Input or Output

This is also called basic I/O mode. In this mode, ports A and B are used as two simple 8-bit I/O
ports and port C as two 4-bit ports. Each port (or half-port in case of C) can be programmed to
function as simply an input or an output port. The input/output features in Mode 0 as follows:

1. Output is latched.
2. Inputs are not latched.
3. Ports do not have handshake or interrupt capability.
4. Any port can be used as input or output port.
5. 4-bit can combined used as a third 8-bit port.

Mode 1: Input or Output with handshake

This is also called strobe I/O mode. In Mode 1: handshake signals are exchanged between the
MPU and peripherals prior to data transfer. The features of this mode include the following:
 1. Two ports (A and B) function as 8-bit I/O ports. They can be configured either as
input or output ports.
2. Each port uses three lines from port C as handshake signals. The remaining two
lines of port C can be used for simple I/O functions.
3. Input and output data are latched.
4. Interrupt logic is supported.

In the 8255, the specific lines from port C used for handshake signals vary according to the I/O
function of a port. Therefore input and output functions in Mode 1 are discussed separately.

Input Control Signals

In this mode the handshaking control the input and output action of the specified port. Port C
lines PC0-PC2, provide strobe or handshake lines for port B. This group which includes port B
and PC0-PC2 is called as group B for Strobed data input/output. Port C lines PC3-PC5 provide
strobe lines for port A.

This group including port A and PC3-PC5 from group A. Thus port C is utilized for generating
handshake signals. The salient features of mode 1 are listed as follows:

1. Two groups – group A and group B are available for strobed data transfer.

2. Each group contains one 8-bit data I/O port and one 4-bit control/data port.

3. The 8-bit data port can be either used as input and output port. The inputs and outputs both are
latched.

4. Out of 8-bit port C, PC0-PC2 are used to generate control signals for port B and PC3-PC5 are
used to generate control signals for port A. the lines PC6, PC7 may be used as independent data
lines.

The control signals for both the groups in input and output modes are
explained as follows:

Input control signal definitions (mode 1 )

• STB( Strobe input ) – If this lines falls to logic low level, the data available at 8-
bit input port is loaded into input latches.
• IBF ( Input buffer full ) – If this signal rises to logic 1, it indicates that data has
been loaded into latches, i.e. it works as an acknowledgement. IBF is set by a low
on STB and is reset by the rising edge of RD input.

• INTR ( Interrupt request ) – This active high output signal can be used to
interrupt the CPU whenever an input device requests the service. INTR is set by a
high STB pin and a high at IBF pin. INTE is an internal flag that can be controlled
by the bit set/reset mode of either PC4(INTEA) or PC2(INTEB) as shown in fig.

• INTR is reset by a falling edge of RD input. Thus an external input device can be
request the service of the processor by putting the data on the bus and sending the
strobe signal.
Output control signal definitions (mode 1)

• OBF (Output buffer full ) – This status signal, whenever falls to low, indicates
that CPU has written data to the specified output port. The OBF flip-flop will be
set by a rising edge of WR signal and reset by a low going edge at the ACK
input.

• ACK ( Acknowledge input ) – ACK signal acts as an acknowledgement to be

given by an output device. ACK signal, whenever low, informs the CPU that the
data transferred by the CPU to the output device through the port is received by
the output device.

• INTR ( Interrupt request ) – Thus an output signal that can be used to interrupt
the CPU when an output device acknowledges the data received from the CPU.
INTR is set when ACK, OBF and INTE are 1. It is reset by a falling edge on WR
input. The INTEA and INTEB flags are controlled by the bit set-reset mode ofPC6 and PC2
respectively.
Mode 2: Bidirectional Data Transfer

This mode of operation of 8255 is also called as strobed bidirectional I/O. This mode of
operation provides 8255 with an additional features for communicating with a peripheral device
on an 8-bit data bus. Handshaking signals are provided to maintain proper data flow and
synchronization between the data transmitter and receiver. The interrupt generation and other
functions are similar to mode 1.

• In this mode, 8255 is a bidirectional 8-bit port with handshake signals. The Rd and WR signals
decide whether the 8255 is going to operate as an input port or output port.

• The Salient features of Mode 2 of 8255 are listed as follows:

1. The single 8-bit port in group A is available.

2. The 8-bit port is bidirectional and additionally a 5-bit control port is available.

3. Three I/O lines are available at port C.( PC2 – PC0 )

4. Inputs and outputs are both latched.

5. The 5-bit control port C (PC3-PC7) is used for generating / accepting handshake signals for
the 8-bit data transfer on port A.

Control signal definitions in mode 2:

• INTR – (Interrupt request) As in mode 1, this control signal is active high and is used to
interrupt the microprocessor to ask for transfer of the next data byte to/from it. This signal is
used for input ( read ) as well as output ( write ) operations.

Control Signals for Output operations:

• OBF ( Output buffer full ) – This signal, when falls to low level, indicates that the
CPU has written data to port A.

• ACK ( Acknowledge ) This control input, when falls to logic low level, acknowledges that the
previous data byte is received by the destination and next byte may be sent by the processor. This
signal enables the internal tristate buffers to send the next data byte on port A.

• INTE1 ( A flag associated with OBF ) This can be controlled by bit set/reset mode with PC6.

Control signals for input operations :

• STB (Strobe input ) A low on this line is used to strobe in the data into the input
latches of 8255.

• IBF ( Input buffer full ) When the data is loaded into input buffer, this signal rises
to logic ‘1’. This can be used as an acknowledge that the data has been received
by the receiver.

• The waveforms in fig show the operation in Mode 2 for output as well as input
port.

Handshake mode of 8255 with 8085 : Block Diagram

2. BSR MODE:

The BSR mode is concerned only with the 8 bit of port C, which can be set or reset by writing an
appropriate control word in the control register. A control word with bit d7=0 is recognized as a
BSR control word. It does not alter any previously transmitted control word with bit d7=1 : thus
the I/O operations of ports A & B are not affected by the BSR control word. In the BSR mode
individual bits of port C can be used for applications such as an on/off switch.
CONTROL WORD REGISTER

The figure below shows the register called the control register. The contents of this register
called the control word specify an I/O function for each port, that is the ports can function
independently as input or output ports, which is achieved by the Control Word Register (CWR).

Bit D7 of the control register specifies either the I/O function or the Bit Set/ Reset function. If
the bit D7=1, bits D6-D0 determine the I/O function in various modes. If bit D7=0, port C
operates in the Bit Set/Reset (BSR) mode. The BSR control word does not affect functions of
port A and B.

To communication with peripherals through the 8255, three steps are necessary:

1. Determine the addresses of ports A,B and C and of the control register according to
the Chip Select logic and the address lines A0 and A1.
2. Write a control word in the control register.
3. Write I/O instructions to communicate with the peripherals through ports A, B and C.
Bibliography

 en.wikipedia.org/wiki/Intel_8255
 discovery.bits-pilani.ac.in/.../LEC31-35%20IOInterfacing_8255.ppt
 tams-www.informatik.uni-hamburg.de/...pio8255/pio-demo.html
 nptel.tvm.ernet.in/courses/Webcourse-contents/IISc.../module3.pdf
 www.scribd.com/.../8255-PPI-Programmable-Peripheral-Interface
 Godse, Microprocessor and interfacing