DIGITAL SYSTEM MODULE 5 & MODULE 6

TWO MARKS

1 .What is programmable logic array? How it differs from ROM?

In some cases the number of don’t care conditions is excessive, it is more economical
to use a second type of LSI component called a PLA. A PLA is similar to a ROM in
concept; however it does not provide full decoding of the variables and does not
generates all the minterms as in the ROM.

2.Define PLA

PLA is Programmable Logic Array(PLA). The PLA is a PLD that consists of a

programmable AND array and a programmable OR array.

3.Define PAL

PAL is Programmable Array Logic. PAL consists of a programmable AND array and a
fixed OR array with output logic.

4. Draw the block diagram for serial in serial out shift register.

5 Differentiate latch and Flip flop.

 6. Name the different types of Counters.

 Asynchronous Counters.
 Synchronous Counters.
 Asynchronous Decade Counters.
 Synchronous Decade Counters.
 Asynchronous Up-Down Counters.
 Synchronous Up-Down Counter
 7. Differentiate between static hazard and dynamic hazard.

STATIC HAZARD DYNAMIC HAZARD

Static hazard occur when an input changes and it Dynamic hazard occur when output
causes the output to change at the same moment changes for two adjacent inputs while the
before output becomes stable. output should change only once.

Dynamic hazard occur only in multilevel

Static hazard occur in combinational circuits. circuits.

Static hazard is easy to resolve. Dynamic hazard is complex to resolve.

Removal of static-1 hazard ensures no

It can be eliminated by using redundant gates. occurrence of dynamic hazard.

Static hazard is further classified as Static-1 and

Static-0. Dynamic hazard is not further classified.

It results in a transition to a wrong stable

It causes temporary false output value. state.

8. List the basic types of programmable logic array.

 Programmable Logic Array (PLA) ...

 Programmable Array Logic (PAL) ...
 Generic Logic Array (GLA) ...
 Complex Programmable Logic Device (CPLD) ...
 Field Programmable Gate Array (FPGA)

9. Define Counters.
A counter is used to count pulse and give the output in binary form.

Name the different types of counter.

a) Synchronous counter b) Asynchronous counter

 i) Up counter

ii) Down counter

iii) Modulo – N counter iv) Up/Down counter

10. What are the uses of a counter?

i) The digital clock

ii) Auto parking control

iii) Parallel to serial data conversion.

11. Differentiate Flip flop and shift register.

A flip-flop is a device which stores a single bit (binary digit) of data; one of its two states
represents a "one" and the other represents a "zero". Such data storage can be used for
storage of state, and such a circuit is described as sequential logic in electronics.

There are basically four different types of flip flops and these are:

 Set-Reset (SR) flip-flop or Latch.

 JK flip-flop.
 D (Data or Delay) flip-flop.
 T (Toggle) flip-flop.
shift register
A shift register is a type of digital circuit using a cascade of flip flops where the output of one flip-flop is
connected to the input of the next. They share a single clock signal, which causes the data stored in the
system to shift from one location to the next.
Following are the four types of shift registers based on applying inputs and accessing of outputs. Serial
In − Serial Out shift register. Serial In − Parallel Out shift register. Parallel In − Serial Out shift register.
Parallel In − Parallel Out shift register.
12.Compare and contrast between programmable logic array and programmable array
logic.

S.NOPLA PAL
PLA stands for Programmable
1. Logic Array. While PAL stands for Programmable Array Logic.

2. PLA speed is lower than PAL. While PAL’s speed is higher than PLA.

3. The complexity of PLA is high. While PAL’s complexity is less.

4. The cost of PLA is also high. While the cost of PAL is low.

Programmable Logic Array is While Programmable Array Logic is more available

5. less available. than Programmable Logic Array.

6. It is less used than PAL. While it is more used than PLA.

Counters in Digital Logic

Counter Classification
Counters are broadly divided into two categories
1. Asynchronous counter
2. Synchronous counter
1. Asynchronous Counter
In asynchronous counter we don’t use universal clock, only first flip flop is
driven by main clock and the clock input of rest of the following flip flop is driven
by output of previous flip flops. We can understand it by following diagram-

. Synchronous Counter
Unlike the asynchronous counter, synchronous counter has one global clock
which drives each flip flop so output changes in parallel. The one advantage of
synchronous counter over asynchronous counter is, it can operate on higher
frequency than asynchronous counter as it does not have cumulative delay
because of same clock is given to each flip flop.
   Synchronous  counter circuit

Decade Counter
A decade counter counts ten different states and then reset to its initial states. A
simple decade counter will count from 0 to 9 but we can also make the decade
counters which can go through any ten states between 0 to 15(for 4 bit
counter).

Clock
pulse Q3 Q2 Q1 Q0

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

10 0 0 0 0

          Truth table for simple decade counter

 Decade counter circuit diagram
We see from circuit diagram that we have used nand gate for Q3 and Q1 and
feeding this to clear input line because binary representation of 10 is—
1010
And we see Q3 and Q1 are 1 here, if we give NAND of these two bits to clear
input then counter will be clear at 10 and again start from beginning.
Important point: Number of flip flops used in counter are always greater than
equal to (log2 n)  where n=number of states in counter.

4 bit binary Ripple Counter using T flip flop and

explain in detail.
Ripple Counter
Ripple counter is a special type of Asynchronous counter in which the clock pulse
ripples through the circuit. The n-MOD ripple counter forms by combining n number of
flip-flops. The n-MOD ripple counter can count 2n states, and then the counter resets to
its initial value.

Only the first flip-flop is clocked by an external clock. ... Asynchronous counters are also called
ripple-counters because of the way the clock pulse ripples it way through the flip-flops.
4-Bit Ripple Counter. This circuit is a 4-bit binary ripple counter. All the JK flip-flops are
configured to toggle their state on a downward transition of their clock input, and the output of
each flip-flop is fed into the next flip-flop's clock.

Ripple counter is a special type of Asynchronous counter in which the clock pulse ripples
through the circuit. The n-MOD ripple counter forms by combining n number of flip-flops. The
n-MOD ripple counter can count 2n states, and then the counter resets to its initial value.

synchronous 4-bit up/down counter using

JK flip-flops.
Binary 4-bit Synchronous Up Counter

It can be seen above, that the external clock pulses (pulses to be counted) are
fed directly to each of the J-K flip-flops in the counter chain and that both
the J and K inputs are all tied together in toggle mode, but only in the first flip-
flop, flip-flop FFA (LSB) are they connected HIGH, logic “1” allowing the flip-
flop to toggle on every clock pulse. Then the synchronous counter follows a
predetermined sequence of states in response to the common clock signal,
advancing one state for each pulse.
The J and K inputs of flip-flop FFB are connected directly to the output QA of
flip-flop FFA, but the J and K inputs of flip-flops FFC and FFD are driven from
separate AND gates which are also supplied with signals from the input and
output of the previous stage. These additional AND gates generate the
required logic for the JK inputs of the next stage.
If we enable each JK flip-flop to toggle based on whether or not all preceding
flip-flop outputs (Q) are “HIGH” we can obtain the same counting sequence as
with the asynchronous circuit but without the ripple effect, since each flip-flop
in this circuit will be clocked at exactly the same time.
Then as there is no inherent propagation delay in synchronous counters,
because all the counter stages are triggered in parallel at the same time, the
maximum operating frequency of this type of frequency counter is much
higher than that for a similar asynchronous counter circuit.

4-bit Synchronous Counter Waveform Timing Diagram

Because this 4-bit synchronous counter counts sequentially on every clock

pulse the resulting outputs count upwards from 0 ( 0000 ) to 15 ( 1111 ).
Therefore, this type of counter is also known as a 4-bit Synchronous Up
Counter.
However, we can easily construct a 4-bit Synchronous Down Counter by
connecting the AND gates to the Q output of the flip-flops as shown to
produce a waveform timing diagram the reverse of the above. Here the
counter starts with all of its outputs HIGH ( 1111 ) and it counts down on the
application of each clock pulse to zero, ( 0000 ) before repeating again.

Binary 4-bit Synchronous Down Counter

As synchronous counters are formed by connecting flip-flops together and any

number of flip-flops can be connected or “cascaded” together to form a
“divide-by-n” binary counter, the modulo’s or “MOD” number still applies as it
does for asynchronous counters so a Decade counter or BCD counter with
counts from 0 to 2n-1 can be built along with truncated sequences. All we need
to increase the MOD count of an up or down synchronous counter is an
additional flip-flop and AND gate across it.

Decade 4-bit Synchronous Counter

A 4-bit decade synchronous counter can also be built using synchronous
binary counters to produce a count sequence from 0 to 9. A standard binary
counter can be converted to a decade (decimal 10) counter with the aid of
some additional logic to implement the desired state sequence. After reaching
the count of “1001”, the counter recycles back to “0000”. We now have a
decade or Modulo-10 counter.
Decade 4-bit Synchronous Counter

The additional AND gates detect when the counting sequence reaches

“1001”, (Binary 10) and causes flip-flop FF3 to toggle on the next clock pulse.
Flip-flop FF0 toggles on every clock pulse. Thus, the count is reset and starts
over again at “0000” producing a synchronous decade counter.
We could quite easily re-arrange the additional AND gates in the above
counter circuit to produce other count numbers such as a Mod-12 counter
which counts 12 states from”0000″ to “1011” (0 to 11) and then repeats
making them suitable for clocks, etc.