MM54HCT688/MM74HCT688 8-Bit Magnitude Comparator (Equality Detector)

February 1988

MM54HCT688/MM74HCT688
8-Bit Magnitude Comparator (Equality Detector)
General Description
This equality detector utilizes advanced silicon-gate CMOS MM54HCT/MM74HCT devices are intended to interface be-
technology to compare bit for bit two 8-bit words and indi- tween TTL and NMOS components and standard CMOS
cate whether or not they are equal. The P e Q output indi- devices. These parts are also plug in replacements for LS-
cates equality when it is low. A single active low enable is TTL devices and can be used to reduce power consumption
provided to facilitate cascading of several packages and en- in existing designs.
able comparison of words greater than 8 bits. All inputs are protected from damage due to static dis-
This device is useful in memory block decoding applica- charge by diodes to VCC and ground.
tions, where memory block enable signals must be generat-
ed from computer address information. Features
The comparator combines the low power consumption of Y TTL input compatible
CMOS, but inputs are compatible with TTL logic levels, and Y Typical propagation delay: 20 ns
the output can drive 10 low power Schottky equivalent Y Low quiescent current: 80 mA maximum (74HCT Series)
loads. Y Large output current: 4 mA
Y Same as HCT521

Logic Diagrams

TL/F/5371 – 2

C1995 National Semiconductor Corporation TL/F/5371 RRD-B30M105/Printed in U. S. A.

 Absolute Maximum Ratings (Notes 1 & 2) Operating Conditions
If Military/Aerospace specified devices are required, Min Max Units
please contact the National Semiconductor Sales Supply Voltage (VCC) 4.5 5.5 V
Office/Distributors for availability and specifications. DC Input or Output Voltage 0 VCC V
Supply Voltage (VCC) b 0.5 to a 7.0V (VIN, VOUT)
DC Input Voltage (VIN) b 1.5 to VCC a 1.5V Operating Temp. Range (TA)
DC Output Voltage (VOUT) b 0.5 to VCC a 0.5V MM74HCT688 b 40 a 85 §C
MM54HCT688 b 55 a 125 §C
Clamp Diode Current (IIK, IOK) g 20 mA
Input Rise or Fall Times
DC Output Current, per pin (IOUT) g 25 mA
(tr, tf) 500 ns
DC VCC or GND Current, per pin (ICC) g 50 mA
Storage Temperature Range (TSTG) b 65§ C to a 150§ C
Power Dissipation (PD)
(Note 3) 600 mW
S.O. Package only 500 mW
Lead Temperature (TL)
(Soldering 10 seconds) 260§ C

DC Electrical Characteristics (VCC e 5V g 10% unless otherwise specified)

74HCT 54HCT
TA e 25§ C
Symbol Parameter Conditions TA eb40 to 85§ C TA eb55 to 125§ C Units
Typ Guaranteed Limits
VIH Minimum High Level 2.0 2.0 2.0 V
Input Voltage
VIL Maximum Low Level 0.8 0.8 0.8 V
Input Voltage
VOH Minimum High Level VIN e 0.8V or 2.0V
Output Voltage lIOUTl e 20 mA VCC VCCb0.1 VCCb0.1 VCCb0.1 V
lIOUTl e 4.0 mA, VCC e 4.5V 4.2 3.98 3.84 3.7 V
lIOUTl e 4.8 mA, VCC e 5.5V 5.7 4.98 4.84 4.7 V
VOL Maximum Low Level VIN e V0.8V or 2.0V
Voltage lIOUTl e 20 mA 0 0.1 0.1 0.1 V
lIOUTl e 4.0 mA, VCC e 4.5V 0.2 0.26 0.33 0.4 V
lIOUTl e 4.8 mA, VCC e 5.5V 0.2 0.26 0.33 0.4 V
IIN Maximum Input VIN e VCC or GND g 0.1 g 1.0 g 1.0 mA
Current
ICC Maximum Quiescent VIN e VCC or GND 8.0 80 160 mA
Supply Current IOUT e 0 mA
VIN e 2.4V or 0.5V (Note 4) 0.3 0.4 0.5 mA
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package: b 12 mW/§ C from 65§ C to 85§ C; ceramic ‘‘J’’ package: b 12 mW/§ C from 100§ C to 125§ C.
Note 4: Measured per pin. All other inputs held at VCC or ground.

2
AC Electrical Characteristics
VCC e 5V, TA e 25§ C, CL e 15 pF, tr e tf e 6 ns (unless otherwise specified)

Guaranteed
Symbol Parameter Conditions Typ Units
Limit
tPHL Maximum Propagation 19 30 ns
Delay - P or Q to Output
tPLH Maximum Propagation 13 22 ns
Delay - P or Q to Output
tPHL Maximum Propagation 13 20 ns
Delay - Enable to Output
tPHL Maximum Propagation 10 18 ns
Delay - Enable to Output

AC Electrical Characteristics
VCC e 5V g 10%, CL e 50 pF, tr e tf e 6 ns (unless otherwise specified)
74HCT 54HCT
TA e 25§ C
Symbol Parameter Conditions TA eb40 to 85§ C TA eb55 to 125§ C Units
Typ Guaranteed Limits
tPHL Maximum Propagation 23 35 44 53 ns
Delay - P or Q to Output
tPLH Maximum Propagation 16 24 30 36 ns
Delay - P or Q to Output
tPHL Maximum Propagation 16 24 30 36 ns
Delay - Enable to Output
tPLH Maximum Propagation 11 20 25 30 ns
Delay - Enable to Output
tTHL, tTLH Maximum Output Rise 8 15 19 22 ns
and Fall Time
CPD Power Dissipation 45 pF
Capacitance (Note 5)
CIN Maximum Input 5 10 10 10 pF
Capacitance
Note 5: CPD determines the no load dynamic power consumption, PD e CPD VCC2 f a ICC VCC, and the no load dynamic current consumption,
IS e CPD VCC a ICC.

Connection Diagram Truth Table

Dual-In-Line Package
Inputs
Data Enable PeQ
G
P, Q
PeQ L L
PlQ L H
PkQ L H
X H H

TL/F/5371 – 1
Top View
Order Number MM54HCT688 or MM74HCT688

3
MM54HCT688/MM74HCT688 8-Bit Magnitude Comparator (Equality Detector)
Physical Dimensions inches (millimeters)

Order Number MM54HCT688J or MM74HCT688J

NS Package J20A

Order Number MM74HCT688N

LIFE SUPPORT POLICY NS Package N20A

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SEMICONDUCTOR CORPORATION. As used herein:

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failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.

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