0.

5 V Supply Resistorless Voltage Reference for Low

Voltage Applications

Renato Campana V. Hamilton Klimach Sergio Bampi

PGMicro - Graduate Program PGMicro - Electrical PGMicro - Informatics Institute
on Microlectronics Engineering Department Federal Univ. of Rio Grande
Federal Univ. of Rio Grande Federal Univ. of Rio Grande do Sul
do Sul. do Sul Porto Alegre, Brazil
Porto Alegre, Brazil Porto Alegre, Brazil [email protected]
[email protected] [email protected]

ABSTRACT linearly combines it with the proportional-to-absolute tem-

The analysis and design of a resistorless sub-bandgap voltage perature (PTAT) characteristic of the voltage difference be-
reference using a Schottky diode instead of a bipolar junc- tween two PN junctions with different current densities, to
tion is presented. It is a self-biased circuit and works in the obtain a temperature independent output voltage [4], ide-
nano-ampere current consumption range at a supply voltage ally independent of the load, power supply, and fabrication
as low as 0.5 V. The design is validated through post-layout process variability. The traditional topology circuit offers
simulation results for a 130 nm CMOS technology, including an output voltage around 1.2 V. Taking advantage of the
process variability analysis. A voltage reference around 240 parasitic bipolar transistors in CMOS technology this bipo-
mV is achieved for VDD = 1.2V , with a temperature coeffi- lar voltage reference circuit was adapted for use in CMOS
cient TC of 43 ppm/◦ C in the range from -40◦ C to 120◦ C circuits [1].
and 192 ppm/◦ C with VDD = 0.5V in the same temperature However, the continuous scaling of transistors dimensions
range. The current consumption is 276 nA for VDD = 1.2V in combination with the need to reduce power consumption
at 27◦ C, and the silicon area is 0.0016 mm2 for the entire in large digital ICs is driving down the supply voltage for
reference. nanoscale CMOS technologies [4], since is the most efficient
way to reduce the power consumption of digital circuits (the
2
dynamic power density is proportional to VDD [5]). For this
Categories and Subject Descriptors reason, supply voltages well below 1V and even down to 0.5V
B.4 [Very Large Scale Integration Design]: Analog and for low voltage and low power (LVLP) applications are pro-
Mixed-Signal Circuits—Analog and mixed-signal circuit op- jected in the ITRS roadmap [4], [5]. Since digital and analog
timization circuits are usually together in mixed-signal integrated cir-
cuits, the aforementioned circuits and systems must operate
more and more under LVLP conditions [2], [6], and special
General Terms techniques should be used to design them. Recent research
Theory, Design, Performance has demonstrated the feasibility of designing analog and RF
circuits that can operate with low supply voltages around to
Keywords 0.5 V [4], [7], [8], [9], [10], [11], [12].
In the case of the traditional bandgap voltage reference,
Sub-Bandgap voltage reference, low supply voltage, Schot- with an output voltage (VREF ) near to 1.2 V which exceeds
tky diode, ultra-low power. the sub 1 V supply voltage, several alternative circuit topolo-
gies have been proposed to overcome that limitation. Some
1. INTRODUCTION of these new circuit topologies are still based on the bandgap
The Bandgap Reference (BGR) circuit is an essential block principle and generate an output voltage equal to a fraction
of several analog and mixed-signal circuits such as data con- of the 1.2V [2]. But, for these cases, the minimun supply
verters, voltage regulators and phase-locked loops [1], [2]. voltage cannot be lower than the forward biased PN junction
This reference, introduced by Widlar in 1971 [3], uses the voltage (about 0.6 V) [13]. Some of these circuits operate
complementary-to-absolute-temperature (CTAT) character- with supply range from 0.85 V to 0.9 V [14], [15], [16], [17],
istic of the forward voltage drop across a PN junction and or around 0.75 V [18].
MOS-only voltage references, on the other hand, can op-
erate at lower supply voltages and are not bound by the
Permission to make digital or hard copies of all or part of this work for limitations due to the forward biased PN junction voltage.
personal or classroom use is granted without fee provided that copies are Most designs exploit the negative temperature dependence
not made or distributed for profit or commercial advantage and that copies of the MOS threshold voltage and combine it with a PTAT
bear this notice and the full citation on the first page. To copy otherwise, to characteristic, which can be obtained with MOS devices bi-
republish, to post on servers or to redistribute to lists, requires prior specific ased in the subthreshold region. Some high performance
permission and/or a fee. Request permissions from [email protected].
SBCCI August 31 - September 04, 2015, Salvador, Brazil voltage references operating down to 0.85 V voltage supply
© 2015 ACM. 978-1-4503-3763-2/15/08 $15.00. have been reported in [2], [13], [19], [20], [21].
DOI: http://dx.doi.org/10.1145/2800986.2800987
 In this work, we suggest to replace the PN junction used
in a sub-bandgap reference proposed in [20], by a CMOS-
compatible Schottky diode, since the forward biasing voltage
of this device for the same current density level is much lower
than the PN junction, which impacts in additional power
supply reduction.
This paper is organized as follows: after the introduction,
the basic operation principle of the proposed circuit is shown
in section II. A compact MOSFET model is presented and
applied to the circuit in section III. Section IV is dedicated
to develop the design methodology of the circuit. Simulation Figure 3: Vdiode vs temperature curve for the 2µm x 2µm Schot-
results are presented in section V and finally, in section VI tky Diode, with Idiode =60 nA
some conclusions from this work are drawn.

2. CIRCUIT OPERATING PRINCIPLE MN1 and MN2 gate-source voltages and consequently their
drain current since they are in series, defining the Schottky
The circuit topology circuit was proposed in [20] and it diode current IDSH , through a feedback path that uses a
is shown in Fig.1, but using a Shottky diode instead of the current mirror to bias the diode (MP8 and MP9). Since
traditional bipolar transistor (BJT). In the original circuit, the MN1 and MN2 transistors have the same current, and
the forward bias voltage (usually from 0.5 to 0.6V ) imposes assuming that they have the same aspect ratio, the diode
a limit for the minimum supply voltage (VDDmin ), as can voltage appears divided by two at the gate of MN1. This
be seen through the voltage critical path MP8-BJT. Using a voltage is then added to a PTAT voltage generated by three
Shottky diode this critical path can work at a lower voltage self-cascode structures in cascade, composed by MN2-MN3,
because the diode forward voltage is reduced to around 0.2 MN4-MN5 and MN6-MN7, to provide a temperature inde-
to 0.3V . pendent output VREF .
VDD Fig. 2 shows the forward I-V curves of two different alter-
native devices used at the node voltage VD in Fig. 1: two
MP9 MP10 MP11 Schottky diodes as shown (with differents geometries), and
MP8 MP12
the conventional vertical bipolar pnp transistor connected
as a diode, at 27◦ C. Under a forward voltage below 0.50
V, the emitter current of the bipolar transistor is on the
order of hundreds of pAs, which could result in significant
MN5
errors when compared to the drain and source leakage cur-
MN3 MN7
VREF rents [20], thus imposing a severe constraint for the mini-
mum power supply voltage. In the same Fig 2, the curves
VD MN2 MN4 MN6 of the Schottky diodes can work in the 0.2-0.3 V interval
with currents from tens to hundreds of nanoamperes, thus
IDSH constituting an advantage over the bipolar device when the
target is the operation under very low supply voltages.
MN1
+ Fig. 3 shows the Schottky diode voltage over temper-
VGS1 ature characteristics when biased with Idiode = 60nA for
- which the forward voltage is 0.25 V at room temperature.
Through this figure one can see that this device presents a
Figure 1: Voltage Reference Schematic Diagram CTAT behavior like the PN junction, with a temperature
dependence around δVD /δT ≈ −1.5mV /◦ C.

3. CIRCUIT ANALYSIS
3.1 The UICM Model
The Unified Current Control Model UICM [22], has proven
to be an important tool for circuit design due to its accurate
modelling of MOSFETs through any inversion level. From
this model the drain current of a long channel MOSFET is
expressed as

ID = IF − IR = ISQ (if − ir )S (1)

where IF and IR are the forward and reverse components
Figure 2: I-V curves for the Schottky Diodes and the Bipolar of the current, if and ir are the forward and reverse inver-
Transistor
sion coefficientes (or ’levels’) and S = W/L is the active
area aspect ratio, where W and L are the MOSFET width
The equilibrium of the bias condition of the circuit can and lenght, respectively. ISQ is a process related parameter
be understood as follows. The diode voltage establishes the called ’sheet specific current’ being defined as
 If both transistors are biased in weak inversion (if < 1),
0 φ2t the F (if ) therm of Eq. (4) can be approximated by a Taylor
ISQ = µCox n (2) i
expansion given by F (if ) ≈ −1 + ln( 2f ), and applying that
2
where n is the subthreshold slope factor, µ is the chan- to the last Eq. we have
nel effective mobility (both slightly dependent on the gate  
0
voltage), Cox is the gate capacitance per unit area and φt = if down
VDSdown = φt ln (6)
kB T /q is the thermal voltage, where kB is the Boltzmann’s if up
constant, q is the electronic charge, and T is the absolute Now, applying the Eq. (1) to this circuit, one can obtain
temperature. When the transistor is saturated, the reverse the following equations for the transistor currents in terms
current IR is neglibible with respect to the forward current of the inversion levels
IF and the drain current is almost independent of the drain
voltage, i.e.
IDup = KIref = ISQ Sup if up

ID ≈ IF = ISQ Sif (3)

if up
The relationship between the inversion levels and the ter- Iref = ISQ Sup (7)
K
minal voltages is the UICM equation given by
IDdown = (K + Z)Iref = ISQ Sdown (if down − irdown ) (8)
VP − VS(D) p p
= F (if (r) ) = 1 + if (r) −2+ln 1 + if (r) (4) Since in this circuit if up = irdown , Iref is given by Eq.
φt
(7), and applying it to Eq. (8) results
where VS(D) is the source (drain) voltage, referred to the
bulk terminal. VP is the pinch-off voltage, defined as VP = if down

Z

Sup
(VGB − VT )/n, where VT is the threshold voltage. The tran- =1+ 1+ (9)
if up K Sdown
sistor operates in weak inversion for if < 1, in strong inver-
sion for if > 100, and in moderate inversion for 1 < if < Now replacing the last statement in the Eq. (6) finally
100. More details about the UICM model can be found results
in [22].    
Z +K Sup
3.2 Self-Cascode VDSdown = φt ln 1 + (10)
K Sdown
The association of two MOSFETs as in the Fig. 4, where As one can see in the last equation, the SC performs as a
Mup operates in the saturation region and Mdown operates PTAT generator circuit if the transistors Mup and Mdown are
in the triode region, is called the Self-Cascode (SC) circuit biased in the subthreshold region, with VDSdown typically
and generates a PTAT voltage in the VDSdown , when the less than a hundred milivolts [20].
transistors are biased in the subthreshold region.
3.3 Voltage Reference Circuit
According to the circuit of Fig. 1, the reference voltage
KIREF (VREF ) that results in the output node can be expressed
through the voltage drop acroos MN1 added to the SC PTAT
voltages

MUP ZIREF
VREF = VDS6 + VDS4 + VDS2 + VGS1 (11)
Since the same current flows in M1 and M2, and they
have approximately the same aspect ratio, their gate-source
MDOWN voltages is almost equal, resulting that VGS1 ≈ VD /2, being
VD the Schottky diode voltage.
By applying Eq. (10) the last equation (11), and remem-
bering that the current mirrors (MP8-MP12) have the same
Figure 4: Self-Cascode circuit aspect ratio, so ID6 = 2ID7 , ID4 = 3ID5 and ID2 = 4ID3 ,
then the VREF results as:
When two MOS transistors share the same gate voltage    
(VG ), both have the same pinch-off voltage (VP ), so applying S7 S5 S3
Eq. (4) to the Mdown transistor results in the following VREF = φt ln 1+2 1+3 1+4 + VD /2
S6 S4 S2
expression for its drain-source voltage (12)
where the first term of the equation represents the PTAT
VDSdown = φt [F (if down ) − F (irdown )] voltage and the second one (VD /2) presents the CTAT be-
havior. Such as mentioned before, since δVD /δT ≈ −1.5mV /
As both transistors share the same gate voltage and the ◦
C, so through the Eq. (12) it is possible to verify that
source of Mup is tied to the drain of Mdown , then if up = temperature compensation of VREF can be performed with
irdown , so the last Eq. can be rewritten as a proper sizing of devices S2 − S7 to provide a positive
δVP T AT /δT ≈ 0.75mV /◦ C, making this VREF temperature
VDSdown = φt [F (if down ) − F (if up )] (5) independent [20], [6].
4. DESIGN PROCEDURE
According to the section II and Fig. 1, the Schottky diode
inclusion through the voltage critical path MP8-diode re-
duced the limit for the VDDmin . From Fig. 2 one can MP8-MP12
see that when this device of 2µm x 2µm anode size is bi-
ased with IDSH = 60nA the diode voltage results VD ≈

45 µm
250mV and the supply voltage could be reduced to 350
MN4 MN6
mV ( 250mV + 100mV of VSDsat ) , when compared to a MN1 MN2 MN3
MN5 MN7
junction diode based sub-bandgap reference. The aspect
ratios of MP8-MP12 were chosen to be equal to improve
layout aspects and matching. They are all biased in weak
Schottky
inversion so they have a minimum saturation voltage around Diode
VSDsat ≈ 100mV . The chosen inversion level for these tran-
sistors was if p =0.2, resulting the aspect ratio (16/2) for
all PMOS according to Eq. (3), being the specific current 35 µm
around ISQP ≈ 32nA for the standard PMOS transistors in
Figure 5: Voltage Reference layout
this technology.
From Fig. 1 one can see that the proposed circuit uses
three self-cascode structures to provide the PTAT voltage,
composed by MN2-MN3, MN4-MN5 and MN6-MN7 respec-
tively, and from section III they must be biased near the
subthreshold condition to operate as PTAT generators (in
fact the SC also works as a PTAT circuit when the transis-
tors are biased in strong inversion, but only if both are kept
under constant inversion levels).
Since under the chosen bias condition and 27 ◦ C the for-
ward Schottky diode voltage is ≈ 250 mV, and the VGS1
is around half of that voltage, the total PTAT voltage that
must be added by the SC circuits to compensate the diode
CTAT dependence is ≈ 125 mV, resulting a final reference
voltage around 250 mV. The chosen PTAT voltages of each
Figure 6: Voltage Reference vs. Temperature with VDD = 1.2V
SC were around 35 mV for the first one and 45 mV for
the last ones, resulting the inversion levels around if 2 =
0.4, if 3 = 0.3 for the first SC and if 4,6 = 3, if 5,7 = 1 for the
last two. From Eq. (3) the SC transistors aspect ratio can
be calculated, resulting the values shown in table I. We de-
terminated the specific current to be around ISQN ≈ 200nA
for the standard NMOS transistors in this technology.
The final sizing is presented in Table I after some size ad-
justments that were done from circuit simulation. All the
PMOS transistors have the same aspect ratio and, it chosen
Schottky diode anode size is 2µm x 2µm, since according to
Fig. 2, is the minimum size for the foundry-characterized
Schottky diode, and which the minimum current consump-
tion.
Figure 7: Voltage Reference vs. Supply Voltage for 27◦ C
Table 1: MOSFETs SIZING

MN1 MN2 MN3 MN4 MN5 MN6 MN7 MP

by Eq. (13) [20], is 43 ppm/◦ C for VDD = 1.2V and 192
W (um) 17 15 4.5 1.5 1.5 1 1.5 16 ppm/◦ C for VDD = 0.5V , both inside a very wide tempera-
L (um) 5 5 5 5 5 5 5 2 ture range from -40◦ C to 120◦ C.

VREF max − VREF min

T CEF F = (13)
5. SIMULATION RESULTS (Tmax − Tmin ) VREF (27◦ C)
The results presented in this section are from post-layout Fig. 7 shows the reference voltage dependence on the
simulations. The layout is shown in the Fig. 5 and the supply voltage, or VDD vs. VREF . From this figure, one can
occupied area is 0.0016 mm2 . see that the minimum supply value VDDmin is around 0.4 to
Fig. 6 shows the temperature dependence of the output 0.5 V. One finds that this voltage reference circuit does not
reference voltage with a supply voltage of VDD = 1.2V The have low line sensitivity (LS).
voltage reference value varies between 237mV and 239mV The analysis of the circuit sensitivity to the fabrication
for a temperature range from -40◦ C to 120◦ C. variability effects was done through Monte Carlo simula-
The effective temperature coefficient (T CEF F ), as given tion, that was performed separately for ’mismatch’ and for
’process’ variations, with 1000 runs each. These simulations that the cited Voltage References operate with smaller tem-
are shown in Fig. 8. Through these figures, one can see perature ranges, and some of them use trimming [21].
that the larger sensitivity of the circuit relies on process If a higher TC can be tolerated, the VDDmin can be re-
variation effects, reaching a maximum of 81 mV over the duced to VDD = 0.45V , resulting a TC=210 ppm/◦ C. Our
typical VREF ≈ 240mV for a 3σ requirement. Process vari- Voltage Reference design for very low VDD does not use any
ations impact is larger in MOSFETs biased in subthreshold trimming strategy yet. Finally, the total power consumption
region [20] like the ones used in this reference circuit to save is less than 330 nW for the overall supply voltage range, at
power. According to Eq. (12), the VGS1 term represents room temperature.
the CTAT voltage that results from the combination of the
diode characteristics with the MOSFETs characteristics, in- 6. CONCLUSIONS
cluding the threshold voltage VT , which is a parameter that
presents large process variability in state of the art CMOS In this paper we proposed a resistorless voltage refer-
technologies [6]. ence circuit that uses a Schottky diode instead of a junc-
tion diode, since with that inclusion, the circuit can operate
with supply voltage as low as 0.5 V. It was analysed us-
ing a consistent MOSFET model that is valid from weak
to strong inversion condition and design equations were de-
rived. A design methodology was proposed and validated
through the implementation of the circuit in a standard 130
nm CMOS process, where post-layout simulations include
process and mismatch variability effects analysis. A voltage
reference of 239 mV was achieved for a supply voltage of 1.2
V, with temperature coefficients of 43 ppm/◦ C in the range
from -40◦ C to 120◦ C and 192 ppm/◦ C with VDD = 0.5V
in the same temperature range. The current consumption
is 276 nA with VDD = 1.2V at 27◦ C, and the chip area is
(a) 0.0016 mm2 .
Improvements are necessary to increase PSRR and reduce
line sensitivity. A trimming technique may be also necessary
to deal with the large process sensitivity, possibly including
diode curvature compensation.
The circuits were sent to fabricated. It expected those
prototypes for test measurements.

Acknowledgment
The authors acknowledge the IC-Brazil Program for CAD
tools, the CNPq and CAPES for financial support, and MO-
SIS for silicon prototyping.

(b)
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 Table 2: PERFORMANCE COMPARISON OF THIS WORK TO OTHER LOW SUPPLY VOLTAGE REFERENCES

This work [4] [13] [18] [21]

Tech. 130 nm 90 nm 110 nm 130 nm 180 nm
Voltage reference type Schottky Schottky VT O Bipolar and VT O
switched capacitor
Comments Simulated Measured Measured Measured Measured
Temp. Range −40◦ to 120◦ 0◦ to 100◦ 10◦ to 90◦ −25◦ to 85◦ −25◦ to 85◦
Minimun VDD 500 mV 550 mV 242 mV 0.75 0.7
VREF 239 mV @ VDD = 1.2 V 247 mV 195.6 184.84 438.7
216 mV @ VDD = 0.5 V
43 @ VDD = 1.2 V 270 134 40 22.11
T.C. (ppm/◦ C)
192 @ VDD = 0.5 V
Power 330 nW @ VDD = 1.2 V 358 uW 5.35 uW 170 nW 19 nW
113 nW @ VDD = 0.5 V
32 @ VDD = 1.2 V N/A N/A 40 N/A
PSRR (dB) @ 1 kHz
27 @ VDD = 0.5 V
LS (mV /0.1V ) 32.8 3 0.8 N/A 0.571
Area (mm2 ) 0.0016 0.059 0.013 0.07 0.041

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