41. What are adaptive sequencing circuits. Explain any 2 adaptive circuits in brief.

(2 marks)

2.

.
3.Draw the ckt diagram of a TSPC based rising edge triggered D flipflop and explain its
operation.(3 marks)
4. What are the modern methodology used in SoCs to remove clock jitter and skew?
5. What do you mean by TSPC? Draw the circuitry of TSPC flipflop
6)
7.

8. What is setup and holdup time?

9.

10. Explain the circuit designing for Latch?

11. **
8.
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10.

11. What is clock skew and clock jitter? What are the causes of clock jitters?
12. Design the function Y=A+BC in TSPC logic
13.
14.

Find setup and hold time for conditions mentioned below:

a.without any skew(take jitter =0)
b. positive skew( tskew=5ps)
c. negative skew (tskew=10ps)

15a. What is time borrowing? [ 2 marks]

b. What is the maximum time the two-phased latch can borrow? [1 mark]

16.
.
17.Explain positive and negative skew
18.
19. What is a skewed gate? What is the impact on rise delay, fall delay if high skewed gates are
present?
18. file:///tmp/mozilla_anonymous0/IMG_20181115_215959.jpg

19. Given are the timing parameters of a flip flop circuit. Determine maximum logic
propagation delay available within a 500ps clock cycle. Tskew:0ps, tsetup:65ps, tclk-q:50ps,
tcd:35ps, thold:30ps.
A.) tpd: 385ps

20.)
21.)

How are Setup and Hold path relevant in synchronous logic?

Explain in detail, the techniques involved in reducing the area of a register file:

What are the advantages and disadvantages of positive and negative clock skew?

In some super critical applications, there are 2 D-flip flops connected in series with the output of
the first one provided as input to the other one to "double-clock" the data. Explain the purpose of
this setup?

QFor each of the following sequencing styles, determine the maximum logic propagation delay available within a
500 ps clock cycle. Assume there is zero clock skew and no time borrowing takes place.

a) Flip-flops

b) Two-phase transparent latches

c) Pulsed latches with 80 ps pulse width

Q Prove

Q What is the advantage of using dual edge-triggered flip-flop over the normal flip-flop?

Q It’s chaotic time (as always) in the country with three major states having assembly elections and
Lok Sabha elections approaching soon. Elections are all about timing. Modi ji wants to teach his
party followers about this success mantra. Let’s assume you are Amit Shah, a big fan of the Digital
VLSI Design course (let’s pretend it too). You remember learning about the topic of timing analysis
in the sequential circuits and would like to help your mota bhai (Modi Ji) applying some of those
concepts in real life. Answer the following questions to come up with the perfect “Chanakya Neeti”.

a) Mention few sources of clock uncertainties. Explain any two non-idealities introduced in the
clock due to these uncertainties. (2 marks) b) Calculate the sequencing overhead delay and
minimum delay constraint in a circuit with the pulsed latch. Assume tpw > tsetup 3 marks)

c) Explain the concept of time borrowing w.r.t. a latch. Why is time borrowing not so
obvious in a flip-flop based system? Calculate the maximum time that can be borrowed in
the circuit drawn below? Draw the timing diagram for clock 2 to maximise the borrowed
time. t1 is a symmetric clock with a time period of 10 ns. The datapath between any two
latches: 10ns (5 marks)
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Explain the functioning of following latches.
a.TSPC b.C2MOS

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Suppose one cycle of logic is particularly critical and the next cycle is nearly empty.

Determine the maximum amount of time the first cycle can borrow into the sec-

ond for each of the following sequencing styles. Assume there is zero clock skew

and that the cycle time is 500 ps.

a) Flip-flops

b) Two-phase transparent latches with 50% duty cycle clocks

c) Pulsed latches with 80 ps pulse width

Q

Q Explain clock jitter and clock skew.

Q
Q
What are the two schemes one can use to manage timing constraints? Explain the fundamental
difference between the two. Comment on which scheme would be better.
The two schemes are canary and razor.
In canary, I make a dummy critical path, which takes the longest time. Even if there is a slight problem
in my circuitry, the canary circuit will die, hence saving my rest of the circuitry from failing.
In razor scheme, I begin to operate my circuit faster and add additional flops at few stages. Now I
check early sample and the late sample, where flops were added. I compare them using xor gate, and
if the output of XOR is 0, well and good, both the values were same. If 1 is the output, this means my
circuit failed. Consequently, I'll redo this particular pipeline at a lower frequency, while rest of the
circuit can still work fast.

On the comment part, one can say that canary would require greater area of the chip, since a whole
extra critical path has to be implemented, while comparatively, razor won't eat up my chip area as
much. Additionally, both are well suited for saving power/performance at low voltage.

Q. List differences between latches and flip flops in terms of timing constraints to be met.

Q.
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Question
Use the timing parameters in Table for the following question:

Q1.
For each of the following sequencing styles, determine the maximum logic propagation
delay available within a 500 ps clock cycle. Assume there is zero clock skew and
no time borrowing takes place.
a) Flip-flops
b) Two-phase transparent latches
c) Pulsed latches with 80 ps pulse width
Ans.
(a) tpd = 500 - (50 + 65) = 385 ps; (b) tpd = 500 - 2(40) = 420 ps; (c) tpd = 500 - 40 =
460 ps.
Repeat Q1 if the clock skew between any two elements can be up to 50 ps.
Ans.
(a) tpd = 500 - (50 + 65 + 50) = 335 ps; (b) tpd = 500 - 2(40) = 420 ps; (c) tpd = 500 -
(50 + 25 - 80 + 50) = 455 ps.

Question
Prove this equation
ans:
If the pulse is wide and the data arrives while the pulsed latch is transparent, the
latch contributes its D-to-Q delay just like a regular transparent latch. If the pulse is
narrow, the data will have to setup before the earliest skewed falling edge. This is at
time tsetup - tpw + tskew before the latest rising edge of the pulse. After the rising
edge, the latch contributes a clk-to-Q delay. Hence, the total sequencing overhead is
tpcq + tsetup - tpw + tskew

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