Types of Flip-Flops: Electronics Computing Digital Circuit Bit Memory Input Clock Output Complement
Types of Flip-Flops: Electronics Computing Digital Circuit Bit Memory Input Clock Output Complement
Four types of flip-flops find common applicability in clocked sequential systems: these are called the T
("toggle") flip-flop, the S-R ("set-reset") flip-flop, the J-K flip-flop, and the D ("delay") flip-flop. The behavior
of the flip-flop is described by what is termed the characteristic equation, which derives the "next" (i.e.,
after the next clock pulse) output, <math>Q_{next}<math>, in terms of the input signal(s) and/or the
current output, <math>Q<math>.
The first electronic flip-flop was invented in 1919 by W. H. Eccles and F. W. Jordan. It was initially called
the Eccles-Jordan trigger circuit.
See also: monostable multivibrator, astable multivibrator.
Types of flip-flops
T flip-flop
If the T input is high (onion head), the T flip-flop changes state ("toggles") whenever the clock input is
strobed. If the T input is low, the flip-flop holds the previous value. This behavior is described by the
characteristic equation:
T Q Qnext
0 0 0
0 1 1
1 0 1
1 1 0
Left: A circuit symbol for a T-type flip-flop, where > is the clock input, T is the toggle input and Q is the
stored data output.
S-R flip-flop
The "set/reset" flip-flop sets (i.e., changes its output to logic 1, or retains it if it's already 1) if both the S
("set") input is 1 and the R ("reset") input is 0 when the clock is strobed. The flip-flop resets (i.e., changes
its output to logic 0, or retains it if it's already 0) if both the R ("reset") input is 1 and the S ("set") input is 0
when the clock is strobed. If both S and R are 0 when the clock is strobed, the output does not change. If,
however, both S and R are 1 when the clock is stobed, no particular behavior is guaranteed. This is often
written in the form of a "truth table":
S R Qnext
0 0 Hold
0 1 0
1 0 1
1 1 unstable
S R Q Qnext
0 0 0 0
0 0 1 1
0 1 X 0
1 0 X 1
1 1 X unstable
X means "don't care", or the output will be the same regardless of which state the X is in.
Left: A circuit symbol for a SR-type flip-flop, where > is the clock input, S is the set input, R is the reset
input, Q is the stored data output, and Q' is the inverse of Q.
It is the responsibility of the circuit designer to ensure that the S = R = 1 condition does not arise. Given
this externally imposed condition, one typically avoids writing a characteristic equation for the S-R flip-
flop. Various "master-slave" interconnections of S-R flip-flops are possible to achieve particular behaviors.
J-K flip-flop
The J-K flip-flop augments the behavior of the S-R flip-flop by interpreting the S = R = 1 condition as a
"flip" command. Specifically, the combination J = 1, K = 0 is a command to set the flip-flop; the
combination J = 0, K = 1 is a command to reset the flip-flop; and the combination J = K = 1 is a command
to toggle the flip-flop, i.e., change its output to the logical complement of its current value.
Left: A circuit symbol for a JK-type flip-flop, where > is the clock input, J and K are data inputs, Q is the
stored data output, and Q' is the inverse of Q.
J K Q Qnext
0 0 0 0
0 0 1 1
0 1 X 0
1 0 X 1
1 1 0 1
1 1 1 0
The J-K flip-flop was named after Jack Kilby, the man who invented integrated circuits in 1958.
D flip-flop
The D ("delay") flip-flop takes one input, which it conveys to the output when the clock is strobed.
Regardless of the current value of the output, it will assume a value 1 if D = 1 when the flip-flop is strobed
or a value 0 if D = 0 when the flip-flop is strobed. This flip-flop can be interpreted as a primitive delay
line or zero-order hold, since the data is posted at the output one clock cycle after it arrives at the input.
Left: A circuit symbol for a D-type flip-flop, where > is the clock input, D is the data input and Q is the
stored data output.
<math>Q_{next} = D \,<math>
D Q Qnext
0 X 0
1 X 1