Basic instructions (S7-300, S7-400)

Basic Instructions

cH
This section contains information on the following topics:

* LAD (87-300, 87-400)

° FBD (87-300, S7-400)
* STL (S7-300, S7-400)
* SCL (S7-300, S7-400)
° GRAPH (87-300, S7-400)
 LAD (S7-300, S7-400)

LAD

This section contains information on the following topics:

* Bit logic operations (S7-300, 87-400)

* Timer operations (S7-300, S7-400)
* Counter -300, $7-400
* Comparator operations (87-300, S7-400)
° Math functions (87-300, S7-400)
* Move operations (S7-300, S7-400)
* Conversion operations (S7-300, $7-400)
¢ Program control operations (S7-300, S7-400)
* Word logic operations (S7-300, S7-400)
* Shift and rotate (S7-300, S7-400)
* Additional instructions (S7-300, 7-400)
 Bit logic operations (S7-300, S7-400)

Bit logic operations

This section contains information on the following topics:

° —{/- Normally open contact (S7-300, S7-400)

° —{/;- Normally closed contact (S7-300, S7-400)
¢ —|NOTH-- Invert RLO (S7-300, $7-400)
° —()—: Assignment (87-300, 87-400)
° R)}—: Reset $7-300, 87.
° S)— Set ‘87-300, S7
* SR: Set/reset filp-flop (S7-300, S7-400)
° RS: Reset/eet flip-flop (S7-300, S7-400)
° —{P}-: Scan operand for positive signal edge (S7-300, S7-400)
° —jN[-: Scan operand for negative signal edge (S7-300, S7-400)
* P_TRIG:
Scan RLO for nal 7-300, S7-400)
* N_TRIG: Scan RLO for negative signal edge (S7-300, S7-400)
 ---| |---: Normally open contact (S7-300, S7-400)

—| }—: Normally open contact Ae

Description
The activation of the normally open contact depends on the signal state of the associated operand.
When the operand has signal state "1", the normally open contact closes and the signal state at the
output is set to the signl state of the input.

When the operand has signal state "0", the normally open contact is not activated and the signal state
at the output of the instruction is reset to "0".

Two or more normally open contacts are linked bit-by-bit by AND when connected in series. With a
series connection, power flows when all contacts are closed.

The normally open contacts are linked by OR when connected in parallel. With a parallel connection,
power flows when one of the contacts is closed.

Parameters
The following table shows the parameters of the instruction:

Parameters | Deciarafon | Data type Memory area Description

<Operand> | Input BOOL I, Q, M, D,L, T, c | QPerand

is queried.
whose signal state

Example
The following example shows how the instruction works:

Create a global data block with the following content for this purpose:

Name of the block:

Name
start1

start2
start3
startOut

Write the following program code:

“SLI_GDB_ “SLI_gDB_ “SLI_gDB_

NOContact". NOContact*. NOContact*.
start1 start2 startOut
JL JL fy ]
if 1 f YY 4 1

“SLI_gDB_
NOContact*.
start3
J 1
it

The "SLI_gDB_NOContact".startOut operand is set when one of the following conditions is fulfilled:

¢ The "SLI_gDB_NOContact".start1 and "SLI_gDB_NOContact".start2 operands have the signal state

mq"
 ---| |---: Normally open contact (S7-300, S7-400)

¢ The "SLI_gDB_NOContact".start3 operand has the signal state "1".

Overview
of the valid data types
LAD programming examples
Basic Informationon LAD
Memory areas (S7-300, S7-400)
 ---|/ |---: Normally closed contact (S7-300, S7-400)

—| / +: Normally closed contact Ae

Description
The activation of the normally closed contact depends on the signal state of the associated operand.
When the operand has signal state "1", the normally closed contact opens and the signal state at the
output of the instruction is reset to "0".

When the operand has signal state "0", the normally closed contact is not enabled and the signal state
of the input is transferred to the output.

Two or more normally closed contacts are linked bit-by-bit by AND when connected in series. With a
series connection, power flows when all contacts are closed.

The normally closed contacts are linked by OR when connected in parallel. With a parallel connection,
power flows when one of the contacts is closed.

Parameters
The following table shows the parameters of the instruction:

Parameters | Deciarafon | Data type Memory area Description

<Operand> | Input BOOL I, Q, M, D,L, T,c | QPerand

is queried.
whose signal state

Example
The following example shows how the instruction works:

“Tagin1* “Tagin_2” “TagOut”

1 1 C 4
“Tagin_3”
14

The "TagOut" operand is set when one of the following conditions is fulfilled:

© The operands "Tagin_1" and "TagIn_2" have signal state "1".

¢ The operand "TagIn_3" has the signal state "0".

Overview
of the valid data types
LAD programming examples
Basic Informationon LAD
Memory areas (S7-300, S7-400)
 —|NOTI-: Invert RLO (S7-300, $7-400)

—|NOTI-: Invert RLO Ae ?

Description
You use the "Invert RLO" instruction to invert the signal state of the result of logic operation (RLO). If
the signal state is "1" at the input of the instruction, the output of the instruction has signal state "0". If
the signal state is "0" at the input of the instruction, the output has the signal state "1".

Example
The following example shows how the instruction works:

“Tagin_1* "Tag Out*

1 {NOT} CH
“Tagin_2° “Tagin_3"
} | J |
lf 1 |

Operand "TagOut" is reset when one of the following conditions is fulfilled:

¢ The operand "TagIn_1" has the signal state "1".

© The signal state of the operands "TagIn_2" and "TagIn_3" is "1".

Overview
of the valid data types
LAD programming examples
Basic information on LAD
Memory areas (S7-300, S7-400)
 ---( )---: Assignment (S7-300, S7-400)

—()—: Assignment Ae

Description
You can use the "Assignment" instruction to set the bit of a specified operand. If the result of logic
operation (RLO) at the input of the coil has signal state "1", the specified operand is set to signal state
"1". If the signal state is "0" at the input of the coil, the bit of the specified operand is reset to "0".

The instruction does not influence the RLO. The RLO at the input of the coil is sent directly to the out-
put.

Parameters
The following table shows the parameters of the "Assignment" instruction:

Parameters | Deciarafion | Data type Memory area Description

<Operand> | Output BOOL ,Q,M, D,L Operand to which the RLO

is assigned.

Example
The following example shows how the instruction works:

"Tagin1* “Tagin_2* “Tag Out _1°

1| y | roy |
Vt if ed 1

"Tagin_3" "Tagin_4" “TagOut_2”

14 J | c J
I 1 \ 4 1

The "TagOut_1" operand is set when one of the following conditions is fulfilled:
© The operands "Tagin_1" and "TagIn_2" have signal state "1".

¢ The signal state of the operand "Tagin_3" is "0".

The "TagOut_2" operand is set when one of the following conditions is fulfilled:

* Operands "Tagin_1", "Tagin_2", and "TagIn_4" have signal state "1".

© The signal state of the "Tagln_3" operand is "0" and the signal state of the "TagIn_4" operand is
mq"

Overview
of the valid data types
LAD programming examples
Basic Information on LAD
Memory areas (S7-300, S7-400)
 --( R )--: Reset output (S7-300, S7-400)

—( R)-—: Reset output

Description
You can use the "Reset output" instruction to reset the signal state of a specified operand to "0".

The instruction is only executed if the result of logic operation (RLO) at the input of the coil is "1". If
power flows to the coil (RLO = "1"), the specified operand is reset to "0". If the RLO at the input of the
coil is "0" (no signal flow to the coil), the signal state of the specified operand remains unchanged.

Parameters
The following table shows the parameters of the "Reset output" instruction:

Parameters
| Declaration Data type Memory area Description
Operand that is reset when
<Operand> | Output BOOL |,Q,M, D, L, T,C
RLO ="1".

Example
The following example shows how the instruction works:

“Tagin_1* “Tagin_2* "Tag Out®

} | } | fp)
If 1] LR}
"Tagin_3*
|
I

Operand "TagOut" is reset when one of the following conditions is fulfilled:

© The operands "Tagin_1" and "TagIn_2" have signal state "1".

¢ The signal state of the operand "Tagin_3" is "0".

Overview
of the valid data types
LAD programming examples
Basic informationon LAD
Memory areas (S7-300, S7-400)
 --( S )--: Set output (S7-300, S7-400)

—( S )—: Set output

Description
You can use the "Set output" instruction to set the signal state of a specified operand to "1".

The instruction is only executed if the result of logic operation (RLO) at the input of the coil is "1". If
power flows to the coil (RLO = "1"), the specified operand is set to "1". If the RLO at the input of the
coil is "0" (no signal flow to the coil), the signal state of the specified operand remains unchanged.

Parameters
The following table shows the parameters of the "Set output" instruction:

Parameters
| Declaration Data type Memory area Description
Operand which is set with
<Operand> | Output BOOL 1,Q,M,D,L
RLO ="1".

Example
The following example shows how the instruction works:

“Tagin_1* “Tagin_2* "Tag Out"

} | } | Cen
If 1] 15}
"Tagin_3*
|
I

The "TagOut" operand is set when one of the following conditions is fulfilled:
© The operands "Tagin_1" and "TagIn_2" have signal state "1".

¢ The signal state of the operand "Tagin_3" is "0".

Overview
of the valid data types
LAD programming examples
Basic informationon LAD
Memory areas (S7-300, S7-400)

-10-
 SR: Set/reset flip-flop (S7-300, S7-400)

SR: Set/reset filp-flop Ae

Description
Use the instruction "Set/reset flip-flop" to set or reset the bit of the specified operand, depending on
the signal state of the inputs S and R71. If the signal state at input S is "1" and the input R71 is "0", the
specified operand is set to "1". If the signal state is "0" at input S and "1" at input R1, the specified
operand will be reset to "0".

Input R1 takes priority over input S. When the signal state is "1" on both inputs S and R1, the signal
state of the specified operand is reset to "0".

The instruction is not executed if the signal state at the two inputs S and R11 is "0". The signal state of
the operand then remains unchanged.

The current signal state of the operand is transferred to output Q and can be queried there.

Parameters
The following table shows the parameters of the "Set/reset flip-flop" instruction:

Parameters | Deciarafion | Data type Memory area Description

Ss Input BOOL 1,Q,M,D,L Enable setting
R1 Input BOOL 1, Q, M, D, L, T, C | Enable resetting
<Operand> InOut BOOL 1,Q,M,D,L Operand that is set or reset.
Q Output BOOL 1,Q,M,D,L Signal state of the operand

Example
The following example shows how the instruction works:

*“TagSR*
"Tagin_1* SR "Tag Out®
1 | S ah—t >
“Tagin_2*
1| RI

The operands "TagSR" and "TagOut" are set when the following conditions are fulfilled:
¢ The operand "TagIn_1" has the signal state "1".

¢ The operand "TagIn_2" has the signal state "0".

The operands "TagSR" and "TagOut" are reset when one of the following conditions is fulfilled:

© The operand "TagIn_1" has signal state "0" and the operand "TagIn_2" has signal state "1".

© The operands "Tagin_1" and "TagIn_2" have signal state "1".

Overviewof the valid data types

Address areas of the CPUs (S7-300, 87-400)
Master control relay (S7-800, S7-400)

-11-
 SR: Set/reset flip-flop (S7-300, S7-400)

—(MCR<): Open MCR ranges (S7-300, S7-400)

Basic information on LAD
Memory areas (S7-300, S7-400)

-12-
 RS: Reset/set flip-flop (S7-300, $7-400)

RS: Reset/set filp-flop

Description
You can use the "Reset/set flip-flop" instruction to reset or set the bit of a specified operand based on
the signal state of the inputs R and S1. If the signal state is "1" at input R and "0" at input S1, the
specified operand will be reset to "0". If the signal state is "0" at input R and "1" at input S1, the speci-
fied operand is set to "1".

Input S1 takes priority over input R. When the signal state is "1" at both inputs R and S1, the signal
state of the specified operand is set to "1".

The instruction is not executed if the signal state at the two inputs R and $1 is "0". The signal state of
the operand then remains unchanged.

The current signal state of the operand is transferred to output Q and can be queried there.

Parameters
The following table shows the parameters of the "Reset/set flip-flop" instruction:

Parameters | Deciarafon | Data type Memory area Description

R Input BOOL 1,Q,M,D,L Enable resetting
S1 Input BOOL |, Q, M, D, L, T, C | Enable setting
<Operand> InOut BOOL 1,Q,M,D,L Operand that is reset or set.
Q Output BOOL 1,Q,M,D,L Signal state of the operand

Example
The following example shows how the instruction works:

“Tag RS*
“Tagin_1* RS
L
R Q
“Tagin_2°
} | 31

The operands "TagRS" and "TagOut" are reset when the following conditions are fulfilled:
¢ The operand "TagIn_1" has the signal state "1".

¢ The operand "TagIn_2" has the signal state "0".

The operands "TagRS" and "TagOut" are set when one of the following conditions is fulfilled:

© The operand "TagIn_1" has signal state "0" and the operand "TagIn_2" has signal state "1".

© The operands "Tagin_1" and "TagIn_2" have signal state "1".

Overview
of the valid data types
Address areas of the CPUs (S7-300, 87-400)
Master control relay (S7-300, S7-400)
 RS: Reset/set flip-flop (S7-300, S7-400)

—(MCR<): Open MCR ranges (S7-300, S7-400)

Basic information on LAD
Memory areas (S7-300, S7-400)

-14-
 --|P|--: Scan operand for positive signal edge (S7-300, S7-400)

—|P|-: Scan operand for positive

signal edge Ae

Description
You can use the "Scan operand for positive signal edge" instruction to determine if there is a "0" to "1"
change in the signal state of a specified operand (<Operand1>). The instruction compares the current
signal state of <Operand1> with the signal state of the previous scan, which is saved in an edge
memory bit (<Operand2>). If the instruction detects a change in the result of logic operation (RLO)
from "0" to "1", there is a positive, rising edge.

The following figure shows the change in the signal state in case of a negative and a positive signal
edge:

Positive signal edge Negative signal edge

Signal
state f
1

0 - Timer

The positive signal edge is queried each time the instruction executes. When a positive signal edge is
detected, <Operand1> is set to signal state "1" for one program cycle. In all other cases, the operand
has the signal state "0".

Specify the operand to be queried (<Operand1>) in the operand placeholder above the instruction.
Specify the edge memory bit (<Operand2>) in the operand placeholder below the instruction.

Note
Modification of the address of the edge memory bit

The address of the edge memory bit must not be used more than once in the program, otherwise
the bit memory is overwritten. This step influences the edge evaluation and the result is therefore
no longer unique. The memory area of the edge memory bit has to be located in a DB (static area
for FB) or in the bit memory area.

Parameters
The following table shows the parameters of the "Scan operand for positive signal edge" instruction:

Parameters | Deciarafion | Data type Memory area Description

<Operand1> | Input BOOL 1, Q, M, D, L, T, C | Signal to be scanned
Edge memory bit in which
<Operand2> | InOut BOOL 1,Q,M,D,L the signal state of the previ-
ous query is saved.

Example
The following example shows how the instruction works:

-15-
 --|P|--: Scan operand for positive signal edge (S7-300, S7-400)

| “Tagin_1* “Tagin_2" “Tagin_3* “Tagin_4* “Tagin_5* “TagOut*

} | }| } | |P J | n- > J
T I | 1 | tT L 4 1
| "Tag_M*

Operand "TagOut" is set when the following conditions are fulfilled:

© The operands "Tagin_1", "Tagin_2", and "TagIn_3" have signal state "1".

¢ There is a rising edge at operand "TagIn_4". The signal state of the previous scan is stored in the
edge memory bit "Tag_M".
¢ The signal state of the operand "Tagin_5" is "1".

Overview
of the valid data types
LAD
Basic Information on LAD
Memory areas (S7-300, S7-400)

-16-
 --|N|--: Scan operand for negative signal edge (S7-300, S7-400)

—|IN-: Scan operand for negative signal edge Ae

Description
You can use the "Scan operand for negative signal edge" instruction to determine if there is a "1" to
"0" change in the signal state of a specified operand (<Operand1>). The instruction compares the cur-
rent signal state of <Operand1> with the signal state of the previous scan that is saved in an edge
memory bit <Operand2>. If the instruction detects a change in the result of logic operation (RLO) from
"1" to "0", there is a negative, falling edge.

The following figure shows the change in the signal state in case of a negative and a positive signal
edge:

Positive signal edge Negative signal edge

Signal
state f
1

0 - Timer

The negative signal edge is queried each time the instruction executes. When a negative signal edge
is detected, <Operand1> is set to signal state "1" for one program cycle. In all other cases, the oper-
and has the signal state "0".

Specify the operand to be queried (<Operand1>) in the operand placeholder above the instruction.
Specify the edge memory bit (<Operand2>) in the operand placeholder below the instruction.

Note
Modification of the address of the edge memory bit

The address of the edge memory bit must not be used more than once in the program, otherwise
the bit memory is overwritten. This step influences the edge evaluation and the result is therefore
no longer unique. The memory area of the edge memory bit has to be located in a DB (static area
for FB) or in the bit memory area.

Parameters
The following table shows the parameters of the "Scan operand for negative signal edge" instruction:

Parameters | Deciarafion | Data type Memory area Description

<Operand1> | Input BOOL 1, Q, M, D, L, T, C | Signal to be scanned
Edge memory bit in which
<Operand2> | InOut BOOL 1,Q,M,D,L the signal state of the previ-
ous query is saved.

Example
The following example shows how the instruction works:

-17-
 --|N|--: Scan operand for negative signal edge (S7-300, S7-400)

| “Tagin_1* “Tagin_2" “Tagin_3* “Tagin_4* “Tagin_5* “TagOut*

} | }| } | {Ni J | n- > J
T I | 1 | tT L 4 1
| "Tag_M*

Operand "TagOut" is set when the following conditions are fulfilled:

© The operands "Tagin_1", "Tagin_2", and "TagIn_3" have signal state "1".

¢ There is a negative signal edge at operand "TagIn_4". The signal state of the previous scan is stor-
ed in the edge memory bit "Tag_M".
¢ The signal state of the operand "Tagin_5" is "1".

Overview
of the valid data types
LAD
Basic Information on LAD
Memory areas (S7-300, S7-400)

- 18-
 P_TRIG: Scan RLO for positive signal edge (S7-300, S7-400)

P_TRIG: Scan RLO for positive signal edge

Description
Use the "Scan RLO for positive signal edge" instruction to query a "0" to "1" change in the signal state
of the result of logic operation (RLO). The instruction compares the current signal state of the RLO
with the signal state of the previous query, which is saved in an edge memory bit (<operand>). If the
instruction detects a change in the RLO from "0" to "1", there is a positive signal edge.

The positive signal edge is queried each time the instruction executes. As soon as a positive single
edge is detected, the output Q of the instruction returns the signal state "1" for the length of a program
cycle. In all other cases, the output returns the signal state "0".

Note
Modification of the address of the edge memory bit

The address of the edge memory bit must not be used more than once in the program, otherwise
the bit memory is overwritten. This step influences the edge evaluation and the result is therefore
no longer unique. The memory area of the edge memory bit has to be located in a DB (static area
for FB) or in the bit memory area.

Parameters
The following table shows the parameters of the instruction "Scan RLO for positive signal edge":

Parameters | Deciarafion | Data type Memory area Description

CLK Input BOOL 1,Q,M,D,L Current RLO
Edge memory bit in which
<Operand> InOut BOOL M, D the RLO of the previous
query is saved.
Q Output BOOL 1,Q,M,D,L Result of edge evaluation

Example
The following example shows how the instruction works:

"Tagin_1* “Tagin_2° P_TRIG CASI

| | } | CLK QKH—L ump #4
is

“Tag_M*"

"Tagin_3"
1 |
Tt

The RLO of the previous query is saved in the edge memory bit "Tag_M". If a "0" to "1" change is
detected in the signal state of the RLO, the program jumps to jump label CAS1.

Overview
of the valid data types
LAD
Basic information
on LAD

-19-
 P_TRIG: Scan RLO for positive signal edge (S7-300, S7-400)

Memory areas (S7-300, S7-400)

- 20-