INVITED

PAPER

Science and Engineering

Beyond Moore’s Law
This paper describes Moore’s law for CMOS technology, examines its limits, and
considers some of the possible future pathways for both CMOS and successor
technologies with objective of encouraging some radical rethinking for the
development of possible future information processing technologies.
By Ralph K. Cavin, III, Life Fellow IEEE , Paolo Lugli, Fellow IEEE , and Victor V. Zhirnov

ABSTRACT | In this paper, the historical effects and benefits of energy-efficient information processor relative to the perfor-
Moore’s law for semiconductor technologies are reviewed, and mance of an end-of-scaling silicon processor of the same
it is offered that the rapid learning curve obtained to the bene- volume. The paper concludes by pointing out some of the
fit of society by feature size scaling might be continued in sev- crucial differences between E.coli information processing and
eral different ways. The problem is that as features approach conventional approaches with the hope technologies can be
the range of a few nanometers, electron-based devices depart invented using the hints offered by biosystems.
radically from the ideal switch and, in fact, become very leaky
in the OFF state. It is argued that there are some short-term KEYWORDS | Beyond CMOS; biological computation; logic;
solutions involving more highly parallel manufacturing, in- memory; more than Moore; scaling limits
creased design efficiency, and lower cost packaging technolo-
gies that could continue the steep learning curve for cost
reductions that have historically been achieved via Moore’s I . INTRODUCTION
Law scaling. Another alternative might be to increase chip One of the remarkable technological achievements of the
functionality by integrating devices that offer broadened chip last 50 years is the integrated circuit. Built upon previous
functionality including, e.g., sensors, energy sources, oscilla- decades of research in materials and solid state electronics,
tors, etc. A third alternative would be to invent an entirely new and beginning with the pioneering work of Jack Kilby and
information processing state variable based on different Robert Noyce, the capabilities of integrated circuits have
physics, using electron spin, magnetic dipoles, photons, etc., grown at an exponential rate. Codified as Moore’s law,
to improve the performance and reduce switching energy for integrated circuit technology has had and continues to
devices whose smallest features are on the order of a few have a transformative impact on society. This paper endea-
nanometers. Each of these alternatives is being actively ex- vors to describe Moore’s law for complementary metal–
plored and an overview of each strategy and progress to date is oxide–semiconductor (CMOS) technology, examine its
given in the paper. A final alternative offered in the paper is to limits, conider some of the alternative future pathways for
learn from information processing examples in nature, specif- CMOS, and discuss some of the recent proposals for suc-
ically in living systems. An E.coli cell of about one cubic micro- cessor CMOS technologies. In the spirit of the editorial
meter volume is shown to be an incredibly powerful and guidance for this issue, an analysis of the living cell as an
information processor is offered and estimates of its per-
formance are given. For comparison, an equal volume
CMOS cell is postulated, equipped with extremely scaled
technologies, and performance estimates are generated.
Manuscript received January 25, 2012; accepted February 15, 2012. Date of publication Indications are that the living cell is architected and ope-
April 18, 2012; date of current version May 10, 2012.
R. K. Cavin, III and V. V. Zhirnov are with Semiconductor Research Corporation,
rates in such a way that it is extraordinarily energy efficient
Research Triangle Park, NC 27709 USA (e-mail: [email protected]; relative to the performance of the comparison CMOS cell.
[email protected]).
P. Lugli is with Lehrstuhl für Nanoelektronik, Technische Universität München,
This analysis is offered with the hope that it will encourage
D-80333 Munich, Germany (e-mail: [email protected]). radical rethinking of possible future information process-
Digital Object Identifier: 10.1109/JPROC.2012.2190155 ing technologies.

1720 Proceedings of the IEEE | Vol. 100, May 13th, 2012 0018-9219/$31.00 Ó 2012 IEEE
 Cavin et al.: Science and Engineering Beyond Moore’s Law

II. BENEFITS OF SCALING: MOORE’S

LAW FOR S E MICONDUCTORS
In 1965, Gordon Moore [1] observed that the number of
transistors on a chip could be expected to double annually
for at least ten years. At different time points in the ensuing
decades, it has appeared that doubling time has varied from
18 months to three years. Overall, however, the chip tran-
sistor count has continued to increase, and conversely, the
size of each transistor has decreased, at an amazing rate,
and Gordon Moore’s postulate became known as Moore’s
law. Fig. 1 is a plot of transistor count for a variety of
microprocessor chips (listed in Table 1) versus time. Moore
Fig. 1. The number of transistors per microprocessor chip versus was indeed prescient for the transistor count, on average,
time, showing introduction of new enabling technologies. has doubled approximately every two years.

Table 1 Microprocessor Data Used to Create Fig. 1

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Cavin et al.: Science and Engineering Beyond Moore’s Law

As feature sizes have decreased, the real density of binary switches, is the maximum binary throughput (BIT),
transistors has correspondingly increased supporting that is, the maximum number of on-chip binary transitions
either more functionality for a given chip size or the per unit time. It is the product of the number of devices M
reduction in chip size to obtain a given level of with the clock frequency of the microprocessor f
functionality. The latter benefit enabled the fabrication
of more chips per wafer and thus continued cost reduction
trends. Cost reductions have also resulted from increased  ¼ Mf : (1)
wafer sizes, again allowing the production of more chips/
wafer. Also the individual transistor switching time and
energy decrease with feature size scaling. (Note that  is an aggregate indicator of technology
Minimum feature sizes circa 1980 were on the order of capability.)
3 m, while today they are about 32 nm (a 100-fold de- The computational performance of microprocessors 
crease), giving four orders of magnitude increase in device is often measured in (millions) of instructions per second
density. Supply voltages in this time frame have decreased (IPSs) that can be executed against a standard set of
from five to one volt in an effort to reduce power con- benchmarks. There is a strong correlation between system
sumption. capability for IPS ðÞ and the binary throughput , as
It has been the history of the semiconductor industry shown in Fig. 5, and to a good approximation
that, as obstacles are encountered, scientific and engineer-
ing solutions are developed to continue the cadence more
 ¼ f ðÞ ¼ kp : (2)
or less as indicated by Moore’s law. In the 1990s, it became
evident that scaling was encountering a number of barriers
including increasing interconnect power consumption, For the selected class of microprocessors, k  0:1 and
transistors that were consuming increased power in their p  0:64 with a high degree of accuracy (the determina-
off state, etc. This led to the search for new material tion coefficient R2 ¼ 0:98). This strong correlation sug-
systems and associated processes to sustain the growth in gests a possible fundamental law behind the empirical
transistor counts that was providing increasing per- observation.
formance and functionality for the electronics and other Fig. 2 also shows an estimated capability of the human
industries. An example of technology innovation was the brain in M–B metrics. While it is difficult to quantify the
introduction of copper interconnects to replace alumi- brain operations, there have been several attempts to esti-
num-based interconnects on chip [2], [3]. Initially, this mate computational performance of the brain. In [10], an
was viewed as a difficult task since copper diffuses in estimate of equivalent binary transitions was made from
silicon (Si) and can be detrimental to metal–oxide– the analysis of the control function of brain: the equiv-
semiconductor field-effect transistor (MOSFET) perfor- alent number of binary transitions to support language,
mance. However, barrier systems were developed so that deliberate movements, information-controlled functions
the higher conductivity of copper could be exploited. As of the organs, hormone system, etc., resulting in an
another example, the decrease in the gate oxide thickness Beffective[ binary throughput of the brain   1019 b/s. An
to a few nanometers was leading to increased gate leakage
currents and higher off state power consumption. Re-
search led to the incorporation of new gate materials with
a higher dielectric constant (e.g., hafnium oxide) so that
drive capacitance could be maintained and tunneling re-
duced [4], [5]. Due to the incompatibility of the high-k
dielectric with the traditional polisilicon gate, a new metal
gate technology was introduced [5]. In order to increase
channel mobility, new strained Si channel technologies
were developed [6]. Looking ahead, the pace of innovation
continues with, for example, research to determine if
higher channel mobility might be achieved by introducing
compound III-V channel materials into the Si MOSFET [7].
Even the structure of the MOSFET is under renewed
consideration, e.g., the different variations of the multiple-
gate FET devices [8], e.g., Trigate, are now being intro-
duced into production. These innovations have continued
to provide increases in integrated circuit performance [9].
One indicator of the ultimate performance of an infor- Fig. 2. Benchmark capability  (instructions per second) as a
mation processor, realized as an interconnected system of function of  (bits per second).

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 Cavin et al.: Science and Engineering Beyond Moore’s Law

Fig. 3. Transistor cost as a function of the cumulative number of transistors shipped [12].

estimate of the number of equivalent IPSs was made in [11] percent every time total cumulative volume doubles. This
from the analysis of brain image processing capability is applicable across a wide range of products but the strik-
resulting in   1014 IPSs. It is clear that the brain is not ing difference for semiconductors is that the rate of de-
on the microprocessor trajectory in Fig. 2, giving rise to the crease in cost per unit for semiconductors has occurred at a
hope that there may exist alternate technologies and com- much higher rate than for many other industries. Figs. 3
puting architectures offering higher performance (at much and 4 (courtesy of W. Rhynes of Mentor Graphics [12])
lower levels of energy consumption). In the following sec- illustrate the learning curve for transistors and for
tions, some of such technologies, complementary and/or microprocessors.
alternative to CMOS circuitry, will be discussed in detail. Note from Fig. 3 that the per-transistor cost decreases
Without customers for the increased volume of tran- by approximately a factor of two for every doubling of
sistors and chips, there would be little incentive to continue transistor production. To put this in a temporal perspec-
to drive scaling at an exponential pace. The $300 billion tive, the average compound annual rate of cost reduction
dollar semiconductor industry (circa 2011) provides for transistors is on the order of 35% per year. In Fig. 3, the
essential components for the much larger electronics de- cost per millions of instructions per second (MIPS) for
vices and systems industries as well as automotive, enter- personal computers has shown an even more dramatic rate
tainment, medical device, and other technology-based of cost decreaseVa reduction on the order of a factor of
industries. One effect of the rapidly increasing capability of nine in cost-per-MIP every two years.
integrated circuit systems is to support rapid growth in It is interesting to contemplate whether integrated cir-
functionality and this has translated into a feature-driven cuits will be able to sustain these steep learning curves
market. That is, electronics customers, as a rule, replace indefinitely. There exist formidable technical and eco-
their older electronic systems well before they are no nomic challenges to doing so and some of these are con-
longer useful because the newer devices offer a compelling sidered in this paper. A good example is the search for new
increase in capability. This contrasts with many other in- lithographic tools that can provide efficient and cost-
dustries where purchases are driven by the need for re- effective patterning for features less than 10 nm in size.
placement at the end of the useful life of the product. The There is a focus today on extreme ultraviolet lithography
net effect is that electronic products have been part of a to replace optical lithography but this technology is not
closed cycle where increasing markets have supported the yet production ready. At the same time, research in di-
capability of industry to invest in the continuous reduction rected self-assembly [13], [14] continues to make good
of semiconductor costs via the introduction of new progress and offers the hope for some relief for optical
technologies. methods. Moreover, there are clear and fundamental limits
Moore’s law is actually connected to a more funda- for the scaling of electron-based devices [15]. In spite of
mental premise, known as the learning curve, which re- directed research programs that seek to provide alterna-
lates decreases in the price of product to corresponding tives to the MOSFET switch for logic applications where
increases in the volume of production of that product. The other nonelectron representations for information might
learning curve for semiconductors has shown much less be used, such as the Nanoelectronics Research Initiative
volatility over the years than Moore’s law. The learning (www.src.org/program/nri), no compelling replacement
curve states that the cost per unit decreases by a fixed options have yet been identified [16], [17]. It appears that

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Cavin et al.: Science and Engineering Beyond Moore’s Law

Fig. 4. Personal computer cost (inflation adjusted) per millions of instructions per second versus cumulative units shipped [12].

for many of the proposed alternative devices, their unique energy efficiency and performance of information proces-
properties might be utilized to advantage to achieve a sing systems, the introduction of 3-D packaging technol-
special function when integrated with CMOS technologies. ogies, etc. All of these opportunities will require advances
On the other hand, continuing research in alternative in science and engineering, but this is nature of the
memory technologies has resulted in the identification of semiconductor enterprise.
potential replacements offering the potential for smaller
sizes that could meet information processing performance
specifications. Indeed, progress in memory technology I II . BMORE MOORE[: E XT RE ME LY
may foretell changes in memory architectures for infor- SCALED CMOS LOGIC AND
mation processing and could support an increased focus MEMORY DEVICES
on data-centric as opposed to logic-centric processing. In order to assess the performance characteristics for
Nevertheless, what will happen when we reach scaling extremely scaled transistors and memory cells, it is in-
limits for CMOS-like technologies? Can the learning curve structive to consider the generic structure and the physical
shown above be continued at the same rates as have been layout of a transistor (binary switch) and a nonvolatile
sustained to date? memory cell. The approach taken is to utilize simple
Continuation of the semiconductor learning curve physical and geometrical models to make evident the
beyond the end of scaling rests on several factors. 1) It is essential performance characteristics of FETs at the limits
essential to sustain an ever-broadening applications space of scaling.
for integrated circuits since this provides the revenue base
for advances in semiconductor technology. 2) As scaling of A. Electronic Switch (FET)
features becomes more difficult, it will be necessary for An energy barrier is used to control electron transport
advances in design, architectures, 3-D packaging, etc., to in FETs. The barrier can be formed, e.g., by doping that
play an increased role in cost reduction. 3) Parallel creates built-in charges in the barrier (channel) region, as
fabrication to decrease manufacturing costs per unit tran- shown in Fig. 5(a). The height and the width of the barrier
sistor needs to be emphasized, e.g., by increasing wafer determine essential operational characteristics of transis-
size [18]. In this paper, possibilities for continuing the tors such as device size, switching speed, operating
semiconductor virtuous cycle are explored. The perspective voltage, off leakage current, etc. In order to control the
is that the future for semiconductor technologies is very barrier height, a gate electrode is coupled to the barrier
bright, even as we face scaling limits, primarily because the region, separated by a thin layer of gate insulator, e.g.,
opportunities for integration of new functionalities with SiO2 or HfO2 . When a voltage is applied to the gate, an
CMOS is at an early point and the possibilities for ex- electric field is created between the gate and the barrier
panding applications incorporating new on-chip physical region. This electric field changes the barrier height, thus
domains (e.g., mechanical, thermal, chemical, optical) of allowing electrons to pass through the channel. The width
operation is just beginning. Examples include the integra- of the barrier is defined by device fabrication, and is
tion of sensors that respond to a wide range of stimuli, new represented by geometrical characteristics such as channel
architectures that can reason from data leading to inte- length Lch or gate length Lg . In the following, it will be
grated systems that can assess and respond, inclusion of assumed Lch  Lg  F, where F is the critical feature size.
devices operating in new physical domains to increase the In order to retain gate control with scaling, it is necessary

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 Cavin et al.: Science and Engineering Beyond Moore’s Law

Fig. 5. Semiconductor FET: (a) materials system; (b) generic floorplan; (c) scaling limits; and (d) connected binary switches.

to decrease the gate insulator thickness Tox proportionally for circuit/system physical-level explorations of different
to the decrease of the channel length. For an optimized scenarios of extreme scaling.1 A detailed treatment of the
FET structure, a rule of thumb suggests Tox =Lch  1=30 tiling framework can be found in [20], and two
[19]. The device platform for modern microelectronics is important examples will be considered in Section III-C.
known as MOSFET. One fundamental issue that limits physical scaling of
The barrier representation of a binary switch (e.g., MOSFETs, and therefore the minimum tile size F, is
FET) shown in Fig. 5(a) also suggests a generic topology quantum mechanical tunneling, which dramatically in-
for the ultimately scaled device [Fig. 5(b)]. The 2-D floor creases the off leakage current, as depicted in Fig. 5(c). A
plan of a smallest possible binary switch is a 3F  F simple estimate of the tunneling limit can be made using
rectangle consisting of three square Btiles[ of the same the Heisenberg relation [see numerical insert in Fig. 5(c)].
size F (representing the source, channel, and drain re- For typical parameters for Si FET, this estimate results in a
gions of the MOSFET). Further, it can be assumed that minimum channel length of 4 nm. More detailed cal-
the associated insulator and metal layout elements are culations yield similar findingsVit is argued in a number
also composed of tiles of minimum size F. Finally, the of studies that tunneling off-state leakage becomes
metal interconnects, which connect individual devices in overwhelming for Lch ¼ 4–7 nm, and this is sometimes
more complex logic circuits, can also be represented as a
combination of the square tiles, as shown in Fig. 5(b). It
1
is straightforward to show from both topology and phy- A practical device is somewhat larger than the ideal shown in Fig. 5(b);
sics considerations that in the limiting case, it is useful e.g., wraparound gates, larger area of source and drain to minimize contact
resistance, increased gate width to increase on current, etc. However, the
to consider the size of the interconnect tile as equal to idealized representation shown in Fig. 5(b) will be used in this paper to cast
the device tile F. The tiling framework is a useful tool MOSFET technology most favorably for packing density.

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Cavin et al.: Science and Engineering Beyond Moore’s Law

Table 2 ITRS Performance Projections for Extremely Scaled High-Performance FETs (2007 ITRS Edition [22])

cited as the Bultimate[ FET [21]. These assessments are barriers of sufficient height Eb to retain charge (as shown
consistent with the International Technology Roadmap for in Fig. 6). The properties of the barrier, i.e., barrier
Semiconductors (ITRS) [22], which projected the minimal height Eb and width a, determine the retention time of a
physical gate length in high-performance logic FET to be in memory cell.
the range from 4.5 nm (2007 ITRS) to 5.9 nm (2011 ITRS). In order to obtain a nonvolatile memory cell, suffi-
Note that the result for the smallest channel length in ciently high barriers must be created to retain the charge
Fig. 5(c) depends on the mass of the information-bearing for a long period of time. As it was argued in [23], for
particles, e.g., the effective mass of electrons in Si. Heavier > 10 y retention, the barrier height Eb must be more than
particle mass could, in principle, allow for further scaling. 1.7 eV. High barriers are formed by using layers of
One approach to deal with the severe leakage in a insulator (I), which surround a metallic storage node (M).
scaled transistor is to develop families of FETs, optimized Such an I–M–I structure forms the storage node in the
for specific applications. For example, if highest switching floating gate cell, the basic element of flash memory. The
speed is the goal, the smallest channel length and therefore barrier height Eb is a material-specific property [see a table
thinnest gate dielectrics are required. As a result, the insert in Fig. 6(a)]. As shown in Fig. 6(a), the stored
leakage can be relatively high, which still could be tole- electrons can Bleak[ from the storage node either over the
rated in some applications. On the other hand, in other barrier (if the barrier is not sufficiently high), resulting in
applications, such as, e.g., mobile devices, standby power leakage current Iob , or by tunneling through the barrier (if
minimization is mandatory. This can be achieved by in- the barrier is not sufficiently wide), thus resulting in
creasing Lg and Tox , and thus giving up some performance leakage current IT . For long retention (e.g., > 10 y) the
and device density. A set of parameters projected for ex- theoretical barrier width must be > 5 nm for all known
tremely scaled transistors developed by ITRS is shown in dielectric materials (typically > 7 nm in practical devices).
Tables 2 and 3 for high-performance and low standby The corresponding practical minimum size of the floating
power transistors, respectively. gate cell is 10 nm [23].
The requirement for a large barrier insulator height
B. Nonvolatile Electronic Memory and thickness also results in a fundamentally high operat-
In memory cells that store electron charge, such as ing voltage, both for write and read. For example, during
flash, dynamic random-access memory (DRAM), or static the write operation, electrons are injected into the storage
random-access memory (SRAM), two distinguishable node, and this requires operation in the Fowler–Nordheim
states 0 and 1 are created by the presence (e.g., state 0) (F-N) tunneling regime for faster injection. The condition
or absence (e.g., state 1) of electrons in a specific location for F-N tunneling is eVb > Eb , i.e., the potential difference
(the charge storage node). In order to prevent losses of the across the barrier between the storage node and the ex-
stored charge, the storage node is defined by energy ternal contact must be larger than the barrier height. Since

Table 3 ITRS Performance Projections for Extremely Scaled Low Standby Power FETs (2007 ITRS Edition [22])

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 Cavin et al.: Science and Engineering Beyond Moore’s Law

Fig. 6. The two-energy-barrier model for a memory cell: (a) the principle of storage and sensing; (b) WRITE operation; and (c) READ operation.

the storage node is isolated from the external contacts by channel of the FET by external commands, similarly to the
two barriers (i.e., it is floating), this requires the total logic FET. However, differently from a conventional
write voltage applied to the opposite external contacts of transistor, the degree of accessibility of the channel from
the memory cell to be more than the doubled barrier the control gate is rather limited. First, the control gate is
height: eVwrite > 2Eb , as shown in Fig. 6(b). (A symmetric physically far from the channel, since the minimal thick-
barrier structure is assumed.) Thus, the floating gate ness of both top and bottom dielectric layers is large due to
structure inherently requires high voltage for the write the retention requirements, and the minimal thickness of
operation: for example, for SiO2 barriers, V writemin > 6 V, the insulator stack is > 10 nm. Second, the control gate
and the write voltage should be > 10–15 V for faster affects the channel only indirectly, as the floating gate lies
( ms-s) operations. between the control gate and the channel. Therefore, a
The presence or absence of stored electric charge in the large read voltage must be applied to the control gate for
storage can be detected by an electrometer type device reliable on/off transitions of the sense transistor. The
[shown schematically in Fig. 6(a)]. The sensing device maximum read voltage is however limited by the condi-
should be in immediate proximity to the storage node. A tion for the F-N tunneling discussed above, and for the
FET is commonly used as a sensor, and a complete nonvo- read operation, it is eVread G 2Eb , for example, for SiO2
latile floating gate memory cell consists of a stack of me- barriers, Vreadmax G 6 V for a nondisturbing read. In prac-
tallic and insulating layers on the top of a FET channel, as tice, a typical read voltage is 4.5–5 V.
shown in Fig. 6(b). The sensing FET is controlled by the
voltage Vread applied to an external electrode, the control C. 2-D and 3-D Layouts of Logic and Memory Circuits
gate. The source-drain current of the FET depends on the Binary switches in logic circuits will be assumed to be
presence or absence of charge in the floating gate, thus the isolated, thus allowing for arbitrary wiring. From the tiling
memory state can be sensed by measuring the FET current. consideration, the most compact layout for an array of
The control gate allows modulation of the semiconductor isolated devices (assuming at least one tile between each

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Cavin et al.: Science and Engineering Beyond Moore’s Law

Fig. 7. Representation for maximum device density for (a) logic and (b) memory circuits.

device for insulation) results in maximum packing density tiles k (devices and interconnects), the average switching
of binary switches on a 2-D plane [Fig. 7(a)] energy per bit is

1 1
nL ¼ : (3a) Ebit ðkÞ ¼ k  Esw : (4a)
8F2 2

In the following, (3a) will be assumed as the device density

(The factor 1/2 originates from the assumed 50% activity
in the logic layout. Next, interconnects need to be added.
factor.)
To estimate the minimum number of interconnect tiles per
Now assuming the average interconnect length hLi ¼
device, assume that in a three-terminal device, for each
6F, the total number of tiles per device k ¼ 3 þ 6 ¼ 9,
terminal, at least one Bcontacting[ interconnect tile (three
then from (4a), we obtain
total) is needed and one Bconnecting[ interconnect tile
(three total) is needed. This results in six interconnect tiles
per binary switch. Including the contacting tiles would
9
result in eight interconnect tiles per switch. Thus, the Ebit ¼ Esw : (4b)
average interconnect length obtained from the tiling con- 2
sideration is hLi ¼ ð6  8ÞF. This estimate is consistent
with the wire-length distribution analysis in practical
The total dynamic energy consumption by a circuit of N
microprocessors [24]. For this densest arrangement, at
binary switches will be NEbit . Correspondingly, the energy
least three additional layers of interconnects would be
dissipated by transistors themselves (without intercon-
needed.
nects) is NEsw . It follows from (4b) that the ratio of tran-
Memory cells are typically organized in regular
sistor energy use to the total energy consumed by a logic
X–Y arrays, thus only simple regular wiring is needed.
circuit constitute about 2/9 or 22% of the total dynamic
Regularly wired memory cells in an array can be connected
energy consumption, which is consistent with the energy
in series, thereby enabling higher packing density, as shown
breakdown analysis in practical microprocessor chips [26].
in Fig. 7(b)
For memory arrays, due to the regular wiring, in many
instances, the properties of interconnecting array wires
1 determine the operational characteristics of the memory
nM ¼ : (3b) system. A given cell in an array is selected (e.g., for read
4F2
operation) by applying appropriate signals to both inter-
connect lines, thus charging them. The relatively large
[The serial connection of Fig. 7(b) represents a nand operating voltage of flash results in rather large line charg-
array, the typical array architecture of mainstream flash ing energy  Cline V 2 , where Cline is the line capacitance.
memory products.] For F ¼ 10 nm and a 128  128 array, the line capacitance
The tiling framework provides a methodology to esti- is 1014 F [27]. If there is a random access read with
mate the average energy per bit in an arbitrary logic circuit. Vread  5 V, there results an energy per line access (and
As was argued in [25], at the limits of scaling, the energy therefore for random access operation) of 1013 J, or
per tile is nearly the same for both devices and intercon- 1015 J/bit for serial access. For write operation with
nect tiles and approximately equals to the device switching Vwrite  15 V, the write energy is 1012 J/line. (In prac-
energy (Esw in Tables 2 and 3). For the total number of tical flash memory devices, the read energy is of the

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 Cavin et al.: Science and Engineering Beyond Moore’s Law

Table 4 BUltimate CMOS[: Limiting Density and Energetics

order of 1013 –1011 J/bit read and 109 –1010 J/bit (MDMs), micrometer size mirror realized on top of a
write [28], [29].) CMOS circuit which controls their 3-D movement, are
A model for a tightly integrated 3-D system is useful as already used in projectors and TV sets [34]. A more am-
a conceptual tool in estimating ultimate performance of bitious path will be the integration not just of different
CMOS systems. The limits for the 3-D integration can be functions within one material system, but also the integ-
conceived using the methodology for stacking of 3-D tiles. ration of different technologies, as, for instance, Si and
For example, in logic circuits, the thickness of the FET III-V semiconductors. Several examples can be provided to
layer is 3 F (including vertical extension due to gate and indicate how relevant such integration would be. As one
1/2 interlayer insulation from each side) and the inter- looks at the fact that interconnection delay is already the
connect layer thickness 2 F (with insulation). As was bottleneck for the speed of an integrated circuit, it is clear
mentioned above, for this densest arrangement at least that optical links would provide an obvious solution.
three additional layers of interconnects would be needed. Nonlinear optical passive components can be fabricated in
Thus, the resulting thickness of one logic circuit layer is Si technology, which could provide guiding, routing, and
9 F. In memory circuits, the thickness of one layer can be other optical functionality directly on chip. Light sources
6 F, which includes a layer of array grid interconnects and though are still a domain of compound semiconductors
interlayer insulation. Taking into account (3a) and (3b) like GaAs and InP. Thus, the integration of light-emitting
obtain limiting 3-D density for logic to be 1=72F3 and for diodes (LEDs) or lasers realized with such materials is
memory 1=24F3 . Table 4 summarizes the essential para- necessary. Lattice mismatch of the semiconductors, ther-
meters of CMOS logic and memory devices in the limits of mal mismatch of the processes, and fabrication compat-
scaling. A question that arises is whether alternative tech- ibility pose serious challenges to integration, even at a
nologies exist that could offer further improvements beyond hybrid level. Beside optics and radio frequency (RF), the
CMOS. Some examples are considered in Section V. integration with CMOS of other functions such as sensing,
biological screening, or information storage can be of great
interest. A review of some Bmore than Moore[ devices and
IV. NOT JUST MOORE a brief discussion of the open challenges are provided
(MORE T HAN MOORE) below. Such a concept is nicely summarized in the scheme
of a possible future chip shown in Fig. 8, which would be
The possibility to extend the functionality of CMOS
based on CMOS technology but would incorporate several
circuits by integration with other technologies has been
other functionalities coming from alternative technologies
referred to as Bmore than Moore[ [30]. An example that
[35]. The integration can be achieved directly on chip,
has already encountered an extraordinary market success
requiring that the new technologies be fully compatible
in the last few years is provided by CMOS imagers which
with CMOS. This is referred to as a Bsystem-on-chip[
can be found in any cell phone camera [31]. There Si pho-
approach. Alternatively, a 3-D integration is possible,
todetectors or phototransistors constitute the optical sen-
where several chips, possibly realized with different
sors, which are monolithically integrated on a CMOS chip
technologies are stacked on top of each other (Bsystem
[32]. Another multifunctional combination within Si tech-
on package[).
nology is provided by the integration of microelectrome-
chanical system (MEMS) devices with CMOS [33]. In this
case, hybrid integration is already available at a prototype A. RF Technologies
level; monolithic integration will follow once issues re- Wireless communication has witnessed an unprece-
lated to thermal mismatch between the two processes are dented (and maybe unexpected) development in recent
solved. Along the same line, digital micromirror devices years. It is therefore more and more important to

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Cavin et al.: Science and Engineering Beyond Moore’s Law

The signal produced by this class of devices is very small

and impedance matching can be a problem. One alterna-
tive is provided by movable gate transistors, which combine
the advantage of a vibrating micro/nanostructure with the
large output signal provided by the transistor drain current.
Highly scaled versions of the in-plane resonant gate tran-
sistors with a front-end process have been reported based
on silicon-on-nothing technology [42]. However, the sub-
100-nm gaps and 400-nm-thick single crystal resonators
suffered from the poor electron mobility. Nevertheless, full
CMOS compatibility is guaranteed. An alternative struc-
ture has been proposed, the vibrating-body FET, where a
combined effect due to modulation of the carrier density
and of the piezoresistance in the channel is achieved.
Fig. 8. Illustration of the integration of many technologies on a Si nanowires are the ideal channel material due to their
single CMOS substrate [35]. pronounced piezoelectric properties.
Another appealing candidate for an RF oscillator that is
fully CMOS compatible is provided by spin transfer torque
effectively bridge the two worlds of digital information effects [43]. In nanosized magnetic multilayer structures,
processing and of RF transmission. If one looks at a mo- metallic spin valves and magnetic tunnel junctions can
dern cellular phone, a variety of specialized modules are drive uniform precession of the free-layer magnetization
present which perform specific tasks. Ideally, one unique under an external input (provided by a magnetic field or an
chip should incorporate all necessary functionalities. RF electrical current). This precession produces voltage re-
functions are provided by antennas, filters, switches, and sponses that make those magnetic multilayers high-
converters, which in turn use RF transistors, mechanical frequency spin torque oscillators. Oscillation frequencies
filters, and other active or passive devices. Many new ranging from several hundred megahertz to tens of giga-
materials and concepts have been introduced recently, hertz have been demonstrated [44]. The challenges that
which might have an important impact on RF applications need to be overcome for practical applications include
in the future. In addition, they might help in the integ- 1) reaching output powers in the milliwatt range, 2) im-
ration with CMOS technology. proving the spectral purity of the oscillator, and 3) realiz-
MEMS technology has reached maturity and commer- ing auto-oscillating structures, thus eliminating the need
cial success in recent years thanks to its application in for external magnetic fields.
electronic components for automotive and mobile com- RF mixers are an important building block of an RF
munication [36]. One of its appealing features is the full front end. One candidate technology is the resonant tun-
compatibility with CMOS technology. By scaling MEMS to neling diode [45]. Another candidate that should have
the nanoscale, further RF functionalities could be reached provided low-noise solutions at RF, the single-electron
(e.g., nanoelectromechanical system (NEMS) resonators). transistor, could only demonstrate interesting perfor-
Traditionally, some RF components such as the quartz mance at low temperature [46]. In principle, carbon-based
crystals used in the reference oscillator are kept off-chip. devices possess the necessary nonlinearities in electrical
In fact, integration leads to very poor quality factors and characteristics to demodulate an AM signal [47], [48]. The
temperature instability, mainly due to the poor perfor- main challenge consists, once again, in the integration of
mance of the integrated inductors and capacitors. The best such technologies with CMOS [49].
opportunities for miniaturization and integration of refe- It could be mentioned here that an alternative tech-
rence oscillators are provided by capacitively transduced nology for RF applications (at least up to few megahertz)
microelectromechanical and nanoelectromechanical has been developed in recent years, based on polymeric
(MEM/NEM) resonators, which have reached in recent devices and circuits. The advantages of such components
years operating frequencies of several gigahertz. Scaling to are the low cost of their fabrication, the independence on
nanometer dimensions poses several problems connected, the type of substrate used, and the possibility of large area
e.g., to fluctuations, friction, and dissipation mechanisms manufacturing. Full organic radio-frequency identification
at the nanoscale. Nanostructures have been used and de- (RFID) circuits including electronics and antennas have
monstrated in NEMS such as platinum [37] or Si [38] been realized. Such circuits include more than 1000 or-
nanowires and carbon nanotubes (CNTs) [39], [40]. They ganic thin film transistors (OTFTs) and can operate up to
are appealing due to their high stiffness, low density, 13.5 MHz [50]. Organic electronics [51] will not compete
defect-free structure, and ultrasmall cross section. Re- in speed with CMOS-based solutions, since the low mobi-
cently, graphene material has also attracted considerable lity of organic semiconductors (typically below 1 cm2 /VS)
attention for these applications [41]. limits the maximum achievable frequency. Nevertheless,

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 Cavin et al.: Science and Engineering Beyond Moore’s Law

applications such as active matrix backbones for OLED the other hand, the difficulty to integrate III-V and II-VI
display, ultralow-cost RFID systems, or biocompatible/ materials with CMOS. A different approach uses a dif-
disposable sensors can be envisaged. ferent concept. Rather than converting the optical signal
into an electrical one via creation of electron-hole pairs
B. Optical Technologies following photon absorption, one can use the change is
As mentioned earlier, interconnections have become some property of the sensing material, for instance, re-
one of the limiting factors of the speed of integrated cir- sistance or temperature, under illumination. The most
cuits. Moving to optical interconnect would greatly en- successful component of this type is the bolometer, which
hance the available bandwidth, reduce the heat dissipation can be structured into arrays and driven by CMOS cir-
on-chip, and assure immunity from electrical interference. cuitry. A thorough review of infrared detector technologies
Si or Si-compatible optical components have long been can be found in [60]. Infrared uncooled cameras based on
demonstrated [52], [53]. Attempts to obtain efficient microbolometers integrated on CMOS are available on the
Si-based light sources have instead not been very suc- market. They provide acceptable performance but they are
cessful. Si-based micro/nanostructured devices have been quite expensive.
introduced [54]. Considerable interest has been attracted Photodetectors can be realized also using conductive
by the demonstration of a Si laser based on the Raman polymers [61]. The advantages of such materials are:
effect [55]. Currently, only optical pumping has been de- 1) the possibility to realize devices, circuits, and systems
monstrated. For any realistic application, electrical pump- on large area substrates, which in turn can be of different
ing has to be achieved. The field of passive components nature (e.g., glass, plastic, textile, and paper); and 2) the
(waveguides, filters, connectors) has witnessed considera- reduced fabrication cost since the material can be pro-
ble advances with the discovery of photonic bandgap cessed from solutions. Thus, cheap preparation techniques
structures [56]. Nanotechnology has allowed researchers such as ink jet printing, spin coating, and spray casting can
to realize 3-D, 2-D, or 1-D periodic structures with tail- be used [62]. The component that has received great at-
ored spectral transmission properties. By inserting defects tention not only in the research field but also on the
into an otherwise perfectly symmetric lattice, it is also market is the organic light-emitting diode (OLED) [63]. In
possible to deflect a light beam over distances of a few fact, OLED displays have been introduced in several cel-
nanometers. Thus, an unconventional way to guide and lular and smartphones. This is the first time that an organic
deflect light on a chip can be fabricated with unprece- device, based on conductive polymers, has entered a large
dented properties [57]. Furthermore, by exploiting the volume market. Besides OLEDs, other electronic and op-
properties of surface plasmons in quantum dots structures, toelectronic organic components have been demonstrated
the absorption and/or transmission properties of materials [64]. Organic solar cells based on blends of conducting
and surfaces can be engineered [58]. Being based on Si or polymers have also been fabricated with roll-to-roll pro-
on Si-compatible materials, such optical components can cesses, displaying a conversion efficiency of few percent
be easily integrated with CMOS. [65]. Due to the flexibility in fabrication methods, organic
Another optical component which is fully based on Si photodetectors (OPDs) can be integrated onto CMOS. In-
technology is the CMOS imager, which has witnessed verted structures for OPDs that can directly be fabricated
considerable commercial success in recent years mostly on CMOS as end-of-the-line process have been demon-
due to their use in camera phones. Keys to this success strated [66]. CMOS imagers with OPD active pixels would
have been features inherent to CMOS technology, such as guarantee a much larger fill factor with respect to Si pho-
size, weight, power consumption, mechanical robustness, todetectors. In connection to IR imagers, either low gap
and price. Two challenges remain on the agenda: the ex- polymers [67] or hybrid system combining polymers with
tension of the detectable range, especially to infrared, and quantum dots [68] have displayed room temperature sen-
scaling of the optical components to keep pace with the sitivity in this wavelength range. Their use for hybrid
CMOS miniaturization. CMOS imagers would allow the realization of IR imagers
Typically, CMOS imagers employ a Si photodetector or at a cost comparable to conventional CMOS imagers.
phototransistor as optical sensor. Spectrally, the sensitivity Concerning pixel reduction, current technology allows
of such components is limited to the visible range because for 2.2-m pixel pitch, and demonstrations exist for
of the Si energy gap. In order to move into the infrared and 1.7 m. Pixel size reduction in active pixel sensors is cru-
far infrared range, which is very attractive for a variety of cial since it leads to higher numbers of pixels at almost
applications in the fields of security, screening, and envi- constant price. A further reduction is challenging, both
ronmental monitoring, a possibility is to use small gap due to limited optical capabilities and to signal noise. A
semiconductor materials. Photodetectors and imagers large part of today’s imager cost is taken by lenses, whose
using, e.g., InAs or CdTe have been demonstrated and complexity is bound to increase with miniaturization. In
even commercialized [59]. The main problems with such order to reverse such a trend: 1) innovative strategies
technologies are on the one side the need to cool down the exploiting coherent effects at the nanoscale have to be
detector in order to have an acceptable noise level and, on found, for instance, exploiting plasmonics and photonic

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Cavin et al.: Science and Engineering Beyond Moore’s Law

bandgaps; and 2) image correction via on-chip computa- used as semitransparent electrodes, sensors, transistors,
tion will have to be implemented, fully exploiting the and in general, for flexible and stretchable electronics
capability of the CMOS chip. [75]–[79]. Such solution-based technology is compatible
with CMOS.
C. Sensing Technologies In many applications, sensors should operate in a stan-
The computational power and the maturity of CMOS dalone mode at extremely low levels of energy consump-
technology can be of great advantage in the sensor field, tion. In some cases, operational energy could be harvested
where environmental parameters have to be determined from the sensor environment, e.g., in the form of solar,
and corresponding actions undertaken. Since the signals to thermal, electromagnetic, or mechanical energy. Cur-
be sensed are mostly nonelectrical in nature, appropriate rently, there is continuing progress in miniature energy
transducer elements are needed. Examples of external phy- harvesting devices to support autonomous operations of
sical stimuli are mechanical (pressure, motion, vibration), sensor units [80], [81]. Understanding of maximum per-
electrical (voltage), thermal (temperature difference), elec- formance potential of such energy harvesting devices,
tromagnetic (light), chemical (presence of a particular given practical size constraints, requires further studies. In
chemical species), etc. In response to the external stimulus, parallel with the need to scavenge energy from the envi-
the transducer generates an electrical signal that is further ronment, there will be an increasing need to store it in
processed by accompanying circuitry and is used to provide batteries or capacitors.
actionable information to the end user. Sensor metrics Nanostructure and nanodevices, as well as novel mate-
include sensitivity, selectivity, and repeatability. Nanotech- rials, can be decisive in the search for efficient power
nology can provide adequate solutions in the form of novel solution of future electronic systems. Some very promising
materials and structures with high sensitivity and into the Si results have already been obtained. Among them, the so-
mainframe technology. Two kinds of transducers are called third-generation solar cells promise enhanced effi-
currently receiving considerable attention for sensing: 1-D ciency and/or reduced costs by using quantum nanostruc-
structures (e.g., nanowires and nanotubes) [69], [70] and tures or organic semiconductors [82]. CNT or graphene
NEM devices [71]. sheets provide ideal solutions for compact, long-lasting
Sensors may potentially be everywhere, providing in- miniature super capacitors [83]. Nanowires possess opti-
strumentation for the state of the environment, security, cal, electrical, and theormelectric properties which can be
supporting regulation of different processes, etc. It is useful in a number of energy-related applications [84]. In
necessary in many applications for the sensors to com- most cases, the technologies and devices just mentioned
municate their data to a central information collection/ can be used as standalone technologies or in hybrid sys-
decision-making authority. This gives rise to the need to tems integrated on CMOS.
establish sensor communication networks that can be
used, for instance, to create autonomic systems that are
user-transparent, self-healing, self-configuring, self- V. BEYOND MOORE
optimizing, and self-protecting analogous to many of the
functions of the human nervous systems such as control of A. Terminology and Context
heart rate, breathing, etc. Of course, sensor networks in There is an international effort underway to identify an
general represent an important field of endeavor where alternative to the CMOS transistor, which within one-to-
issues of configuration, optimum communication proto- two decades will no longer submit to feature size and
cols, and information carrying capacity are essential voltage scaling [22]. Many of these alternative devices
concerns [72]. operate using state variables other than charge and some of
One example of the many application areas for sensors them may offer functionalities beyond those of a binary
is in fields related to biology. The state of the living system device that could be useful for more complex operations.
can be monitored by sensing different physical parameters, Indeed, the choice of state variable for a device not only
e.g., chemical, electrical, optical, thermal, magnetic, etc. has ramifications for device performance but echoes up the
There are indications that 1-D structures, such as semicon- abstraction hierarchy to impact device-to-device commu-
ductor nanowires and CNTs, may offer superior sensitivity nication, achievable chip complexity, and ultimately sys-
to planar devices and allow for picomolar detection of tem performance capability. The dependency is depicted
biomolecules [73]. An additional attractive feature of 1-D in Fig. 9. The symbols in Fig. 9 have the following
structures is that they might lend themselves to minimally meaning:
invasive probes to contact or even puncture the cellular Lsw the smallest device (switch) feature, e.g., gate
membrane, or even to be ingested into the cell itself. This length in CMOS;
suggests the intriguing possibility of electrically monitor- tsw device switching time, i.e., time required to
ing processes inside the cell [74]. Recently, it has been change state;
shown that nanowires and nanotubes can also be used not Esw the energy required to change the device state
individually but rather as a conductive film, which can be (switching energy);

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 Cavin et al.: Science and Engineering Beyond Moore’s Law

refer to as variables. For example, physical entities might

include electrons, atoms, ferromagnetic (FM) domains,
etc. Associated with these physical entities are properties
such as charge, spin, magnetic dipoles, etc.; the same
entity might be used in two different devices, each exploit-
ing a different property of that entity. In the following,
Bproperty[ is used as a synonym for the word Bvariable[ to
agree with conventional usage.
Now each device has input, state, and output variables:
for example, the FET utilizes the electron as the physical
entity, and the properties of charge are used for the input,
output, and state variables. On the other hand, the
spinFET utilizes electrons but it is controlled by electron
spin, its state is defined by spin, and its output is trans-
Fig. 9. State variable and different facets of information
ferred as charge.
processing system. Table 5 provides a tabulation of physical entities and
the properties employed by several of the emerging de-
vices. Also, an expanded taxonomy employed by the ITRS
Ncar the number of information carriers required to Emerging Research Devices Chapter [22] is shown in
transmit state to downstream devices; Fig. 10.
M the device count, a measure of system
complexity; B. Novel Device Examples
 binary information throughput, a measure of
technological capability; 1) III-V, Ge Channel, and Nanowire FET: It is well known
 instructions per second, a measure of informa- that III-V compound semiconductors are ideal candidates
tion processor capability. for high-speed devices (several tens of gigahertz), due
The state of a binary switch is that minimum set of to their excellent bulk electron (e.g. 33 000 cm2 V1 s1
physical variables that fully describe the system and its for InAs and 80 000 cm2 V1 s1 for InSb) and hole
response to a given set of control variables. In character- (1250 cm2 V1 s1 for InSb and 850 cm2 V1 s1 for GaSb)
izing the functionality of various candidate devices, it is mobilities. The integration of GaAs and InP on Si sub-
important to draw a distinction between the physical enti- strates has been long sought but never achieved. Advances
ties used in their realization and the properties of these in epitaxial techniques have recently offered new perspec-
entities utilized in the operation of the device, which we tives on this challenge. In particular, Sb-based compound

Table 5 Taxonomy for Candidate Information Processing Devices

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Cavin et al.: Science and Engineering Beyond Moore’s Law

solid (VLS) growth mechanism has been used to de-

monstrate a variety of nanowires, including core-shell and
core-multishell heterostructures [90], [91]. Hetero-
geneous composite nanowire structures have been con-
figured in both core-shell and longitudinally segmented
configurations using group IV and compound materials.
The longitudinally segmented configurations are grown
epitaxially so that the material interfaces are perpendicular
to the axis of the nanowire. This allows substantial lattice
mismatches without significant defects. Vertical transis-
tors have been fabricated in this manner using Si, InAs,
and ZnO, with quite good characteristics [92]–[94]. The
small lateral dimension of the nanowires allows their di-
rect growth on lattice-mismatched substrates without the
typical problems of dislocations and defects encountered
in films. Thus, for instance, InAs of very good morpho-
Fig. 10. ITRS taxonomy for information processing logical quality has been grown directly on Si. Circuit and
nanotechnologies [22]. system functionality of nanowire devices has been demon-
strated, including individual CMOS logic gates and other
prototype circuit elements [95], [96]. Still a lot of work is
semiconductors are seen as realistic CMOS channel needed to minimize parasitic components and achieve the
replacement materials due to the high mobilities for both high frequencies which have been predicted.
electrons and holes [85], [86]. A further appealing system One of the crucial parameters controlling the power
is provided by InAs, which can be grown in the form of dissipation of CMOS devices is the subthreshold swing. In
nanowires directly on Si substrates with excellent material conventional MOSFETs, the thermal injection of carriers
quality [87]. The major challenges include the need for from the source to the channel sets a room temperature
high-quality, high-k gate dielectrics (if MOSFETs are going limit value of 60 mV/dec.
to be used), damage-free low-resistivity junctions, and Tunnel FETs based on a gated p-i-n junction are ex-
heterointegration on a very large-scale integration (VLSI)- pected to display an abrupt Ion =Ioff transition, thus lower-
compatible Si substrates. Similarly to III-V semiconductors, ing the subthreshold swing below the intrinsic MOSFET
germanium (Ge) is also a potential channel replacement limit [97]. Such improvement is intrinsically connected to
material because of its excellent bulk electron mobility of the quantum mechanical band-to-band tunneling process
3900 cm2 V1 s1 , almost three times higher than in bulk Si. [98], which reacts sharply to variation of the gate voltage.
Unfortunately, the poor quality of the Ge/dielectric has High-performance tunnel FETs have been explored using
resulted in much lower mobilities in fabricated transistors low bandgap materials like Ge [99], SiGe [100], or based
[88]. Strain engineering of Ge n-channel MOSFETs has on Si nanowires [101] and CNTs [102]. A major challenge
also been studied as a performance booster technology and is the integration of such materials and structures on ad-
its effectiveness has been demonstrated at a small strain vanced Si platforms [103].
level. An open issue is whether the low electron saturation A completely different type of switch can be
velocity in Ge will limit the short channel performance achieved exploiting the mechanical displacement of a
of n-channel Ge MOSFETs relative to Si n-channel solid beam controlled electrostatically to create a con-
MOSFETs. In conclusion, III-V compound semiconductor ducting path between two electrodes [104]. Such micro/
and Ge FETs are considered viable candidates to extend nanoelectromechanical (M/NEM) switch has two major
CMOS to the end of the Roadmap. advantages with respect to MOSFETs: negligible leakage
Nanowire FETs are structures in which the con- and negligible subthreshold swing. Thus, standby energy
ventional planar MOSFET channel is replaced with a dissipation as well as dynamic energy consumption can be
semiconducting nanowire. Such nanowires have been drastically reduced. The most recent developments suggest
demonstrated with diameters as small as 0.5 nm. They may that M/NEM switches are attractive for ultralow-power
be composed of a wide variety of materials, including digital logic applications. In addition, it is expected that
Si, Ge, various III-V compound semiconductors (GaN, the energy performance as well as the functional densities
AlN, InN, GaP, InP, GaAs, InAs), II-VI materials (CdSe, can largely improve with scaling. M/NEM switches can be
ZnSe, CdS, ZnS), as well as semiconducting oxides fabricated by top-down approaches using conventional
(In2 O3 , ZnO, TiO2 ) [89]. Nanowires can exhibit quantum lithography techniques on Si, reaching actuation gaps as
confinement behavior, i.e., 1-D conduction, that can lead small as 15 nm [105]. Alternatively, bottom-up approaches
to the reduction of short channel effects and other limi- employing CNTs [106] or Si nanowires [107] have been
tations to the scaling of planar MOSFETs. Vapor–liquid– followed. In all cases, the leakage was virtually zero. The

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 Cavin et al.: Science and Engineering Beyond Moore’s Law

main weakness is switching speed, as the beam requires strated, in excess of 200 GHz [115]. In order to achieve
around 1 ns to move from the off position to the on better performances, the quality of the source and drain
position. A further challenge for M/NEM switches is the contacts have to be improved, especially in the top gate
control of the surface forces and the reliability of the configuration. Graphene FETs were first based on exfo-
contacts. liated graphene to form a transistor channel, which offers
the highest mobility, but is hardly manufacturable [116].
2) Carbon Electronics: The previous century has been the Recently, epitaxial graphene on SiC substrates and chemical
Silicon Century. The pervasion of electronic and optoelec- vapor deposition (CVD)-grown graphene on, e.g., copper
tronic devices in whole sectors of the society has been made foils, have been obtained [117], [118]. Back-gated graphene
possible mostly due to the success of CMOS technology FETs with SiO2 dielectric were typically shown to have room
(along the line of Moore’s law). The new century might be temperature field-effect mobilities up to around 10 000 cm2 /
the Carbon Century. Diamond has very interesting semi- Vs [119]. Suspended graphene or graphene sheet on flat and
conducting properties, for instance, great heat and charge inert substrate such as boron nitride can reach mobilities
conductivity. Unfortunately, it is very difficult to obtain above 100 000 cm2 /Vs at room temperature [120], [121]. In
diamond in crystalline form at wafer level. Twenty years top gate devices, lower mobilities are found, possibly because
ago, CNTs were discovered. Some of their attributes make of a degradation of the channel properties when the gate
them very appealing in view of the miniaturization of elec- dielectric is deposited [122]. Due to the peculiar band struc-
tronic components. Despite a huge research effort, CNTs ture of graphene, electron and hole mobilities are similar. It
have not yet found a real application in nano and opto- also displays no energy gap, at least for extended single
electronics. Part of the problem is the difficulty to control sheets. One crucial consequence are bipolar transport
the exact morphology (which in turn determines the CNT characteristics, which imply very small Ion =Ioff ratios. This
electronic properties) in a reliable and reproducible way. is of course a major limitation for digital applications. Several
Recently, applications for a CNT network have emerged methods to open a bandgap have been proposed, as, for
which make such system competitive with polymer mate- instance, through the use of graphene nanoribbons [123].
rials for large area, low-cost electronics, and optoelectron-
ics. A new carbon-made material has now appeared on the 3) Memristors: Recently, interest on hysteretic devices
scene, receiving a great deal of attention. Graphene, a 2-D has risen in the context of nonvolatile memories. Such
hexagonal grid of carbon atoms, has unique electronic, devices, named memristors, were pioneered in the work of
electrical, optoelectronic, and mechanical properties. It is Chua in the 1970s [124]. There, he indicated the memristor
therefore an appealing candidate for a variety of compo- as the missing element, in addition to inductors, resistors,
nents like, e.g., transistors, sensors, electrodes, lasers. Al- and capacitors, needed for a coherent description of elec-
though it is too early to forecast the market impact of tronic circuits. Much later, other groups rediscovered the
graphene, the academic and industrial community as well definition in connection to nonlinear elements embedded
the funding agencies are betting strongly on that novel in a crossbar architecture [125].
nanomaterial. In the following, we will briefly discuss some One possible memristor structure can be based on a
of the important achievements for carbon-based devices polymeric film sandwiched between two metal electrodes
and outline the main challenges. [126], [127]. As pointed out earlier in connection to poly-
CNT FETs are attractive because of the high mobility of meric devices, the main motivation for using such material
charge carriers, the intrinsically small dimensions, and the is the low fabrication cost. On the other hand, scaling has
possibility of minimizing short channel effects via all- not been widely discussed. Although polymeric resistive
around gate geometry. In the past two years, significant memory arrays have been demonstrated, including a 3-D
advances have been made in fabricating and characterizing stack of three active layers, the memory operation mecha-
CNT FETs [108], [109]. For instance, transistors with nisms are still unclear [128]. Some research suggests that
15-nm channel length displayed no short channel effects the changes in resistance could be due to intrinsic mole-
and a transconductance of 40 S for a single channel [110]. cular mechanisms, charge trapping, or redox/ionic me-
Frequencies as high as 15 GHz have been reached [111]. chanisms [129].
Nevertheless, major challenges remain, in particular con- Another type of memristic devices is the so-called
cerning the ability to control 1) bandgap energy and nano- Batomic switch,[ basically an electrochemical switch based
tube chirality with sufficient precision for industrial on the diffusion of metal cations and their reduction/
applications; 2) the positioning of the nanotubes in re- oxidation processes to form/dissolve a metallic conductive
quired locations and directions; 3) the deposition of a gate path [130]. The metal atoms are introduced into the ionic
dielectric; and 4) the formation of low-resistance electrical conductive materials from a reversible electrode. The ato-
contacts. mic switch was initially developed as a two-terminal
Thanks to the extremely high electron mobilities, gra- device using sulfide materials that were embedded in a
phene is an ideal material for RF transistors [112]–[114]. crossbar architecture with scalability down to 20 nm [131].
Very high values of cutoff frequency have been demon- Later, an atomic switch using fully CMOS compatible

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Cavin et al.: Science and Engineering Beyond Moore’s Law

materials was developed to enable the formation of back-to-back configuration for bipolar memory cells.
these devices in the metal layers of CMOS devices. This Alternatively, a selector exhibiting resistive switching be-
configuration resulted in the development of new type havior could be used. That is, the selector works on the
of programmable logic device [132]. Three-terminal same principle as the restore element, the main difference
atomic switches characterized by high Ion =Ioff ratio, low being that it can be volatile. One possible device is based
on-resistance, nonvolatility, and low-power consumption on a metal–insulator transition and exhibits a high resis-
have also been demonstrated [133]. Several operating tance for voltage below a given value. As an example, a
mechanisms have been proposed, including gate-con- VO2 -based device has been demonstrated as a select device
trolled formation and annihilation of a metal filament, for NiOx resistive random access memory (RRAM) element
and gate-controlled nucleation of a metal cluster, but no [140]. The main challenge for switch-type select devices is
complete understanding of the process currently exists. to identify the right material and the switching mechanism
Switching speed, cyclic endurance, uniformities of the to achieve the required reliability, drive current density,
switching bias voltage, and resistances both for the on-state and Ion =Ioff ratio.
and the off-state should be improved for general usage as a In addition to memories, it has been suggested that
logic device [134]. logic gates can also be built using memristors [141]. Fur-
In a variety of materials, ion migration combined with a thermore, neuromorphic architectures based on memris-
redox process can cause a change in resistance of a metal– tive crossbars have been investigated [142], [143].
insultor–metal structure [135]. For instance, for silver
electrode, Ag+ cations can drift through the insulator in 4) Molecular Electronics: One approach to beyond CMOS
the presence of an applied voltage, forming a highly con- electronics is based on the use of single conductive mole-
ductive filament connecting the metal electrodes resulting cules [144], [145]. Due to their intrinsically small size and
in the on-state of the cell. Reversing the applied voltage, the possibility to use self-assembling techniques, single
an electrochemical dissolution of these filaments takes molecules could be an alternative to Si nanostructures for
place, resetting the system into the high-resistance nonvolatile memories, diodes, or switches [146], [147]. In
off-state [136]. In the case of transition metal oxides, such fact, when properly functionalized, single molecules can
as TiO2 , the motion of oxygen vacancies is responsible for display nonlinear electrical characteristics and, in some
the change in the cell resistance. In a third class of cases, hysteresis [148]. In a molecular memory, data are
materials, a unipolar thermochemical mechanism leads to stored by applying an external voltage that causes a tran-
a stoichiometry change due to a current-induced increase sition of the molecule into one of two possible conduction
of the temperature. In some cases, a formation process is states. Data are read by measuring resistance changes in the
required before the bistable switching can be started. Since molecular cell. The concept emphasizes extreme scaling; in
the conduction is often of filamentary nature, memories principle, one bit of information can be stored in the space
based on this bistable switching process can be scaled to of a single molecule, namely, few nanometers. Computing
very small feature sizes. The switching speed is limited by with molecules as circuit building blocks is an exciting
the ion transport, typically rather slow. Thus, the distance concept with several desirable advantages over conven-
between the electrodes has to be limited to a few nanome- tional circuit elements. Because of their small size, very
ters. Although the microscopic nature of the switching dense circuits could be built and bottom-up self-assembly
process has yet to be understood in detail, recent experi- of molecules in complex structures could be applied. How-
mental demonstrations of scalability, retention, and endu- ever, major challenges still exist. First, the very nature of
rance are encouraging [137]. the molecular conduction and molecular switching has not
From an architectural point of view, memristive de- been fully understood. The role of the metallic leads is not
vices could be coupled with two-terminal select devices in clear and parasitic effects due to the environment could
order to build passive memory arrays (crossbars) [138]. appear which might determine the transport characteristics
The general requirements for such two-terminal switches of a molecular device. In any case, prototypical molecular
are sufficient on-currents at proper bias to support read memories have been built, which show remarkable en-
and write operations and sufficient on/off ratio to enable durance and reproducibility [149], [150]. At an architec-
selection even in the absence of a transistor. These speci- tural level, both molecular quantum cellular automata
fications are quite challenging and severely limit the maxi- (QCA) and crossbar structures have been investigated
mum size of a crossbar array [139]. Currently, two [151], [152].
approaches to integrating a two-terminal select device
with storage node are being pursued. The first approach 5) Magnetic Components: Electronic systems combining
integrates the external select device in series with the computing and storage capabilities could be realized based
storage element in a multilayer stack. The second approach on magnetic structures. Magnetic random-access memo-
uses a storage element with inherent nonlinear properties. ries (RAMs) [153] are a mature technology with some
The simplest realizations of two-terminal memory select products already on the market. The control of single
devices use semiconductor diode structures, possibly in a spins of either atoms or electrons has also been proven a

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 Cavin et al.: Science and Engineering Beyond Moore’s Law

promising new way to achieve electronic functionalities. NML lines and gates with CMOS-compatible clock struc-
The possibility to build logic circuits with magnetic tures have been reported [162]. Furthermore, NML ap-
nanostructures has been demonstrated at a prototypical pears to be scalable to the ultimate limit of using individual
level. There, a novel architecture based on field coupling atomic spins. Whether a circuit ultimately exhibits reliable
[called magnetic quantum cellular automaton (MQCA)] is and deterministic switching is a function of how it is
adopted [154], where the spatial arrangement of coupled clockedVand requires additional study.
nanomagnets can be used to build logic functions and Field coupling via magnetic interaction belongs to a
complete circuits. In the following, we will briefly describe novel class of architectures called MQCA [154]. A cellular
some of the suggested magnetic components. automaton (CA) is an array of cells, organized in a regular
In spin transistors, the current is controlled by the grid [163], [164]. Each cell can be in one of a finite number
magnetization configuration of the ferromagnetic electro- of states from a predefined state set, which is usually a set
des or by the spin direction of the carriers [155]. Thus, of integers. The state of each cell is updated according to
feature could lead to low-power circuit architectures that transition rules, which determine the cell’s next state from
are inaccessible to ordinary CMOS circuits. Recently, an its current state as well as from the states of the neigh-
experimental demonstration of spin FET was reported boring cells. The functionality of each cell is defined by the
[156], [157]. Oscillatory spin signals controlled by a gate transition rules of the CA. Typically, each cell encodes one
voltage were observed implying spin precession of spin- bit into a single electrical or magnetic dipole. The cell-to-
polarized carriers in the channel. However, the origin of cell communication is guaranteed by magnetic interaction
the observed spin signals is not yet clear. Spin MOSFETs between neighboring dipoles. A QCA architecture has
using ferromagnetic electrodes have also been proposed some appealing features: its regular structure has the po-
but not yet demonstrated [158]. tential for manufacturing methods that can deliver huge
Spin wave devices (SWDs) are a type of magnetic logic numbers of cells in a cost-effective way. Top-down as well
exploiting collective spin oscillation (spin waves) for in- as bottom-up manufacturing methods can be used. Fur-
formation transmission and processing [159]. The spin thermore, the design of a cell can be relatively simple as
waves are generated in a magnetoelectric cell which is compared to that of a microprocessor unit, so design ef-
driven by external voltage pulses. Such a cell also acts as forts are greatly reduced. Wires are completely unneces-
detector and storage element. The information is encoded sary since the cells can interact with their neighboring
into the initial phase of the spin wave. Spin waves propa- cells through some physical mechanism. Thus, inter-
gate through spin wave buses and interfere at the points of connection delay and power dissipation through inter-
junction constructively or destructively, depending on the connects are avoided. Clearly, QCAs also have some
relative phase. The result of computation can be stored in drawbacks and challenges. For instance, input and output
the magnetization or converted into the voltage pulse by of data to cells with nanometer dimensions may be diffi-
the output magnetoelectric cells. The primary expected cult. Clocking the cells requires additional wires or external
advantages of SWDs are: 1) the ability to utilize phase in inputs. Speed might be a limiting factor. Room temperature
addition to amplitude for building logic devices with a operation has to be assured for any realistic application, which,
fewer number of elements than required for transistor- up to now, has only been demonstrated for magnetic QCAs.
based approach; 2) nonvolatile magnetic logic circuits; and A concept that combines spin-controlled devices and
3) parallel data processing on multiple frequencies at the nanomagnetic logic has been proposed recently [165]. In
same device structure by exploiting each frequency as a the all-spin logic (ASL), the information stored in the
distinct information channel. Prototypes operating at room nanomagnets propagates as spin current in spin coherent
temperature and at gigahertz frequency have been channels. Recent advancements have shown that a com-
demonstrated. bination of spintronics and magnetics can provide a low-
In nanomagnetic devices, binary information can be power alternative to charge-based information processing.
encoded in the magnetization state. Fringing field inter- Key elements of ASL are the spin injection into metals and
actions between neighboring nanomagnets can be used to semiconductors from magnetic contacts and the switching
perform Boolean logic operations [160]. A functionally of magnets by injected spins. Major challenges to be over-
complete logic set based on nanomagnets has been dem- come are room temperature operation and a further im-
onstrated [161]. In addition, nanomagnetic devices have provement of the energy-delay product. It should be
nonlinear response characteristics, the output of one de- mentioned that ASL could also provide a natural imple-
vice is capable of driving another, power amplification (or mentation for biomimetic systems with architectures that
gain) is present, and dataflow directionality can be ob- are radically different from the standard von Neumann
tained. Nanomagnet logic (NML) has therefore a great architecture.
potential for low-power applications. A clock modulates
the energy barriers between magnetization states in an 6) New Architectures for Beyond CMOS: Research on
NML circuit. Recently, experimental demonstrations of architectures that exploit the properties of the devices de-
individual island switching as well as the reevaluation of scribed in this section is at an early stage of development.

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Cavin et al.: Science and Engineering Beyond Moore’s Law

Many different possibilities exist, two of which are CA and cell and the term in carbo is used to refer to the E.coli cell
neural-inspired networks. CA typically use a form of near- in the following.
est neighbor communication and they can be shown to be
universal. Theoretical and experimental quantification of B. Bio-Cell Information Processor
CA performance relative to the von Neumann architecture Are there example information processing systems now
remains an open question [164]. Neural networks take a extant from which inspiration might be drawn for new
different approach by seeking to emulate structures in the technologies? It has been recognized that individual cells,
brain and these have been studied for decades. So far it the smallest units of living matter, possess amazing com-
appears that neural networks can offer advantages for spe- putational capabilities, and are indeed the smallest known
cial classes of problems. There are indications that mem- information processors [168]. As is argued in a number of
ristors in crossbar arrays may be able to emulate neural studies, individual living cells, such as bacteria, have the
behavior. In the next section, a perspective on architectures attributes of a Turing machine, capable of a general-
for computation inspired by the operation of living cells is purpose computation [168]–[170]. It can also be viewed as
provided. universal constructor in the sense of von Neumann because
it manufactures copies of itself, thus a computer making
computers [169].
VI . BIOLOGICAL COMPUTATION: Just how does the cell go about implementing its
LI VI NG CELL EXAMPLE information processing system? The cell is a very complex
organism and any brief attempt to describe its operations is
A. A Basis for Quantitative Comparisons bound to be inadequate. A vastly oversimplified view of
The reliance of CMOS and many other proposed infor- cellular processes is presented below.
mation technologies on electron charge to support their A cell’s primary functions can be described as follows.
operations places them at risk as features scale downward 1) Reproduction: making cells by acquiring/
into the few nanometer regime. Not only does tunneling processing information from internal storage
become detrimental to performance, but also smaller fea- (DNA) and utilizing the structural building
tures usually make the devices more susceptible to minute, blocks and energy from the nutrients.
manufacturing-induced, variations in material structure The reproduction task requires a massive infor-
and composition. It has been said that the creativity of mation processing effort, a crude estimate of
nature far exceeds that of humans and it seems reasonable which is made in Section VII-A. In short, elemen-
to seek inspiration for new information processing tech- tary structural building blocks (22 amino acids and
nologies from this source. In that which follows, it is five nucleotides) need to be synthesized or ac-
argued that the living cell can be viewed as an information quired, and then utilized to form functional build-
processor that is extraordinarily efficient in the execution ing blocks, which include different proteins, RNA,
of its functions. The living cell is, in a sense, a universal and DNA molecules. Finally, all building blocks
constructor as suggested by von Neumann, which is capa- need to be properly placed within cell’s volume for
ble of creating copies of itself [166], [167]. The model that assembly. A special cell-cycle control mechanism
is used in the following is the E.coli cell which has di- regulates the sequence, timing, etc., of the cell
mensions on the order of 1 m and which has been heavily assembly process.
studied so that quantitative estimates of its complexity, 2) Adaptation for survival: Acquiring/processing
performance, and energy efficiency are available. Given information from external stimuli with feed-
this, it is important to point out that many of the mysteries back from DNA.
of cell operation are yet unresolved and are the focus of Single-cell organisms, such as E.coli bacteria,
continuing investigations. could not survive without the ability to sense the
In order to provide a benchmark for E.coli cell oper- environment and adapt to its changes (positive or
ation, we first extrapolate the capabilities of a 1-m scale negative). For example, in response to the exter-
CMOS information processor when end-of-scaling CMOS nal presence of specific nutrients, particular pro-
technology is utilized. Favorable assumptions for the 1-m teins are produced within the cell to facilitate the
CMOS cell are offered including the stipulation that no uptake and digestion of those nutrients. In the
volume is required for energy storage and for communi- absence of nutrients, the cell can switch to a rest-
cation. A development is then offered, from available data, ing mode, where the reproductive process is inhi-
of the information processing capability of the E.coli cell. bited. In addition, single-cell organisms can
It is argued that the information processing capabilities of respond to a variety of external stimuli such as
the E.coli cell far exceed that of the 1-m CMOS cell and temperature, light, presence of toxic chemicals,
inferences are drawn suggestive of directions for future magnetic field, etc. Many single-cell organisms
information processing technologies. The terminology also possess motility organs (e.g., flagellae in case
in silico is used to refer to the semiconductor benchmark of E. coli).

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Fig. 11. Unicellular organism as information processor.

3) Extracellullar communication: Sending and plexity of the cell, and are absolutely dominant in humans
receiving signals to coordinate community [173]. Proteins can alter their 3-D structural shapes (con-
behavior. formation) in response to external stimuli, and different
Many unicellular organisms communicate to conformations can represent different logic states. These
each other by the release and detection of special nanomechanical changes form a state variable, sometimes
signal molecules. Cells use chemical signaling to called conformon [175]. The essential functions of the
detect population density and to exchange infor- protein devices are determined by their conformational
mation about the local environment. Cell-to-cell states. A simple example of the Bbinary[ conformational
communication coordinates the behavior of a cell change is the ion channel protein, which is embedded in a
population to increase access to nutrients, provide cell’s membrane and acts as a gate for ions, and can be
for collective defense, or enable the community to opened or closed depending on command from either in-
escape in case of threats to its survival. ternal or external sources, e.g., light, pressure, chemical
In the following, we offer a simple estimate of single- signal, etc. Different nanomechanical conformations of
cell computational capabilities based on two different ap- these protein devices are recognized by other elements of
proaches. A bottom-up approach counts the cell hardware, the in carbo cell circuit by a process based on selective
i.e., the number of memory and logic elements in the affinity of certain biomolecules with given conformational
in carbo processor. The top-down approach deals with total states. Molecular recognition implemented with confor-
amount of computation needed to implement operations mons plays a fundamental role in the communication of
to assemble a new cell. information packages within the processor, and it facilitates
targeted interactions between different elements, e.g.,
C. Cell Hardware protein–protein, protein–DNA, RNA–ribosome, etc.
Fig. 11 shows a cartoon of a cell as information pro- The protein conformons control all processes in the cell,
cessor. It contains a localized long-term memory block M such as sensing, signaling, information retrieval, etc. Some
(DNA molecule), a number of short-term memory and examples will be given in the next section.
logic units L (different protein and RNA molecules),
(input) sensors S to monitor both outside environment 2) Memory Hardware: All data about structure and ope-
and the cell interior (extracellular and intracellular recep- ration of a living cell are stored in the long DNA molecule.
tor proteins), and two output units: the ribosomes, where DNA coding uses a base-4 (quaternary) system. The infor-
new structural building blocks for reproduction are mation is encoded digitally by using four different mole-
Bprinted,[ and signaling units that Bwirelessly[ connect cular fragments, called nucleobases, to represent a state:
to neighboring cells by sending signal molecules. adenine (A), cytonine (C), guanine (G), and thymine (T).
The cell hardware is made from three types of macro- The four molecular state symbols are attached in series to a
molecules: proteins, DNA, and RNA. Table 6 presents a flexible Btape[ or a Bbackbone[ made of sugar and phos-
summary of the statistics and functions of these molecules phate groups. The complete DNA unit consists of two
in E.coli cell. A description of essential features of different complementary Btapes[ forming the so-called double he-
parts of the cell hardware is given below. lix. Each state symbol (base) on the first tape forms a pair
(base pair) with a complementary state symbol on the
1) Logic Hardware: Many proteins (Fig. 12) in living second tape: adenine forms a pair with thymine, while
cells have as their primary function the transfer and pro- cytosine forms a pair with guanine. Information content in
cessing of information, and are therefore regarded as logic each tape is identical, but is written with different (com-
elements of the in carbo processor [171]–[174]. In fact, as plimentary) sequences of symbols. Thus, the base pair (bp)
recent studies indicate, the proportion of components de- is a natural unit of information stored in DNA. One bp
voted to computational networks increases with the com- equals to two bits of binary information and corresponds to

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Cavin et al.: Science and Engineering Beyond Moore’s Law

Table 6 Essential Parameters of the E.coli Molecular Processor

approximately 0.34 nm of length along the tape, as shown a) read from long-term memory: The access to the
in Fig. 13. DNA memory is facilitated by special protein devices,
Some examples of DNA storage capacity (genome size) which form memory interface circuitry. For example, the
are given in Table 7. Note that the storage density of mole- DNA-binding proteins (forming transcription factor com-
cular DNA memory is 10 Mb/m3 or 1019 b/cm3 , which is plex) act as gates to the specific snippets of DNA, and they
much denser than the density limits for the electronic long- therefore represent a mechanism to retrieve information
term memory evaluated in Section III-B. Also it is inter- from a specific DNA address. The cell’s signaling network
esting to note that the single-cell organism Amoeba Dubia regulates the state of the DNA-gating proteins that deter-
stores a huge amount of information (1.34 Tb), compared to mine when and where a DNA snippet (a gene) is activated,
6 Gb stored in the human genome. thus address specification. Next, the information is re-
trieved from the specified address by a special device
formed by the RNA polymerase protein. This protein acts as
a memory read head moving along the specified snippets of

Fig. 12. Protein molecule formed from different amino acids Fig. 13. A fragment of DNA molecule formed from four
(shown as circles of different colors). different nucleotides.

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Table 7 DNA Storage Capacity (Genome Size) for Several Representative Cellular Organisms

DNA and copying its information by synthesizing pieces of shape [176]. For example, if a case of von Neumann
messenger RNA (mRNA) molecules. The mRNA then universal constructor is considered, i.e., a computer with
transfers the information to the sites of protein synthesis, the task of controlled the assembly of the structure (e.g.,
the ribosomes. RNA is thus part of the memory interface, another computer) from building blocks, a certain amount
with functions of the memory buffer (DRAM, SRAM) and of information must be processed, which is related to the
the information package which facilitates interactions complexity of materials system. For each step, the com-
between memory, logic, and input/outputs (I/Os). Note puter must: 1) select the appropriate category of the
that the information can be retrieved from different parts of building blocks; and 2) calculate x-, y-, z-coordinates of the
DNA memory simultaneously, thus this is a highly parallel position for each of the building blocks. If there are N
process with many RNA more or less simultaneously different building blocks (in the case of ultimate bottom-
accessing snippets of the DNA and transferring this up construction, these building blocks could be atoms
information to the ribosomes to make proteins. composing a material structure), information content of
Different parts of the DNA memory of the cell are selection in step 1 is
continuously accessed to support its operation. One ex-
ample is signal transduction, which is the DNA-controlled
process of cellular response to external stimuli. Is ¼ log2 N (bit) (5)
b) Writing to long-term memory: The view that DNA is
a read-only memory has undergone a dramatic change in and the information of the xyz-positioning is
recent years. The copying of the parental DNA to the off-
spring, called vertical gene transfer, is the basis for inhe-
ritance and until recently was regarded as the only or at Ixyz ¼ 3n (6)
least the vastly predominant mechanism for transferring
the genetic information. There is, however, an alternative
mechanism for information transfer, which is lateral gene where n is the lengths of a binary number representing
transfer. This can happen: 1) by a direct uptake (swallow- each coordinate. In this estimate, n ¼ 32 b will be used,
ing) of naked DNA from the cell environment; 2) by a virus; which is sufficient for representing numbers with practi-
and 3) by direct physical contact between two cells. cally arbitrary precision (Bfloating point[ format).
Fragments of DNA, imported from outside, can be Thus, if the total number of the building blocks in a
integrated into the host DNA, and thus new information material structure is K, the total information processed in
is written in the memory unit. Until the advent of the assembly is
genome-sequencing era, a prevailing opinion among the
research community was that lateral gene transfer was a
IK ¼ Kðlog2 N þ 3nÞ: (7)
rare and insignificant event. Currently, it is recognized
that in prokaryotic, e.g., bacterial cells, lateral transfer is
the predominant form of genetic variation and is one of the Now, consider the task assembling of living cell of
primary driving forces for bacterial evolution. In fact, the E.coli bacterium from individual atoms. The elemental
scale of lateral gene transfer can be very large: for example, composition of the bacterial cell is known with high
two different strains of E.coli differ more radically in their accuracy and is shown in Table 8 [177]. The cell is
genetic information than all mammals. mainly composed of ten different atoms with the total
number of  3  1010 atoms. Thus, using (7), we obtain
VII. QUANTITATIVE ESTIMATES FOR
T HE BI O -CELL AND THE Si- C E L L Icell  3  1010  ðlog2 10 þ 3  32Þ  3  1012 bit:

A. The Bio-Cell
The overall information content of a material system This result is remarkably close to the experimental es-
consists of information about the system’s composition and timates of the informational content of bacterial cells

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Cavin et al.: Science and Engineering Beyond Moore’s Law

Table 8 Elemental Composition of E.coli [177] system, larger scale devices or/and smaller device count
must be used.
What is the smallest device count that could suffice
for the Si-cell? von Neumann has argued that the
minimum logic circuit complexity required to implement
general-purpose computing is of the order of a few
hundred devices [178]. In an attempt for a more accurate
estimate of the von Neumann threshold, a model 1-bit
minimal Turing machine (MTM) has been constructed
with total device count of about 320 binary switches/
transistors and requires 8-b instruction words for its
operation [25]. In the following, it will be assumed that
the logic processor of the Si-cell is implemented by an
MTM. This also allows the maximization of the amount
of memory in Si-cell (which is much less than the
bio-cell).
Suppose the MTM is implemented within the Si-cell
using FETs with Lg  4.5 nm with the parameters listed in
based on microcalorimetric measurements which range
Table 4. The remainder of the 1-m cube is available for
from 1011 to 1013 bits per cell. In the following, it is
memory.
assumed that Icell  1011 bit, i.e., the conservative estimate
Implementation of each of the MTM instructions
is used.
requires a minimum of three sequential operations/
cycles [25]. On average, 50% of transistors are active
B. The Si-Cell during each cycle, thus 160 switching events per cycle
For a system-level comparison between extremely or 500 switching events per instruction. Since execu-
scaled Si-based technology and carbon-based computa- tion of one instruction results in one output bit, the ratio
tional elements in biosystems, consider a hypothetical of the total transistor switchings (raw bits) to the output
computer that is realized in a cube of 1 m in size (the bits is 1/500. Therefore, in order to generate 1011 output
volume of the bio-cell). Such computer, later referred bits, the typical outcome of biological computation, at
to as Si-cell, must contain logic circuitry and non- least 5  1013 raw bits must be processed in the MTM. It
volatile memory to store program. Suppose further all takes 3  1011 MTM cycles to complete the computational
components of the computer are to be implemented in task (i.e., three MTM cycles per one output bit). If it is
ultimately scaled Si technology summarized in Table 4. required that these events occur over 2400 s (to match the
In the following, 3-D-stacked logic and memory circuit bio-cell), the cycle time tcycle ¼ 8 ns. This appears to be
layers will be used to fill the 1-m3 volume. (In Table 4, easily achievable by CMOS technology. The total switch-
the thickness of one layer in the stack is assumed to be ing energy and power per MTM cycle are
9F for logic and 6F for memory.) The corresponding
densest conceivable 3-D arrangement of FETs is
1.5  1017 transistors/cm3 , and thus 1-m3 volume could Ecycle ¼ N  Ebit ¼ 320  2.93  1018
contain up to 150 000 logic transistors. For nonvolatile ¼ 9.36  1016 J (8a)
memory, the densest 3-D stack of nand layers is
4.2  1016 b/cm3 , or 42 kb of memory in 1-m3 .
Comparing to the bio-cell in Table 6, the Si-cell [note that Ebit in (8a) corresponds to the 50% activity
can contain 10 less logic elements and more than factor (4b)] and
100 less memory. (Note that this estimate was made
even before partitioning of the 1-m3 volume between
logic and memory and not including an energy Ecycle 9.36  1016
Pactive ¼ ¼ ¼ 1.17  107 W: (8b)
source.) tcycle 8  109
Next, according to Table 4, the off-state leakage power
in the ultimate FET circuit is 2.34 nW per transistor,
thus 357 W of total static power dissipation in a system (There is also leakage power consumption and this is
of 152 000 FETs. This results in catastrophic heat densities approximately 749 nW.)
in the 1-m3 cube: q ¼ 357 W/6 m2 ¼ 5800 W/cm2 . Next, the energy consumed by the memory access
This is almost equal to the heat density at the Sun’s needs also be taken into account. At each cycle, an 8-b
surface (6000 W/cm2 , as shown in Table 8). Clearly, instruction must be read from the memory block.
such Si-cell computer cannot exist. Therefore, for such a Assuming a serial read (typical for nand memory) with

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 Cavin et al.: Science and Engineering Beyond Moore’s Law

Table 9 Energetics of Si-cell Implemented With Ultimate (i.e., no additional space overheads), the maximum heat
High-Performance CMOS Technology
flux through the walls of the cube must be G 1 W/cm2
(max. free water convection cooling rate).
If only passive air or water cooling is used, the max
heat flux should be G 1 W/cm2 , thus total power
dissipation G 6  108 W, which limits the cycle time to
be > 1.70 s. For this, the total time needed to emulate
the bio-cell task (i.e., equivalent of 1011 output bits) will
be 510 000 s, which is more than 200 larger than time
needed for the bio-cell.
As follows from the above, the bio-cell outperforms
the Si-cell in all respects. A summary of the comparison
between the two cells is presented in Section VII-C and
some of the implications are discussed.

C. Comparisons and Implications

As is clear from the previous section, the Si-cell
only one line in memory array charged, the energy for fundamentally cannot match the bio-cell in the density of
reading eight serial bits is close to 1013 J memory and logic elements, or operational speed, or ope-
rational energy. A core challenge is the MTM requirement
for a large number of memory accesses per output bit. The
EM 1013 J above analysis suggests that there is much to be learned
PMcycle ¼  ¼ 1.25  105 W:
tcycle 8  109 s from the designs of nature and they may provide hints as to
how future technologies could evolve. Fig. 14 provides a
brief summary of comparative data. As follows from the
A summary of energetics of Si-cell implemented with analysis, the number of functional elements in the bio-cell
ultimate high-performance CMOS and also for low standby is extraordinary and far exceeds foreseeable device
power technologies is given in Tables 9 and 10. As follows densities of semiconductors. This may be at least in part
from the tables, the Si-cell cannot operate in this mode due to different mass of information carriers: As was argued
due excessive heat generation. Therefore, the cycle time in Section III, the smallest size for both memory and logic
has to be increased to reduce the power dissipation. Note devices depends on the mass of the information-bearing
that the predominant source of power consumption in both particles, e.g., the smallest barrier width in Si devices is
cases is a consequence of charging memory access lines. 5 nm due to low effective mass of electrons in Si. Heavier
How much heat could be tolerated by a Si-cell com- particle mass, in principle, allows for smaller device size,
puter? Table 11 provides some reference numbers for sev- which seems to be realized in the in carbo logic and
eral model heat generators along with heat removal memory elements. Emerging technologies discussed in
capabilities for different cooling techniques. If it is postu- Section V-B3, such as memristors, atomic switch, and redox
lated that only passive cooling can be used for the Si-cell memory, also use heavier mass particles, and their potential
for very dense circuits needs to be further explored.
Table 10 Energetics of Si-cell Implemented With Ultimate
As was shown in the previous section, memory access is
Low-Standby Power CMOS Technology the most severe limiting factor of Si-cell. Not only is there
simply not enough nonvolatile memory bits, but also access
to them to support computations takes too much energy. In
larger scale computers, this problem is easily circumvented
by initial massive serial readout from the nonvolatile media
(e.g., hard disk drives or flash memory) and buffering these
data in low-energy SRAM or DRAM. However, at the scale of
the 1-m cube, there is no space for the buffers, and just
direct access to nonvolatile memory was assumed for the Si-
cell operation. Another related observation is that organiz-
ing solid state memory in crossbar arrays, while an elegant
solution is at larger scale, also contributes to excessive energy
dissipation. In this regard, access to the DNA memory can be
viewed as similar to access to hard disc drives [179], [180]. It
could be argued that at least in theory, the serial access
principle of hard disc drives might be a better solution for

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Table 11 Cooling Capabilities for Air and Water and Examples of Representative Heat Generating Systems

low-energy systems (of course, in practice, the mechanical pient molecular structures. In contrast, data transfer in
overheads significantly add to the total energy consumption electrical circuits follows predetermined routes that re-
of hard disk drives). quire an expenditure of energy. Whereas electrical circuits
The architectural organization of computation in utilize a controllable energy barrier whose operation re-
in carbo systems appears to be much more efficient than quires an expenditure of energy and whose physical extent
for Si computers. As was mentioned in Section II, the is determined by electron tunneling considerations, it is
biological processors, such as brain, are not on the compu- not clear that there is a similar use of energy barriers in the
tational trajectory for Si microprocessors in Fig. 2, sug- ribosome’s execution of RNA instructions.
gesting that there may exist alternate technologies and As a side remark, although not emphasized in this study,
computing architectures offering higher performance (at the bio-cell incorporates within its volume the capability to
much lower levels of energy consumption). One key factor incorporate and transform materials from its environment
here is that basic algorithms need to work in very few steps into energy yielding molecules in a form accessible to its
[181]. Indeed, it appears that the bio-cell utilizes fine- processes. Such additional processes for energy transforma-
grained and massive parallelism per instruction, i.e., by tion were not included in the analyses of the Si-cube.
sending out into the cytoplasm multiple copies of DNA Finally, in 1959, Feynman [182] gave a presentation in
instructions by RNA messengers. Also, the bio-cell uti- which he suggested the possibility of building computers
lizes undirected thermally driven motion of the mRNA whose dimensions were Bsubmicroscopic.[ Although the
molecules to achieve connectivity to the ribosomes in the progress of CMOS technology has been extraordinary,
cytoplasm. A correct transfer to an appropriate ribosome is submicroscopic computers remain outside our grasp. As
achieved by electrostatic attraction arising from conforms, has been indicated above, nature appears to have success-
i.e., from the specific shapes of the transmitted and reci- fully addressed the submicroscopic design challenge.

Fig. 14. Comparison of significant parameters of the bio-cell and the Si-cell.

1744 Proceedings of the IEEE | Vol. 100, May 13th, 2012

 Cavin et al.: Science and Engineering Beyond Moore’s Law

VIII . SUMMARY CMOS modules with special-purpose structures based on

Feature size scaling has enabled a very steep learning the novel devices.
curve for CMOS technology that has helped to create a It also may be that dramatic improvements in infor-
feature-driven marketplace. Although there are compelling mation processing technologies will result from a radical
physical arguments that physical scaling must end for rethinking of both architectures and supporting technolo-
CMOS, it appears that the benefits of Moore’s law will gies. A comparative analysis between the bio-cell and the
continue for some time, aided by the advent of new mate- Si-cell was offered to stimulate thinking about alternative
rials, processes, and device structures. Very likely, the scenarios. As the bio-cell goes about its complex task of
application space for CMOS technology will continue to creating a copy of itself, it does so using fine-grained
grow rapidly as new functionalities are combined with processes, devices, and architectures that are completely
more traditional information processing and communica- different and much more energy efficient than existing
tion capabilities. CMOS/von Neumann paradigms. Perhaps, the design of
At the same time, there is intense research underway to nature’s information processors can inspire radical
find alternatives to CMOS technology that have the po- breakthroughs in inorganic information processing.
tential to extend the benefits of Moore’s law scaling for There is substantial momentum to sustain Moore’s law
decades into the future. It was pointed out that there are for many more decades because of the benefits that it accrues
many options at this time, but there is no one-for-one to society. The challenges that lie before us to achieve this
substitute for CMOS technology yet available. Replace- are substantial but so is the creativity of scientists and
ment options may eventually be identified, but it appears engineers. Although the road ahead is not well marked, there
that a likely scenario is that this research will yield devices are many indications that there are no insurmountable
with functionalities that can be integrated with CMOS barriers that would deny progress in information processing
technology to provide unique capabilities or to replace technologies for the foreseeable future. h

REFERENCES A. Pouydebasque, M. Szczap, A. Farcy, [19] T. Skotnicki and F. Boeuf, BOptimal

F. Arnaud, S. Clerc, M. Sellier, A. Cathignol, scaling methodologies and transistor
[1] G. E. Moore, BCramming more components J. P. Schoellkopf, E. Perea, R. Ferrant, and performance,[ in High-K Gate Dielectric
onto integrated circuits,[ Electronics, H. Mingam, BInnovative materials, devices, Materials for VLSI MOFET Applications,
vol. 38, pp. 114–117, 1965. and CMOS technologies for low-power H. Huff and D. Gilmer, Eds.
[2] S. P. Murarka and S. W. Hymes, BCopper mobile multimedia,[ IEEE Trans. Electron New York: Springer-Verlag, 2005,
metallization for ULSI and beyond,[ Critical Devices, vol. 55, no. 1, pp. 96–130, Jan. 2008. pp. 143–194.
Rev. Solid State Mater. Sci., vol. 20, [10] W. Gitt, BInformationVThe 3rd [20] S. Shankar, V. Zhirnov, and R. Cavin,
pp. 87–124, 1995. fundamental quantity,[ Siemens Rev., BComputation from devices to system
[3] R. H. Havemann and J. A. Hutchby, vol. 56, pp. 36–41, 1989. level thermodynamics,[ ECS Trans.,
BHigh-performance interconnects: [11] H. Moravec, BWhen will computer hardware vol. 25, no. 7, pp. 421–431, 2009.
An integration overview,[ Proc. IEEE, match the human brain?[ J. Evol. Technol., [21] W. Haensch, E. J. Nowak, R. H. Dennard,
vol. 89, no. 5, pp. 586–601, May 2001. vol. 1, pp. 1–12, 1998. P. M. Solomon, A. Bryant, O. H. Documaci,
[4] G. D. Wilk, R. M. Wallace, and [12] W. Rhynes, BKeynote: FLess of Moore_,[ A. Kumar, X. Wang, J. B. Johnson, and
J. M. Anthony, BHigh-k gate dielectrics: presented at the TECHCON, Austin, TX, M. V. Fischetti, BSilicon CMOS devices
Current status and materials properties Sep. 14, 2009. beyond scaling,[ IBM J. Res. Develop., vol. 59,
considerations,[ J. Appl. Phys., vol. 89, pp. 339–361, 2006.
5243, 2001. [13] D. J. C. Herr, BDirected block copolymer
self-assembly for nanoelectronics [22] International Technology Roadmap for
[5] C. H. Jan, P. Bai, S. Biswas, M. Buehler, fabrication,[ J. Mater. Res., vol. 26, Semiconductors (ITRS). [Online]. Available:
Z. P. Chen, G. Curello, S. Gannavaram, pp. 122–139, 2011. www.itrs.net
W. Hafez, J. He, J. Hicks, U. Jalan, N. Lazo, [23] V. Zhirnov and T. Mikolajick, BChapter 26:
J. Lin, N. Lindert, C. Litteken, M. Jones, [14] C. Bencher, J. Smith, L. Y. Miao, C. Cai,
Y. M. Chen, J. Y. Cheng, D. P. Sanders, Flash memories,[ in Nanoelectronics and
M. Kang, K. Komeyli, A. Mezhiba, S. Naskar, Information Technology, R. Waser, Ed.
S. Olson, J. Park, R. Parker, L. Pei, M. Tjio, H. D. Truong, S. Holmes, and
W. D. Hinsberg, BSelf-assembly patterning New York: Wiley, 2012.
I. Post, N. Pradhan, C. Prasad, M. Prince,
J. Rizk, G. Sacks, H. Tashiro, D. Towner, for sub-15 nm half-pitch: A transition from [24] J. D. Meindl, BLow power microelectronics:
C. Tsai, Y. Wang, L. Yang, J. Y. Yeh, lab to fab,[ Proc. SPIE, vol. 7970, 79700F, Retrospect and prospect,[ Proc. IEEE,
J. Yip, and K. Mistry, BA 45 nm low power 2011. vol. 83, no. 4, pp. 619–635, Apr. 1995.
system-on-chip technology with dual gate [15] V. V. Zhirnov, R. K. Cavin, J. A. Hutchby, [25] R. Cavin, W. Joyner, and T. Noll,
(logic and I/O) high-k/metal gate strained and G. I. Bourianoff, BLimits to binary BChapter 22: Performance estimates for
silicon transistors,[ in Proc. Int. Electron logic switch scalingVA Gedanken model,[ microprocessors: At technology limits
Devices Meeting, 2008, pp. 637–640. Proc. IEEE, vol. 91, no. 11, pp. 1934–1939, and in practice,[ in Nanoelectronics and
[6] S. E. Thompson, G. Sun, Y. S. Choi, and Nov. 2003. Information Technology, R. Waser, Ed.
T. Nishida, BUniaxial-process-induced [16] T. N. Theis and P. M. Solomon, BIn quest New York: Wiley, 2012.
strained-Si: Extending the CMOS roadmap,[ of the FNext Switch_: Prospects for greatly [26] G. Chandra, P. Kapur, and K. C. Saraswat,
IEEE Trans. Electron Devices, vol. 53, no. 5, reduced power dissipation in a successor to BScaling trends for the on chip power
pp. 1010–1020, May 2006. the silicon field-effect transistor,[ Proc. IEEE, dissipation,[ in Proc. 5th Int. Interconnect
[7] M. Mayberry, BProgress towards the merger vol. 98, no. 12, pp. 2005–2014, Dec. 2010. Technol. Conf., Burlingame, CA, Jun. 3–5,
of compound semiconductors and silicon,[ [17] K. Bernstein, R. K. Cavin, W. Porod, 2002, pp. 170–172.
Solid State Technol., vol. 52, pp. 16–17, 2009. A. Seabaugh, and J. Welser, BDevice and [27] V. V. Zhirnov, R. K. Cavin, S. Menzel,
[8] K. J. Kuhn, BMoore’s crystal ball: Device architecture outlook for beyond CMOS E. Linn, S. Schmelzer, D. Bräuhaus,
physics and technology past the 15 nm switches,[ Proc. IEEE, vol. 98, no. 12, C. Schindler, and R. Waser, BMemory
generation,[ Microelectron. Eng., vol. 88, pp. 2169–2184, Dec. 2010. devices: Energy-space-time tradeoffs,[
pp. 1044–1049, 2011. [18] M. Mayberry, BKeynote: FA look forward_,[ Proc. IEEE, vol. 98, no. 12, pp. 2185–2200,
presented at the TECHCON, Austin, TX, Dec. 2010.
[9] T. Skotnicki, C. Fenouillet-Beranger,
C. Gallon, F. Baeuf, S. Monfray, F. Payet, Sep. 13, 2010.

Vol. 100, May 13th, 2012 | Proceedings of the IEEE 1745

Cavin et al.: Science and Engineering Beyond Moore’s Law

[28] L. M. Grupp, A. M. Caulfield, J. Coburn, Solid-State Circuits, vol. 45, no. 1, [63] J. H. Burroughes, D. D. C. Bradley,
S. Swanson, E. Yaakobi, P. H. Siegel, and pp. 214–223, Jan. 2010. A. R. Brown, R. N. Marks, K. Mackay,
J. K. Wolf, BCharacterizing flash memory: [45] I. Magrini and A. C. G. Manes, BA low local R. H. Friend, R. L. Burn, and A. B. Holmes,
Anomalies, observations, and applications,[ oscillator power K-band mixer based on BLight-emitting diodes based on conjugated
in Proc. MICRO, New York, Dec. 12–16, tunneling diodes,[ Microw. Opt. Technol. polymers,[ Nature, vol. 347, pp. 539–541,
2009, pp. 24–33. Lett., vol. 51, no. 4, pp. 1140–1143, 2009. 1990.
[29] N. Derhacobian, S. C. Hollmer, N. Gilbert, [46] R. Knobel, C. S. Yung, and A. N. Cleland, [64] A. C. Arias, J. D. MacKenzie, I. McCulloch,
and M. N. Kozicki, BPower and energy BSingle-electron transistor as a J. Rivnay, and A. Salleo, BMaterials and
perspectives of nonvolatile memory radio-frequency mixer,[ Appl. Phys. Lett., applications for large area electronics:
technologies,[ Proc. IEEE, vol. 98, no. 2, vol. 81, no. 3, pp. 532–534, 2002. Solution-based approaches,[ Chem. Rev.,
pp. 283–298, Feb. 2010. vol. 110, no. 1, pp. 3–24, 2010.
[47] H. Wang, A. Hsu, J. Wu, K. Jing, and
[30] W. Arden, M. Brillouët, P. Cogez, T. Palacios, BGraphene-based ambipolar [65] S. Günes, H. Neugebauer, and
M. Graef, B. Huizing, and R. Mahnkopf, RF mixers,[ IEEE Electron Device Lett., N. S. Sariciftci, BConjugated polymer-based
More-than-Moore, White Paper. [Online]. vol. 31, no. 9, pp. 906–908, Sep. 2010. organic solar cells,[ Chem. Rev., vol. 107,
Available: http://www.itrs.net/Links/ no. 4, pp. 1324–1338, 2007.
[48] C. Rutherglen and P. Burke, BCarbon
2010ITRS/IRC-ITRS-MtM-v2%203.pdf. [66] D. Baierl, B. Fabel, P. Lugli, and
nanotube radio,[ Nano Lett., vol. 7, no. 11,
[31] C. B. Les, BImage sensor market: Changing, pp. 3296–3299, 2007. G. Scarpa, BEfficient indium-tin-oxide (ITO)
but moving upward,[ Photon. Spectra, free top-absorbing organic photodetector
[49] N. Rouhi, D. Jain, and P. J. Burke,
vol. 43, pp. 27–28, 2009. with highly transparent polymer top
BNanoscale devices for large-scale
[32] A. El Gamal and H. Eltoukhy, BCMOS image electrode,[ Organic Electron., vol. 12, no. 10,
applications,[ IEEE Microw. Mag.,
sensors,[ IEEE Circuit Device Mag., vol. 21, pp. 1669–1673, 2011.
vol. 11, no. 7, pp. 72–80, Dec. 2010.
no. 3, pp. 6–20, May–Jun. 2005. [67] T. Agostinelli, M. Caironi,
[50] E. Cantatore, T. C. T. Geuns, G. H. Gelinck,
[33] G. K. Fedder, R. T. Howe, T. K. Liu, and D. Natali, M. Sampietro, G. Dassa,
E. van Veenendaal, A. F. A. Gruijthuijsen,
E. P. Quevy, BTechnologies for cofabricating E. V. Canesi, C. Bertarelli, G. Zerbi,
L. Schrijnemakers, S. Drews, and
MEMS and electronics,[ Proc. IEEE, vol. 96, J. Cabanillas-Gonzalez, S. De Silvestri, and
D. M. de Leeuw, BA 13.56-MHz RFID system
no. 2, pp. 306–322, Feb. 2008. G. Lanzani, BA planar organic near infrared
based on organic transponders,[ IEEE J.
light detector based on bulk heterojunction
[34] C. Liao and J. Tsai, BThe evolution of MEMS Solid-State Circuit, vol. 42, no. 1, pp. 94–92,
of a heteroquaterphenoquinone and
display,[ IEEE Trans. Ind. Electron., vol. 56, Jan. 2007.
poly[2-methoxy-5-(20 -ethyl-hexyloxy)-1,
no. 4, pp. 1057–1065, Apr. 2009. [51] J. Lewis, J. Burroughes, Y. Ohmori, and 4-phenylene vinylene],[ J. Appl. Phys.,
[35] EU Commision, Technology Roadmap for K. S. Narayan, BOrganic electronics,[ vol. 104, no. 11, pp. 114 508–114 513, 2008.
Nanoelectronics, 2001. [Online]. Available: Proc. IEEE, vol. 97, no. 9, pp. 1555–1557,
[68] T. Rauch, M. Böberl, S. F. Tedde, J. Fürst,
ftp://ftp.cordis.europa.eu/pub/esprit/docs/ Sep. 2009.
M. V. Kovalenko, G. Hesser, U. Lemmer,
melnarm.pdf. [52] G. T. Reed, G. Mashanovich, F. Y. Gardes, W. Heiss, and O. Hayden, BNear-infrared
[36] A. Hussain, J. Hone, H. W. Postma, and D. J. Thomson, Nature Photon., vol. 4, imaging with quantum-dot-sensitized
X. M. H. Huang, T. Drake, M. Narbic, pp. 518–526, 2010. organic photodiodes,[ Nature Photon.,
A. Scherer, and M. L. Roukes, [53] J. Leuthold, C. Koos, and W. Freude, vol. 3, pp. 332–336, 2009.
BNanowire-based very-high-frequency BNonlinear silicon photonics,[ Nature [69] X.-L. Huang and Y.-K., BChemical sensors
electromechanical resonator,[ Appl. Photon., vol. 4, pp. 535–544, 2010. based on nanostructured materials,[ Sens.
Phys. Lett., vol. 83, no. 6, 1240, 2003.
[54] D. Liang and J. E. Bowers, BRecent progress Actuators B, vol. 122, pp. 659–671, 2007.
[37] G. M. Rebeiz, RF MEMS: Theory, Design in lasers on silicon,[ Nature Photon., vol. 4, [70] B. L. Allen, P. D. Kichambare, and
and Technology. New York: Wiley, pp. 511–517, 2010. A. Star, BCarbon nanotube
2003.
[55] H. Rong, S. Xu, Y. Kuo, V. Sih, O. Cohen, field-effect-transistor-based biosensors,[
[38] X. L. Feng, R. He, P. Yang, and M. L. Roukes, O. Raday, and M. Paniccia, BLow-threshold Adv. Mater., vol. 19, pp. 1439–1451, 2007.
BVery high frequency silicon nanowire continuous-wave Raman silicon laser,[ [71] M. Li, H. X. Tang, and M. L. Roukes,
electromechanical resonators,[ Nano Lett., Nature Photon., vol. 1, pp. 232–237, BUltra-sensitive NEMS-based cantilevers
vol. 7, no. 7, pp. 1953–1959, 2007. 2007. for sensing, scanned probe and very
[39] V. Sazonova, Y. Yaish, H. Ustunel, [56] C. M. Soukoulis and M. Wegener, BPast high-frequency applications,[ Nature
D. Roundy, T. A. Arlas, and P. L. McEuen, BA achievements and future challenges in the Nanotechnol., vol. 2, pp. 114–120, 2007.
tunable carbon nanotube electromechanical development of three-dimensional photonic [72] N. M. Freris, H. Kowshik, and P. R. Kumar,
oscillator,[ Nature, vol. 431, pp. 284–287, metamaterials,[ Nature Photon., vol. 5, BFundamentals of large sensor networks:
2004. pp. 523–530, 2011. Connectivity, capacity, clocks, and
[40] H. B. Peng, C. W. Chang, S. Aloni, [57] M. Lipson, BGuiding, modulating, and computation,[ Proc. IEEE, vol. 98, no. 11,
T. D. Yuzvinsky, and A. Zettl, BUltrahigh emitting light on Silicon-challenges and pp. 1828–1846, Nov. 2010.
frequency nanotube resonators,[ Phys. opportunities,[ J. Lightw. Technol., vol. 23, [73] G. Zheng, X. Gao, and C. M. Lieber,
Rev. Lett., vol. 97, 087203, 2006. no. 12, pp. 4222–4238, Dec. 2005. BFrequency domain detection of
[41] J. S. Bunch, A. M. van der Zande, [58] J. A. Dionne, L. A. Sweatlock, M. T. Sheldon, biomolecules using silicon nanowire
S. S. Verbridge, I. W. Frank, A. P. Alivisatos, and H. A. Atwater, biosensors,[ Nano Lett., vol. 10,
D. M. Tanenbaum, J. M. Parpia, BSilicon-based plasmonics for on-chip pp. 3179–3183, 2010.
H. G. Craighead, and P. L. McEuen, photonics,[ IEEE J. Sel. Topics Quantum [74] I. Heller, W. T. T. Small, S. G. Lemay, and
BElectromechanical resonators from Electron., vol. 16, no. 1, pp. 295–306, C. Dekker, BProbing macrophage activity
graphene sheets,[ Science, vol. 315, Jan./Feb. 2010. with carbon-nanotube sensors,[ Small,
pp. 490–493, 2007.
[59] G. Konstantatos and E. H. Sargent, vol. 5, pp. 2528–2532, 2009.
[42] C. Durand, F. Casset, P. Renaux, BNanostructured materials for photon [75] J. A. Rogers, T. Someya, and Y. Huang,
N. Abele, B. Legrand, D. Renaud, detection,[ Nature Photon., vol. 5, BMaterials and mechanics for
E. Ollier, P. Ancey, A. M. Ionescu, and pp. 391–400, 2010. stretchable electronics,[ Science,
L. Buchaillot, BIn-plane silicon-on-nothing
[60] A. Rogalski, BInfrared detectors: Status vol. 327, pp. 1603–1607, 2010.
nanometer-scale resonant suspended gate
and trends,[ Progr. Quantum Electron., [76] L. Hu, D. S. Hecht, and G. Grüner,
MOSFET for In-IC integration perspectives,[
vol. 27, no. 2–3, pp. 59–210, 2003. BCarbon nanotube thin films: Fabrication,
IEEE Electron Device Lett., vol. 29, no. 5,
pp. 494–496, May 2008. [61] S. F. Tedde, J. Kern, T. Sterzl, J. Fürst, properties, and applications,[ Chem. Rev.,
P. Lugli, and O. Hayden, BFully spray vol. 110, no. 10, pp. 5790–5844, 2010.
[43] J. A. Katine and E. E. Fullerton,
coated organic photodiodes,[ Nano Lett., [77] Q. Cao and J. A. Rogers, BUltrathin films
BDevice implications of spin-transfer
vol. 9, no. 3, pp. 980–983, 2009. of single-walled carbon nanotubes for
torques,[ J. Magn. Magn. Mater., vol. 320,
pp. 1217–1226, 2008. [62] A. Abdellah, B. Fabel, P. Lugli, and electronics and sensors: A review of
G. Scarpa, BSpray deposition of organic fundamental and applied aspects,[
[44] P. Villard, U. Ebels, D. Houssameddine,
semiconducting thin-films: Towards the Adv. Mater., vol. 20, pp. 29–53, 2008.
J. Katine, D. Mauri, B. Delaet, P. Vincent,
fabrication of arbitrary shaped organic [78] N. Rouhi, D. Jain, and P. J. Burke,
M.-C. Cyrille, B. Viala, J.-P. Michel,
electronic devices,[ Organic Electron., BHigh-performance semiconducting
J. Prouvée, and F. Badets, BA GHz
vol. 11, no. 6, pp. 1031–1038, 2010. nanotube inks: Progress and prospects,[
spintronic-based RF oscillator,[ IEEE J.

1746 Proceedings of the IEEE | Vol. 100, May 13th, 2012

 Cavin et al.: Science and Engineering Beyond Moore’s Law

ACS Nano, vol. 5, no. 11, pp. 8471–8487, field-effect transistor,[ Nano Lett., [109] Z. X. Wang, H. L. Xu, Z. Y. Zhang, S. Wang,
2011. vol. 4, no. 7, pp. 1247–1252, 2004. L. Ding, Q. S. Zeng, L. J. Yang, T. A. Pei,
[79] S. M. Goetz, C. M. Erlen, H. Grothe, [95] W. Lu, P. Xie, and C. M. Lieber, X. L. Liang, M. Gao, and L. M. Peng,
W. Wolf, P. Lugli, and G. Scarpa, BOrganic BNanowire transistor performance limits and BGrowth and performance of yttrium oxide
field-effect transistors for biosensing applications,[ IEEE Trans. Electron Devices, as an ideal high-kappa gate dielectric for
applications,[ Organic Electron., vol. 10, vol. 55, no. 11, pp. 2859–2876, Nov. 2008. carbon-based electronic,[ Nano Lett., vol. 10,
no. 4, pp. 573–580, 2009. pp. 2024–2030, 2010.
[96] B. A. Sheriff, D. Wang, J. R. Heath, and
[80] J. A. Paradiso and T. Starner, BEnergy J. N. Kurtin, BComplementary symmetry [110] A. D. Franklin and Z. H. Chen, BLength
scavenging for mobile and wireless nanowire logic circuits: Experimental scaling of carbon nanotube transistors,[
electronics,[ Perv. Comput., vol. 4, pp. 18–27, demonstrations and in silico optimizations,[ Nature Nanotechnol., vol. 5, pp. 858–862,
2005. ACS Nano, vol. 2, no. 9, pp. 1789–1798D, 2010.
[81] J. Olivo, S. Carrara, and G. De Micheli, 2008. [111] L. Nougaret, H. Happy, G. Dambrine,
BEnergy harvesting and remote powering [97] Q. Zhang, W. Zhao, and A. Seabaugh, V. Derycke, J. P. Bourgoin, A. A. Green,
for implantable biosensors,[ IEEE Sensors J., BLow-subthreshold-swing tunnel and M. C. Hersam, B80 GHz field-effect
vol. 11, no. 7, pp. 1573–1586, Jul. 2011. transistors,[ IEEE Electron Device Lett., transistors produced using high purity
vol. 27, no. 4, pp. 297–300, Apr. 2006. semiconducting single-walled carbon
[82] C. Deibel, V. Dyakonov, and C. J. Brabec,
nanotubes,[ Appl. Phys. Lett., vol. 94,
BOrganic bulk-heterojunction solar cells,[ [98] S. O. Koswatta, M. S. Lundstrom, and
243505, 2009.
IEEE J. Sel. Topics Quantum Electron., vol. 16, D. E. Nikonov, BPerformance comparison
no. 6, pp. 1517–1527, Nov./Dec. 2010. between p-i-n tunneling transistors [112] L. Liao, Y.-C. Lin, M. Bao, R. Cheng, J. Bai,
and conventional MOSFETs,[ IEEE Trans. Y. Liu, Y. Qu, K. L. Wang, Y. Huang, and
[83] M. D. Stoller, S. Park, Y. Zhu,
Electron Devices, vol. 56, no. 3, pp. 456–465, X. Duan, BHigh-speed graphene transistors
J. An, and R. S. Ruoff, BGraphene-based
Mar. 2009. with a self-aligned nanowire gate,[ Nature,
ultracapacitors,[ Nano Lett., vol. 8, no. 10,
vol. 467, pp. 305–308, 2010.
pp. 3498–3502, 2008. [99] O. M. Nayfeh, C. N. Chleirigh, J. Hennessy,
L. Gomez, J. L. Hoyt, and D. A. Antoniadis, [113] D. Waldmann, J. Jobst, F. Speck, T. Seyller,
[84] A. I. Hochbaum and P. Yang,
BDesign of tunneling field-effect transistors M. Krieger, and H. B. Weber, BBottom-gated
BSemiconductor nanowires for energy
using strained-silicon/strained-germanium epitaxial graphene,[ Nature Mater., vol. 10,
conversion,[ Chem. Rev., vol. 110, no. 1,
type-II staggered heterojunctions,[ pp. 357–360, 2011.
pp. 527–546, 2010.
IEEE Electron Device Lett., vol. 29, no. 9, [114] I. Meric, M. Y. Han, A. F. Young,
[85] T. Ashley, M. T. Emeny, D. G. Hayes,
pp. 1074–1077, Sep. 2008. B. Ozyilmaz, P. Kim, and K. L. Shepard,
K. P. Hilton, R. Jefferies, J. O. Maclean,
[100] K. K. Bhuwalka, J. Schulze, and I. Eisele, BCurrent saturation in zero-bandgap,
S. J. Smith, A. W.-H. Tang, D. J. Wallis, and
BPerformance enhancement of vertical top-gated graphene field-effect transistors,[
P. J. Webber, BHigh-performance InSb
tunnel field-effect transistor with SiGe Nature Nanotechnol., vol. 3, pp. 654–659,
based quantum well field effect transistors
in the pþ layer,[ Jpn. J. Appl. Phys., 2008.
for low-power dissipation applications,[ in
IEEE Int. Electron Devices Meeting Tech. Dig., vol. 43, no. 7A, pp. 4073–4078, [115] X. S. Li, W. W. Cai, J. H. An, S. Kim, J. Nah,
2009, DOI: 10.1109/IEDM.2009.5424207. Jul. 2004. D. X. Yang, R. Piner, A. Velamakanni, I. Jung,
[101] K. Boucart, W. Riess, and A. M. Ionescu, E. Tutuc, S. K. Banerjee, L. Colombo, and
[86] L. Xia, J. B. Boos, B. R. Bennett,
BLateral strain profile as key technology R. S. Ruoff, BLarge-area synthesis of
M. G. Ancona, and J. A. del Alamo,
booster for all-silicon tunnel FETs,[ high-quality and uniform graphene films
BHole mobility enhancement in InGaSb
IEEE Electron Device Lett., vol. 30, no. 6, on copper foils science,[ Science, vol. 324,
quantum-well field-effect transistors,[
pp. 656–658, Jun. 2009. pp. 1312–1314, 2009.
Appl. Phys. Lett., vol. 98, 053505, 2011.
[102] J. Appenzeller, Y.-M. Lin, J. Knoch, and [116] M. C. Lemme, T. J. Echtermeyer, M. Baus,
[87] S. Hertenberger, D. Rudolph, M. Bichler,
P. Avouris, BBand-to-band tunneling in and H. Kurz, BA graphene field-effect
J. Finley, G. Abstreiter, and G. Koblmueller,
carbon nanotube field-effect transistors,[ device,[ IEEE Electron Device Lett., vol. 28,
BGrowth kinetics in position-controlled and
Phys. Rev. Lett., vol. 93, no. 19, no. 4, pp. 282–284, Apr. 2007.
catalyst-free InAs nanowire arrays on Si (111)
grown by selective area molecular beam pp. 196805-1–196805-4, 2004. [117] J. Kedzierski, P.-L. Hsu, P. Healey,
epitaxy,[ J. Appl. Phys., vol. 108, 2010, [103] A. C. Seabaugh and Q. Zhang, BLow-voltage P. W. Wyatt, C. L. Keast, M. Sprinkle,
DOI: 10.1063/1.3525610. tunnel transistors for beyond CMOS logic,[ C. Berger, and W. A. de Heer, BEpitaxial
Proc. IEEE, vol. 98, no. 12, pp. 2095–2110, graphene transistors on SiC substrates,[
[88] D. Kuzum, T. Krishnamohan, A. Nainani,
Dec. 2010. IEEE Trans. Electron Devices, vol. 55, no. 8,
Y. Sun, P. A. Panetta, H.-S. P. Wong, and
pp. 2078–2085, Aug. 2008.
K. C. Saraswat, BHigh-mobility Ge [104] K. Akarvardar, D. Elata, R. Parsa, G. C. Wan,
N-MOSFETs and mobility degradation K. Yoo, J. Provine, P. Peumans, R. T. Howe, [118] S. Bae, H. F. Kim, Y. Lee, X. F. Xu, J.-S. Park,
mechanisms,[ IEEE Trans. Electron Devices, and H.-S. P. Wong, BDesign considerations Y. Zheng, J. Balakrishnan, T. Lei, H. R. Kim,
vol. 59, no. 1, pp. 59–66, Jan. 2011. for complementary nanoelectromechanical Y. I. Song, Y.-J. Kim, K. S. Kim, B. Özyilmaz,
logic gates,[ in IEEE Int. Electron Devices J.-H. Ahn, B. H. Hong, and S. Iijima,
[89] H. Yan and P. Yang, BSemiconductor
Meeting Tech. Dig., 2007, pp. 299–302. Nature Nanotechnol., vol. 5, pp. 574–578,
nanowires: Functional building blocks
2010.
for nanotechnology,[ in The Chemistry [105] W. W. Jang, J. O. Lee, J.-B. Yoon, M.-S. Kim,
of Nanostructured Materials, P. Yang, Ed. J.-M. Lee, S.-M. Kim, K.-H. Cho, D.-W. Kim, [119] K. S. Novoselov, A. K. Geim, S. V. Morozov,
River Edge, NJ: World Scientific, 2004. D. Park, and W.-S. Lee, BFabrication and D. Jiang, Y. Zhang, S. V. Dubonos,
characterization of a nanoelectromechanical I. V. Grigorieva, and A. A. Firsov, BElectric
[90] J. Xiang, W. Lu, Y. Hu, Y. Wu,
switch with 15-nm-thick suspension air gap,[ field effect in atomically thin carbon films,[
H. Yan, and C. M. Lieber, BGe/Si nanowire
Appl. Phys. Lett., vol. 92, no. 10, 2008, Science, vol. 306, pp. 666–669, 2004.
heterostructures as high-performance
field-effect transistors,[ Nature, vol. 441, DOI: 10.1063/1.2892659. [120] X. Du, I. Skachko, A. Barker, and E. Y. Andrei,
pp. 489–493, 2006. [106] S. Fujita, K. Nomura, K. Abe, and T. H. Lee, BApproaching ballistic transport in suspended
B3-D nanoarchitectures with carbon graphene,[ Nature Nanotechnol., vol. 3,
[91] W. Lu and C. M. Lieber, BNanoelectronics
nanotube mechanical switches for future pp. 491–495, 2008.
from the bottom up,[ Nature Mater., vol. 6,
pp. 841–850, Nov. 2007. on-chip network beyond CMOS [121] C. R. Dean, A. F. Young, I. Meric, C. Lee,
architecture,[ IEEE Trans. Circuits Syst. I, L. Wang, S. Sorgenfrei, K. Watanabe,
[92] W. M. Weber, L. Geelhaar, A. P. Graham,
Reg. Papers, vol. 54, no. 11, pp. 2472–2479, T. Taniguchi, P. Kim, K. L. Shepard, and
E. Unger, G. S. Duesberg, M. Liebau,
Nov. 2007. J. Hone, BBoron nitride substrates for
W. Pamler, C. Chèze, H. Riechert, P. Lugli,
[107] Li, S.-M. Koo, M. D. Edelstein, J. S. Suehle, high-quality graphene electronics,[ Nature
and F. Kreupl, BSilicon-nanowire transistors
and C. A. Richter, BSilicon nanowire Nanotechnol., vol. 5, pp. 722–726, 2010.
with intruded nickel-silicide contacts,[
Nano Lett., vol. 6, pp. 2660–2666, 2006. electromechanical switches for logic [122] X. S. Li, C. W. Magnuson, A. Venugopal,
device application,[ Nanotechnology, J. H. An, J. W. Suk, B. Y. Han, M. Borysiak,
[93] L.-E. Wernersson, C. Thelander, E. Lind, and
vol. 18, 315202, 2007. W. W. Cai, A. Velamakanni, Y. W. Zhu,
L. Samuelson, BIII-V nanowiresVExtending
[108] L. Ding, A. Tselev, J. Y. Wang, D. N. Yuan, L. F. Fu, E. M. Vogel, E. Voelkl, L. Colombo,
a narrowing road,[ Proc. IEEE, vol. 98, no. 12,
H. B. Chu, T. P. McNicholas, Y. Li, and and R. S. Ruoff, BGraphene films with large
pp. 2047–2060, Dec. 2010.
J. Liu, BSelective growth of well-aligned domain size by a two-step chemical vapor
[94] H. T. Ng, J. Han, T. Yamada, P. Nguyen, deposition process,[ Nano Lett., vol. 10,
semiconducting single-walled carbon
Y. P. Chen, and M. Meyyappan, BSingle pp. 4328–4334, 2010.
nanotubes,[ Nano Lett., vol. 9, pp. 800–805,
crystal nanowire vertical surround-gate
2009.

Vol. 100, May 13th, 2012 | Proceedings of the IEEE 1747

Cavin et al.: Science and Engineering Beyond Moore’s Law

[123] X. L. Li, X. R. Wang, L. Zhang, S. W. Lee, and I.-K. Yoo, J.-S. Kim, and B.ã H. Park, BTwo Nanoelectron. Optoelectron., vol. 3, pp. 55–
H. J. Dai, BChemically derived, ultrasmooth series oxide resistors applicable to high speed 68, 2008.
graphene nanoribbon semiconductors,[ and high density nonvolatile memory,[ [155] S. Sugahara and J. Nitta, BSpin-transistor
Science, vol. 319, pp. 1229–1232, 2008. Adv. Mater., vol. 19, pp. 3919–3923, 2007. electronics: An overview and outlook,[
[124] L. O. Chua, BMemristorVThe missing [140] V. V. Zhirnov, R. Meade, R. K. Cavin, and Proc. IEEE, vol. 98, no. 12, pp. 2124–2154,
circuit element,[ IEEE Trans. Circuit Theory, G. Sandhu, BScaling limits of resistive Dec. 2010.
vol. CT-18, no. 5, pp. 507–519, Sep. 1971. memories,[ Nanotechnology, vol. 22, 254027, [156] S. P. Dash, S. Sharma, R. S. Patel,
[125] D. B. Strukov, G. S. Snider, D. R. Stewart, 2011. M. P. de Jong, and R. Jansen, BElectrical
and R. S. Williams, BThe missing memristor [141] Q. Xia, W. Robinett, M. W. Cumbie, creation of spin polarization in silicon at
found,[ Nature, vol. 453, pp. 80–83, 2008. N. Banerjee, T. J. Cardinali, J. J. Yang, room temperature,[ Nature, vol. 462,
[126] C. Scott and L. D. Bozano, BNonvolatile W. Wu, X. Li, W. M. Tong, D. B. Strukov, pp. 491–494, 2009.
memory elements based on organic G. S. Snider, G. Medeiros-Ribeiro, and [157] C. H. Li, O. M. J. van’t Erve, and B. T. Jonker,
materials,[ Adv. Mater., vol. 19, R. S. Williams, BMemristor-CMOS hybrid BElectrical injection and detection of spin
pp. 1452–1463, 2007. integrated circuits for reconfigurable logic,[ accumulation in silicon at 500 K with
Nano Lett., vol. 9, no. 10, pp. 3640–3645, magnetic metal/silicon dioxide contacts,[
[127] Heremans, G. H. Gelinck, R. Müller,
2009. Nature Commun., vol. 2, 2011, article 245.
K.-J. Baeg, D.-J. Kim, and Y.-Y. Noh,
BPolymer and organic nonvolatile memory [142] D. Kuzum, R. G. D. Jeyasingh, [158] H. C. Koo, J. H. Kwon, J. Eom, J. Chang,
devices,[ Chem. Mater., vol. 23, pp. 341–358, B. Lee, and H.-S. P. Wong, BNanoelectronic S. H. Han, and M. Johnson, BControl of spin
2011. programmable synapses based on phase precession in a spin-injected field effect
change materials for brain-inspired transistor,[ Science, vol. 325, pp. 1515–1518,
[128] S. Song, B. Cho, T.-W. Kim, Y. Ji, M. Jo,
computing,[ Nano Lett., 2011, Sep. 2009.
G. Wang, M. Choe, Y. H. Kahng, H. Hwang,
DOI: 10.1021/nl201040y.
and T. Lee, BThree-dimensional integration [159] A. Khitun, D. E. Nikonov, and K. L. Wang,
of organic resistive memory devices,[ Adv. [143] S. H. Jo, T. Chang, I. Ebong, B. B. Bhadviya, BMagnetoelectric spin wave amplifier for
Mater., vol. 22, pp. 5048–5052, 2010. P. Mazumder, and W. Lu, BNanoscale spin wave logic circuits,[ J. Appl. Phys.,
memristor device as synapse in vol. 106, 2009, DOI: 10.1063/1.3267152.
[129] T. Lee, L.-Z. Yu, and H.-C. Chen, BMemory
neuromorphic systems,[ Nano Lett.,
bistable mechanisms of organic memory [160] A. Imre, G. Csaba, L. Ji, A. Orlov,
vol. 10, no. 4, pp. 1297–1301, 2010.
devices,[ Appl. Phys. Lett., vol. 97, 043301, G. H. Bernstein, and W. Porod, BMajority
2010. [144] H. Song, M. A. Reed, and T. Lee, BSingle logic gate for magnetic quantum-dot cellular
molecule electronic devices,[ Adv. Mater., automata,[ Science, vol. 311, no. 5758,
[130] R. Waser and M. Aono, BNanoionics-based
vol. 23, pp. 1583–1608, 2011. pp. 205–208, 2006.
resistive switching memories,[ Nature
Mater., vol. 6, pp. 833–840, 2007. [145] M. A. Reed, J. Chen, A. M. Rawlett, [161] E. Varga, A. Orlov, M. T. Niemier,
D. W. Price, and J. M. Tour, BMolecular X. S. Hu, G. H. Bernstein, and W. Porod,
[131] T. Sakamoto, H. Sunamura, H. Kawaura,
random access memory cell,[ Appl. Phys. BExperimental demonstration of fanout
T. Hasegawa, T. Nakayama, and M. Aono,
Lett., vol. 78, no. 23, pp. 3735–3737, 2001. for nanomagnetic logic,[ IEEE Trans.
BNanometer-scale switches using copper
sulfide,[ Appl. Phys. Lett., vol. 82, [146] M. Tour, L. Cheng, D. P. Nackashi, Y. X. Yao, Nanotechnol., vol. 9, no. 6, pp. 668–670,
pp. 3032–3034, 2003. A. K. Flatt, S. K. St Angelo, T. E. Mallouk, Dec. 2010.
and P. D. Franzon, BNanoCell electronic [162] M. T. Alam, M. J. Siddiq, G. H. Bernstein,
[132] S. Kaeriyama, T. Sakamoto, H. Sunamura,
memories,[ J. Amer. Chem. Soc., vol. 125, M. Niemier, W. Porod, and X. S. Hu,
M. Mizuno, H. Kawaura, T. Hasegawa,
pp. 13 279–13 283, 2003. BOn-chip clocking for nanomagnet logic
K. Terabe, T. Nakayama, and M. Aono, BA
nonvolatile programmable solid-electrolyte [147] C. N. Lau, D. R. Stewart, R. S. Williams, devices,[ IEEE Trans. Nanotechnol., vol. 9,
nanometer switch,[ IEEE J. Solid-State and M. Bockrath, BDirect observation no. 3, pp. 348–351, May 2010.
Circuits, vol. 40, no. 1, pp. 168–176, of nanoscale switching centers in metal/ [163] G. L. Snider, A. O. Orlov, I. Amlani, X. Zuo,
Jan. 2005. molecule/metal structures,[ Nano Lett., G. H. Bernstein, C. S. Lent, J. L. Merz, and
vol. 4, pp. 569–657, 2004. W. Porod, BQuantum-dot cellular automata:
[133] T. Sakamoto, N. Iguchi, and M. Aono,
BNonvolatile triode switch using [148] J. E. Green, J. W. Choi, A. Boukai, Review and recent experiments,[ J. Appl.
electrochemical reaction in copper Y. Bunimovich, E. Johnston-Halperin, Phys., vol. 85, no. 8, pp. 4283–4285,
sulfide,[ Appl. Phys. Lett., vol. 96, 2010, E. Delonno, Y. Luo, B. A. Sheriff, K. Xu, 1999.
DOI: 10.1063/1.3457861. Y. Shik Shin, H.-R. Tseng, J. F. Stoddart, [164] V. Zhirnov, R. Cavin, G. Leeming, and
and J. R. Heath, BA 160-kilobit molecular K. Galatsis, BAn assessment of integrated
[134] I. Valov, R. Waser, J. R. Jameson, and
electronic memory patterned at 1011 bits digital cellular automata architectures,[
M. N. Kozicki, BElectrochemical
per square centimetre,[ Nature, vol. 445, IEEE Computer, vol. 41, no. 1, pp. 38–44,
metallization memories-fundamentals,
pp. 414–441, 2007. Jan. 2008.
applications, prospects,[ Nanotechnology,
vol. 22, 254003, 2011. [149] T. Pro, J. Buckley, K. Huang, A. Calborean, [165] B. Behin-Aein, D. Datta, S. Salahuddin, and
M. Gely, G. Delapierre, G. Ghibaudo, S. Datta, BProposal for an all-spin logic
[135] R. Waser, R. Dittman, G. Staikov, and
F. Duclairoir, J.-C. Marchon, E. Jalaguier, device with built-in memory,[ Nature
K. Szot, BRedox-based resistive switching
P. Maldivi, B. De Salvo, and S. Deleonibus, Nanotechnol., vol. 5, pp. 266–270, 2010.
memoriesVNanoionic mechanisms,
BInvestigation of hybrid molecular/silicon
prospects, and challenges,[ Adv. Mater., [166] N. G. Cooper, BFrom Turing and
memories with redox-active molecules
vol. 21, pp. 2632–2663, 2009. von Neumann to the present,[ Los Alamos
acting as storage media,[ IEEE Trans.
[136] H. Akinaga and H. Shima, BResistive random Sci., pp. 22–27, Fall, 1983.
Nanotechnol., vol. 8, no. 2, pp. 204–212,
access memory (ReRAM) based on metal Mar. 2009. [167] J. von Neumann, Theory of Self-Reproducing
oxides,[ Proc. IEEE, vol. 98, no. 12, Automata. Chicago, IL: Univ. Illinois Press,
[150] E. Lörtscher, J. W. Ciszek, J. Tour, and
pp. 2237–3225, Dec. 2010. 1966.
H. Riel, BReversible and controllable
[137] M.-J. Lee, C. B. Lee, D. Lee, S. R. Lee, switching of a single-molecule junction,[ [168] S. Ji, BThe cell as the smallest DNA-based
M. Chang, J. H. Hur, Y.-B. Kim, C.-J. Kim, Small, vol. 2, no. 8–9, pp. 973–977, 2006. molecular computer,[ Biosystems, vol. 52,
D. H. Seo, S. Seo, U.-I. Chung, I.-K. Yoo, and pp. 123–133, 1999.
[151] G. Csaba and P. Lugli, BRead-out design
K. Kim, BA fast, high-endurance and scalable [169] A. Danchin, BBacteria as computer making
rules for molecular crossbar architectures,[
non-volatile memory device made from computers,[ FEMS Microbiol. Rev., vol. 33,
IEEE Trans. Nanotechnol., vol. 8, no. 3,
asymmetric Ta2 O5x /TaO2x bilayer pp. 3–26, 2009.
pp. 369–374, May 2009.
structures,[ Nature Mater., vol. 10,
[152] C. S. Lent, B. Isaksen, and M. Lieberman, [170] C. T. Fernando, A. M. L. Liekens,
pp. 625–630, 2011.
BMolecular quantum-dot cellular automata,[ L. E. H. Bingle, C. Beck, T. Lenser,
[138] R. Rosezin, E. Linn, L. Nielen, C. Kugeler, D. J. Stekel, and J. E. Rowe, BMolecular
J. Amer. Chem. Soc., vol. 125, no. 4,
R. Bruchhaus, and R. Waser, BIntegrated circuits for associative learning in
pp. 1056–1063, 2033.
complementary resistive switches for passive single-celled organisms,[ J. Roy. Soc.
high-density nanocross arrays,[ Electron [153] J. Akerman, BTowards a universal memory,[
Interface, vol. 6, pp. 463–469, 2009.
Device Lett., vol. 32, no. 2, pp. 191–193, Science, vol. 308, pp. 508–510, 1721.
[171] D. Bray, BProtein molecules as
Feb. 2011. [154] A. Orlov, A. Imre, G. Csaba, L. Ji,
computational elements in living cells,[
[139] M. J. Lee, Y. Park, D.-S. Suh, E.-H. Lee, W. Porod, and G. H. Bernstein,
Nature, vol. 376, pp. 307–312, 1995.
S. Seo, D.-C. Kim, R. Jung, B.-S. Kang, BMagnetic quantum-dot cellular automata:
S.-E. Ahn, C.ã B. Lee, D.ã H. Seo, Y.-K. Cha, Recent developments and prospects,[ J.

1748 Proceedings of the IEEE | Vol. 100, May 13th, 2012

 Cavin et al.: Science and Engineering Beyond Moore’s Law

[172] N. Ramakrishnan, U. S. Bhalla, and [176] R. U. Ayres, Information, Entropy and [180] D. J. D’Onofrio and G. An, BA comparative
J. J. Tyson, BComputing with proteins,[ Progress. New York: AIP, 1994. approach for the investigation of biological
Computer, vol. 42, pp. 47–56, 2009. [177] University of WisconsinVMadison, information processing: An examination
[173] L. F. Agnati, D. Guidolin, C. Carone, The Microbial World. [Online]. Available: of the structure and function of computer
M. Dam, S. Genedani, and K. Fuxe, http://textbookofbacteriology.net/ hard drives and DNA,[ Theor. Biol. Med.
BUnderstanding neuronal cellular themicrobialworld/nutgro.html. Model, vol. 7, pp. 3–20, 2010.
network architecture,[ Brain Res. Rev., vol. [178] J. von Neumann, The Computer and the [181] L. G. Valiant, BA quantitative theory of
58, pp. 379–399, 2008. Brain. New Haven, CT: Yale Univ. Press, neural computation,[ Biol. Cybern., vol. 95,
[174] A. Wagner, BFrom bit to it: How a complex 1959. no. 3, pp. 205–211, 2006.
metabolic network transforms information [179] G. Bate, BBits and genes: A comparison [182] R. P. Feynman, Miniaturization,
into living matter,[ BMC Syst. Biol., vol. 1, of the natural storage of information D. H. Gilbert, Ed. New York: Reinhold,
2007, DOI: 10.1186/1752-0509-1-33. in DNA and digital magnetic recording,[ 1961, pp. 282–296.
[175] S. Ji, BFree energy and information IEEE Trans. Magn., vol. MAG-14, no. 5,
content of Conformons in protein and pp. 964–965, Sep. 1978.
DNA,[ Biosystems, vol. 54, pp. 107–130,
2000.

ABOUT THE AUTHORS

Ralph K. Cavin, III (Life Fellow, IEEE) received the created Institute for Nanoelectronics. His current research interests
B.S.E.E. and M.S.E.E. degrees from Mississippi involve, besides nano imprint lithography, the modeling, fabrication, and
State University, Starkville, in 1961 and 1962, characterization of organic devices for electronics and optoelectronics
respectively, and the Ph.D. degree in electrical applications, the design of circuits and architectures for nanostructures
engineering from Auburn University, Auburn, AL, and nanodevices, the numerical simulation of microwave semiconductor
in 1968. devices, and the theoretical study of transport processes in nanostruc-
He was Senior Engineer at the Martin-Marietta tures. He is the author of more than 250 scientific papers and the
Company, Orlando, FL, from 1962 to 1965. In 1968, coauthor of the books The Monte Carlo Modelling for Semiconductor
he joined the faculty of the Department of Device Simulations (New York: Springer-Verlag, 1989) and High Speed
Electrical Engineering, Texas A&M University, Optical Communications (Norwell, MA: Kluver, 1999).
College Station, obtaining the rank of Full Professor. In 1983, he joined Dr. Lugli served as General Chairman of the IEEE International Con-
the Semiconductor Research Corporation, Triangle Park, NC, as Director ference on Nanotechnology held in Munich, Germany, in 2004. He is a
of Design Sciences. He became Head of the Department of Electrical and member of the German BNational Academy of Science and Engineering[
Computer Engineering from 1989 to 1994 and Dean of Engineering at (ACATECH).
North Carolina State University, Raleigh, from 1994 to 1995. He served as
the Semiconductor Research Corporation Vice President for Research
Operations from 1996 to 2007 and is currently the SRC Chief Scientist. His Victor V. Zhirnov received the M.S. degree in
technical interests span very large-scale integration (VLSI) design, applied physics from the Ural Polytechnic Insti-
advanced information processing technologies, semiconductor device tute, Ekaterinburg, Russia, in 1989 and the Ph.D. in
and technology limits, and control and signal processing. He has solid state electronics and microelectronics from
authored or coauthored over 100 refereed technical papers and the Institute of Physics and Technology, Moscow,
contributions to books. He has served as an advisor to a number of Russia, in 1992.
government, industrial, and academic institutions. He is the Director of Special Projects at the
Semiconductor Research Corporation, Triangle
Paolo Lugli (Fellow, IEEE) graduated in physics Park, NC, which he joined in 2004. He holds
from the University of Modena, Modena, Italy, in adjunct faculty position at North Carolina State
1979. He received the M.Sci. and Ph.D. degrees in University, Raleigh, and has served as an advisor to a number of govern-
electrical engineering from Colorado State Univer- ment, industrial, and academic institutions. From 1992 to 1998, he was a
sity, Fort Collins, in 1982 and 1985, respectively. Senior Scientist at the Institute of Crystallography, Russian Academy of
In 1985, he joined the Physics Department, Science, Moscow, Russia. From 1998 to 2004, he was a Research Pro-
University of Modena, as a Research Associate. fessor at North Carolina State University. His research interests include
From 1988 to 1993, he was an Associate Professor nanoelectronics devices and systems, properties of materials at the
of BSolid State Physics[ at the BEngineering nanoscale, bio-inspired electronic systems, etc. He has authored and
Faculty[ of the 2nd University of Rome BTor coauthored over 100 technical papers and contributions to books.
Vergata,[ Rome, Italy, where in 1993, he was appointed as Full Professor Dr. Zhirnov is the Chair of the Emerging Research Device (ERD)
of BOptoelectronics.[ In 2002, he joined the Technische Universität Working Group for the International Technology Roadmap for Semi-
München, Munich, Germany, where he was appointed Head of the newly conductors (ITRS).

Vol. 100, May 13th, 2012 | Proceedings of the IEEE 1749