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Computer Organization

The document discusses encoding instructions for a processor with 12-bit instructions and 32 registers. It asks if it is possible to encode 3 two-address, 30 one-address, and 45 zero-address instructions. It also asks about the minimum number of bits needed to encode instructions for a computer that allows only 2-address instructions with one operand as a register and the other as a memory location, given the computer has 50 registers, 55 total instructions, and 64KB of byte-addressable memory. Several other questions are asked about effective memory addresses and memory consumption for instructions.

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shubham
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139 views4 pages

Computer Organization

The document discusses encoding instructions for a processor with 12-bit instructions and 32 registers. It asks if it is possible to encode 3 two-address, 30 one-address, and 45 zero-address instructions. It also asks about the minimum number of bits needed to encode instructions for a computer that allows only 2-address instructions with one operand as a register and the other as a memory location, given the computer has 50 registers, 55 total instructions, and 64KB of byte-addressable memory. Several other questions are asked about effective memory addresses and memory consumption for instructions.

Uploaded by

shubham
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Assignment-1

Consider the case of a processor with an instruction length of 12 bits and with 32 general-
purpose register so the size of the address fields is 5 bits. Is it possible to have instruction
encodings for the following?

3 two-address instructions

30 one-address instructions

45 zero-address instructions

There are 50 registers, and total 55 instructions available in a generalpurpose computer.


The computer allows only 2-address instructions, where one operand can be a register and
another can be a memory location. The memory is byte addressable with 64KB (Kilo
bytes) in size. Find the minimum number of bits to encode the instruction?

Registers R1 and R2 contain data values 1800 and 3800 respectively in decimal, and the
word length of the processor is 4 bytes. The effective address of the memory operand for
the instruction “ADD 100(R2),R6” will be_________________

Registers R1 and R2 contain data values 600 and 800 respectively in decimal, and the
word length of the processor is 4 bytes. The effective address of the memory operand for
the instruction “LOAD R5,10(R1,R2)” will be___________________________

Consider a processor with 64 registers and an instruction set of size 12. Each instruction
has 5 distinct fields, namely opcode, two-source register identifiers, one destination
register identifier, and a 12-bit immediate value. Each instruction must be stored in
memory in a byte-aligned fashion (i.e. from an address that is a multiple of 4). If a
program has 100 instructions, the amount of memory consumed by the program
is_____________ bytes

Consider a processor with 64 registers and an instruction set of size twelve. Each
instruction has five distinct fields, namely, opcode, two source register identifiers, one
destination register identifier, and a twelve-bit immediate value. Each instruction must
be stored in memory in a byte-aligned fashion. If a program has 100 instructions, the
amount of memory (in bytes) consumed by the program text is ____________.

A machine has a 32-bit architecture, with 1-word long instructions. It has 64 registers,
each of which is 32 bits long. It needs to support 45 instructions, which have an
immediate operand in addition to two register operands. Assuming that the immediate
operand is an unsigned integer, the maximum value of the immediate operand is
___________. 
A computer has 32-bit instructions and 12-bit addresses. There are 250 two address
instructions. How many one address instructions can be formulated?
Assignment-2

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