19EL013
Full adder using data flow and gate level
Full adder using data flow Modelling Code :
module fulladd ( // module and name
input A, B, // I. port declarations
input Cin,
output Cout,
output wire Sum );
assign {Cout, Sum} = A + B + Cin;
endmodule
Full adder using gate level Modelling Code :
module fulladd(a, b, c_in,c_out,sum);
output sum, c_out;
input a, b, c_in;
wire s1, c1, c2;
xor (s1, a, b);
xor (sum, s1, c_in);
and (c1, a, b);
and (c2, s1, c_in);
or (c_out, c2, c1);
endmodule
Test Bench :
module testcomp;
reg a_tb, b_tb;
reg Cin;
wire y_tb;
wire Co_tb;
fulladd and_1(a_tb, b_tb,Cin,Co_tb,y_tb );
initial begin
a_tb=0; b_tb=0; Cin=0; #50;
$display("a_tb\tb_tb\tCin\ty_tb\tCo_tb\t");
$display("%b\t%b\t%b\t%b\t%b\t",a_tb, b_tb, Cin, y_tb, Co_tb);
a_tb=0; b_tb=0; Cin=1; #50;
$display("%b\t%b\t%b\t%b\t%b\t",a_tb, b_tb, Cin, y_tb, Co_tb);
a_tb=0; b_tb=1; Cin=0; #50;
$display("%b\t%b\t%b\t%b\t%b\t",a_tb, b_tb, Cin, y_tb, Co_tb);
a_tb=0; b_tb=1; Cin=1;#50;
$display("%b\t%b\t%b\t%b\t%b\t",a_tb, b_tb, Cin, y_tb, Co_tb);
a_tb=1; b_tb=0; Cin=0; #50;
$display("%b\t%b\t%b\t%b\t%b\t",a_tb, b_tb, Cin, y_tb, Co_tb);
a_tb=1; b_tb=0; Cin=1; #50;
$display("%b\t%b\t%b\t%b\t%b\t",a_tb, b_tb, Cin, y_tb, Co_tb);
a_tb=1; b_tb=1; Cin=0; #50;
$display("%b\t%b\t%b\t%b\t%b\t",a_tb, b_tb, Cin, y_tb, Co_tb);
a_tb=1; b_tb=1; Cin=1;#50;
$display("%b\t%b\t%b\t%b\t%b\t",a_tb, b_tb, Cin, y_tb, Co_tb);
end
//enabling the wave dump
initial begin
$dumpfile("dump.vcd"); $dumpvars;
end
endmodule
19EL013
4x1 mux using data flow, gate level and behavioural design style
Using Data Flow Modelling Code :
module mux4_to_1 (out, i0, i1, i2, i3, s1, s0);
// Port declarations from the I/O diagram
output out;
input i0, i1, i2, i3;
input s1, s0;
// Use nested conditional operator
assign out = s1 ? ( s0 ? i3 : i2) : (s0 ? i1 : i0) ;
endmodule
Using Gate Level Modelling Code :
module mux4_to_1 (out, i0, i1, i2, i3, s1, s0);
output out;
input i0, i1, i2, i3;
input s1, s0;
wire s1n, s0n;
wire y0, y1, y2, y3;
not (s1n, s1);
not (s0n, s0);
and (y0, i0, s1n, s0n);
and (y1, i1, s1n, s0);
and (y2, i2, s1, s0n);
and (y3, i3, s1, s0);
or (out, y0, y1, y2, y3);
endmodule
Using behavioural Modelling Code :
module mux4_to_1 (out, i0, i1, i2, i3, s1, s0);
output out;
input i0, i1, i2, i3;
input s1, s0;
reg out;
always @(s1 or s0 or i0 or i1 or i2 or i3)
begin
case ({s1, s0})
2'b00: out = i0;
2'b01: out = i1;
2'b10: out = i2;
2'b11: out = i3;
default: out = 1'bx;
endcase
end
endmodule
Test Bench :
module stimulus;
reg IN0, IN1, IN2, IN3;
reg S1, S0;
mux4_to_1 mymux(OUTPUT, IN0, IN1, IN2, IN3, S1, S0);
// Stimulate the inputs
// Define the stimulus module (no ports)
initial
begin
// set input lines
IN0 = 1; IN1 = 0; IN2 = 1; IN3 = 0;
#1 $display("IN0= %b, IN1= %b, IN2= %b, IN3= %b\n",IN0,IN1,IN2,IN3);
// choose IN0
S1 = 0; S0 = 0;
#1 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1, S0, OUTPUT);
// choose IN1
S1 = 0; S0 = 1;
#1 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1, S0, OUTPUT);
// choose IN2
S1 = 1; S0 = 0;
#1 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1, S0, OUTPUT);
// choose IN3
S1 = 1; S0 = 1;
#1 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1, S0, OUTPUT);
end
initial begin
$dumpfile("dump.vcd"); $dumpvars;
end
endmodule
19EL013
3x8 decoder using gate level and behavioural
Using Gate Level Modelling
Code :
module decoder(a,b,c, D0, D1, D2, D3,D4, D5, D6, D7);
input a,b,c;
output D0, D1, D2, D3,D4, D5, D6, D7;
wire abar,bbar,cbar;
// Gate Level Modeling
not(abar,a);
not(bbar,b);
not(cbar,c);
and(D0,abar,bbar,cbar);
and(D1,abar,bbar,c);
and(D2,abar,b,cbar);
and(D3,abar,b,c);
and(D4,a,bbar,cbar);
and(D5,a,bbar,c);
and(D6,a,b,cbar);
and(D7,a,b,c);
endmodule
Test Bench :
module top;
reg a,b,c;
wire D0, D1, D2, D3,D4, D5, D6, D7;
decoder and_1(a,b,c, D0, D1, D2, D3,D4, D5, D6, D7);
initial begin
a = 0; b = 0; c = 0; #50; // Assign values and some delay
$display("A\tB\tC|\tD0\tD1\tD2\tD3\tD4\tD5\tD6\tD7\t");
$display("----------------------------------------------------------------------------------");
$display("%d\t%d\t%d|\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t", a, b, c, D0, D1, D2, D3,D4,D5,D6,D7);
a = 0; b = 0; c = 1; #50;
$display("%d\t%d\t%d|\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t", a, b, c, D0, D1, D2, D3,D4,D5,D6,D7);
a = 0; b = 1; c = 0; #50;
$display("%d\t%d\t%d|\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t", a, b, c, D0, D1, D2, D3,D4,D5,D6,D7);
a = 0; b = 1; c = 1; #50;
$display("%d\t%d\t%d|\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t", a, b, c, D0, D1, D2, D3,D4,D5,D6,D7);
a = 1; b = 0; c = 0; #50;
$display("%d\t%d\t%d|\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t", a, b, c, D0, D1, D2, D3,D4,D5,D6,D7);
a = 1; b = 0; c = 1; #50;
$display("%d\t%d\t%d|\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t", a, b, c, D0, D1, D2, D3,D4,D5,D6,D7);
a = 1; b = 1; c = 0; #50;
$display("%d\t%d\t%d|\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t", a, b, c, D0, D1, D2, D3,D4,D5,D6,D7);
a = 1; b = 1; c = 1; #50;
$display("%d\t%d\t%d|\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t", a, b, c, D0, D1, D2, D3,D4,D5,D6,D7);
end
//enabling the wave dump
initial begin
$dumpfile("dump.vcd"); $dumpvars;
end
endmodule
Using behavioural Modelling
Code :
module decoder(in,out);
input [2:0] in;
output [7:0] out;
reg [7:0] out;
//Behavioral Modeling
always @(in)
case ({in})
3'b000 : out = 8'b00000001;
3'b001 : out = 8'b00000010;
3'b010 : out = 8'b00000100;
3'b011 : out = 8'b00001000;
3'b100 : out = 8'b00010000;
3'b101 : out = 8'b00100000;
3'b110 : out = 8'b01000000;
3'b111 : out = 8'b10000000;
//Default
default: out = 8'b00000000;
endcase
endmodule
Test Bench :
module top;
reg [2:0] in;
wire [7:0] out;
decoder and_1(in,out);
initial begin
in = 3'b000; #100;
$display("A\tB\tC|\tD0\tD1\tD2\tD3\tD4\tD5\tD6\tD7\t");
$display("----------------------------------------------------------------------------------");
$display("%d\t%d\t%d|\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t",
in[0],in[1],in[2],out[0],out[1],out[2],out[3],out[4],out[5],out[6],out[7]);
in = 3'b001; #100;
$display("%d\t%d\t%d|\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t",
in[0],in[1],in[2],out[0],out[1],out[2],out[3],out[4],out[5],out[6],out[7]);
in = 3'b010; #100;
$display("%d\t%d\t%d|\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t",
in[0],in[1],in[2],out[0],out[1],out[2],out[3],out[4],out[5],out[6],out[7]);
in = 3'b011; #100;
$display("%d\t%d\t%d|\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t",
in[0],in[1],in[2],out[0],out[1],out[2],out[3],out[4],out[5],out[6],out[7]);
in = 3'b100; #100;
$display("%d\t%d\t%d|\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t",
in[0],in[1],in[2],out[0],out[1],out[2],out[3],out[4],out[5],out[6],out[7]);
in = 3'b101; #100;
$display("%d\t%d\t%d|\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t",
in[0],in[1],in[2],out[0],out[1],out[2],out[3],out[4],out[5],out[6],out[7]);
in = 3'b110; #100;
$display("%d\t%d\t%d|\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t",
in[0],in[1],in[2],out[0],out[1],out[2],out[3],out[4],out[5],out[6],out[7]);
in = 3'b111; #100;
$display("%d\t%d\t%d|\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t",
in[0],in[1],in[2],out[0],out[1],out[2],out[3],out[4],out[5],out[6],out[7]);
end
//enabling the wave dump
initial begin
$dumpfile("dump.vcd"); $dumpvars;
end
endmodule
