Experiment No.
5,
SIMULATION OF DPSK
Aim: To plot the Bit Error Rate (BER) of Differential Phase Shift Keying (DPSK) signal using OCTAVE
Online.
Generation of DPSK signal
Differential phase shift keying (DPSK) is a common type of phase modulation that conveys data by
changing the phase of the carrier wave. In DPSK the phase of the modulated signal is shifted relative to the
previous signal element. The signal phase follows the high or low state of the previous element. DPSK does not
need a synchronous (coherent) carrier at the demodulator. The input sequence of binary bits is modified such that
the next bit depends upon the previous bit. Therefore, in the receiver, the previous received bits are used to detect
the present bit.
It can seen from the above figure that, when the data bit is Low i.e., ‘0’, the phase of the signal is not reversed,
and continued as it was. When the data is a High i.e., ‘1’, the phase of the signal is reversed. If we observe the
above waveform, we can say that the High state represents an M in the modulating signal and the Low state
represents a W in the modulating signal.
DPSK Transmitter
DPSK is a technique of BPSK, in which there is no reference phase signal. In this case, the transmitted signal
itself is used as a reference signal. The serial data input b(t) is applied to the input of the encoder.
The output of the encoder is applied to one of the input of the product modulator. To the other input of this
product modulator, a sinusoidal carrier of fixed amplitude and frequency is applied.
DPSK Receiver
The received DPSK signal is applied to one input of the multiplier and a delayed version of the received
DPSK signal by the time interval Tb is applied to the other input of the multiplier. The output of the difference is
proportional to cos(Φ) , here Φ is the difference between the carrier phase angle of the received DPSK signal and
its delayed version, measured in the same bit interval. The phase difference between the two sequences for each
bit interval is used to determine the sign of the phase comparator output. When Φ =0, the integrator output is
positive whereas when Φ=π, the integrator output is negative. By comparing the integrator output with a decision
level of zero volt, the decision device can reconstruct the binary sequence by assigning a symbol ‘0’ for negative
output and a symbol ‘1’ for positive output.
Algorithm Initialization
commands DPSK BER
Plotting:
1. Generate carrier signal.
2. Start FOR loop
3. Generate binary data, message signal in polar form with XNOR operation.
4. Generate DPSK modulated signal.
5. Plot message signal and PSK modulated signal.
6. End FOR loop.
7. Plot the binary data and carrier.
Program
clc;
clear all;
close all;
N=10^3
rand('state',100); rand('state',200);
ip=rand(1,N)>0.5,ipD=mod(filter(1,[1 -1],ip),2);
s=2*ipD-1;
n=1/sqrt(2)*[randn(1,N)+j*randn(1,N)]; Eb_N0_db=[-3:10];
for ii=1:length(Eb_N0_db)
y=s+10^(-Eb_N0_db(ii)/20)*n;
ipDHat_coh=real(y)>0;
ipHat_coh=mod(filter([1 -1],1,ipDHat_coh),2);
nErr_dbpsk_coh(ii)=size(find([ip-ipHat_coh]),2);
end
simBer_dbpsk_coh=nErr_dbpsk_coh/N;
theoryBer_dbpsk_coh=erfc(sqrt(10.^(Eb_N0_db/10))).*(1-5*erfc(sqrt(10.^(Eb_N0_db/10))));
close all;
figure
semilogy(Eb_N0_db,theoryBer_dbpsk_coh,'b.-');
hold on;
semilogy(Eb_N0_db,simBer_dbpsk_coh,'mx-');
aixs([-2 10 10^-6 0.5]);
grid on;
legend('theory','simulation');
xlabel('Eb/N0,db');ylabel('bit error rate');
title('bit error probability curve for coherent demodulation of dbpsk');
Model Graph
Output Waveform
Result
Thus the BER program for DPSK has been simulated and the necessary graph was plotted.