Technology Overview

How to Design a
GaN PA MMIC

This white paper describes how to

design a custom GaN PA MMIC
using a commercially available
GaN-on-SiC foundry process. It
uses an X-band PA requirement
as the design example, and runs
through the design process step-
by-step to the point of having a
completed MMIC layout ready
for manufacture. It commences
with selection of the most
appropriate GaN MMIC process
then moves on to transistor level
simulations including load-pull
analysis to determine the Figure 1: Active phased array radars need a solid-state PA for each
optimum impedances at both element
fundamental and harmonics. This
leads on to the detailed schematic PA application MMIC offers advantages in all of these
design and MMIC layout method- The example PA used to illustrate the areas.
ology. Finally the approach for design process is an X-band (8 –
performing electromagnetic (EM) 12GHz) PA for a phased array radar ap- Advantages of GaN-on-SiC
simulation and layout optimis- plication. X-band radar applications in- GaN-on-SiC has become the techno-
ation is described. clude weather surveillance radar, milit- logy of choice for high-power solid
ary radar, and those used for air-traffic state amplifiers. In addition to high
control. Increasingly these are active power density and high efficiency, us-
aperture phased array radars, for which ing GaN devices in a PA also enables
multiple solid-state PAs are needed, as operation at a high voltage, which
shown on the right-hand side in Figure means that it can be matched to higher
1. The active array approach enables output impedances compared to other
the radar to position the beam much device technologies such as GaAs. This
more rapidly using electronic steering means that matching networks can be
rather than traditional mechanical simpler, reducing transmission line
steering, and can generate multiple in- losses. The higher voltage also means
dependent beams. that they can operate at lower current
levels, reducing I²R losses. The power
There may be hundreds or even thou- density of GaN is four to five times
sands of elements in an active phased higher than that of GaAs, which means
array, so even a small improvement in that the MMICs can be smaller, result-
PA efficiency or a reduction in size and ing in a compact, lightweight final
weight will have a massively beneficial design with good reliability. The SiC
effect on the performance of the entire substrate has high thermal conductivity,
system. Realising the PA as a GaN making it easy to remove heat from the

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 Table 1: Example PA specification for phased array radar application

device, and allows the device to operate with a target small-signal gain of 25dB. the transistors and passive components
at higher channel temperatures for the For a phased array radar application, provided by the foundry are valid and
same mean time to failure (MTTF). the power amplifier is run highly com- accurate over the required frequency
pressed, so the output power is spe- range so that the final PA will give a
Design steps cified at 4dB compression with a target good agreement with the simulation.
The design begins with the selection of of +40dBm and power added efficiency
the process and then moves onto device (PAE) of greater than 30%. Input return Having established that GaN-on-SiC is
level simulations, selecting the tran- loss should be better than 10dB, and the very well suited for the planned applic-
sistor unit cell size, the bias point, and operating voltage is set at 28V. ation, and for microwave PAs in gen-
the load and source impedances. This eral, there are a number of commer-
preliminary transistor analysis data is Selecting the most appropriate MMIC cially available processes that could be
then used to determine the number of process for the intended application is considered. For this design the Wolf-
stages needed to meet the specification, very important if optimum PA perform- speed V5 process was selected. Table 2
the number of transistors in the output ance is to be obtained. The maximum summarises the process capabilities;
stage, and the ratio between the driver operating frequency of the process, the GMAX and power density figures are
transistor(s) and the output transistors. required gain, operating voltage and quoted at 30GHz and will be signific-
From here, the detailed schematic power density must all be assessed. An- antly better at 10GHz. The MTTF
design can be performed with optimisa- other consideration is to ensure that the (Mean Time To Failure) is quoted as
tion of bias networks and matching net- Process Design Kit (PDK) models for 106 hours at 225°C. To achieve the
works. A preliminary layout can then
be produced from the schematic design
and EM simulations are conducted to
optimise and finalise the design. The
layout is run through a design rule
checker (DRC) to make sure that the
foundry will be able to fabricate the
design.

Specification and process selection

Table 1 gives a top level specification
for a PA, which was used as the design
example. The amplifier requires a
2GHz bandwidth centred on 10GHz, Table 2: Wolfspeed V5 process capability overview

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 Figure 2: Wolfspeed G28V5 GaN-on-SiC process

same reliability from a GaAs device it

would need to be running at about
150°C, so there is a significant advant-
age in using GaN-on-SiC for this ap-
plication, as it reduces the cooling re-
quirements of the radar system. The
availability of device models that are
valid between VDS values of 10V and
28V and 10 – 300mA/mm means that
simulations can be carried out over a
wide range of bias conditions with the
confidence that the resulting MMIC
will be ‘right first time’ and that its
measured performance will be well-
represented by the design simulations.

A cross-section of the V5 process is de-

picted in Figure 2. It has a 0.15µm gate
length and breakdown voltage of 84V,
an RF power density of 3.75W/mm at
30GHz, and a SiC substrate thickness
of 75µm. The process offers the stand- Figure 3: (a) GaAs PA versus (b) GaN PA power combining to achieve
ard MMIC passive components (resist- required power
ors, MIM capacitors and through-hole
substrate vias) and benefits from the the same 10W power output. The GaAs instabilities occurring. It also clearly
high thermal conductivity SiC sub- IC would require eight transistors, with results in a MMIC with a much smaller
strate. a complex arrangement of transmission die area, which simplifies the design
lines to combine the power, which adds process and gives a higher probability
GaAs vs GaN-on-SiC loss. In contrast the GaN-on-SiC design of a ‘right first time’ design.
The inherent performance advantages requires only two transistors, reducing
of GaN-on-SiC also help to simplify loss and increasing PAE and making it Design Approach
power combining. Figure 3 compares easier to pass the bias evenly to the Having decided on a suitable process,
the circuit required on GaAs with the transistors. Because there are fewer device-level simulations can begin. The
equivalent on GaN-on-SiC to achieve loops, there is less chance of odd-mode V5 transistors have high gain and are

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 heat. Although this happens in other
semiconductor materials, it is more
pronounced in SiC, so this needs to be
taken into consideration.

The die-attach material, usually solder

or silver loaded epoxy, used to attach
the MMIC to the package or module is
also important thermally. Not only does
it need to have good thermal conductiv-
ity, but the bond line thickness needs to
be kept as small as possible, and atten-
tion needs to be paid to avoid gaps in
the die attach material after assembly, a
phenomenon known as voiding.
Figure 4: Quiescent bias selection
It is also necessary to consider the
conditionally stable at X-band. At the tion of a practical number of transist- thermal impact of the package and for
outset of the design process it is normal ors. SMT packaged parts the PCB. Keeping
to introduce resistive losses at the tran- the transistor’s operating temperature
sistor input to ensure that the transistor The quiescent bias of the transistor im- as low as possible improves the reliab-
is unconditionally stable across the de- pacts the small signal gain, the power ility of the amplifier.
sired operating band, plus some guard transfer characteristics and the linear-
band. The resistive losses can be re- ity. These different performance re- One advantage of designing for radar
duced as the detailed design progresses quirements must be considered when applications is that the PA will gener-
and practical losses of matching and deciding on the optimum bias point. ally be operating in pulsed mode, per-
combining networks are introduced. Figure 4 shows the maximum available haps with a 10% duty cycle, which
Stability at lower frequencies must also gain for an 8 x 150µm transistor at 28V means that less heat needs to be dissip-
be addressed as the design progresses, Vds with the bias current increasing ated than with CW operation. However,
often during the design of the bias net- from 10mA/mm up to 50mA/mm. The as pulse widths get longer, the thermal
work. It is also important to confirm un- effect of the quiescent bias on the gain conditions tend towards those of CW
conditional stability at frequencies compression can be evaluated using operation. Thermal resistance still
above the operating band. load pull simulations at a later stage. needs to be kept low to reduce pulse
droop – the phenomenon where the out-
To select the optimum unit gate width, Thermal considerations put power drops off towards the end of
different sizes can be compared. Tran- Because of the high power density in the pulse due to heating effects, which
sistors with shorter unit gate width will GaN-on-SiC it is very important to en- can affect the radar performance.
benefit from higher available gain but sure that the heat can be dispersed effi-
will have a lower output power. The se- ciently. The silicon carbide substrate is Transistor size selection
lection of the most appropriate tran- an excellent thermal conductor, with a Small-signal device-level simulations
sistor size is one of the likely early conductivity of around 450W/mK, are performed to evaluate available
steps in designing a microwave PA. which is around three times that of sil- gain in the intended operating band.
The transistor needs to be small enough icon and nine times that of GaAs. The For this design these simulations resul-
to provide adequate gain but large thermal conductivity is however tem- ted in the selection of an 8 x 150µm
enough to allow the desired output perature-dependent, so as it heats up it transistor with intra-source vias at an
power to be achieved by the combina- becomes less efficient at removing the IDS of 20mA/mm, 28V bias point. The

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 conditions to drive the transistor into a
suitable mode of operation.

The area of the Smith Chart over which

to perform the load pull is first spe-
cified, and the number of impedance
points to simulate is chosen as a bal-
ance between simulation time and ac-
curacy. It is also important to ensure the
transistor is driven far enough into
compression, as this is where it is inten-
ded to be used in its end application,
but it must not be driven too hard as this
Figure 5: Transistor size selection might cause simulation convergence is-
sues. It can sometimes require some
layout of the transistor is shown on the on either side. Although this layout is optimisation to get the balance right.
right in Figure 5, and it can be seen that slightly more compact, it is not quite as
the intrasource via style of transistor good thermally. For this design the Figure 6 shows the load pull simula-
has vias in between the pairs of gate fin- slightly larger intra-source transistor tions at 9GHz, which result in a set of
gers. The yellow ovals represent the was selected. contours that can be used to determine
vias and the thin red lines show the gate the optimum impedances for PAE, out-
fingers. There is a pair of gate fingers Load pull put power and gain. In practice a com-
with a via either side. Spacing out these The next stage of the design process is promise between these three paramet-
pairs of gate fingers means that they are to carry out load pull simulations to de- ers is selected as the design impedance.
further apart, which has thermal ad- termine how the selected transistor size The control panel allows the selection
vantages. Having more vias reduces the performs under large-signal operation. of the input power that corresponds to
electrical inductance, which is also fa- Within Keysight ADS there is a stand- the desired gain compression, and then
vourable for the performance. An al- ard test bench for transistor load pull. It the optimum impedance as well as the
ternative layout is an edge via layout, has the advantage of being easy to set performance figures can be read off. In
where the gate fingers are evenly up, but it is also flexible, so it is pos- this particular simulation the transistor
spaced and there are only two vias - one sible to tune the harmonics and set the is delivering almost 7W output power

Figure 6: Load pull simulations at 9GHz

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with an efficiency of around 60%. It
should be noted that this is the perform-
ance for the transistor alone, so it does
not include any matching network or
power combining losses or the impact
of the driver stage. The overall effi-
ciency of the PA will therefore be lower
than that shown.

The simulation also allows the gain

compression to be inspected. The gate
current and the drain current can also
be examined to look at the effects on
the power supply design. The reason
for simulating at different frequencies
is to see how these impedances shift
with frequency – one challenge of
designing matching networks is to try
to present the optimum impedance at
each frequency, and so this is some-
thing that becomes increasingly diffi-
cult the greater the design bandwidth.
Load pull plots were also produced at
10GHz and 11GHz. At 11GHz the op-
timum output impedance is between Figure 7(a), top: Second harmonic load pull, and (b), bottom: Third
15Ω and 20Ω. This is much higher than harmonic load pull
an equivalent GaAs transistor deliver-
ing the same power. on the left of Figure 7a for a funda- The effect of the third harmonic imped-
mental frequency of 10GHz; these sim- ance on the power and efficiency can
Further load-pull simulations can be ulations can of course be repeated for also be simulated, as shown in Figure
run across a variety of different operat- other frequencies. The effect of second 7b. Unlike the second harmonic, there
ing conditions but in this case these harmonic load on power and PAE is is not much performance advantage to
simulations give us enough information shown on the right of Figure 7a. At a be gained by tuning the third harmonic,
to assess the number of transistors phase of 0°, corresponding to an open but the performance dip around 150°
needed at the output as well as the re- circuit, the PAE (in red) is just less than needs to be avoided.
quired number of gain stages. 60% and the delivered power (in blue)
is around 38.3dBm. Both power and ef- PA Topology Considerations
Harmonic Load-Pull ficiency can be increased by tuning the After the device level simulations, the
The harmonic impedances must also be second harmonic to around 120°, but topology of our PA can be determined.
considered, particularly if the PA is op- care is needed to avoid the region By estimating the gain per stage using
erating heavily into compression. To around 150° where there is a dramatic GMAX simulations and the losses as-
optimise power and efficiency har- dip in power and efficiency. It is also sociated with the matching networks,
monic tuning of the load can be con- worth remembering that any second splitting and combining networks and
sidered, and to do this the phase of the harmonic tuning implemented on the any other relevant components such as
second harmonic is swept around the MMIC should not adversely affect the gain flattening networks, we can work
edge of the Smith chart. This is shown fundamental load. out how many gain stages are required.

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 Figure 8: PA layout

Given the high gain of this process, our too small, it will start compressing be- structure transforms the output imped-
target of 25dB small signal gain should fore the output stage, and will not be ance. For the power-combined output
be achievable using just two stages. able to supply sufficient power to drive devices, it is very important to preserve
the output stage. This would then limit the symmetry of the load that is presen-
Similarly, we can determine the num- the overall output power of the PA. ted to each output transistor.
ber and size of the transistors that must
be combined in each stage of the ampli- Detailed Schematic Design The matching networks must also pass
fier to generate the required power. Our The PA design is progressed using the gate and drain bias to the transistors.
design example uses two transistors in selected topology to the point of being Drain bias is often injected via a shunt
the output stage with their outputs fully realised using all PDK component matching inductor at its RF short point
power combined to achieve the 10W models. Key considerations during the (capacitor to ground). Gate bias net-
output power target. schematic design are matching, bias- works include biasing resistance to
ing, RF power combining/splitting and limit forward gate current whilst avoid-
The size of the driver stage transistor ensuring broadband unconditional sta- ing degradation of large signal per-
also needs to be carefully considered. bility. formance that could occur if the resist-
Although there is always a lot of atten- ors are too large.
tion devoted to the efficiency of the The matching networks aim to present
output stage, the driver stage efficiency the desired impedances to the transist- The power combining of the output
will also contribute to the overall PA ef- ors for maximum performance. Shunt transistors should be integral to the
ficiency. If we make the driver stage inductive elements at the transistor out- matching network design, as this ap-
transistor too large, it will be inefficient puts are frequently used to help com- proach minimises both the die area and
and thus will degrade the overall PA ef- pensate for the intrinsic drain-source associated losses. When multiple
ficiency. However, if the driver stage is capacitance (CDS), whilst a low pass power combined transistors are used

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 well as proximity and discontinuity ef-
fects. These can be accounted for by
EM simulation, discussed later. The
layout tends to be a compromise
between die size and risk. The smaller
the die size the lower the cost and the
commercial team will push for the
smallest possible die size. However, the
more compact the design the greater the
discontinuities and circuit interactions.

Figure 8 shows a representative layout

of the two stage X-band GaN PA under
consideration with the RF input to the
left and the RF output to the right. Both
input and output include Ground-Sig-
Figure 9: Small signal PA performance nal-Ground (GSG) pads to allow RF
On Wafer (RFOW testing). The two
the possibility of odd-mode stability is- Low frequency stability must also be power combined output transistors can
sues arise and loop stability analysis ensured and suitable components can be seen towards the output of the die
should be performed to identify and re- often be added to the gate and drain bi- followed by the matching and power
solve any potential issues. asing networks to ensure this. Above combing network. Odd-mode stabilisa-
band stability must also be ensured up tion resistors are included between the
The input resistance added to the tran- to the Fmax of the transistors. two output transistors. The single tran-
sistors in the early stages of the design sistor used for the input stage can be
to ensure unconditional stability can be Layout seen to the left with its output matching
reduced as the practical losses of PDK The schematic design must be trans- network splitting into two to drive the
matching components are introduced. lated to an MMIC layout for fabrica- two output devices. DC-blocking and
At microwave and mmWave frequen- tion. This will include the addition of stabilisation networks are included on
cies additional resistive losses to ensure interconnect tracks that may have not chip. The DC and RF pads are all la-
in-band stability are often unnecessary. been in the schematic simulation as belled and their function can be easily

Figure 10: Large signal PA performance

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 Table 3: Phased array radar application

identified. The overall die size is 2.80 x For PAs the EM network is normally compression, which is particularly not-
1.60mm. For components intended for built up from output to input. This is a able for a two-stage design. Table 3
assembly into packages the layout necessarily iterative process and can be compares the simulated performance to
should be optimised with the package time consuming but it is vital if best the original target specification and
in mind and the IC to PCB transitions, performance is to be obtained. shows that the target performance is
including bondwire parasitics, must be met.
simulated and accounted for. Simulated Results
Figure 9 shows the simulated small- Summary
EM Simulation signal performance for the PA with Active phased-array radar is a key ap-
EM simulation of the MMIC layout is greater than 25dB gain across the inten- plication for X-band power amplifiers
vital to ensure best agreement between ded 9 – 11GHz band with some guard and GaN-on-SiC technology has been
modelled and measured performance. band both above and below band. Input shown to have several key advantages
The foundry supplies an EM stack-up return losses are around 10 – 15dB. As over other compound semiconductor
along with the PDK that allows EM expected for a PA, the output return processes. The G28V5 GaN-on-SiC
simulation of all passive components to loss is lower than the input return loss process from Wolfspeed has inherently
be performed. The PDK transistor as the output is matched for best large high gain which can reduce the re-
models are then added to the EM simu- signal performance resulting in a com- quired number of gain stages in a radar
lated passive circuitry. It would be a promise between PAE, output power system line-up and thus simplify the
mistake to try and EM simulate the en- and gain. system design and increase PAE. The
tire structure of a first pass MMIC lay- design of a representative 9 – 11GHz
out in one go. The best approach is to Large-signal simulated performance is 10W PA has been outlined in this white
EM simulate the MMIC a piece at a shown in Figure 10 and indicates an paper and the simulated performance
time, gradually increasing the extent of output power of greater than 40 dBm indicates high output power and PAE
the EM simulation. The layout and the (10 W) across 8.5 – 11.5GHz and across the design band.
schematic design can be optimised as greater than 40.5dBm in the design
the EM simulated network builds up. band. PAE is greater than 42.5% at 4dB

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