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Area and power efficient ECC for multiple adjacent

bit errors in SRAMs.
Kumar Rahul Santosh Yachareni
XILINX XILINX
Hyderabad, India Hyderabad, India
[email protected] [email protected]

Abstract—As submicron technology scales, SRAM bitcell All high-speed SRAM use SEC-DED Hamming Code [5]
density increases on the chip. This results in an increase of soft to encode the input data into a code word using the H-Matrix
errors due to radiation induced multiple-bits upsets (MBUs). [5] and write into the memory. If any SEU upsets 1 bit of the
SRAM uses SEC-DED [Single Error Correct – Double Error data stored in the memory, then the ECC decode using the
Detect] code along with word interleaving or column muxing to same H-matrix can correct the 1 bit of corrupted data. The
mitigate these soft errors. The probability of MBUs in the SRAM
bitcells in 16nm/7nm technology has increased considerably.
syndromes generated using the H-matrix is used to detect
Even using word interleaving with 4:1 column mux is not which bit location is in error and correct it [6].
sufficient to mitigate these soft errors. There are powerful ECC This paper is organized as follows. Section II explains
codes which can correct these soft errors but it comes at the cost adjacent bit errors in SRAM with different column mux
of overhead in the parity bits which eventually translates into the scheme. Sections III & IV discuss the ECC Code Algorithm
SRAM size increase. So here we are proposing an area efficient and the ECC Code Matrix and compare the Area, Power and
ECC(72,64) and ECC(39,32) code with no extra parity bit cost Delay impact of different ECC techniques. Section V shows
which can detect and correct adjacent 2-bit error and detect the verification methodology of these codes and section VI
adjacent 3-bit error. We are also proposing an area efficient concludes the paper.
ECC(73,64) and ECC(40,32) code with one extra parity which
can detect and correct both adjacent 2-bit and 3-bit errors. II. ADJACENT BIT ERROR AND COLUMN MUX IN SRAM
Keywords - static random access memory [SRAM], Error- In SRAM, the SEU event corrupting the adjacent bit has high
Correcting Code (ECC), Single Event Upset (SEU), multiple-bits probability [7]. We propose a new ECC(72,64), SEC-DED-
upsets (MBUs), Multiple Unidirectional SEU (MSEU), SEC-DED ADEC-ATED code with the optimized syndrome calculation
[Single Error Correct, Double Error Detect], SEC-DED-ADEC- for ECC encode and decode. ECC(72,64) uses the same
ATED (Single Error Correct, Double Error Detect, Adjacent number of parity bits as the SEC-DED Hamming code
Double Error Correct, Adjacent Triple Error Detect), SEC-DED- H(72,64). ECC(72,64) can correct adjacent 2-bit in error and
ADEC-ATEC (Single Error Correct, Double Error Detect,
detect adjacent 3-bit in error while reducing the number of 2
Adjacent Double Error Correct, Adjacent Triple Error Correct),
FINFET(Fin-Shaped Field Effect Transistor) input XOR gates by 40% as compared to SEC-DED code. A
new ECC(73,64), SEC-DED-ADEC-ATEC code is proposed
I. INTRODUCTION to do adjacent 3-bit error correct with the optimized syndrome
As memory bit cells of an IC get smaller and/or denser, the calculation and reducing the number of 2 input XOR gates by
likelihood of an SEU impacting more than one of such 30% as compared to SEC-DED code. This ECC(73,64) code
memory bit cells simultaneously increases. However, uses only one extra parity bit compared to the code proposed
increasing too is a demand for memory bandwidth, and thus in [8].
the addition of more parity bits to resolve data corruption One way to mitigate the SEU is to use word interleaving
issues through use of an ECC would hamper efforts to satisfy [9], or column mux in the SRAM array design. Column mux
such demand for memory bandwidth. Accordingly, it would of 2:1, 4:1 is used extensively. SRAM used in processors with
be desirable and useful to provide an ECC that addresses both no column mux could have multiple [10] adjacent SRAM bits
of these conflicting issues. With the scaling of submicron affected by the SEU. The probability of 5 physical adjacent
technology, the size of the bit cell is continuously reducing bits corrupted by SEU [11] is less.
and so is the bit cell internal nodes capacitance. So the
probability of the bit cell storage node getting corrupted by the a0 a1 a2 a3 a4 a5 a6 a7
SEU event increases. Study has shown that 1-5% of the SEU
can cause MBUs [1]. SEU can cause several types of MBUs Figure 1a. SEU corrupting 5 adjacent bits. No Column mux
[2], [3], [4]. Analysis of the SRAM bit cell in 7nm FINFET (a0a1… a7 is same word0)
further suggests that the probability of adjacent 3-bit in error
has increased with respect to the planar 28nm SRAM bit cell
and the 16nm FINFET SRAM bit cell.

k,(((

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 Code for generating the ECC code Matrix
Chose any number a and b
a0 b0 a1 b1 a2 b2 a3 b3
Initialize the array synd1[], synd2[] and synd3[] to 0.
While ( N< Wordsize) {
Figure 1b. 2:1 Column mux (a0a1a2a3 is word0 and b0b1b2 synd1_flag = true, synd2_flag = true, synd3_flag = true
b3 is word1) Choose any number i.( between 1 to 2^8 -1)
synd1_flag = synd1_flag (and) synd1[i-1]
a0 b0 c0 d0 a1 b1 c1 d1 if (synd1_flag=true )
{ Match not found }
Figure 1c. 4:1 Column mux (a0a1 is word0, b0b1 is word1, else
c0c1 is word2 and d0d1 is word3) {
synd2bit(b, i)
a0 b0 c0 d0 a1 b1 c1 d1 a2 b2 synd3bit(a, b, i)
synd2_flag = synd2_flag (and) synd2[synd2bit-1] ;
Figure 1d. 4:1 Column mux with MSEU (a0a1a2 is word0, synd3_flag = synd3_flag (and) synd3[synd3bit-1] ;
b0b1b2 is word1, c0c1 is word2 and d0d1 is word3) if (synd2_flag=true)
{ Match not found }
As shown in Fig. 1a, SEU event corrupts 5 adjacent bits with else
no column mux. Fig. 1b with column mux of 2:1, 5 physical {
adjacent bits corrupted is mapped to 3 adjacent bits in error in if (synd3_flag=true )
word0. ECC(73,64) can be used to mitigate all the possible 3 { Match not found }
adjacent bits in error. For the word size of 73, there are 71 such else
possible 3 adjacent bits in error. As shown in Fig. 1c, SEU {
event corrupting 5 adjacent bits, with column mux of 4:1, 5 synd1[i-1], synd2[synd2bit-1], synd3[synd3bit-1] =true;
physical adjacent bits corrupted is mapped to 2 adjacent bits in Output the value i, synd2bit, synd3bit
error in word0 and single bit error in word1, word2, word3. }}}
ECC(72,64) can be used to mitigate all the 2 adjacent bits in
if ( N=73)
error. There is also a very low probability of MSEU. MSEU
{ECC code Matrix generated}
could lead to scenario where two separate 5 physical adjacent
bits get corrupted. This could lead to a case where these two else { chose another a and b} and repeat the While loop
MBUs are aligned and one starts right after the other }
physically. This is a scenario of 10 physical adjacent bits Figure 3. ECC(73,64) Code Matrix Algorithm
corrupted. As shown in Fig. 1d, word0 and word1 has 3
adjacent bits in error and word2, word3 has 2 adjacent bits in The proposed ECC(72,64) or ECC(73,64) code Matrix
error. algorithm has to satisfy certain conditions. The events 1 bit in
error, 2 adjacent bits in error, 3 adjacent bits in error are
III. ECC CODE IMPLEMENTAION mutually exclusive. This algorithm is true for all possible
combinations of events which are mutually exclusive to each
The generation of the ECC code matrix also depends on how other. ECC(73,64) code matrix algorithm shown in Fig. 3.
the data and the parity bits form a 72/73 bit word. Depending should satisfy the following conditions
on how the parity is placed w.r.t to the data the ECC(73,64) or 1) The syndrome of each 1 bit error should be unique.
ECC(72,64) Code Matrix changes. Some of the examples of 2) The syndrome of each 2 adjacent bit error should be
data and parity arrangement are shown in Fig. 2. unique.
3) The syndrome of each 3 adjacent bit error should be
Case1 p0 p1 … p7 d0 d1 … d62 d63 unique.
Case2 d0 d1 … d62 d63 p0 p1 … p7 4) The 1 bit error syndrome can share the common
Case3 d0 … d7 p0 p1 d8 … d15 p2 space with the 2 adjacent bit error syndrome, p0
Case4 d0 … d15 p0 … p3 d16 … d31 distinguishes between the even or odd number of bits
Case5 d0 … d31 p0 … p7 d32 … d63 in error.
5) The 3 adjacent bit error syndrome can share the
Figure 2. Data and Parity arrangement common space with the 2 adjacent bit error
syndrome, p0 distinguishes between the even or odd
Parity bits first followed by the data bits or vice versa. 8 bits number of bits in error.
of data followed by 2 bits parity, 8 bits of data and so on. 16 6) The 1 bit in error syndrome, 3 adjacent bit error
bits of data followed by 4 bits of parity, 16 bits of data and so syndrome should not share the common space.
on. ECC(72,64) or ECC(73,64) code Matrix will be separate
for each of the case . Even with the code matrix change the
algorithm to optimize the syndrome calculation holds true.

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IV. ECC CODE MATRIX AND COMPARISION

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 1 1 1 0 0 0 0 1 0 1 0 1 1 0 1 0 0 1 1 1 0 1 0 1 1 0 0 0 1 0 0 0 1 1 0 0 0 1 0 1 1 1 1 1 0 0 1 0 1 0 1 0 0 0 0 0 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0
0 1 0 1 0 1 0 0 0 0 1 1 1 1 0 0 0 1 0 0 1 1 1 0 0 0 0 0 1 0 0 1 1 1 0 0 1 1 1 1 0 0 1 0 1 0 1 0 1 0 0 1 1 0 0 0 1 0 0 0 1 0 0 1 0 0 1 1 0 1 1 0
0 0 0 0 1 0 1 0 1 0 0 0 1 1 1 1 0 1 0 0 0 0 1 1 1 1 0 0 1 0 0 1 0 0 0 1 0 0 1 1 1 0 0 0 1 0 1 0 1 0 1 0 0 0 1 1 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 1
0 1 0 0 0 0 1 1 1 0 0 0 0 1 0 1 0 0 1 0 1 0 0 0 0 0 1 0 1 0 0 0 1 0 0 1 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 1 0 1 0 0 1 1 1 1 1 1 1 0 1 0 0
0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 0 1 1 0 1 0 1 0 1 0 0 1 1 1 0 0 0 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0 0 1 0 0 1 0 1 1 0 0 0 1 0 0 0 0 1 0 1 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 1 1 1 1 1 0 1 0 1 1 1 0 1 1 0 1 0 1 1 0 0 0 1 1 0 0 1 0 0 1 0 0 1 1 0 1 0 1 1 1 0 1 0 1 0 1 0 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 1 0 0 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 0 1 1 1 1 0 1 1 1 1 1

Figure 4. Proposed ECC(72,64) SEC-DED-ADEC-ATED Code Matrix

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 0 1 1 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 0 0 1 1 1 1 0 0 0 1 1 0 1 1 1 1 0 0 0 0 1 0
0 1 0 0 0 0 0 0 0 0 1 1 0 1 0 1 1 1 1 0 1 0 1 0 1 1 0 0 0 1 1 1 0 1 0 0 0 1 1 1 0 0 0 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 1 0 1 0 1 1 1 0 1 0
0 0 1 0 0 0 0 0 0 1 0 0 0 1 1 0 1 1 1 0 0 1 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 1 1 1 1 0 0 0 1 0 0 0 0 0 0 1 0 1 0 1 1 1 0 0 1 1 1 1 0 0 1 1 0 1 1 1
0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 0 0 0 1 1 0 1 0 0 1 0 1 1 0 0 0 1 0 0 0 0 1 1 0 0 0 0 1
0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 1 1 1 0 0 0 0 1 0 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1
0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 0 1 1 1 0 1 1 0 0 1 0 1 1 0 1 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 1 1 0 1 0 0 1 1 0 1 0 0 0 1 0 0
0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 1 0 1 0 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 0 0 1 0 0 1 0 0 1 0 1 1 0 1
0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0

Figure 5. Proposed ECC(73,64) SEC-DED-ADEC-ATEC Code Matrix

t4 t5 t6 t7 t4t5t6t7
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 1 1 1 1 1 0 1 1 0 1 1 0 1 1 0 1 0 1 0 1 0 0 0 0 1 1 0 0 0 1 1 1 1 0 0 1 1 0
d64 d61 t5 t6 t7 t5t6t7
0 0 1 1 1 0 1 1 1 1 1 0 1 0 0 1 1 1 1 0 1 0 1 0 0 0 1 0 1 0 0 0 1 1 0 0 0 0 1 d51 d57 d55 t4 t6 t7 t4t6t7
0 1 1 1 0 1 1 1 0 1 0 1 0 0 1 0 0 0 0 0 1 0 1 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0
0 1 0 1 1 1 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 0 1 1 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 d63 d48 d53 d45 d42 d38 t6 t7 t6t7
0 0 1 0 1 1 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 1 0 1 0 1 1 1 0 0 1 1 0 t4 t5 t7 t4t5t7
0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 1 0 1 1 0 1 1 1 1 1 0 1 0 1 1 1
d41 d47 d44 d36 d50 t5 t7 t5t7
Figure 6. Proposed ECC(39,32) SEC-DED-ADEC-ATED d62 d60 d58 d56 d40 d46 t4 t7 t4t7
d37 d32 d52 d43 d35 d30 d27 p7 t7 t7
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 d54 d59 d49 d34 t4 t5 t6 t4t5t6
1 0 0 0 0 0 0 0 1 0 1 1 0 1 0 0 1 1 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 1 0 0 1 0 1 0
0 1 0 0 0 0 0 0 0 1 1 0 1 0 1 1 1 1 0 1 0 1 0 1 1 0 0 0 1 1 1 0 1 0 0 0 1 1 1 0 d39 d18 d26 d29 d23 d21 t5 t6 t5t6
0 0 1 0 0 0 0 0 1 0 0 0 1 1 0 1 1 1 0 0 1 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 1 1 1 d33 d28 d25 d20 t4 t6 t4t6
0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 1 0 0 1 0 0 1
0 0 0 0 1 0 0 0 0 0 0 1 0 0 1 1 1 1 0 0 0 0 1 0 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 d31 d24 d19 d17 d15 d13 p6 t6 t6
0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 0 1 1 1 0 1 1 0 0 1 0 1 1 0 1
0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 1 0 1 0 0 1 0
d22 d10 d14 d12 t4 t5 t4t5
d16 d11 d9 d5 d6 p5 t5 t5
Figure 7. Proposed ECC(40,32) SEC-DED-ADEC-ATEC d8 d4 d3 d1 p4 t4 t4
d7 p3 d2 p2 p1 p0
Fig. 4 shows the proposed ECC(72,64) Matrix for SEC-DED- t1 t1 t1 t1
ADEC-ATED code. Fig. 5 shows the proposed SEC-DED- t2 t2 t2 t2
ADEC-ATEC ECC(73,64) Code Matrix. t3 t3 t3 t3
Fig. 6 shows the proposed ECC(39,32) Matrix for SEC-DED- t1t2t3 t2t3 t1t3 t3 t1t2 t2 t1
ADEC-ATED code. Fig. 7 shows the proposed SEC-DED- S1=t1^t1t2^t1t3^t1t2t3
ADEC-ATEC ECC(40,32) Code Matrix.
S2=t2^t1t2^t2t3^t1t2t3
S3=t3^t1t3^t2t3^t1t2t3
S4=t4^t4t5^t4t6^t4t5t6^t4t7^t4t6t7
S5=t5^t4t5^t5t6^t4t5t6^t5t7^t5t6t7
S6=t6^t4t6^t5t6^t4t5t6^t6t7^t4t6t7^t5t6t7
S7=t7^t4t7^t5t7^t6t7^t4t6t7^t5t6t7
t8=p0^p4^p5^p6^d20^d21^p7^d46^d50^d38^d55^d61
S0=t1^t2^t3^t1t2^t1t3^t2t3^t1t2t3^t8

Figure 8. Parity computation for ECC(72,64)

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. The number of 2 input XOR gates for each syndrome Adjacent 2 bit error 0 1 0
calculation depend on the numbers of 1 in each row shown in Adjacent 3 bit error 0 0 1
the ECC matrix in Fig. 4 and Fig. 5. Optimizing the parity
equation into separate minterms is shown in Fig. 8. The Output of the ECC decode is 9-bit syndrome. If all the 9 bit
proposed algorithm uses the approach where there is overlap syndromes are zero, then there is no error. If syndrome S0 is 1,
of minterms between syndromes. Term t1 is a part of then it’s a single bit error. If the syndrome S0 is 0 and if any
computed syndrome S1. t1 is unique to S1. Term t2 is a part of of the other syndrome bits are 1 then it’s a double bit error.
computed syndrome S2 and so on. t1t2 means its common Table 2 shows the status of the flag for all the possible cases
between S1 and S2. t1t2t3 means these terms are common to of bits in error.
S1, S2, S3. Once all these t1, t2, t3, t4, t5, t6, t7 is broken in
minterms, then S1 is computed by doing the XOR of all the
terms which has t1 in common. All the common minterms are VI. CONCLUSIONS
computed separately, and then used in the parity generation The ECC code proposed in this paper can correct multiple
equation. It helps in reducing the number of 2 input XOR adjacent bit in error with minimal area and performance
gates required in the proposed code as well as in the Hamming impact on the SRAM. The proposed code is easy to implement
code. ECC(72,64) encode/decode compared to the Hamming and verify. These codes are useful especially for submicron
Code H(72,64) and other codes is shown in Table 1. As the 16nm/7nm FINFET design where the probability of adjacent
wordsize increases, the method shown in Fig. 8 helps in MBU due to SEU is high. These codes can be used with the
considerable reduction of 2 input XOR gates and hence the word interleaving to mitigate the adjacent MBU. The need of
area and static power of ECC. these specially designed codes will increase with the scaling
submicron technology. The proposed scalable ECC can be
Table 1. Comparison of proposed SEC-DED-ADEC-ATED designed for SRAM with any kind of data bit arrangement in
codes with the other codes. the word.

2-input Max logic References

(n,k) Codes
Xor Gates depth
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