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Processor: Design: BITS Pilani, Pilani Campus

: Overview of CISC processor architectures; Instruction set architecture of CISC processor; hardware flow-charting methods; implementing microprocessor logic from hard-ware flowcharts; RISC instruction set architecture; Pipelined execution of RISC instructions; pipeline execution unit design; control hazards; design of memory hierarchy.

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KrunalKapadiya1
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184 views21 pages

Processor: Design: BITS Pilani, Pilani Campus

: Overview of CISC processor architectures; Instruction set architecture of CISC processor; hardware flow-charting methods; implementing microprocessor logic from hard-ware flowcharts; RISC instruction set architecture; Pipelined execution of RISC instructions; pipeline execution unit design; control hazards; design of memory hierarchy.

Uploaded by

KrunalKapadiya1
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Processor: Design

BITS Pilani, Pilani Campus


Execution Unit
IRE IRF

Internal A Bus

DO

K
PC T2 R0 RN T2 ALU
A0

DI

Internal B Bus

Ext data bus


Ext add bus
BITS Pilani, Pilani Campus
Timing
Signals
From Register
Clock- Fields
Phase From
generator Instr. Reg.
Control Word Part for EX. Unit Control

Control Word Decoder (Exe. Unit Part)

S
Bus1
h
M T M
Program i
E
A R R .. R f ALU D
Counter M
R 0 1 . n t R
P
Bus2 e
r

some of the micro-programmer’s registers


A TYPICAL INSTRUCTION

- ADD R1, D2(B2)

(R1, B2 - Registers ), D2- displacement

(R1) + (Memory)  (R1) ; (B2) + D2  Memory

5A R1 B2 D2
0 15 16 31

BITS Pilani, Pilani Campus


Let us examine the cases of two different initial conditions
that can be presented to the micro-program :
1. Initial Condition-1 : Program counter contains the
address of the instruction that is to be executed by the
micro-program.
2. The instruction has already been fetched and decoded,
and starting address of the micro-program (in control
memory / control store) for the instruction is available at
the decoder output.

BITS Pilani, Pilani Campus


 In the first case, the micro-program must begin by fetching the
instruction to be executed by it , and the sequence of steps it will
perform would look like:
1. Fetch the first instruction half-word using PC as the address
2. Decode the fetched instruction half-word to find the starting
address of micro-program corresponding to the instruction
3. Fetch the remaining instruction half-word
4. Calculate the operand address(es)
5. Fetch the operand(s)
6. Perform the operation on operands
7. Store the result of operation

BITS Pilani, Pilani Campus


 In the second case, the sequence of steps would look like:
1. Fetch the remaining instruction half-word
2. Calculate the operand address(es)
3. Fetch the operand(s)
4. Perform operation on the operands
5. Store the result of operation
6. Update the program counter (PC)
7. Fetch the first half-word of the next instruction
8. Decode the fetched half-word of the next instruction to find
starting address of its micro-program (control word sequence)
9. Branch to the next instruction’s micro-program (control word
sequence)

BITS Pilani, Pilani Campus


HARDWARE FLOWCHARTS

Hardware flow charts capture the activities inside


a processor on a control step by control step basis.

Acts as a design representation at the register


transfer level as well as a tool for optimization of
the design

BITS Pilani, Pilani Campus


The inputs required for the flow chart are

-Instruction set summary


-Execution unit specification
-Rules of operation

To use the method first postulate an initial


version of the EU with operational rules of EU.

BITS Pilani, Pilani Campus


Specifications of a Processor

Programmers Registers
( Index and pointer registers, GPRs)

Instruction Types
(data movement instructions, arithmetic and logic
instructions, program control instructions)

Addressing Modes
(immediate addressing, direct addressing, register addressing,
implied addressing.)

BITS Pilani, Pilani Campus


MIN Instruction set format
• Instruction Format:
First Word Programmer’s Register Set
OP RX Mode RY R0

Operation First Second Second R1


code operand operand operand
register address register R2
mode
Second Word

Displacement Rn

Optional, depending on second operand addressing mode

MIN instruction format and register set


MIN Instruction Set Summary

Some operations Second Operand Address


ADD
AND
BZ Branch if zero bit is set, Mode RY
Second Second
register indirect only operand operand
address register
LOAD Second operand is source, mode
and RX is destination
Address modes
POP Post increment with
AB : Base(RY) plus displacement
register indirect only (second instruction word) is an operand
PUSH Pre decrement with address
register indirect only AI : Register indirect. RY holds an operand
address
STORE AR : Register direct. The result is stored in
SUB RY. For two operand instruction, RY is also an
operand source
TEST
Execution Unit
IRE IRF

Internal A Bus

DO

K
PC T2 R0 RN T1 ALU
A0

DI

Internal B Bus

Ext data bus


Ext add bus
BITS Pilani, Pilani Campus
Making a flow chart

- Register transfer notation is used to describe the operation of


the execution unit

- Each statement in this notation is called a task


(notation has s source-bus-destination)
- Each state comprises of one or more tasks.
- Use rectangles for states

( In a micro coded implementation each state becomes a control


word and a control word sequence is succession of states)

BITS Pilani, Pilani Campus


ADD RX AR RY
( Register- Register)

RR ADD

rx  a  alu
ry  b  alu

Time

t1  b  ry

Parallel tasks are listed in alphabetical order


In a micro coded implementation each state is one micro cycle
BITS Pilani, Pilani Campus
ADD RX AI (RY)
( Register- Memory)
RM ADD

edb  di
ry  b  ao

di  b  alu Time
rx  a  alu

ry  b  ao
t1  a  do

BITS Pilani, Pilani Campus


edb  irf Pre fetch of next
pc  b ao
instruction
rx  a alu
ry  b alu Current instruction
execution
t1  b  ry
pc  a alu
+1 alu
PC Incrementing
t1  b  pc

BITS Pilani, Pilani Campus


Rules of Operation

-A transfer from source to bus to destination takes one state


time

-A source can drive upto three destination loads. For ex: the
task T1  B ALU, AO, PC has three destination loads

-Input to ALU are from the A (internal) bus and either K (values
0, +1, -1) or the B bus

-When ALU is destination T1 automatically loaded from the ALU


output at the end of state time

-A transfer to AO bus activates on-chip external bus controller.


BITS Pilani, Pilani Campus
Level 1 flowcharts

Separate an instruction’s execution into operation tasks and


house keeping tasks.

Operation tasks are required to perform an instruction –


unique to particular instruction

House keeping tasks, such as PC increment, next instruction


fetch are common to all instructions.

BITS Pilani, Pilani Campus


ADD RX AR RY

RR ADD
edb  irf
rx  a alu pc  b ao
ry  b alu
pc  a alu
+1 alu

t1  b  ry irf  ire
t1  b  pc

Operation tasks House keeping


tasks

BITS Pilani, Pilani Campus


ADD RX AI (RY)

RM ADD

edb  di edb  irf


ry  b ao pc  b ao

di b alu pc  a alu


rx  a alu +1 alu

ry  b ao irf  ire


t1 a  do t1  b  pc

Operation tasks House keeping


tasks

BITS Pilani, Pilani Campus

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