Digital Electronics II

LECTURE

AD – DA CONVERTERS
E N G . W I L S O N JAV I E R P E R E Z H O LG U I N

Electronics Engineering School – Eng. Wilson Javier Perez H. DE II Course - 1st Semester 2013 1
 Outline

1. Sampling
2. Anti-Aliasing Filter
3. Analog-to-Digital Conversion
4. Sample-and-Hold and ADC
5. Analog-to-Digital Conversion Methods
a) The flash ADC
b) The dual-slope ADC
c) The successive approximation ADC (SAR)
d) The sigma-delta ADC
6. Digital-to-Analog Conversion Methods
a) Binary-weighted-input DAC
b) R-2R Ladder
7. Resolution and Accuracy of DACs
8. Reconstruction Filter
9. Digital Signal Processing

Electronics Engineering School – Eng. Wilson Javier Perez H. DE II Course - 1st Semester 2013 2
 1. Sampling

Electronics Engineering School – Eng. Wilson Javier Perez H. DE II Course – 1st Semester 2013 3
 Fourier

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 1. Sampling

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 1. Sampling

Most input signals to an electronic system start out as analog signals.

For processing, the signal is normally converted to a digital signal by sampling
the input.

Before sampling, the analog

input must be filtered with Analog
a low-pass anti-aliasing input
signal
Sampling
circuit

filter.
Sampling
The filter eliminates pulses

frequencies that exceed a

certain limit that is
determined by the sampling
rate.
Sampled
version of
input signal

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 4. Sample-and-Hold and ADC

Following the anti-aliasing filter, is the sample-and-hold circuit and the

analog-to-digital converter. At this point, the original analog signal has been
converted to a digital signal.

Samples held
for one clock
pulse

0100 0101 1100 1010

ADC

.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
Many ICs can perform both functions on a single chip and include two or
more channels. For audio applications, the AD1871 is an example of a stereo
audio ADC.

Electronics Engineering School – Eng. Wilson Javier Perez H. DE II Course – 1st Semester 2013 7
 Aliasing Problem

Unfiltered analog
frequency spectrum

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 2. Anti-Aliasing Filter

To understand the need for an anti-aliasing filter, you need to understand the
sampling theorem which essentially states:

In order to recover a signal, the sampling rate must be greater

than twice the highest frequency in the signal.

Stated as an equation, fsample > 2fa(max)

where fsample = sampling frequency
fa(max) = highest harmonic in the analog signal

If the signal is sampled less than this, the recovery process will produce
frequencies that are entirely different than in the original signal.
These “masquerading” signals are called aliases.

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 2. Anti-Aliasing Filter

Most signals have higher frequency harmonic and noise. For most ADCs, the
sampling and filter cutoff frequencies are selected to be able to reconstruct the
desired signal without including unnecessary harmonics and noise.

An example of a reasonable sampling rate is in a digital audio CD. For audio

CDs, sampling is done at 44.1 kHz because audio frequencies above 20 kHz
are not detectable by the ear.

Question What cutoff frequency should

an anti-aliasing filter have for a
digital audio CD?

Answer Less than 22.05 kHz.

Electronics Engineering School – Eng. Wilson Javier Perez H. DE II Course – 1st Semester 2013 12
 3. Analog-to-Digital Conversion

To process naturally occurring analog quantities with a digital system, the

analog signal is converted to digital form after the anti-aliasing filter.

The first step in converting a signal to digital form is to use a sample-

and-hold circuit. This circuit samples the input signal at a rate
determined by a clock signal and holds the level on a capacitor until the
next clock pulse.

10 V
A positive half-wave from 0-10 V is
shown in blue. The sample-and-hold
circuit produces the staircase
representation shown in red.
0V

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 3. Analog-to-Digital Conversion

The second step is to quantize these staircase levels to binary coded form
using an analog-to-digital converter (ADC).
The digital values can then be processed by a digital signal processor or
computer.
Example What is the maximum unsigned binary value for 0.0000
10.0001
the waveform? 100.0001
101.1110
Solution 10 V = 10102 V. The table lists the quantized 111.0111
1000.1011
binary values for all of the steps. 1001.1001
Peak = 10 V 1010.0000
1010.0000
10 V 1001.1001
1000.1011
111.0111
101.1110
100.0001
10.0001
0V 0.0000

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 3. Analog-to-Digital Conversion

Sample Hold Quantize Codification

1011..01

Electronics Engineering School – Eng. Wilson Javier Perez H. 15

 5. Analog-to-Digital Conversion Methods
+VREF
Op-amp
a) The flash ADC: R comparators

Input from +
sample- –
and-hold
R + Priority
– encoder

R 7
+
6
–
The flash ADC uses a series high-speed R
5
4
1 D0 Parallel
+
comparators that compare the input – 3
2
4
D1 binary
D2
output
2
with reference voltages. Flash ADCs R + 1
–
are fast but require 2n – 1 comparators R
0 EN

to convert an analog input to an n-bit +

–

binary number. R
+
Enable
– pulses

Question How many comparators are needed by a 10-bit flash ADC?

Answer 1023
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 5. Analog-to-Digital Conversion Methods

a) The single-slope ADC:

Analog
Input
CLK

+
V

C
Comparator
Counter
t
Clear

Slope Control
Generator Reset Logic

EN Latches

D7 D6 D5 D4 D3 D2 D1 D0
Binary Output

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 5. Analog-to-Digital Conversion Methods

b) The dual-slope ADC:

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 5. Analog-to-Digital Conversion Methods

c) The successive approximation ADC:

Electronics Engineering School – Eng. Wilson Javier Perez H. DE II Course – 1st Semester 2013 32
 5. Analog-to-Digital Conversion Methods

An integrated circuit successive approximation ADC is the ADC0804. This

popular ADC is an 8-bit converter that completes a conversion in 64 clock
periods (100 ms).
VCC

(20)
(1) (5)
CS ADC0804 INTR
(2) (19)
RD
(3) ∆ (18) CLK R (out)
WR D0
CLK IN
(4) ∆ (17)
D1
The completion is signaled by the
Analog Vin+
(6) ∆ (16)
D2 INTR line going LOW.
(7) (15) Digital
input Vin–
∆
D3
(9) ∆ (14) data
REF/2 D4 output
∆ (13)
D5
∆ (12)
D6
∆ (11)
D7

(8) (10)

ANLG DGTL
GND GND

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 5. Analog-to-Digital Conversion Methods

d) The sigma-delta ADC:

With sigma-delta conversion, the difference between two samples of the
analog input signal is integrated and quantized. The density of 1s at the
output is proportional to the input signal.

Summing
point
Analog + ∆ 1-bit Quantized output
input Σ Integrator
quantizer is a single bit
signal – data stream.

DAC

Electronics Engineering School – Eng. Wilson Javier Perez H. DE II Course – 1st Semester 2013 34
 5. Analog-to-Digital Conversion Methods

One option for the sigma-delta method is to count the one-bit quantized output
for a set interval. The output of the counter is latched with the parallel binary
code.
Summing
point
Analog + ∆ 1-bit n-bit Binary code
input Σ Integrator
quantizer counter
Latch
output
signal – . .
. .
. .
. .
. .
1-bit
DAC

Sigma-delta ADCs can have high resolution and have advantages for rejecting
noise signals (such as 60 Hz power line interference).
They are available in ICs with internal programmable amplifiers. For these
reasons, they are widely used in instrumentation applications.
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5. Analog-to-Digital Conversion Methods

Sigma-Delta Converter

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 5. Analog-to-Digital Conversion Methods

If the wave amplitude, accumulated over a given sample period is greater than
the previous sample period, the converter generates “1”.

If the accumulated wave amplitude is lower, the converter generates “0”.

This generates a type of high density pulse modulation with positive half-waves
represented by many consecutive “1s”, while the negative half-waves produce
many “0s” in the sequence.

The D/A Delta-Sigma decoder performs the inverse operation.

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5. Analog-to-Digital Conversion Methods

Electronics Engineering School – Eng. Wilson Javier Perez H. DE II Course – 1st Semester 2013 38
 6. Digital-to-Analog Conversion Methods

a) Binary-weighted-input DAC:
The binary-weighted-input DAC is a basic DAC in which the input current in
each resistor is proportional to the column weight in the binary numbering
system. It requires very accurate resistors and identical HIGH level voltages
for accuracy.

LSB 8R
D0 Rf
The MSB is represented by + –
I0
the largest current, so it has 4R If
the smallest resistor. To D1
I1 –
simplify analysis, assume all 2R Vou
D2 t
current goes through Rf and I=0
+
I2 Analog
none into the op-amp. R output
D3
MSB I3

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 6. Digital-to-Analog Conversion Methods

Example A certain binary-weighted-input DAC has a binary input of 1101.

If a HIGH = +3.0 V and a LOW = 0 V, what is Vout?
120 kW
Rf
20 +3.0 V
60 kW 10 kW
21 0V
–
30 kW
22 +3.0 V Vout
+
15 kW
23 +3.0 V

Solution I out  ( I 0  I1  I 2  I 3 )
 3.0 V 3.0 V 3.0 V 
  0 V    0.325 mA
 120 kW 30 k W 15 k W 
Vout = Iout Rf = (−0.325 mA)(10 kW) = −3.25 V

Electronics Engineering School – Eng. Wilson Javier Perez H. DE II Course – 1st Semester 2013 40
 6. Digital-to-Analog Conversion Methods

b) R-2R Ladder:
The R-2R ladder requires only two values of resistors. By calculating a
Thevenin equivalent circuit for each input, you can show that the output is
proportional to the binary weight of inputs that are HIGH.
VS
Each input that is HIGH contributes to the output: Vout   n i
where VS = input HIGH level voltage
2
n = number of bits Inputs
i = bit number D D1 D2 D3
0

For accuracy, the resistors R1 R3 R5 R7 Rf = 2R

must be precise ratios, 2R 2R 2R 2R
R2 R4 R6 R8
which is easily done in –
integrated circuits. 2R R R R Vou
+ t

Electronics Engineering School – Eng. Wilson Javier Perez H. DE II Course – 1st Semester 2013 41
 6. Digital-to-Analog Conversion Methods

Example An R-2R ladder has a binary input of 1011. If a HIGH = +5.0 V

and a LOW = 0 V, what is Vout?
D0 D1 D2 D3
+5 v +5 v 0v +5 v

R1 R3 R5 R7 Rf
50KW
50KW 50KW 50KW 50KW
R2 R4 R6 R8
–
50KW 25KW 25KW 25KW Vout
+

VS
Solution Apply Vout   to all inputs that are HIGH, then sum the results.
2 n i
5V 5V
Vout ( D0 )   40
 0.3125 V Vout ( D1 )   4 1
 0.625 V
2 2
5V
Vout ( D3 )   43  2.5 V Applying superposition, Vout = −3.43 V
2
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 7. Resolution and Accuracy of DACs

The R-2R ladder is relatively easy to manufacturer and is available in IC

packages. DACs based on the R-2R network are available in 8, 10, and 12-bit
versions.
The resolution is an important specification, defined as the reciprocal of the
number of steps in the output.

Question What is the resolution of the BCN31 R-2R

ladder network, which has 8-bits?

Answer (28 – 1)-1 = 1/255 = 0.39%

The accuracy is another important specification and is derived from a

comparison of the actual output to the expected output.
For the BCN31, the accuracy is specified as ±½ LSB = 0.2%.

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 8. Reconstruction Filter

After converting a digital signal to analog, it is passed through a low-pass

“reconstruction filter” to smooth the stair steps in the output.
The cutoff frequency of the reconstruction filter is often set to the same limit as
the anti-aliasing filter, to block higher harmonics due to the digitizing process.

Reconstruction
Filter

Output of the DAC Final analog output

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 9. Digital Signal Processing

A digital signal processor (DSP) is optimized for speed and working in real time
(as events happen). It is basically a specialized microprocessor with a reduced
instruction set (RISC).
After filtering and converting the analog signal to digital, the DSP takes over.
It may enhance the signal in some predetermined way (reducing noise or
echoes, improving images, encrypting the signal, etc.).
The signal can then be converted back to analog form if desired.

10110 10110
01101 01101
00011 00011
11100 11100 Enhanced
Analog Anti-aliasing Sample-and- Reconstruction
signal filter hold circuit ADC DSP DAC filter analog
signal

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 9. Digital Signal Processing

Program cache/program memory

Because speed is (32-bit address, 256-bit data)
important in DSP
applications, assembly
language is frequently CPU (DSP core)

used because in general Program fetch

Control
it executes faster. Instruction dispatch registers

DMA Instruction decode

EMIF Control
Data path A Data path B logic

Register file A Register file B

Test

Evaluation
.L1 .S1 .M1 .D1 .D2 .M2 .S2 .L2
Interrupts

Data cache/data memory Additional

(32-bit address, 8-, 16-, 32-. 64-bit data) peripherals

A general block diagram of the TMS320C6000 series DSP

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 Selected Key Terms

Nyquist frequency The highest signal frequency that can be sampled at a specified
sampling frequency; a frequency equal or less than half the
sampling frequency.

Quantization The process whereby a binary code is assigned to each sampled

value during analog-to-digital conversion.

Analog-to-digital A circuit used to convert an analog signal to digital form.

converter (ADC)

DSP Digital signal Processor; a special type of microprocessor that

processes data in real time.

Digital-to-analog A circuit used to convert a digital signal to analog form.

converter (DAC)

Electronics Engineering School – Eng. Wilson Javier Perez H. DE II Course – 1st Semester 2013 47
 Quiz

1. If an anti-aliasing filter is not used in digitizing a signal the recovery

process
a. is slowed
b. may include alias signals
c. will have less noise
d. all of the above

Electronics Engineering School – Eng. Wilson Javier Perez H. DE II Course – 1st Semester 2013 48
 Quiz

2. An anti-aliasing filter should have

a. fc more than 2 times the Nyquist frequency
b. fc equal to the Nyquist frequency
c. fc more than ½ fsample
d. fc less than ½ fsample

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 Quiz

3. The number of comparators required in a 10-bit flash ADC is

a. 255
b. 511
c. 1023
d. 4095

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 Quiz

4. The block diagram is for a successive-approximation ADC.

The top block is ?
a. an SAR Vout

b. a DAC
?
c. an ADC D0
Parallel
d. a comparator D1
binary
D2 output
–
Input + D3
signal (MSB) (LSB)
D Serial
binary
C output
CLK

Electronics Engineering School – Eng. Wilson Javier Perez H. DE II Course – 1st Semester 2013 51
 Quiz

5. The ADC804 integrated circuit signals a completed conversion by

VCC
a. INTR goes LOW
(20)
b. CS goes LOW (1) (5)
CS ADC0804 INTR
(2) (19)
c. RD goes LOW RD
(3) ∆ (18) CLK R (out)
WR D0
(4) ∆ (17)
d. CLK R goes HIGH CLK IN
(6) ∆ (16)
D1
Analog Vin+ D2
(7) (15) Digital
input Vin–
∆
D3
(9) ∆ (14) data
REF/2 D4 output
∆ (13)
D5
∆ (12)
D6
∆ (11)
D7

(8) (10)

ANLG DGTL
GND GND

Electronics Engineering School – Eng. Wilson Javier Perez H. DE II Course – 1st Semester 2013 52
 Quiz

6. A sigma-delta circuit is a form of

a. DSP
b. DAC
c. ADC
d. SAR

Electronics Engineering School – Eng. Wilson Javier Perez H. DE II Course – 1st Semester 2013 53
 Quiz

7. The circuit shown is a

a. DSP
8R
b. DAC Rf
+ –
I0
c. ADC 4R If
d. SAR
I1 – Vout
2R
I=0
I2 +
R

I3

Electronics Engineering School – Eng. Wilson Javier Perez H. DE II Course – 1st Semester 2013 54
 Quiz

8. For the circuit shown, the input on the far left is for the
a. Analog input
b. Clock
Inputs
c. LSB
d. MSB
R1 R3 R5 R7 Rf = 2R
2R 2R 2R 2R
R2 R4 R6 R8
–
2R R R R Vout
+

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 Quiz

9. A reconstruction filter
a. is a low-pass filter
b. can have the same response as an anti-aliasing filter
c. smoothes the output from a DAC
d. all of the above

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 Quiz

10. A DSP is a specialized microprocessor that

a. has a very large instruction set
b. is designed to be very fast
c. has internal anti-aliasing and reconstruction filters
d. all of the above

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