The State-of-the-Art of Silicon-on-Sapphire CMOS RF Switches

Dylan Kelly ([email protected]), Chris Brindle, Clint Kemerling, Mike Stuber

Peregrine Semiconductor Corporation
9450 Carroll Park Drive, San Diego, CA, 92121, USA

Abstract — Silicon-on-Sapphire (SOS) CMOS FETs have II. SMALL-SIGNAL SWITCH BEHAVIOR
many properties which are desirable for RF switch applications.
By being manufactured on an insulating sapphire substrate, the When operated as an RF switch, a MOSFET is generally
bulk parasitic capacitances typical of CMOS FETs are biased in strong inversion or deep substhreshold. In most
eliminated. The SOS FET has a very low Ron-Coff product, processes, the FET can be accurately modeled by an on-
allowing for low insertion loss and high isolation in high resistance, RON, and an off-capacitance, COFF, in these regimes
frequency applications. Despite the low breakdown voltage
and at frequencies representative of the communication
intrinsic to Si, SOS FETs can be stacked in series to withstand
high voltages when biased in subthreshold. This work studies the systems mentioned. COFF, is defined as the total capacitance
tradeoffs of SOS RF switch design and compares SOS against from drain-to-source with the gate biased by a high-impedance
other technologies such as GaAs and Si-based SOI. Also source. Both parameters affect the insertion loss and isolation
presented is a high power SP6T switch with insertion loss of 0.6 of a switch, so a FET process can be evaluated for its efficacy
dB at 2 GHz and isolation of 40 dB at 2 GHz. The presented as a switch process by the product of RON-COFF. Table 1
switch has the highest linearity reported to date of any SP6T compares the RON-COFF figure-of-merit from several process
switch with a P1dB of 20 W and OIP3 of >+70 dBm. technologies.

I. INTRODUCTION TABLE 1
Survey of RON-COFF from Several Process Technologies
Ron Ron-Coff
RF switches play an integral role in many wireless and Process Technology
(Ω-mm)
Coff (fF/mm)
(fs)
Reference

wireline systems. As more communications standards are 0.15 um pHEMT 1.5 290 435 [11]
defined and are integrated by manufacturers, the demand for 0.5 um pHEMT 1.5 240 360 [12]
complex RF switching is increasing. In particular, the cellular 0.5 um 100Å Tox SOS 2.8 270 756 This Work

handset market is seeing a rapid increase in switching 0.25 um 50Å Tox SOS 1.6 280 448 This Work

requirements. For example, GSM handsets have evolved

from a single-band TDMA system only needing an SPDT To estimate the insertion loss of a FET at low frequencies,
switch to a communication system integrating up to four GSM one can directly calculate loss from RON,
bands and WCDMA, requiring an SP7T switch. This pattern
is expected to continue with further integration of 802.11,  2 R0 
GPS, diversity antennas, etc. IL = −20 log  , (1)
The GSM standard [1] for handsets represents the most  2 R0 + RON 
challenging set of handset requirements for an RF switch.
Maximum output power at the antenna is specificied as +33 where R0 is the source and load resistance. In a typical switch
dBm, but system integrators generally require the RF switch to FET, the RON may be 4 ohms which yields a low frequency
meet all specifications with +35 dBm input power to loss of of 0.34 dB. Using the 0.5 um SOS technology from
compensate for losses and variations. In a 50-ohm system, table 1, this FET would have a COFF of 190 fF. This off
this 3 W power translates to 17.8 VPK. This voltage can be capacitance will determine the isolation of the switch and also
nearly doubled under mismatch conditions at the antenna. affect the insertion loss if multiple FETs are connected to a
Further, generated harmonics must be suppressed below -30 common node to create a multithrow switch.
dBm, requiring a highly linear switch. With advancements in CMOS and battery technology,
Many different technologies exist for implementing the handset supply voltages continue to drop which can have a
switching function. Traditionally, PIN diodes have dominated significant impact on RON and thus insertion loss. Figure 1
due to their excellent small signal performance and linearity shows RON versus gate voltage with source and drain biased at
[2]. However, pressures on power consumption and size now 0 V.
require solutions involving integrated circuits [3]. For high-
power applications such as GSM, monolithic solutions have
been demonstrated in SOS and GaAs technologies. Research
is on-going in Si [4-7], Si-based SOIs [8], MEMs [9], and
GaN FETs [10], but no published results have met the
requirements of GSM.

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 5 vds pk = 2(VTH − VGS ) , (2)
0.5 um
0.25 um
4
where VGS is the DC gate voltage. At the vds extremes, the
Ron (ohm-mm)

temporarily on FET passes current and clips the voltage. This

3 clipping occurs symmetrically on both the positive and
negative vds excursions with logical swapping of drain and
2 source locations, resulting in odd-order distortion. For a
typical CMOS process, VTH is generally quite low, and may be
1
0 V to achieve the highest mobility by leaving the channel
undoped. To handle large vds, VGS must then be biased well
below 0 V.
0 This model of the off FET assumes that drain-to-source
0 1 2 3 4 leakage current does not limit vds before vds forces the FET into
Vg (V) inversion. Figure 3 shows the breakdown characterisic of a
0.5 um SOS FET.
Fig. 1. RON versus gate voltage for 0.5 um and 0.25 um SOS
processes
1.E-08
While the 0.5 um SOS technology offers an adequate RON of 1.E-09
2.8 Ω-mm with today’s handset supply voltage of 2.75 V, RON
1.E-10
rises steeply with reduction in VG. Due to thinner gate oxide,

Id (A/um)
the 0.25 um SOS technology maintains an RON under 2 Ω-mm 1.E-11
at 1.8 V. 1.E-12

III. LARGE-SIGNAL SWITCH BEHAVIOR 1.E-13

1.E-14
Both GaAs and SOS switches achieve large voltage
handling by ‘stacking’ switches in series [13]. For an SOS 1.E-15
switch, compression is reached when the RF swing forces vGS 0 1 2 3 4 5 6 7 8
to rise above VTH. Figure 2 shows the equivalent circuit of an Vd (V)
SOS FET biased in deep subthreshold with an RF signal
across drain-to-source. When implemented with a gate
resistor whose resistance is much greater than the impedance Fig. 3. Subthreshold Id vs. Vd of a 0.5 um SOS FET
of the gate parasitic capacitances at RF, the FET can be
modeled simply by the parasitic capacitances in series with the For this channel length, BVDSS (2 nA/um) is greater than 6
gate floating at a DC offset. Since the typical SOS FET is a V when biased in deep subthreshold. This drain-to-source
symmetric device, vGS is half of vds. leakage is low enough such that it does not impact linearity
performance for typical gate biases.
In an SOI process such as SOS, FETs can be stacked to
vds
withstand higher voltages as shown in figure 4(a). Similar to
the case in figure 1, the voltage is divided evenly across each
0V 0
FET in the stack. Using GSM as an example in an open load
condition where 35.6 VPK is available across the off FETs, a
-vds stack of eight FETs is a common configuration where each
-1.10

0.5·vds FET withstands 4.45 VPK.

CGDO
VG The stacking concept requires that parasitic capacitances be
⇔
0

-1.1 0

-0.5·vds
small relative to COFF to insure proper voltage division. To
CGSO
maintain the target RON, each FET must be made 8X wider,
resulting in significant area for parasitic coupling. While this
2
area of approximately 5000 um for the source and drain each
is not an issue in SOS, in a Si-SOI process, the bulk
Fig. 2. Equivalent circuit of an SOS FET biased in deep capacitance can be problematic.
subthreshold with RF excitiation

Using this simple model of a single FET, one can see that
for high enough vds, vGS can instanteously rise above VTH, thus
turning on the FET. The peak drain-to-source voltage that
drives vGS above VTH is given by,

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 Cpp
0 0
Cpp -10
-0.4 -20
-30
-0.8 -40

S21 (dB)
-50
-1.2 -60
TX IL -70
(a) (b) -1.6 RX IL -80
Fig. 4. Increasing voltage handling through (a) FET stacking and TX->RX Isolation -90
(b) annotation of select SOI bulk parasitics -2 -100
Assuming a typical buried oxide layer of 1000 Å [14], the 0 500 1000 1500 2000 2500
Cpp from the source and drain to the underlying bulk is 1.7 pF Frequency (MHz)
as shown in figure 4(b). Using the example FET from section
II with COFF of 190 fF scaled by 8X yields a COFF per FET in Fig. 6. Insertion loss and isolation performance of an SOS CMOS
the stack of 1.5 pF. These additional parasitics result in SP6T switch
asymmetric voltage division across the stack and destruction
of the top FET. To mimic a 200 um thick SOS wafer, the Si- The compression behavior with a P1dB of 20 W is shown in
SOI oxide layer would need to be increased to 80 um. figure 7. This is highest P1dB of any CMOS switch reported
to date.
IV. RESULTS
43 1
Pout vs. Pin
An SP6T switch for GSM has been fabricated using this 0.5 42 Ideal 1:1
0.9
um SOS process technology and is shown in figure 5. 41 Compression 0.8
Output Power (dBm)

Compression (dB)
40 0.7
39 0.6
38 0.5
37 0.4
36 0.3
35 0.2
34 0.1
RF Switch Core
33 0
34 35 36 37 38 39 40 41 42 43 44
Input Pow er (dBm)

Fig. 7. Compression behavior of an SOS CMOS SP6T switch at 1

GHz

Switch Bias Harmonic generation of the switch with +35 dBm input
power is shown in figure 8. Harmonic suppression is the best
Negative Voltage Generator reported to date for any SP6T switch with 2fo power of -57
dBm and 3fo of -50 dBm [15-17].
ESD

ESD
ESD

ESD

Decoder

Fig. 5. Microphotograph of a 0.5 um SOS CMOS SP6T switch

The switch is designed with asymmetric TX and RX paths to

provide very low insertion loss through the two TX paths.
The insertion loss and TX-RX isolation are shown in figure 6.

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 REFERENCES
10 P3fo
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P2fo
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[4] R. Caverly, “Linear and Nonlinear Characteristics of the Silicon CMOS
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15 20 25 30 35 40 45 900-MHz and 2.4-GHz Applications on p- Silicon Substrates,” IEEE
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Input Pow er (dBm) [7] T. Ohnakado et al., “21.5-dBm Power-Handling 5-GHz
Transmit/Receive CMOS Switch Realized by Voltage Division Effect of
Fig. 8. Harmonic generation of a SOS CMOS SP6T switch Stacked Transistor Configuration With Depletion-Layer-Extended
Transistors (DETs),” IEEE Journal of Solid-State Circuits, vol. 39, no.
with 1 GHz fundamental 4, pp. 577-584, Apr. 2004.
[8] C. Tinella et al., “A High-Performance CMOS-SOI Antenna Switch for
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meets the IMD requirements with an OIP3 of >+70 dBm. Per no. 7, pp. 1279-1283, July 2003.
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[11] S. Makioka et al., “Super Self-Aligned GaAs RF Switch IC with 0.25
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[12] M/A-COM, Process Data Sheet, HS Switch Process.
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V. CONCLUSION

Silicon-on-Sapphire CMOS technology provides not only

RON-COFF performance comparable to GaAs pHEMT
technology, but also the highest linearity performance reported
for multithrow switches. Combining excellent small-signal
performance with the required IMD performance allows for
scaling SOS switches beyond six-throws to integrate
additional wireless standards such as WCDMA. Further
integration of the handset RF front-end is also possible as
high-quality passives [19-20] and other CMOS circuitry can
be integrated. Last, SOS can leverage advanced CMOS
processing techniques such as large-wafer handling and wafer-
scale packaging for reduced cost and size.

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