Laboratory Manual: Analogue and Digital Communication Lab
Laboratory Manual: Analogue and Digital Communication Lab
(EL-323)
LABORATORY MANUAL
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Page 2 of 18
Lab #
Analogue and Digital National University Roll No: __________
Communication Lab
(EL323)
of Computer and Emerging Sciences
Islamabad Fall 2016
11
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Quantization value (Q) means when the digital output changes 1 LSB, the required input voltage
value also changes, the expression is
FS 1
Q= n
= n
2 −1 2
2n −1 n
Where FS is the full scale, the value equals to
[ ]
2n
, 2 , 2n is defined as resolution, where n is the
ADC digital output bit, so larger the value of n, the higher the resolution. In general, the ADC
technical manual defines resolution in bits. For example, the resolution of ADC0804 is 8 bits.
The methods of conversion for ADC are various, normally can be divided as A/D conversion
methods are digital ramp ADC, successive approximation ADC, flash ADC and tracking ADC. In
this chapter, only the successive approximation ADC is discussed, therefore, we will discuss on the
operation theory of successive approximation of ADC.
Figure-2 is the block diagram of successive approximation ADC, which is provided with 8 bit
resolution. When we input the analog signal, sample-and-hold, S&H will circuit will capture the
input signal Vin to avoid any signal change during conversion period. At this moment, the control
logic will store all the bits and reset to “0”, follow by the most significant bit, MSB D 7 is set to “1”.
Thus, the output voltage of DAC is
This voltage is half of the reference voltage Vref. If the input voltage Vin is higher than V(D), then
D7 remains at “1”, otherwise alters to “0”. Next make the second bit D 6 as “1”, after passing through
a DAC then obtain an output voltage V(D), at this moment capturing the new V(D), at this moment
comparing the new V(D) and Vin, if Vin is higher than V(D), then D 6 remains at “1” otherwise
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Page 3 of 18
Lab #
Analogue and Digital National University Roll No: __________
Communication Lab
(EL323)
of Computer and Emerging Sciences
Islamabad Fall 2016
11
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alters to “0”. Similarly for the others until the comparison of D 7 to D0 have been completed, then we
can obtain the complete D7 to D0 digital output.
Figure-3 shows the pin diagram of ADC0804. In figure-3, the D 0 to D7 of ADC0804 is the 8 bit
´ and RD
output pins, when CS ´ are low, the digital data will be sent to the output pins. In any pins of
´ and RD
CS ´ are high, then D0 to D7 are in floating condition.
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Page 4 of 18
Lab #
Analogue and Digital National University Roll No: __________
Communication Lab
(EL323)
of Computer and Emerging Sciences
Islamabad Fall 2016
11
____________________________________________________________________________________
1
f CLK ≈ (Hz)
1.1∗R∗C
Therefore, we need not input an external clock signal to CLK IN terminal. We can determine the
clock signal by the external R and C via pin 4 and pin 19.
Figure-5 is the circuit diagram of ADC 0804 analog to digital converter, the analog signal input
range is controlled by VR2 and input through the Vin(+) terminal and at the same time, the Vin(-) is
short circuit. Vref/2 is provided by R1, R2 and VR1. C1 and R3 is used to control the clock of the
´ and RD
circuit, CS ´ are short circuit, so that the IC is enable, then let WR
´ and INTR
´ connect to SW1
in order to simulate the control signal.
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Page 5 of 18
Lab #
Analogue and Digital National University Roll No: __________
Communication Lab
(EL323)
of Computer and Emerging Sciences
Islamabad Fall 2016
11
____________________________________________________________________________________
ADC0809 is a 28 bit DIP package, which has a 8-bit resolution and 8 channel multiplexer IC. It
operates with 5 V single power supply, the input signal analog range is from 0 V to 5 V and the
power consumption is 15 mW. The 8 channel multiplexer can directly access any of 8 single ended
analog signals. With 8 bit resolution, the ADC0809 have 28=256 quantization steps. Therefore for
the 5 V voltage power supply condition, each step is 5/256 V, so the quantization value (Q) is
0.01953 V. So 00000000 (00H) represents 0.00 V and 11111111 (FFH) represents (255/256)x5 =
4.9805 V. The unadjusted error is ± 1 LSB, which is same as 0.01953 V where it contains of full-
scale error, offset error, non linearity error and multiplexer error. ADC0809 needs a group of clock
input signals to operate, the frequency range of the clock signal starts from 10 KHz to 1280 KHz.
At 640 KHz clock frequency, the typical conversion time is 100 us.
Figure-6 is the pins diagram of ADC0809. In figure-6, the ADC0809 pins 5, 4, 3, 2, 1, 28, 27 and
26 are the 8 input ports, which is IN7 to IN0. Pins 21, 20, 19, 18, 8, 15, 14 and 17 are the output
ports, which are D7 to D0 and pin 10 is the clock input port. Pin 11 is the power supply Vcc input
port and pin 12 is the positive reference voltage Vref(+) input port. Normmally, pins 11 and 12 are
connected together. Pin 13 is grounded and pin 16 is the negative reference voltage V ref(-) input port
that normally connects to ground pin 13. The selection of channels are controlled by pins 25, 24 and
23 which are ADD A, ADD B and ADD C. If select pin 26 (IN 0) is used as input port, then connect
23, 24 and 25 to ground.
ADC0809 can be easily connected with microprocessor, where pin 6 (START), pin 7 (end of
conversion, EOC), pin 9 (output enable, OE) and pin 22 (address latch enable, ALE) are normally
used to control the ADC and the clock of data conversion of microprocessor. When ADC0809
conversion is finished, EOC can enable the central processing unit (CPU). When CPU is ready to
receive data, it will enable pin OE and read the data. After that enables ALE and START, to let the
ADC0809 continue the next conversion. If under the condition of using multi channel inputs, pin 23
(ADD C), pin 24 (ADD B) and pin 25 (ADD A), ALE and START must be set during the period of
enable.
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Page 6 of 18
Lab #
Analogue and Digital National University Roll No: __________
Communication Lab
(EL323)
of Computer and Emerging Sciences
Islamabad Fall 2016
11
____________________________________________________________________________________
Figure-7 is the circuit diagram of ADC0809 ADC, where EOC (pin 7) output signal is the START
input signal, and the ALE and CLK output signal are the clock signal. The input signal range of
analog input port IN0 is determined by VR1. The IN1 and IN7 input signal ranges are determined
by R1 to R7, which is a group of resistor networks. The channel selection is controlled by SW1,
SW2 and SW3. We use LED to represent the digital output, therefore, LED “ON” represents “1”
and LED “OFF” represents “0”. The brightness of the LED depends on the current flowing through,
so it is related to the serial resistors pack.
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Page 7 of 18
Lab #
Analogue and Digital National University Roll No: __________
Communication Lab
(EL323)
of Computer and Emerging Sciences
Islamabad Fall 2016
11
____________________________________________________________________________________
Basically. DAC is a digital code which represents digita value converted to analog voltage or
current. Below given figure 8 is s genral 4 bit DAC binary codes, the digital input terminal D 3, D2,
D1 and D0 are manipulated by the register in a digital system.
The 4-bit code represents 24=16 group of 2 binary value, as shown in figure 9. For every binary
code input, DAC will output a voltage (Vout), which is double or other order of the binary value.
Figure-8: Truth-Table
Figure 9 is the basic block diagram of DAC. The reference voltage connects to the resistor network, while
the digital input codes are used to control the different switches and is decided whether the reference
voltage connects to resistor network or not. Normally, the DAC output is represented by current, if we wanr
to obtain the voltage the we need to connect an operational aamplifier.
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Page 8 of 18
Lab #
Analogue and Digital National University Roll No: __________
Communication Lab
(EL323)
of Computer and Emerging Sciences
Islamabad Fall 2016
11
____________________________________________________________________________________
Figure-10: Circuit Diagram of DAC with 4-bit R-2R ladder resistor network
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Page 9 of 18
Lab #
Analogue and Digital National University Roll No: __________
Communication Lab
(EL323)
of Computer and Emerging Sciences
Islamabad Fall 2016
11
____________________________________________________________________________________
Where D3, D2, D1 and D0 can be divided into 0 and 1, if switch is on the 1 otherwise 0. So, we just need to
control the values of D3, D2, D1 and D0 correctly and we can get the required output current.
Input Weigtage:
From the DAC digitaal input, when only one of the bit is on and other bits are zero, the DAC output
signal range is called input weight. From figure 8, if every time, we let one of the bits D3, D2, D1 and D0 as
high level and the other bits are at zero level then the value of lowest bit D 0 is 1V, D1 is 2V, D2 is 4V, D3 is
8V. For every bit, the input wieght starts from the lowest bit and then increases by following the weight.
So, we can say that Vout is the sum of weight of the digital input. For example, to find the V out of digital
input 0111, we can sum D2, D1 and D0 bits weight and the total value is 4+2+1=7V.
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Page 10 of 18
Lab #
Analogue and Digital National University Roll No: __________
Communication Lab
(EL323)
of Computer and Emerging Sciences
Islamabad Fall 2016
11
____________________________________________________________________________________
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Page 11 of 18
Lab #
Analogue and Digital National University Roll No: __________
Communication Lab
(EL323)
of Computer and Emerging Sciences
Islamabad Fall 2016
11
____________________________________________________________________________________
The objective to let the courretnt Iout to connecct with the amplifier is to convert the current into voltage. In
the abobe figure, the output voltage is
As
So,
Where I out and Í out are in complementary relations, so when I out equals I FS Í out is zero.
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Page 12 of 18
Lab #
Analogue and Digital National University Roll No: __________
Communication Lab
(EL323)
of Computer and Emerging Sciences
Islamabad Fall 2016
11
____________________________________________________________________________________
Table-1:
The measured results of ADC0804
Digital Output
Analog Input
Ideal Values Experimental Values
Voltages (V)
Binary Digits Binary Digits
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
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Page 13 of 18
Lab #
Analogue and Digital National University Roll No: __________
Communication Lab
(EL323)
of Computer and Emerging Sciences
Islamabad Fall 2016
11
____________________________________________________________________________________
Table-2:
The measured results of ADC0809
Digital Output
Analog Input
Ideal Values Experimental Values
Voltages (V)
Binary Digits Binary Digits
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
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Page 14 of 18
Lab #
Analogue and Digital National University Roll No: __________
Communication Lab
(EL323)
of Computer and Emerging Sciences
Islamabad Fall 2016
11
____________________________________________________________________________________
Table-3:
The measured results of ADC0809 multi-channel input
Digital Output
Analog Input (Ideal Value)
SW3 SW2 SW1 (Experimental Value)
Input Terminal Voltage (V) Binary Digits
GND GND +5 V IN1
GND +5 V GND IN2
GND +5 V +5 V IN3
+5 V GND GND IN4
+5 V GND +5 V IN5
+5 V +5 V GND IN6
+5 V +5 V +5 V IN7
Table-4:
The measured results of DAC0800 unipolar output voltage
Table-5:
The measured results of DAC0800 bipolar output voltage
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Page 16 of 18
Lab #
Analogue and Digital National University Roll No: __________
Communication Lab
(EL323)
of Computer and Emerging Sciences
Islamabad Fall 2016
11
____________________________________________________________________________________
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Page 17 of 18
Lab #
Analogue and Digital National University Roll No: __________
Communication Lab
(EL323)
of Computer and Emerging Sciences
Islamabad Fall 2016
11
____________________________________________________________________________________
Student's feedback (Try giving useful feedback, e.g. did this lab session help you in learning, how to
improve student's learning experience, was the staff helpful, etc):
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Correctness of
TOTAL
AWARDED
Attitude
Neatness
Conclusion
Originality
Initiative
MARKS
TOTAL 10 10 10 20 20 30 100
EARNED
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