09 Verilog Tutorial 1
09 Verilog Tutorial 1
sel out
0 in0
1 in1
Gate Level Modelling Cont...
Data types
● Input - input port
○ input in // 1 bit input port
○ input [3:0] in //4 bit wide input port
● output - output port
○ output out // 1 bit output port
○ Output [3:0] out //4 bit wide output port
● inout - bidirectional port
● Wire (nets) - represent connections between hardware elements
○ wire [7:0] //8 bit wide wire
○ Default value is is z (floating state/High impedance)
Data types Cont...
● Register data types
○ They are not same as hardware registers
○ Used to store values
○ Different variants depending on the value stored
■ reg - unsigned values
■ integer - signed values
■ real - floating point values
○ values are assigned using “=” operator
○ Stores values until a new assignment occurs
Why Behavioural Modelling?
● It's easy to model complex circuits by behavior rather than thinking of implementing them in
terms of gates or data flows.
● Here circuit’s are modelled at a very high level of abstraction. Design at this level resembles
C programming more than it resembles digital circuit design
● Verilog is rich in behavioral constructs that provide the designer with a great amount of
flexibility
Behavioural Modelling in Verilog
● Two basic blocks in Verilog behavioural modelling
○ Always - (To represent iterative blocks)
○ Initial - (Mainly in stimulus/testbench)
initial block
● Sensitivity list determines when
the always block will be triggered
Initial block
● Start at time 0, executes only once
● Multiple initial blocks can start
concurrently & finish independently of
one another
● Usually used in testbench modules,
Practice Exercise
Design a 2:4 decoder using behavioural modelling
Enable Inputs Outputs
E A1 A0 Y3 Y2 Y1 Y0
0 x x 0 0 0 0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
Logic gate design for 2:4 Decoder