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09 Verilog Tutorial 1

The document provides an overview of Verilog, describing it as a hardware description language used for simulating digital circuits. It explains that Verilog offers different levels of programming abstraction including gate, behavioral, and register transfer levels. Key concepts covered include data types in Verilog, behavioral modeling using always and initial blocks, and an example of designing a 2:4 decoder using behavioral modeling.

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43 views

09 Verilog Tutorial 1

The document provides an overview of Verilog, describing it as a hardware description language used for simulating digital circuits. It explains that Verilog offers different levels of programming abstraction including gate, behavioral, and register transfer levels. Key concepts covered include data types in Verilog, behavioral modeling using always and initial blocks, and an example of designing a 2:4 decoder using behavioral modeling.

Uploaded by

Sachintha
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Verilog Tutorial

Prepared by: Amila Indika, Mahendra Bandara


Verilog
● Verilog is one of the Hardware Description Language (HDL)
○ Verilog is mainly used for simulation of digital circuits
○ It is a concurrent language unlike C,Java

● It offers several levels of programming abstractions


○ Gate Level - (Covered in CO221)
○ Behavioural Level - (Focus in this session)
○ Register Transfer Level - (Beyond the scope of this course)
Gate Level Modelling

sel out

0 in0

1 in1
Gate Level Modelling Cont...
Data types
● Input - input port
○ input in // 1 bit input port
○ input [3:0] in //4 bit wide input port
● output - output port
○ output out // 1 bit output port
○ Output [3:0] out //4 bit wide output port
● inout - bidirectional port
● Wire (nets) - represent connections between hardware elements
○ wire [7:0] //8 bit wide wire
○ Default value is is z (floating state/High impedance)
Data types Cont...
● Register data types
○ They are not same as hardware registers
○ Used to store values
○ Different variants depending on the value stored
■ reg - unsigned values
■ integer - signed values
■ real - floating point values
○ values are assigned using “=” operator
○ Stores values until a new assignment occurs
Why Behavioural Modelling?
● It's easy to model complex circuits by behavior rather than thinking of implementing them in
terms of gates or data flows.

● Here circuit’s are modelled at a very high level of abstraction. Design at this level resembles
C programming more than it resembles digital circuit design

● Verilog is rich in behavioral constructs that provide the designer with a great amount of
flexibility
Behavioural Modelling in Verilog
● Two basic blocks in Verilog behavioural modelling
○ Always - (To represent iterative blocks)
○ Initial - (Mainly in stimulus/testbench)

initial always @ (sensitivity list)


begin begin
... ...
<internal code> <internal code>
... ...
end end
Always Block
● Starts at time 0 and executes
statements as a normal loop input and output data

● Looping can be halted either


type cannot store values.
For that reg is used
or output reg out

By ‘$stop’ or ‘$finish’ inside an


When one of this changed this block will be executed

initial block
● Sensitivity list determines when
the always block will be triggered
Initial block
● Start at time 0, executes only once
● Multiple initial blocks can start
concurrently & finish independently of
one another
● Usually used in testbench modules,
Practice Exercise
Design a 2:4 decoder using behavioural modelling
Enable Inputs Outputs

E A1 A0 Y3 Y2 Y1 Y0

0 x x 0 0 0 0

1 0 0 0 0 0 1

1 0 1 0 0 1 0

1 1 0 0 1 0 0

1 1 1 1 0 0 0
Logic gate design for 2:4 Decoder

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