Basic Digital Logic Design

Use Boolean Algebra, Karnaugh Mapping, or an Easy Free Open-

Source Logic Gate Simulator
Disclaimer of Warranty
Copyright©2019 Stephen Bucaro. This material is provided "as-is", the publisher and author make no
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Contents
• Introduction
• Fundamental Digital Logic Gates
• Boolean Algebra
• Karnaugh Mapping
• Logic Gate Simulator
• Binary Numbers
• Binary Adders
• Transfer Characteristics
• Flip-Flops
• Registers
• Counters
• Setup and Hold Times
• Decoders
• Encoders
• Multiplexers and Demultiplexers
• Parity Generator and Parity Checker
• State Machines
 Introduction

CONTENTS

Digital design is based on the binary principle, where everything is either 0 or 1, either low or high. Few
people realize that digital logic existed before the advent of the computer. Digital logic was used for control
and communications systems even before semiconductors where invented. They worked using switches,
relays and solenoids.

If you search the internet you will not find the phrase digital logic separate from computers. It's like the only
purpose for digital logic was to invent the computer. I'm sorry, but as an electronics engineer before
computers, I designed all kinds of control systems for transportation, farming, manufacturing, and many other
industries, using digital logic. In fact it was a heck of a lot more fun than programming today's
microprocessors.

Now days, much of the work of a system is accomplished in programs, but the programs must have a digital
device to execute on. Today, almost all systems work using a microcontroller or microprocessor running a
software. But that's not always the most efficient way to do it. In a system there is always a trade-off between
accomplishing a task with software or hardware (digital logic), each has its advantages.

In this book almost everything is done with a digital logic design, except for the last chapter, State Machines
which is done with software. Although it is possible to design a state machine using digital logic, most texts,
use only block diagrams to describe a state machine. In today's world it would not be considered practical
design a state machine using digital logic. But to make sure you are familiar with the concept, I have provided
some code that, to use you simply hcut and paste it into a text file, save it with the file extension .htm, and
then open it in your web browser.

Software is usually cheaper because increasing its functionality does not require adding more physical
material other than possibly more memory to store the code in. Hardware, like digital logic, is faster and in
some circumstances more reliable. At some point the system has to interface with the real world. Software
can't do the job. That's where hardware comes in.

With digital design you are involved with problem solving. You have a set of inputs and you must design the
logic that will turn that into the desired output or outputs. To accomplish that task you can use Boolean
algebra or Karnaugh mapping. All the advanced features of the most powerful computers, such as mulicore
and parallel processing are done with digital logic. This book will give you the basic principles you need to
design digital logic circuits.
 Fundamental Digital Logic Gates

CONTENTS

Lets look at a simple electric circuit with a battery, a light bulb, and a switch. This circuit is shown below.

With the switch open, the light bulb does not illuminate.

With the switch closed, the light bulb illuminates.

Lets designate the situation where the light is off as "0". Lets designate the situation were the light is
illuminated as "1". What we have is a system with two possible situations, referred to as a "binary" system.

It doesn't matter what voltage the battery is, as long as its high enough to illuminate the light. Light off is
binary 0. Light on is binary 1.

Lets make a slightly more complex circuit.

In the circuit shown above, switch A is open, but the light is still illuminated. That's because switch B is
closed, providing a path from the battery to the light.

The idea behind this circuit is - if switch A OR switch B is closed, the light is illuminated. If both switched
are open, the light will not be illuminated. Of course if both switched are closed the light will be illuminated.

This circuit functions as what we call a logical OR gate.

In the circuit shown above, switch A is closed, but the light is not illuminated. This is because switch B is
open, breaking the path to the battery. If switch B were to be closed, the light would be illuminated because
then there would be a closed path from the battery to the light.

If either switch is open, the light will not be illuminated. Both switch A AND switch B must be closed for the
light to be illuminated.

This circuit functions as a logical AND gate.

These circuits demonstrate the fundamental concept of logic circuits.

Let's substitute the symbol shown below for the logical OR gate function.

If voltage is applied (a logical 1) to either A OR B (or both), voltage (a logical 1) will appear at the output. If
neither input is 1, the output will be 0. The following table describes the logical OR function.
A B Out
0 00
0 11
1 01
1 11
This table is called a "truth table". It is the truth table for a 2-input OR gate.

Let's substitute the symbol shown below for the logical AND gate function.

If a logical 1 is applied only to input A, or only to input B, the output will be 0. Both inputs must be 1 for the
output to be 1. The following table describes the logical AND function.

A B Out
0 00
0 10
1 00
1 11
This is the truth table for a 2-input AND gate.

Let's introduce a very simple gate shown below.

The output of this gate is always the binary opposite of the input. For example if A is 0, the output is 1. If A is
1, the output is 0. This describes the logical NOT function. many people just call it an "inverter". The
following table describes the logical NOT function.

A Out
0 1
1 0
Let's introduce one more gate before we move on to bigger things.
This is an "exclusive or gate" - XOR. The output of the XOR gate is 1 only if
input A or input B are 1. If input A and input B are both 0, or if input A and
input B are both 1, The output of the XOR gate is 0. The following table
describes the logical XOR function.
A B Out
0 00
0 11
1 01
1 10
A gate is not restricted to only 2 inputs. Shown below is a 3 input AND gate.

This is the truth table for a 3-input AND gate:

A B C Out
0 000
0 010
0 100
0 110
1 000
1 010
1 100
1 111
Shown below is a 3 input XOR gate.
This is the truth table for a 3-input XOR gate:

A B C Out
0 000
0 011
0 101
0 110
1 001
1 010
1 100
1 110
Be careful with the last line in this truth table. Many people have been cascading XOR gates to create the odd-
parity checking function. They think the output of the last line should 1. XOR is logic gate, not an odd-parity
checking gate. Apparently they don't understand the meaning of the word "exclusive". IEEE-Std91a-1991
gives the symbol for the exclusive-OR on p. 62 with the definition "The output stands at its 1 state if one and
only one of the two inputs stands at its 1 state."

Shown below is a 2-input AND gate whose output is used as the input to a NOT gate. This creates the NAND
function.

We don't actually need to construct such a circuit because this function is performed by a a NAND gate, the
symbol of which is shown below.

This is the truth table for a 2-input NAND gate:

A B Out
0 01
0 11
1 01
1 10
As you can see the output of the NAND gate is the opposite of the AND gate. Why would they bother to put
such a function as a fundamental gate? Actually combinations of NAND gates can be used to create any of the
other basic logic functions. This makes the NAND gate one of the most useful logic gates.

Shown below is a 2-input OR gate whose output is used as the input to a NOT gate. This creates the NOR
function.

We don't actually need to construct such a circuit because this function is performed by a NOR gate, the
symbol of which is shown below.

A B Out
0 01
0 10
1 00
1 10
As you can see the output of the NOR gate is the opposite of the OR gate.

Shown below is an example of what those designers who have been cascading XOR gates to create the odd-
parity checking function are doing.

A B C Y Out
0 000 0
0 0 1 0 1
0 1 0 1 1
0 1 1 1 0
1 0 0 1 1
1 0 1 1 0
1 1 0 0 0
1 1 1 0 1
To construct this logic table, you would first enter the values of Y based on A XORed with B. Then you
would enter the Output values based on C XORed with Y. Note how that last output disagrees with the same
out from the XOR logic table.

That concludes my explanation of fundamental digital logic gates. If you understood most of what is in this
section, you are well on your way to becoming a digital logic designer. But in order to do that, you will want
to get a working knowledge of Boolean Algebra, a mathematical technique to design complex logic circuits
developed by English mathematician George Boole (1815 - 1864).
 Introduction to Boolean Algebra

CONTENTS

In computer logic, input and output values can be one of only two possible values, 0 or 1. These are called
Boolean values. In some programming languages a Boolean variable can have one of two possible values, true
or false, but in these languages true represents 1 and false represents 0.

Algebra is a system of laws and techniques that can be used to simplify mathematical expressions. Similarly,
Boolean Algebra, named after its inventor the English mathematician George Boole (1815-1864) is a set of
postulates and laws that can be used to simplify logical equations.

In Boolean algebra the plus (+) symbol represents the logical OR operation, the dot (.) represents the logical
AND operation, the prime (') represents the compliment operation (e.g. changing 0 to 1 or changing 1 to 0).

I know that to someone unfamiliar with Boolean algebra, the tables below look scary and boring, but you
don't need to pay much attention to them at this point, I'm simply introducing them. You'll understand them
more easily after I give examples of the use of some of these postulates and laws.

Boolean Algebra Postulates (sometimes called identities)

Boolean Algebra Laws

Converting a Logic Diagram Into Boolean Expression

The primary use of Boolean algebra is to simplify or reduce the gate count of logic circuits, while still having
them perform the same logic function. The first step then, would be to convert the schematic of the circuit you
want to reduce into a Boolean expression. This is not difficult to do. Just work from left-to-right through the
circuit, expressing the logic of each gate in Boolean algebra. Lets convert the logic circuit shown below.
The inputs to the circuit are A,B,C. The output of the fist AND gate is A.B.C. (When expressing an AND
operation in Boolean algebra, the "dot" symbol is optional). The output of the first inverter is B', the output of
the second inverter is C'.

The outputs of the two inverters become inputs to an OR gate, the output of the OR gate then becomes B'+ C'.
This is one input to an AND gate, ANDed with A, the output of the AND gate is A(B'+C').

The output of the first AND gate, ABC along with the output of the second AND gate, A(B'+C'), becomes the
input to an OR gate, resulting in the circuits output function being (ABC) + A(B'+C'). This is the Boolean
statement for this circuit that you would use the rules above to simplify.

Boolean Algebra Order of Operations

In order to apply the rules of Boolean algebra to simplify a logic expression you must use the proper order of
operations. Fortunately the order of operations is the same as that for conventional algebra. From left to right,
operations inside brackets are evaluated first, bars over multiple variables are at the same level as brackets.

The highest operator precedence is the NOT operator. This is followed by the AND function (which has
exactly the same effect as multiplication in conventional algebra), then by the OR function (which has exactly
the same effect as addition in conventional algebra).

Circuit Simplification Examples

Example 1:
C+(BC)'

1. Following the order of operations, we want to direct our attention to the variables within the brackets first.
Also the operator precedence is the NOT operator. Use Demorgan law to change the AND within the brackets
to OR:

C+(B'+C')

2. Use associative law to put C with C':

(C+C')+B'

3. Use complement law to replace C+C' with 1

1+B'

4. Use identity law to eliminate the 1

B'

We find out that the output of the circuit is always the opposite of B, the value of the variable C has no effect
in the circuit, so the entire circuit can be replaced by a single NOT gate.

Example 2:

AB+BC(B+C)

1. Again, we want to direct our attention to the variables within the brackets first. Use distributive law of
ANDing over ORing to get the expression out of the brackets.

AB+BBC+BCC

2. Use identity law in second and third terms. ANDing a variable with itself
is always equal to that variable.
AB+BC+BC

3. Use identity law in second and third terms. ORing a variable with itself is
always equal to that variable.
AB+BC

4. Factor out the B terms.

B(A+C)

The result is, we need only two gates to accomplish the same logical function.

Example 3:

AB + A(B+C) + B(B+C)

1. Use distributive law of ORing over ANDing to get rid of the brackets in second and third terms.

AB + AB + AC + BB + BC

2. Use the identity law of ORing on first two terms and the identity law of ANDing on the fourth term. In
other words AB + AB = AB, and B . B = B.

AB + AC + B + BC

3. Use Redundance law on last two terms B + BC = B.

AB + AC + B

4. Use Redundance law on first and last terms AB + B = B.

B + AC

Note that this example uses the redundancy laws called absorption. These laws seem to magically make a
term disappear. If you are curious enough you may wish to search the Internet for a proof of this law. My
purpose in this text is to show how to put Boolean Algebra to practical use in designing digital circuits, not to
dwell heavily into mathematical proofs.

Example 4:
(A'+ B')'

de Morgan's law is very useful in circuit simplification. I refer to it as a "bar" breaker. To break a bar in a
Boolean expression, change the logic operation (e.g. OR to AND, or AND to OR), then break the bar.

A''. B''

Now each term has a double NOT, which means the NOT bars cancel out and can be removed.

A.B

So the circuit can be simplified to a single AND gate.

Example 5:

(A'. B')'

Similar circuit except with a NAND gate. Change the logic operation, ANDto OR, then break the bar.

A''+ B''

Now each term has a double NOT, which means the NOT bars cancel out and can be removed.

A+B

So the circuit can be simplified to a single OR gate.

Moving from left to right performing operations inside brackets, dealing with bars, following operator
precedence, and using the Boolean algebra laws and postulates, you should be able to reduce any logic
function to the fewest number of gates required.
 Karnaugh Mapping

CONTENTS

A Karnaugh map (K-map) is a graphical method used to minimize Boolean expressions without having to use
Boolean algebra theorems and equation manipulations. This method is named after its inventor the physicist
Maurice Karnaugh (1924 - ). A K-map can be thought of as a special version of a truth table. Let's start with a
K-map of two variables.

The Karnaugh procedure described here is called Sum-Of-Products (SOP). An SOP solution finds groups of
1's in the k-map and OR's them together to form the Boolean expression for the logic table.

• If the output column of the truth table is 0 more often then it is 1, then it might be easier to use the Product-
Of-Sums (POS) method. A Product-Of-Sums (POS) design works similarly, but finds groups of 0's and
AND's them together to form the Boolean expression for the logic table. For a given truth table, either method
will produce the same result.

Definition:product. In digital logic the result of ANDing is called a product.

Definition:sum. In digital logic the result of ORing is called a sum.

Definition:literal. A literal is a variable in a Boolean expression. For example in the expression ab - a is a

literal. It might be written as a', but still the same literal. b is also a literal. It might be written as b', but still the
same literal.

Definition:minterm. A minterm is a row in a truth table where all the literals are ANDed together. For
example if you have a row with a'b, that would be a minterm.

Definition:maxterm. A maxterm is a row in a truth table where all the literals are ORed together. For example
if you have a row with a + 'b, that would be a maxterm.

2-Input Example

Step 1. Convert the truth table into a k-map.

• To draw a K-map for "n" inputs you need 2^n, so for a 2-input k-map you need 4 cells.

Step 2. Find groups.

• To form groups, circle adjacent 1's in a column, and circle adjacent 1's in a row.

Step 3. Create a Logical Expression (minterm) for Each Group.

• The minterm for the first group is Y = A.

• The minterm for the second group is Y = B'.

Step 4. Combine (OR) the Logical Expressions into a Boolean Equation for the Output (OR them).

Y = A + B'

The two expressions (minterms) are ORed together. This is called a SOP (Sum Of Products).

Step 5. Design the Digital Circuit

3-Input Example

Step 1. Convert Truth Table to K-map

Wherever a 1 occurs as an output in the truth table, place a 1 in the corresponding cell in the Karnaugh map.

Step 2. Find Groups

Step 3. Create a Logical Expression for Each Group.

Remember that the output of each group is 1.

In the top group A is 0, B is 1.

C is 1 in one place and 0 in the other so C has no affect on the output and can be eliminated.
The Boolean expression for this group is A' B.

In the bottom group A is 1, C is 1.

B is 0 in one place and 1 in the other so B has no affect on the output and can be eliminated.
The Boolean expression for this group is AC.

Step 4. Combine Logical Expressions Into a Boolean Equation for the Output (OR them).

A' B + AC = Y

Step 5. Design the Digital Circuit

Another 3-Input Example

Step 1. Convert Truth Table to K-map

Step 2. Find Groups

Step 3. Create a Logical Expression for Each Group.

In the horizontal group A is 0, C is 1.

B is 0 in one place and 1 in the other so B has no affect on the output and can be eliminated.
The Boolean expression for this group is A' C.

In the vertical group B is 0, C is 1.

A is 0 in one place and 1 in the other so A has no affect on the output and can be eliminated.
The Boolean expression for this group is B'C.

Step 4. Combine Logical Expressions Into a Boolean Equation for the Output.

A' C + B' C = Y

Step 5. Design the Digital Circuit

Although the Karnaugh map method allows you to minimize Boolean expressions without having to use
Boolean algebra, After about 5 inputs, where you need 32 cells, they become just about as difficult as Boolean
algebra with the same number of inputs.

4-Input Example
Step 1. Convert Truth Table to K-map
Step 2. Find Groups

Step 3. Create a Logical Expression for Each Group.

Remember the columns in a k-map loop around, so the top two boxes on the left side loop around to join the
top two boxes on the right side creating the first group. The Boolean expression for this group is A'D'.

A k-map also loops around vertically, so the four corner boxes loop around to join, creating the second group.
The Boolean expression for this group is B'CD'.

The third group loops around horizontally creating the Boolean expression A'BC'.

Step 4. Combine Logical Expressions Into a Boolean Equation for the Output.
A'D' + B'CD' + A'BC' = Y

Step 5. Design the Digital Circuit

Conclusion

If you've gotten this far in this book, you've worked your way through Boolean Algebra and Karnaugh
Mapping. These are both methods that are loved by puzzle-heads. That's right, there are actually people out
there who love working with things that are difficult and confusing. But for the rest of us, there's Logic Gate
Simulator applications, many of them free. One of the best ones is named Logic Gate Simulator and is a free
open-source tool for experimenting with and learning about logic gates. It has a mind-blowingly simple drag-
and-drop gate layout and wiring interface. You can download it at https://www.kolls.net/gatesim/
 Logic Gate Simulator

CONTENTS

Boolean Algebra and Karnaugh Mapping are methods used to used to minimize the number of gates required
to perform a function. These methods are fine if you love to solve puzzles. But there are simulator
applications that can make life much easier for you. Logic Gate Simulator is a free open-source tool for
experimenting with and learning about logic gates. You can download it at https://www.kolls.net/gatesim/
We're going to use Logic Gate Simulator to study a Data Selector circuit. Logic Gate Simulator has a mind-
blowingly simple drag-and-drop gate layout and wiring interface. To design the data selector circuit, drag 3
NAND gates and a NOT gate from the components library to the design area as shown above. Note that the
image above shows a buffer instead of a NOT gate. Don't use the buffer, drag an actual NOT gate from the
library.

The image above shows the NOT gate along with some other components, input and output terminals and two
oscillators, drag-and-dropped from the library. Make connections between the gates and components by
locating your mouse pointer over a connection point and pressing and holding the mouse button while draging
a "wire" to the other connection point. Set the frequencies of the oscillators by clicking on them and typing in
the frequency. The exact frequency is not important, but one should be twice that of the other so you can see
which one data selector circuit selected.
In the menu select Show Logical Analyzer (Oscilloscope).

When you click on the User input component, it will toggle between white and red. White indicates a logic 0,
red indicates a logic 1. Note in the image above when the input is 0, the top oscillator is sent to the output, as
shown above.
When the input is 1, the bottom oscillator is sent to the output, as shown above.

You'll note in the top oscilloscope trace, when user input is 0, the selected waveform has a glitch in it. This is
most likely caused by me initiating processes on my computer while Logic Gate Simulator is running.
 Binary Numbers

CONTENTS

Digital computers perform all of their amazing work with only two voltage levels. One of those voltages is 0
volts. The other voltage can be anything from 2.5 volts or lower, up to 5 volts, as long as it's not 0 volts. A
computer interprets 0 volts as "0", and the other voltage as "1".

Humans use the decimal number system. The decimal number system uses ten characters; 0,1,2,3,4,5,6,7,8,
and 9 to represent numbers. That's why decimal numbers are sometimes called base-10 numbers.

Computers use the binary number system. The binary number system has only two characters; 0 and 1. The
binary numbers are base-2 numbers. You would think that would make computers very limited, but their
amazing speed more than compensates for the limited number of characters in their number system.

The decimal system is a positional system. That means the actual value of a digit depends on its position in a
number. For example in the number 10, the 1 represents ten units, while in the number 100, the 1 represents
one hundred units. To interpret a number you add together the values of all the digits in their positions in the
number. For example 110 equals one hundred and ten units.
The binary system is also a positional system. The binary number 10 equals a value of 2 in the decimal
system. The binary number 100 equals decimal system 4. Similar to the decimal system, to interpret a number
you add together the values the digits in their positions. For example the binary number 110 equals decimal
system 6.

You might think it's very difficult to convert binary to decimal but all you have to do is think in powers of 2.
Lets think about binary numbers with 4 characters. Going from right to left the powers of 3 would be valued
at decimal 1, 2, 4, and 8. It's actually easier to think from left to right, so the positions would be valued at
8,4,2,1.

So a the binary number 1010 equals 8+2 or decimal 10. The binary number 0110 equals 4+2 or decimal 6.
The binary number 1101 equals 8+4+1 or decimal 13.

Representing Negative Binary Numbers

If a processor has 8 bit registers, the largest binary number it can store is 11111111 (255 decimal). If we want
to use 8 bit registers to represent signed numbers, we can allocate one of the register's cells to represent the
number's sign. Conventionally the left-most cell is reserved for the sign bit. A value of 0 in the sign bit cell
indicates that the register contains a positive number. A value of 1 in the sign bit cell indicates that the register
contains a negative number.

Giving up a register cell, leaving only seven bits to represent a number, allows a register to hold positive
numbers up to only 1111111 (127 decimal). However it allows us to also represent negative numbers down to
-128.

Adding Binary Numbers

Adding binary numbers is easy if you remember that 1 + 1 = 0 with a carry of 1. If you're adding 1 + 1 + (a
carry of 1), the sum is 1 with a carry of 1, in other words 1 + 1 + 1 = 1 with a carry of 1. Some examples are
shown below.
These examples might be stored in a seven-bit registers. In the last example, a carry bit from the most
significant bits goes beyond the seven bits that the register can hold. This carry bit would become an
"overflow" bit and would be stored in a special "status" register that, when checked by the software would
cause an "exception" that might cause the the results to go to a different format.

Subtracting Binary Numbers

Subtracting binary numbers might also be easy for humans, but it's easier to design logic circuits to add, so
computers subtract by adding the two's compliment of the subtrahend. For example to subtract 0111 from
1001 you first have to convert 0111 to it's two's compliment.

To convert a number to its two's compliment, invert the number (change every 0 to a 1, and change every 1 to
an 0) then add 1. Some examples are shown below.
In the last example, 23 - 29 results in a negative result. A value of 1 in the left-most cell, the sign bit, indicates
that the register contains a negative number.

The Hexadecimal Number System

Computers today use 64 bit, or 128 bit, or even larger numbers. You can imagine this would make them very
difficult to convert to decimal, or for humans to comprehend at all. To allow humans to more easily
comprehend binary numbers, the hexadecimal number system is used.

The hexadecimal number system involves breaking long binary numbers into chunks of four bits. Then,
similar to the decimal number system, different characters are used to represent the value of the four bits in a
position. We use the same characters as the decimal system, but unfortunately binary chunks of 1010, 1011,
1100, 1101, and 1111 are greater than 9. We need 16 different characters. So we start using the characters a, b,
c, d, e, and f to complete the set. The hexadecimal number system is base-16.

So counting in hexadecimal goes like this; 0,1,2,3,4,5,6,7,8,9,a,b,c,d,e,f. The hexadecimal system is also a
positional system. So, for example, when you get to f in the far right position, and you want to add one more,
you set the right postion to 0 and carry a 1 to the next position to the left.
This reminds you of the decimal position system where when you get to 9 in the far right position, and you
want to add one more, you set the right postion to 0 and carry a 1 to the next position to the left. Except in the
hexadecimal system, the 1 you are carrying is worth 16 (decimal).

To go further, if the second position from the right reaches f and you need to add a hexadecimal 1 to that
position, you would set it to 0 and carry a 1 to the next position to the left. Except in this position the 1 you
are carrying is worth 256 (decimal).

As intuitive as this "carry a 1" procedure is in the decimal, for most people it is difficult to understand when
doing it in the hexadecimal number system. Not to worry, in practice nobody actually ever does that in the
hexadecimal number system. The whole thing with hexadecimal numbers is to just try to visualize their
values, just like you would visualize the value of a decimal number like say 230.

The 0x Prefix

If you're looking at the number bf2 you can be sure it's a hexadecimal number, but what if you're looking at
the number 269? Is it a decimal number or a hexadecimal number? This is important because 269
hexadecimal equals 617 decimal (but 269 decimal equals 269 decimal). That's why it's standard procedure to
prefix a hexadecimal number with 0x, as in 0x269. Note that the 0x at the front of a hexadecimal number has
no numerical value itself, it's just characters to identify the number as being a hexadecimal number.

Byte, Kilobyte, and Megabyte

Earlier I mentioned that The hexadecimal number system involves breaking binary numbers into chunks of
four bits. In the early days, computers were designed to handle 8 bits at a time. That's why 8 bits is called a
byte. In other words a byte requires 2 hexadecimal characters (example 0xb5).

Today 64-bit processors are common, which means that they can handle 64 bits at a time. But did we change
the definition of byte from 8 bits to 64 bits? No, we just say a 64-bit processor can handle 8 bytes at a time.

Now, as you know, in the metric system a Kilo is 1000 of something. So is a Kilobyte 1000 bytes? Well, yes
and no. If you're talking about binary mathematics, 1 kilobyte = 1024 bytes. But if you're talking about the
storage capacity of a disk drive, 1 kilobyte = 1000 Bytes. A way for disk drive makers to cheat? Maybe.

Lets just say when were talking about a kilobyte, we mean about a 1000 bytes. To go further, 1000 kilobytes =
1 megabyte. 1000 megabytes = 1 gigabyte. 1000 gigabytes = 1 terabyte. Of course when you get to the
terabyte range, the difference between 1000 gigabytes and 1024 gigabytes equaling a terabyte is 24 gigabytes,
that's a considerable difference.
 Binary Adders

CONTENTS

One important functions performed by digital logic is mathematics. This section describes the digital logic
circuits used to perform binary addition and subtraction.

A B Sum Carry
000 0
011 0
101 0
110 1
The circuit shown above and its accompanying logic diagram performs the function of adding two one-bit
binary numbers. The output of the circuit provides the sum along with a possible carry. When adding higher-
bit binary numbers however, provisions for a carry-in from a previous stage must be provided. For this reason,
this circuit is called a "half-adder".

In the circuit shown above, a second stage has been added to accept a carry-in from a previous stage. The
carry-out of this circuit is created by ORing the carry bits of both stages. This circuit is called a "full-adder".
 Logic diagram of the full adder.

To simplify circuit diagrams we could indicate a full adder using a simple box labeled with the circuit's
function and with its inputs and outputs labeled.

By connecting eight full-adder circuits together, each circuit's carry-out output to the carry-in input of the next
circuit, we can construct an eight-bit binary adder.
A Control Out
0 0 0
1 0 1
0 1 1
1 1 0

Shown above is an exclusive OR (XOR) gate and it's logic table, except this time we labeled one of its inputs
Control. Note that when the control input is low (binary 0), the output is the same as the binary value on the A
input. When the control input is high (binary 1), the output is the inverted value of the A input. What we have
here is a controllable inverter. In other words with 0 on control, the input passes though unchanged, with 1 on
control, we have an inverter.

As previously described, in binary mathematics, subtracting a number is accomplished by instead adding the
two's complement of the number. In the circuit shown above we run every bit of the second number of a
binary math operation through a controllable inverter. If we wish to add the two numbers, we put 0 on the
control line. If we wish to subtract the second number we put 1 on the control line. (In actual operation we
would need to add 1 to the inverted number before adding).
 Digital Logic Transfer Characteristics

CONTENTS

In an ideal world, the inverter circuit shown above would invert the signal instantaneously.

In the real world, gates don't transfer logic levels instantaneously. It takes a finite amount of time for electrons
and holes to move through the semiconductor material. Okay, so typical CMOS gate propagation delays are
less than 100 ps (pico seconds), but there are other delays in the real world circuit caused by parasitic
resistance, capacitance, and inductance.

In the real world, a binary 0 is not represented by exactly zero volts. The above mentioned effects cause a
binary low to be at some voltage below V(OLmax). When the output from the inverter gate on the left
switches from high-to-low, the input of the inverter gate on the right won't recognize that switch until the
voltage falls below V(ILmax). Only then will the second inverter begin to switch its output logic level from
low to high.
The actual voltages of these transfer characteristics depends upon the semiconductor type, family, and applied
source voltage.

In the real world, a binary 1 is not represented by exactly the supply voltage. The above mentioned effects
cause a binary 1 to be at some voltage above V(OHmin). In the circuit shown above, when the output of the
inverter gate on the left switches from low-to-high, the input of the inverter gate on the right won't recognize
that switch until the voltage falls below V(IHmin). Only then will the second inverter begin to switch its
output logic level from high to low.

What if the output voltage of the inverter gate on the left begins to go low, achieves V(OLmax), but a
transient causes the output voltage to spike above V(OLmax) before it drops back to V(OLmax)? The input of
the inverter gate on the right would not see the transient as long as the voltage spike does not go above
V(ILmax). It would switch its output to high as normal.
The voltage range between V(OLmax) and V(ILmax) is called the lower noise margin.

Similarly, what if the output voltage of the inverter gate on the left begins to go high and achieves V(OHmin),
but then a transient causes the output voltage to spike below V(OHmin) before it rises back to V(OHmin)?
The input of the inverter gate on the right would not see the transient as long as the voltage spike does not go
below V(IHmin). It would switch its output to low as normal.

The voltage range between V(OHmin) and V(IHmin) is called the upper noise margin.

The real world is a noisy place (both audio wise and electrical wise), and if there were not noise margins built
into all logic circuitry, there would be no reliable electronics in this world. But noise margins don't mean you
can design electrically noisy circuits or operate circuitry in an electrically noisy environment without proper
shielding. If the output voltage of the inverter above spends too much time in the zone between V(ILmax) and
V(IHmin), there is no predicting what the output of the inverter on the right will do. This is the ambiguous
zone.
 Flip-flops

CONTENTS

Shown below is the logic diagram for an RS flip-flop created with NOR logic gates. A review of the logic
table for a NOR gate shows that a 1 on any input produces an 0 on the output. Only 1 on both inputs produces
a 1 on the output.

A 1 applied to the S (set) input causes its output to go to 0. The output is looped back to an input on the
bottom NOR gate, causing its output to go to 1. The output of the bottom NOR gate is also the output of the
RS flip-flop, which has now been set to 1.

After the set pulse is removed, the top NOR gate still has a 1 on an input, this time looped back from the
output of the bottom NOR gate, So the Q output remains set to 1.
A 1 applied to the R (reset) input causes its output to go to 0. The output is looped back to an input on the top
NOR gate, causing its output to go to 1. The output of the bottom NOR gate which is also the output of the RS
flip-flop, has now been reset to 0.

After the reset pulse is removed, the bottom NOR gate still has a 1 on an input, this time looped back from the
output of the top NOR gate, So the Q output remains reset to 0.

Shown above is the logic table for an RS flip-flop. A 1 applied to the S input sets the Q output to 1. A 1
applied to the R input resets the Q output to 0. The value m when 0 is applied to both inputs indicates that the
output maintains its previous value. The value n when 1 is applied to both inputs indicates a nonsense state. In
other words, you would never try to set and reset the flip-flop at the same time.

Add a few more gates to the input side of an RS flip-flop and you create a D type flip-flop, as shown above.
This flip-flop has a D (data) input and a C (clock) input. Binary data bits are available on the D input, but the
value of the data bit is not transferred to the output of the flip-flop until a clock pulse (a transitory binary 1) is
applied to the C input. The waveform for this is shown below.
Studying the logic diagram you can see that when 0 is applied to the C input, the output of both AND gates
will be 0, which leaves the RS flip-flop in its previous state. when 1 is applied to the C input, the value of the
D is applied to the top AND gate, and D's opposite value (because of the inverter) will be applied to the
bottom input. So if D is 1 when C is 1, the RS flip-flop will be set. If D is 0 when C is 1, the RS flip-flop will
be reset.

You can see how useful a D flip-flop is in storing data. Data is transferred and stored in the D flip-flop only
when its C control line is 1. When its C control line is 0, data on the D input will be ignored. That data may be
stored in a different D flip-flop without affecting this flip-flop. A D flip-flop is some times called a latch. To
simplify logic diagrams, a latch is usually drawn as a box.

Another type of flip-flop id the JK flip-flop. The logic diagram for the JK flip-flop is shown above. Note that
the JK flip-flop can be constructed with an RS flip flop and two 3-input AND gates. To simplify logic
diagrams, the JK flip flop is usually drawn as a box.

The values on the outputs of the JK flip-flop depend upon the values on inputs when the JK flip-flop is
clocked. The outputs do not change until there is a rising edge on the clock input. Shown below is the logic
table for the JK flip-flop.
The interesting thing about the JK flip-flop is that when it's clocked with logic 0 on both inputs, the outputs
don't change. When the JK flip-flop is clocked with logic 1 on both inputs, the outputs toggle, that is the value
on Q goes to /Q and the value on /Q goes to Q. This function of the JK flip-flop makes it very useful.
 Registers

CONTENTS

Registers are very important for storing a byte or word of data, and also for converting data from parallel to
serial or serial to parallel. A register is just a group of D flip-flops, or "cells". The register usually has as many
cells as the processor's word size.

Shown above is a 4-bit Parallel-In Parallel-Out (PIPO) register. The data bits are placed on the D0-D3 inputs,
then a clock pulse loads them into the flip-flops. The data will then be stored in the register and available at
the Q0-Q3 outputs when it is needed.

Shown above is a 4-bit Serial-In Parallel-Out (SIPO) register. The data bits are placed on the Data input one at
a time, as each bit is applied, a clock pulse loads them into the first flip-flop. Also on each clock pulse the
data on the Q output of each flip-flop will be loaded into the next flip-flop's D input. After 4 clock pulses the
data will be avaiable in parallel form at the Q0-Q3 outputs.
Shown above is a 4-bit Parallel-In Serial-Out (PISO) register. The data bits are placed on the D1-D4 inputs,
D1 being the most significant bit. To write the data to the register, the Write/Shift control is held LOW. To
shift the data, the Write/Shift control line is brought HIGH and the registers are clocked. After 4 clock pulses
the data will have been shifted out the Q output of the last D flip flop.

In this circuit you may recognise the NAND gates and NOT gate as data selector circuits with the Write/Shift
control selecting either the D1-D2 inputs or the Q outputs of the flip-flops.

The only register function we have not discused is Serial-In Serial-Out (SISO). This can be accomplished
using the first circuit, PIPO, except taking the output from the last Q output and providing the proper number
of clock pulses.
 Counters

CONTENTS

A counter circuit has outputs that generate a sequence of binary numbers that represent a binary count from a
starting number (usually 0) to a highest number depending upon the number of outputs the counter circuit has.

The goal of creating a 4-bit binary counter is to achieve the output table shown above. It has 16 different
output states that are the binary number sequence from 0000 to 1111. When the counter output value reaches
1111, on the next count it returns to 0000 and resumes the binary number sequence.

There are two types of digital circuits, combinational and sequential. With a
combinational circuit, the output depends only on the values present at the
inputs. With a sequential circuit, the output depends not only on the values
present at the inputs, but also on the sequence of past inputs.
A counter is a sequential circuit. Sequential circuits, including counters can be synchronous, or asynchronous.
Counters are constructed with flip flops. In a synchronous counter, a clock pulse is connected to of all the flip-
flops and the change from one output count to the next is triggered by a clock pulse.
In an asynchronous counter, the first flip-flop may be triggered by an external pulse, but all subsequent flip-
flops are clocked by the output of the preceding flip-flop. Asynchronous counters are sometimes called ripple-
counters because of the way the output pulses ripples through the flip-flops.

Shown above is the logic gate diagram for a JK flip flop.

The Master-Slave flip-flop is two flip-flops connected together in a series configuration with the slave having
an inverted clock pulse. The outputs from Q and Q' from the slave flip-flop are fed back to the inputs of the
master flip-flop, with the outputs of the master flip flop connected to the inputs of the slave flip flop. This
feedback connection causes the outputs of the JK flip-flop to toggle on each clock pulse.

The block shown above represents the JK flip flop logic.

Synchronous Counter
Shown above, 4 JK flip-flops are connected with the same clock input going to all of the flip-flops. For this
reason, this circuit is called a Synchronous Counter.

Shown above, 4 D flip-flops are connected. The first flip-flop is connected to a clock pulse input, but all
subsequent flip-flops are clocked by the output of the preceding flip-flop. As the clock pulse moves from the
input to the output of each stage of the asynchronous counter, there is a slight delay. This is called
propagation delay and must be accounted for in other parts of the circuit which use the output of the counter.
 Setup and Hold Times

CONTENTS

In order for flip-flops to reliably latch the binary value of the input to the output certain requirements must be
met. Not just the voltage levels being above or below the noise margin, but timing specification must also be
met. The two timing specifications are Setup time and Hold time.

For a positive-edge triggered clock, the level on the input will be reliably transferred to the output only if the
input voltage has been stable above (for binary 1) or below (for binary 0) the noise margin for a minimum
time before the rising edge of the clock occurs. This is referred to as Setup Time.

Similarly, the input voltage must hold stable for a minimum time after the rising edge of the clock occurs.
This is referred to as Hold Time.

For a negative-edge triggered clock, the level on the input will be reliably transferred to the output only if the
input voltage has been stable for a minimum time before the falling edge of the clock, and has been stable for
a minimum time after the falling edge of the clock occurs.

The exact length of time required for setup and hold times depends upon the type of semiconductor used in
the circuit. Older types of semiconductors may have setup times around 20 ns (nano seconds) and hold times
around 3 ns. Newer semiconductors, which have lower power requirements and smaller die size, may have
typical setup and hold times in the single digit peco seconds range.

Setup time violations are difficult to fix. Hold time violations are usually fixed by adding buffers (placing a
gate or gates in the signal path). In some designs, timing violations can be fixed by the software.
 Decoders

CONTENTS

A decoder is a circuit that converts a binary code input into select or control lines.

Shown below is an example of a simple decoder that decodes a 3-bit opcode into one of eight control signals.

The input to the decoder is a 3-bit opcode, A, B, C. The decoder has three inverters that provide the
compliments to the three inputs A', B', C'. AND gates are connected to specific signals such that only when all
of its inputs are binary 1, will the output of the AND gate be 1. That output will be an Enable input to control
the circuitry that performs function.
The binary code in the circuit shown above is 001. Note that that the AND gate with output E1 is the only
gate with 1's on all three inputs. This causes the gates output to be 1. All other gates have at least one 0 on an
input, causing their outputs to be 0. The E1 output could be the control signal to load a register, or the control
signal to some other circuit.
 Encoders

CONTENTS

A decoder takes a binary value on its inputs and uses it to bring one of n lines high. An encoder performs the
reverse operation, it takes an input on one of n input lines and encodes it into a binary number. So you need to
have enough output lines to create a binary number high enough for the number of inputs.

Decimal to BCD Encoder

A BCD (Binary Coded Decimal) Encoder consists of 10 input lines (for decimals 0 to 9) and 4 output lines
(for binary codes 0 to 9). Three of the output codes available will not be used. The truth table for decimal to
BCD encoder is shown below.

This truth table can be implemented using OR gates as shaown below.

 Multiplexers and Demultiplexers

CONTENTS

A multiplexer (or MUX) is a circuit that selects between several digital input signals and directs that signal to
a single output line. Multiplexers are used extensively in telecomunications because the bandwidth required to
send a sinlge voice is very small while the bandwidth of the telecomunications medium is very high. By
rapidly switching between voice channels many conversations can be sent over a single wire.

4-Input-Multiplexer

In the circuit shown above, when 00 is applied to select lines S1 S0, those logic levels are inverted and
applied to the 2nd and 3rd inputs of gate A, allowing data D0 to pass though to the OR gate output Y. The
other 3 AND gates have 0 in at least one of their inputs, so that their outputs will be 0.

when 01 is applied to select lines S1 S0, S0 is high and S1 is inverted to a high, allowing data D1 to pass
though to the OR gate output Y. The other 3 AND gates have 0 in at least one of their inputs, so that their
outputs will be 0.

Similarly when 10 is applied to select lines, the Data on the input D2 appears on the data output line. When
S1S0 equal to 11 is applied to select lines, the Data on the input D3 appears on the data output line.

4-Output-Demultiplexer
Having mutiplexed 4 channels together, at the receiving end the signals must be demultiplexed. In the circuit
shown above, the input data line is connected to all four AND gates. Similar to the Multiplexer circuit, the
select lines S1 and S0 enable only one AND gate at a time so the data on the input line of that gate passes
through to the selected output line.
 Parity Generator and Parity Checker

CONTENTS

Parity is a method used in networking where blocks of data, be they bites, words, or any size transmission
blocks, are set to contain an even or odd number of 1 bits in the block. For example if even parity is used,
blocks with an even number of 1 bits can be sent directly. But blocks with an odd number of 1 bits will have
their parity bit set to 1 to make the block contain an even number of 1 bits before being sent.

Most errors that occur during transmission affect only one bit in a block. So at the receiving end, the data is
checked to make sure it still has an even number of 1 bits. If there is an odd number of 1 bits, then the data in
that block has been corrupted and it will be have to be resent.

Because of the high speed of data transmission, it's not practical to set parity with software. It is extremely
fast to set parity with digital logic. And, the "exclusive or gate" - XOR, seems to have been invented just for
detecting even parity. The following table describes the logical XOR function.

A B Out
0 00
0 11
1 01
1 10
Shown below is a 4-bit pairity detecting circuit using cascaded XOR gates.

Shown below is the truth table for the pairity detecting circuit.

A B X C Y D Parity
0 000000
0 111011
1 010110
1 101101
As you can see, the output of the circuit is a 1 only when there is an odd number of 1s in the data byte. The
output of this circuit could therefor be used as a pairity bit.

The same circuit could be used as an odd parity bit generator by inverting the output. And, of course, the same
circuits could be used as parity bit detectors at the receiving end of the circuit, generating an output only when
the parity of the receiving byte is not the type expected.
 State Machines

CONTENTS

A State Machine is a program, logic circuit, or mechanical device, that has a finite number of legal states. For
example a traffic control signal can be in the state of red, yellow, or green. It can't be in the state red and green
because that might cause a disaster. It can't be in the state of violet because nobody would know what that
means.

Sometimes a state machine is called a finite state machine. It's possible to have an infinite state machine, but
that doesn't have many practical uses. A state machine begins from a start state, it then transitions from one
legal state to another legal state. You can view a state as a set of specific set of input and output conditions.
An action is a change that causes the state machine to transition to another legal state.

Which state the state machine to transition to depends not only upon the current action, but also on what its
past states were. So which state an action causes a transition to depends no only on the current state, but on
the past state or past states. To accomplish this, a state machine has finite amount of internal memory.

A state machine can be represented with a special kind of flow chart called a state diagram. On a state
diagram, each state is represented by a circle, and each transition is represented by an arrow. Sometimes the
circles contain labels like "state 1, state 2, state 3, ..." or "S1, S2, S3, ...". Transition arrows can be labeled
with letters like "A, B, C, ..." Then a separate table or chart specifies each state and transition.

A very common, very simple, example of a state machine is a traffic control signal. The legal states are red,
yellow, and green. When red it transitions directly to green. When green, it must transition to yellow before it
can transition to red. Shown below is JavaScript code for the traffic control signal state machine.
As you know, to use this code you simply have to cut and paste it into a text file (Windows Notepad), save it
with the file extension .htm, and then load it into your web browser.

Another very common, very simple, example of a state machine is a vending machine. In the state diagram
shown above you can see that a soda costs 25 cents, and to keep it simple, the machine accepts only nickels
and dimes, and it does not give change.

The machine starts with no money. Each state is defined by the coins that have been previously deposited into
the machine, and the state that it transitions to is determined by the current coin being deposited. Eventually
coins totaling 25 cents will have been deposited and a soda will be dispensed, after which the machine
transitions back to its starting point. Shown below is JavaScript code for the soda vending machine state
machine.
Most of you will recognize that using a double expression switch statement is overkill for this application.
This is for heuristic purposes. The first expression in each branch represents a past state and the second
expression represents a condition that triggers a transition to another state. A multiple expression switch
statement is a great way to make this apparent.
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