Silan Semiconductors: 1/3 Duty General-Purpose LCD Driver
Silan Semiconductors: 1/3 Duty General-Purpose LCD Driver
Silan Semiconductors: 1/3 Duty General-Purpose LCD Driver
Semiconductors SC75823
DESCRIPTION
The SC75823 is a general-purpose LCD driver that can be used
for frequency display in microprocessor-controlled radio receives
QFP-64-14x14-0.8
and in other display applications. In addition to being able to directly
drive up to 156 LCD segments.
FEATURES
• Supports both 1/3 duty 1/2 bias and 1/3 duty 1/3 bias LCD
drive of up to 156 segments under serial data control.
• Serial data input supports CCB format communication with the
LQFP-64-10 x 10-0.5
system controller.
• Serial data control of the power-saving mode based backup
function and all the segments forced off function.
• High generality since display data is displayed directly without ORDERING INFORMATION
decoder intervention. Device Package
• The INH pin can force the display to the off state. SC75823A LQFP-64-10 X 10-0.5
• The LCD drive bias voltage can be provided internally or SC75823B QFP-64-14 X 14-0.8
externally.
• Power supply voltage: 4.5 to 6.0V
BLOCK DIAGRAM
COM1 COM2 COM3 S52 S51 S1
VDD1
Common Driver Latch & Driver
VDD2
INH
Shift Register
Clock
OSC
Generator
Address
Detector
DI CL CE VDD VSS
S47
S46
S45
S44
S43
S42
S41
S40
S39
S38
S37
S36
S35
S34
S33
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
S49 49 32 S32
S50 50 31 S31
S51 51 30 S30
S52 52 29 S29
COM1 53 28 S28
COM2 54 27 S27
COM3 55 26 S26
VDD 56 25 S25
SC75823
INH 57 24 S24
VDD1 58 23 S23
VDD2 59 22 S22
VSS 60 21 S21
OSC 61 20 S20
CE 62 19 S19
CL 63 18 S18
DI 64 17 S17
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
Input Low Level Voltage VIL CE, CL, DI, INH 0 0.7 V
Recommended External Resistance ROSC OSC 47 kΩ
Recommended External Capacitance COSC OSC 1000 pF
Guaranteed Oscillator Range fOSC OSC 19 38 76 kHz
Data Setup Time tds CL, DI: figure 2 100 ns
Data Hold Time tdh CL, DI: figure 2 100 ns
CE Wait Time tcp CE, CL: figure 2 100 ns
CE Setup Time tcs CE, CL: figure 2 100 ns
CE Hold Time tch CE, CL: figure 2 100 ns
High-level Clock Pulse Width tφH CL: figure 2 100 ns
Low-level Clock Pulse Width tφL CL: figure 2 100 ns
Rise Time tr CE, CL, DI: figure 2 100 ns
Fall Time tf CE, CL, DI: figure 2 100 ns
INH Switching Time t2 INH , CE: figure 3 10 µs
ELECTRICAL CHARACTERISTICS
Characteristics Symbol Test Condition Min. Typ. Max. Unit
Input High Level Current IIH CE, CL, DI, INH ; VI=6V 5 µA
Input Low Level Current IIL CE, CL, DI, INH ; VI=0V -5 µA
OSC;ROSC=47kΩ,
Oscillator Frequency fOSC 38 kHz
COSC=1000pF
Hysteresis Width VH CE, CL, DI, INH ; VDD=5V 0.3 V
Output High Level Voltage VOH1 S1 to S52; IO=-20µA VDD-1.0 V
Output Low Level Voltage VOL1 S1 to S52; IO=20µA 1.0 V
Output High Level Voltage VOH2 COM1 to COM3; IO=-100µA VDD-1.0 V
Output Low Level Voltage VOL2 COM1 to COM3; IO=100µA 1.0 V
1/2 bias, COM1 to COM3;
VMID1 1/2VDD±1.0 V
IO=±100µA
Intermediate Level Voltage
1/3 bias, COM1 to COM3;
VMID2 2/3VDD±1.0 V
IO=±100µA
(To be continued)
Note: * Except the bias voltage generation divider resistors that are built into VDD1 and VDD2.(see figure 1)
Figure 1
VDD
VDD1
VDD2
Except these resistors
CE VIH
VIL
t¶H t¶L
CL VIH
VIH VIH
50%
VIL VIL
tr tf
tcp tcs tch
VIH VIH
DI
VIL VIL
tds tdh
CE VIH
VIL
t¶L t¶H
CL VIH VIH VIH
50%
VIL VIL
tr tf
tcp tcs tch
VIH VIH
DI VIL VIL
tds tdh
Segment outputs for displaying the display data transferred by serial data
1-52 S1 to S52 O
input.
53 COM1
Common driver outputs. The frame frequency fO is given by:
54 COM2 O
fO=(fOSC/384)Hz
55 COM3
Oscillator connection
61 OSC I/O An oscillator circuit is formed by connecting an external resistor and
capacitor to this pin.
62 CE CE: chip enable
Serial data transfer inputs. These pins are
63 CL I CL: synchronization clock
connected to the control microprocessor.
64 DI DI: transfer data
Display off control input
INH =low (VSS)……Display forced off (S1 to S52, COM1 to COM3=low)
57 INH I INH =high (VDD)……Display on
note that serial data transfers can be performed when the display is forced
off.
Used for the 2/3 bias voltage when bias voltage are provided externally.
58 VDD1 I
Connect to VDD2 when 1/2 bias is used.
Used for the 1/3 bias voltage when bias voltage are provided externally.
59 VDD2 I
Connect to VDD1 when 1/2 bias is used.
56 VDD -- Power supply. Provide a voltage of between 4.5 and 6.0V
60 VSS -- Ground. Connect this pin to the system ground.
FUNCTION DESCRIPTION
Serial data transfer format
1. When CL is stopped at the low level
CE
CL
*: don't care
CL
*: don't care
• CCB address…….41H
• D1 to D156……….Display data
Dn (n=1 to 156)=1……..Display on
Dn (n=1 to 156)=0……..Display off
• DR…………………1/2-bias drive or 1/3-bias drive switching control data
• SC…………………Segments on/off control data
• BU…………………Normal mode/power-saving mode control data
B0 B1 B2 B3 A0 A1 A2 A3
*: don't care
DR Drive type
0 1/2-bias drive
1 1/3-bias drive
SC Display state
0 On
1 Off
BU Mode
0 Normal mode
1 Power-saving mode. In this mode the OSC pin oscillator is stopped and the common and segment
pins output VSS levels.
Segment Segment
COM3 COM2 COM1 COM3 COM2 COM1
output pin output pin
S1 D1 D2 D3 S27 D79 D80 D81
To be continued
For example, the table below lists the segment output states for the S11 output pin.
Display data
Segment output pin (S11) state
D31 D32 D33
0 0 0 The LCD segments corresponding to COM1 to COM3 are off.
0 0 1 The LCD segments corresponding to COM1 is on.
0 1 0 The LCD segments corresponding to COM2 is on.
0 1 1 The LCD segments corresponding toCOM1 and COM2 are on.
1 0 0 The LCD segments corresponding to COM3 is on.
1 0 1 The LCD segments corresponding to COM1 and COM3 are on.
1 1 0 The LCD segments corresponding to COM2 and COM3 are on.
1 1 1 The LCD segments corresponding to COM1 to COM3 are on
Since the LSI internal data (D1 to D156, DR, SC and BU) is undefined when power is first applied, the display is
off (S1 to S52, COM1 to COM3= low) by setting the INH pin low at the same as power is applied. Then,
meaningless display at the power-on can be prevented by transferring serial data from the controller while the
display is off and setting INH pin high after the transfer completes.(see figure3).
VDD
INH
VDD
INH VIL
t1
t2
CE Transfer of VIL
display and
control data
VDD
COM1 VDD1, VDD2, (1/2 VDD)
VSS
VDD
COM2 VDD1, VDD2
VSS
VDD
COM3 VDD1, VDD2
VSS
VDD
LCD driver output when all LCD
segments corresponding to COM1, VDD1, VDD2
COM2, and COM3 are turnned off. VSS
VDD
LCD driver output when only LCD
segments corresponding to COM1, VDD1, VDD2
are on.
VSS
VDD
LCD driver output when only LCD
segments corresponding to COM2, VDD1, VDD2
are on. VSS
VDD
LCD driver output when only LCD
segments corresponding to VDD1, VDD2
COM1and COM2 are on.
VSS
VDD
LCD driver output when only LCD
segments corresponding to COM3 VDD1, VDD2
are on.
VSS
LCD driver output when LCD VDD
segments corresponding to COM1 VDD1, VDD2
and COM3 are on.
VSS
VDD
LCD driver output when LCD
segments corresponding to COM2 VDD1, VDD2
and COM3 are on.
VSS
VDD
LCD driver output when all LCD
segments corresponding to VDD1, VDD2
COM1,COM2, and COM3 are on.
VSS
VDD
VDD1 (2/3 VDD)
COM1 VDD2 (1/3 VDD)
VSS
VDD
VDD1
COM2
VDD2
VSS
VDD
VDD1
COM3 VDD2
VSS
VDD
LCD driver output when all LCD
segments corresponding to COM1, VDD1
COM2, and COM3 are turnned off. VDD2
VSS
VDD
LCD driver output when only LCD VDD1
segments corresponding to COM1,
are on. VDD2
VSS
VDD
VDD1
LCD driver output when only LCD
segments corresponding to COM2, VDD2
are on.
VSS
VDD
LCD driver output when LCD VDD1
segments corresponding to
COM1and COM2 are on. VDD2
VSS
VDD
LCD driver output when only LCD VDD1
segments corresponding to COM3
are on. VDD2
VSS
VDD
LCD driver output when LCD VDD1
segments corresponding to COM1
and COM3 are on. VDD2
VSS
VDD
LCD driver output when LCD VDD1
segments corresponding to COM2 VDD2
and COM3 are on.
VSS
VDD
LCD driver output when all LCD VDD1
segments corresponding to
COM1,COM2, and COM2 are on. VDD2
VSS
61
OSC
VDD 56 VDD COM1 53
57 INH COM2 54
58 VDD1
OPEN
59 VDD2 S1 1
62 CE
From the
63 CL
microcontroller
64 DI S52 52
TEST CIRCUIT2
1/3 Bias (for use with normal size panels)
61
OSC
VDD 56 VDD COM1 53
57 INH COM2 54
LCD panel (up to 156 segments)
COM3 55
60 VSS
58 VDD1
59 VDD2 S1 1
C0.047F C C
62 CE
From the
63 CL
microcontroller
64 DI S52 52
61
OSC
VDD 56 VDD COM1 53
57 INH COM2 54
58 VDD1
10KR1K R
C0.047F 59 VDD2 S1 1
C C R
62 CE
From the
63 CL
microcontroller
64 DI S52 52
14.00B0.10
48 33
49 32
14.00B0.10
16.00B0.20
15.00
12.00
1.0
64 17
1 16
LQFP-64-10x10-0.5 UNIT: mm
12.00B0.20 1.50B0.10
10.00B0.10
48 33
49 32
7.50
11.00
10.0B0.2
13.6B0.4
1.0
64 17
1 16
Revision History
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