CS 303 LOGIC DESIGN

LAB 1.

LOGIC GATES

Sarajevo, 2014/2015
 CS 303 Logic Design - Laboratory Manual

LAB 1. LOGIC GATES

Objective
 To get acquainted with the Analog/Digital Training System.
 To get acquainted with different standard integrated circuits (ICs).
 To study the basic logic gates: AND, OR, INVERT, NAND, NOR, and XOR.
 To understand formulation of Boolean function and truth table for logic circuits.

Apparatus
- Analog/Digital Training System
- IC Type 7400 Quadruple 2-input NAND gates
- IC Type 7402 Quadruple 2-input NOR gates
- IC Type 7404 Hex Inverters
- IC Type 7408 Quadruple 2-input AND gates
- IC Type 7432 Quadruple 2-input OR gates
- IC Type 7486 Quadruple 2-input XOR gate

Theory
See Chapters 2 & 3 in the book.

Analog/Digital Training System:

The Analog/Digital Training System consists of DC power supply, breadboard, pulse generator and a
digital probe.

Useful features include:

1. DC Power Supply:
 Fixed DC Outputs: +5V & -5V
 Variable DC Outputs: +3V to +15V, -3V to -15V

2. Breadboard:
 Terminal strips arranged for easy connection of standard ICs

3. Pulse Generator:
 Variable duty cycle: (set to 50%)
 Frequency range: 1Hz – 10MHz
 Amplitude: 0VP-P - 10 VP-P

4. Digital Probe

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The Breadboard

The breadboard consists of two terminal strips and two bus strips (often broken in the centre). Each bus
strip has two rows of contacts. Each of the two rows of contacts is node. That is, each contact along a
row on a bus strip is connected together (inside the breadboard). Bus strips are used primarily for power
supply connections, but are also used for any node requiring a large number of connections.

In the example of breadboard shown in figure 1.1, each terminal strip has 60 rows and 5 columns of
contacts on each side of the centre gap. Each row of 5 contacts is a node.

You will build your circuits on the terminal strips by inserting the leads of circuit components into the
contact receptacles and making connections with 22-26 gauge wire. There are wire cutter/strippers and
a spool of wire in the lab. It is a good practice to wire +5V and 0V power supply connections to separate
bus strips.

The 5V supply MUST NOT BE EXCEEDED since this will damage the ICs (Integrated circuits) used during
the experiments. Incorrect connection of power to the ICs could result in them exploding or becoming
very hot.

Digital Integrated IC’s

Digital ICs are a collection of resistors, diodes and transistors fabricated on a single piece of
semiconductor material usually silicon and referred to as “chip”. The chip is enclosed in a protective
plastic or ceramic package with pins extended out for connecting the IC to other devices. The most
common type of package is a dual-in-line package (DIP) as shown in figure 1.2. The pins are numbered
counterclockwise when viewed from the top of the package with respect to an identifying notch or dot
at on end of the chip. The DIP below is a 14-pin package. 16, 20, 24, 28, 40 and 64 pin packages are also
available.

The fabricated resistors, diodes and transistors reside in the chip are called logic gates. Different chip
may contain different amount of these logic gates.

Digital ICs are often categorized according to their circuit complexity as measured by the number of
equivalent logic gates in an IC. There are currently five standard levels of complexity as in Table 1.1.

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 CS 303 Logic Design - Laboratory Manual

Fig. 1.1: The breadboard. The shaded lines indicate connected holes

Fig. 1.2: (a) Dual-In-Line Package (b) Top view showing Pin numbers

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Complexity Approx. gates per chip Typical products

Small scale integration (SSI) Less than 12 Logic gates, flip flops

Adders, Counters,
Medium scale integration (MSI) 12 to 99
Multiplexers

ROM, RAM, 8 bit

Large scale integration (LSI) 100 to 9999
Microprocessors

16 and 32 bit
Very large scale integration (VLSI) 10, 000 to 99, 999
Microprocessors

64 bit microprocessors,
Ultra large scale integration (ULSI) 100, 000 to more
special processors

Table.1.1: Standard levels of complexity

Building the Circuit on Breadboard

Throughout these experiments, we will use TTL chips to build circuits. The steps for wiring a circuit
should be completed in the order described below:

Make sure the power is off before you build anything!

Connect the +5V and ground (GND) leads of the power supply to the power and ground bus strips
on your breadboard. Before connecting up, use a voltmeter to check that the voltage does not
exceed 5V.

Plug the chips you will be using into the breadboard. Point all the chips in the same direction with
pin 1 at the upper-left corner. (Pin 1 is often identified by a dot or a notch next to it on the chip
package)

Connect +5V and GND pins of each chip to the power and ground bus strips on the breadboard.

Select a connection on your schematic and place a piece of hook-up wire between corresponding
pins of the chips on your breadboard. It is better to make the short connections before the longer
ones. Mark each connection on your schematic as you go, so as not to try to make the same
connection again at a later stage.

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Consult your instructor to check the connections, before you turn the power on.

If an error is made and is not spotted before you turn the power on. Turn the power off
immediately before you begin to rewire the circuit.

At the end of the laboratory session, collect you hook-up wires, chips and all equipment and return
them to the demonstrator.

Tidy the area that you were working in and leave it in the same condition as it was before you
started.

Common Causes of Problems

Not connecting the ground and/or power pins for all chips.

Not turning on the power supply before checking the operation of the circuit.

Leaving out wires.

Plugging wires into the wrong holes.

Driving a single gate input with the outputs of two or more gates.

Modifying the circuit with the power on.

In all experiments, you will be expected to obtain all instruments, leads, components at the start of the
experiment and return them to their proper place after you have finished the experiment.

Example Implementation of a Logic Circuit

Build a circuit to implement the Boolean function F = A · B using TTL IC 74LS00 (AND gate) and TTL IC
7404 (INVERTER) as per discussed in figure 1.3.

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Quad 2 Input 7400 Hex 7404 Inverter

Fig. 1.3: The complete designed and connected circuit

Sometimes the chip manufacturer may denote the first pin by a small indented circle above the first pin
of the chip. Place your chips in the same direction, to save confusion at a later stage. Remember that
you must connect power to the chips to get them to work.

Basic Logic Gates

AND A multi-input circuit in which the output is 1 only if all inputs are 1.The symbolic
representation of the AND gate is shown in Table 1.2.

OR A multi-input circuit in which the output is 1 when any input is 1. The symbolic
representation of the OR gate is shown in Table 1.2.

INVERT The output is 0 when the input is 1, and the output is 1 when the input is 0. The
symbolic representation of an inverter is shown in Table 1.2.

NAND AND followed by INVERT. The symbolic representation of the NAND gate is shown in
Table 1.2.

NOR OR followed by INVERT as shown in Table 1.2.

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EX-OR The output of the Exclusive –OR gate, is 0 when it’s two inputs are the same and its
output is 1 when its two inputs are different.

Truth Table Representation of the output logic levels of a logic circuit for every possible
combination of levels of the inputs. This is best done by means of a systematic
tabulation.

Table 1.2

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Instructions
Connect circuits for each of the logic gate as explained in experiment 1 and note your
observations in truth table.

Inputs Outputs
VCC
A B Z 14 13 12 11 10 9 8

OFF OFF

OFF ON
ON
OFF 1 2 3 4 5 6 7
ON
ON Gnd
7432
(a) OR GATE 7432 (Quad 2 input)

Inputs Outputs

A B Z
VCC
14 13 12 11 10 9 8

OFF OFF

OFF ON
ON
OFF
ON
ON 1 2 3 4 5 6 7

Gnd
(b) AND GATE 7408 (Quad 2 input) 7408

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VCC
Inputs Output 14 13 12 11 10 9 8

A Z

OFF

ON
1 2 3 4 5 6 7
(c) NOT GATE 7404 Gnd
7404
Inputs Outputs VCC
14 13 12 11 10 9 8
A B Z

OFF OFF

OFF ON
1 2 3 4 5 6 7
ON
OFF Gnd
ON
7402
ON

(d) NOR GATE 7402 (Quad 2 input)

Inputs Outputs
VCC
A B Z 14 13 12 11 10 9 8

OFF OFF

OFF ON
ON
OFF
1 2 3 4 5 6 7
ON
ON Gnd
7400
(e) NAND GATE 7400 (Quad 2 input)

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Inputs Outputs

A B Z VCC
14 13 12 11 10 9 8

OFF OFF

OFF ON
ON
OFF
ON
ON 1 2 3 4 5 6 7

Gnd
7486
(f) EXCLUSIVE XOR GATE 7486 (Quad 2
input)

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 CS 303 Logic Design - Laboratory Manual

PROBLEMS

PROBLEM 1._________________________________________________________________

Implement 3 input AND gate using 2 input AND gates and 3 input OR gate using 2 input OR
gates.

PROBLEM 2._________________________________________________________________

Implement NAND gate using AND gates and NOR using OR gates.

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 CS 303 Logic Design - Laboratory Manual

CS 303 LOGIC DESIGN

LAB 1. REPORT

LOGIC GATES

Assistant: Professor:

_______________________________ _______________________________

Student name:__________________________________

Student ID:______________________________________

Due Date:________________________________________

Sarajevo, 2014/2015
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 CS 303 Logic Design - Laboratory Manual

CS 303 LOGIC DESIGN

LAB 2.

ADDERS AND DECODERS

Sarajevo, 2014/2015

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 CS 303 Logic Design - Laboratory Manual

LAB 2. ADDERS AND DECODERS

Objective
 To design and test adder circuits.
 To design and build BCD-to-7 segment converter

Apparatus
 Analogue/Digital trainer kit
 IC Type 7404 Hex Inverters
 IC Type 7408 Quadruple 2-input AND gates
 IC Type 7432 Quadruple 2-input OR gates
 7486 Quad 2-input XOR gate.
 7483 4-bit binary Adder.

 SN 7400 quad 2-input NAND gates (1)

 SN 7410 triple 3-input NAND gates (4)
 SN 7420 dual 4-input NAND gates (4)
 SN 7447 BCD-to-seven segment decoder.

Theory
1. Addition
IC Type 7483 is a 4-bit binary adder with a fast carry. The pin assignment is shown in Fig
3.1. The two 4-bit input binary numbers are A1 through A4 and B1 through B4 . The 4-
bit sum is obtained from S1 through S 4 . Ci is the input carry and Co is the output carry.
The IC Chip can be used as an Adder-Subtractor circuit. 5
1 A4 Vcc 14
C
3 A3
S4
o 15
8 A2
10 S3 2
A1 748
16 B 6
3 S2
4 B
4 9
S1
7 B
3
11 B
2
Ci GND
1
13 12

Fig.3.1: IC type 7483 4-bit adder

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Fig. 3.2: Block diagram for 4 bit parallel adder

2. BCD-to-seven Segment converter:

A light emitting Diode (LED) is a PN junction diode. When the diode is forward biased, a
current flows through the junction and the light is emitted. See Fig.3.3.
LED
150 K A
- +

SW1 +
5V
-
GND
Operation of LED

Fig.3.3

A seven segment LED display contains 7 LEDs. Each LED is called a segment and they are
identified as (a, b, c, d, e, f, g) segments. See Figure 3.4.
a

f b
g

e c

Fig. 3.4. Digits represented by the 7 segments

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Cathode
inputs

a
a
a a b a
b b c Common
b f b
f c d anode
f
d e g
e c
e f
g Common f +
g g d 5V
anode
g -
e 150
e c
c GND
Driving a Seven - Segment LED
Display With Switches
d

Wiring of a Common - Anode

Seven Segment LED Display

Fig. 3.5. Digits represented by the 7 segments

The display has 7 inputs each connected to an LED segment. All anodes of LEDs are tied
together and joined to 5 volts (this type is called common anode type). A limiting resistance
network must be used at the inputs to protect the 7-segment from overloading.
BCD inputs are converted into 7 segment inputs (a, b, c, d, e, f, g) by using a decoder, as shown
in Fig. 3.5. A decoder is a combinational circuit that converts binary information from n input
lines to a maximum of 2n output lines. The input to the decoder is a BCD code and the outputs
of the systems are the seven segments a, b, c, d, e, f, and g. For further information and pin
connections, consult the specification sheet for decoder and 7-segment units.

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 CS 303 Logic Design - Laboratory Manual

Instructions
Part 1: Half adder
(1) Construct the half adder circuit shown and complete the truth table for all combinations of
inputs A and B.

Carry Inputs Outputs

A
A B CARRY SUM

Sum
B

(2) Determine the Boolean expressions for the SUM and CARRY outputs

SUM =

CARRY =

(3) How many bits can the circuit ADD at the same time?

(4) What is the limitation of the half adder circuit?

(5) Implement Half adder in lab and verify its operation.

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 CS 303 Logic Design - Laboratory Manual

Part 2: Full adder

(1) Construct the full adder circuit shown below using XOR, AND and OR gates and complete the truth
table for all combinations of inputs.

Inputs Outputs

A B C CARRY SUM

CARRY

A
H.A. CARRY
B

SUM CARRY

H.A.
C SUM

Fig 3.6: Full Adder Circuit

Note: Redraw the circuit showing all details, pin numbers, etc…

(2) Implement full adder in lab and verify its operation.

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Part 3: BCD to Seven-Segment Display

(1) First design a combinational circuit, which would implement the decoder function for only
the segment “a”, of the display. This can be done in the following steps:
a) Write down the truth table with 4 inputs and 7 outputs (Table 3.1).

b) For only the output “a”, obtain a minimum logic function. Realize this function using NAND
gates and inverters only. For example if decimal 9 is to be displayed a, b, c, d, f, g must be 0
and the others must be 1 (For common anode type display units), if decimal 5 is to be
displayed then a, f, g, c, d must be 0 and the others must be 1.

c) Connect the output “a” of your circuit to appropriate input of 7-segment display unit. By
applying BCD codes verify the displayed decimal digits for that segment for “a” of the
display.

d) Replace your circuit by a decoder IC 7447 for all of the seven segments. Observe the
display and record the segments that will light up for invalid inputs sequence.

7 13
A a
1 12
BCD B b
2 11
Number C c Outputs
6 Decoder 10
Inputs D d Seven-Segment
3 ( 7447A ) 9 Code
Lamp Test LT e
4 15
Blanking BI/RBO f
5 14
Zero Blanking RBI g
16 8
Vcc Gnd
+5V +5V
Decimal Output
Vcc a
a
b a
1s A b
c
c f b
2s B Decoder d
d
BCD ( 7447A ) e g Common
4s C e e c anode
Input f
f
8s D g d
g
GND 150
Wiring a 7447A Decoder and Seven - Segment LED Display
Fig. 3.7

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e) Comment on the design if you don’t want to see any digit for invalid input sequence.

Table 3.1
Dec. BCD Outputs
A B C D a b c d e f g
0 0 0 0 0
1 0 0 0 1
2 0 0 0 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1

+5V

16
47 Ohm
47 dot
4 1 CA
5
BI/RBO G
14 g
RBI 15 13 14
3
LT F 9 10
E
6
D D
10 8
input 2 11 7
from 1
C C 12 2
switches B B
7
A A
13 11 a
8
8
BCD-to-Seven Segment Decoder and 7-segment display
Note: In an actual 7-segment display the dot is on the left

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PROBLEMS

PROBLEM 1._________________________________________________________________

What is an encoder? Describe in your own words.

PROBLEM 2._________________________________________________________________

What is BCD?

PROBLEM 3._________________________________________________________________

Give an idea how to create a subtractor.

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 CS 303 Logic Design - Laboratory Manual

CS 303 LOGIC DESIGN

LAB 2. REPORT

ADDERS AND DECODERS

Assistant: Professor:

_______________________________ _______________________________

Student name:__________________________________

Student ID:______________________________________

Due Date:________________________________________

Sarajevo, 2014/2015
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