ECEN474: (Analog) VLSI Circuit Design

Fall 2012

Lecture 2: MOS Transistor Modeling

Sam Palermo
Analog & Mixed-Signal Center
Texas A&M University
Announcements
• No Lab this week
• Lab 1 next week

• Current Reading
• Razavi Chapters 2 & 16

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Analog IC Design Olympics (Extra Credit)
• Analog IC Design Olympics Contest is on September 15
• http://amsc.tamu.edu/olympics.htm
• Register by August 31 at noon

• Open to all TAMU Grad Students

• Teams of 2 will compete in a circuit design contest
• Designs are judged by a distinguished industrial committee
• Broadcom, NXP, Qualcomm, Silicon Labs, TSMC, TI, Stone Soup Labs

• Extra Credit Opportunity for Grad Students

• 20 points added to a homework score
• Undergrads will have an extra credit opportunity later in the semester

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Agenda
• MOS Transistor Modeling
• Threshold Voltage, VT
• DC I-V Equations
• Body Effect
• Subthreshold Region

4
TAMU-474-09 J. Silva-Martinez

MOS Transistor
P-type transistor
S

G
B

BASIC IDEA:
Thin oxide Thick oxide
B S G D
SOURCE-DRAIN CURRENT IS
CONTROLLED BY THE
SOURCE-GATE VOLTAGE.

N+ P+ P+ The system is “isolated” if the

diodes are biased in reverse region
Substrate or well N
by using the Bulk terminal.
P-channel Polysilicon (heavily doped)

-5-
 Threshold Voltage, VT
[Razavi]

• Applying a positive voltage to the gate repels holes in the p-substrate

under the gate, leaving negative ions (depletion region) to mirror the
gate charge

• Before a “channel” forms, the device acts as 2 series caps from the
oxide cap and the depletion cap
• If VG is increased to a sufficient value the area below the gate is
“inverted” and electrons flow from source to drain
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 VT Definition
[Silva]
• The threshold voltage, VT,
is the voltage at which an
“inversion layer” is formed
• For an NMOS this is when the
concentration of electrons
equals the concentration of
Qdep holes in the p- substrate
VT = Φ MS + 2Φ F + = Φ MS + 2Φ F + γ 2Φ F
Cox

Φ MS is the difference between the work functions of the polysilicon gate and the silicon substrate

kT  N sub 
Φ F is the Fermi potential, Φ F = ln 
q  ni 

Qdep is the depletion region charge, Qdep = 4qε si Φ F N sub

ε ox
Cox is the gate cap/area, Cox =
tox Note, γ will be defined later
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TAMU-474-09 J. Silva-Martinez

MOS Transistor
Accumulation: Two diodes back to back N-type transistor
D-S current is zero
VG<0 D
B VS=0 VD>0
G
B

P+ ++++++++++
N+ N+
P+ S
substrate P

Under this condition, there are 3 possible

Inversion: Channel is connecting D and S
applications:
D-S current is possible
VG>0 Subthreshold (extremely low-voltage low-
B VS=0 VD>0
power applications)

Linear region (voltage controlled resistor,

P+ N+
---------- N+ linear OTA’s, multipliers, switches)
IDS Quasi free electrons
Substrate P N+ Saturation region (Amplifiers)

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TAMU-474-09 J. Silva-Martinez

MOS Transistor
Triode Region (D-S channel is complete) N-type transistor
VG>0
B VS=0 VD ~ 0 D

G
B
P+ N+
---------- N+

substrate P S

Channel
In this condition, there are 3 possible
Saturation Region (D-S channel is incomplete) applications:
VG>0
B VS=0 VD > 0
Subthreshold (extremely low-voltage low-
power applications)

P+ N+ N+ Linear region (voltage controlled resistor,

linear OTA’s, multipliers, switches)
substrate P
Saturation region (Amplifiers)
N-channel

-9-
TAMU-474-09 J. Silva-Martinez

MOS Transistor
Subthreshold (weak inversion) N-type transistor
VT >VG>0
B VS=0 VD>0 IDS Linear region
VGS3
Saturation
--------
P+ N+ N+
VGS2
substrate P (NA)
Subthreshold
Mobile carriers VGS1
concentration< NA VD
Saturation (Strong inversion) S

VG>VT
B VS=0 VD>0 Subthreshold (extremely low-voltage low-
power applications)

-------- Linear region (voltage controlled resistor,

P+ N+ N+
linear OTA’s, multipliers, switches)
substrate P (NA)
Saturation region (Amplifiers)
Mobile carriers
Concentration> NA
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 MOS Equations in Triode Region (Small VDS)

[Sedra/Smith]
dQ dQ dx
Current from Source to Drain : I = = = Qd ( x)υ
dt dx dt
Incremental Charge Density : Qd ( x) = −COX W (VGC ( x ) − VT )

Gate - to - Channel Voltage : VGC ( x ) − VT = VGS − VCS ( x) − VT

dv( x )
Electron Velocity : υ = − µ n E ( x ) = µ n
dx
dv( x )
I DS = − I = COX W (VGS − VCS ( x) − VT ) µ n
dx
L VDS

∫I DS dx = ∫µ C n OX W (VGS − VT − VCS ( x))dv( x )

0 0

W 1 
I = − I DS I DS = µ nCOX VGS − VT − VDS VDS
L 2 
ε ox
Capacitance per unit gate area : Cox =
t ox

Electron mobility : µ n
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Triode or Linear Region
[Silva]

VDS

x=0 x=L
V ( x ) = VDS
x
V (0 ) = 0 V (L ) = VDS
L
VGC ( x ) = VGS − V ( x ) = VGS − VDS
x
L
• Channel depth and transistor current is a function of the overdrive
voltage, VGS-VT, and VDS
• Because VDS is small, VGC is roughly constant across channel length
and channel depth is roughly uniform
1
RDS ≈
µ nCOX (VGS − VTn − 0.5VDS )VDS
W
µCox (VGS − VTn )
I DS = W
L For small VDS L
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TAMU-474-09 J. Silva-Martinez

MOS Equations in Linear Region

VGS VDS Drain current: Expression used in SPICE level 1

GND
µ n C OX (VGS −VT −0.5VDS )VDS
W
ID =
tox L

N+ N+ W
ID
L Linear approximation

VGS VDS
GND IDSAT

tox

N+ N+ W VGS > VT
VDS
Non-linear channel VDSAT

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Triode Region Channel Profile
VGC ( x ) = VGS − V ( x ) = VGS − VDS
x
[Sedra/Smith] L

• If VGC is always above VT throughout the channel length, the

transistor current obeys the triode region current equation
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Saturation Region Channel Profile
VGC ( x ) = VGS − V ( x ) = VGS − VDS
x
L

• When VDS ≥ VGS-VT=VOV,

VGC no longer exceeds VT,
resulting in the channel
“pinching off” and the
current saturating to a
value that is no longer a
function of VDS (ideally)

[Sedra/Smith]
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Saturation Region

[Silva]

x
VDSsat=VGS-VT VDS-VDSsat VGC ( x ) = VGS − V ( x ) = VGS − VDS
L

x=0 x=L
V ( x ) = VDS
x
V (0 ) = 0 V (L ) = VDS
L

• Channel “pinches-off” when VDS=VGS-VT and the current saturates

• After channel charge goes to 0, the high lateral field “sweeps” the
carriers to the drain and drops the extra VDS voltage
W V 
I DS = µ nCOX VGS − VTn − DS VDS
L 2  VDS =VGS −VTn
VDSsat = VGS − VTn
µ nCOX W
I DS = (VGS − VTn )2
2 L
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NMOS ID – VDS Characteristics
VOV = VGS − VTN [Sedra/Smith]

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 MOS “Large-Signal” Output Characteristic
[Sedra/Smith]

Note: Vov=VGS-VT
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 What about the PMOS device?
NMOS PMOS

[Silva]

• The current equations for the PMOS device are

the same as the NMOS EXCEPT you swap the
current direction and all the voltage polarities
NMOS PMOS
W
Linear: I DS =
L
µ nCOX (VGS − VTn − 0.5VDS )VDS I SD =
W
L
( )
µ p COX VSG − VTp − 0.5VSD VSD

Saturation: I DS =
W
2L
µ nCOX (VGS − VTn )2 I SD =
W
2L
(
µ p COX VSG − VTp)2

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PMOS ID – VSD Characteristics
VOV = VSG − VTP [Karsilayan]

(Saturation)

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 Body Effect
[Razavi]
• If the body and source potential are
equal, a certain VG=VT0 is required to
form an inversion layer
Qdep 0
VT 0 = Φ MS + 2Φ F + = Φ MS + 2Φ F + γ 2Φ F
Cox

• As VS becomes positive w.r.t.

VB, a larger depletion region
forms, which requires a higher
VG to form a channel
• The net result is that VT
increases due to this “body
VT = VT 0 + γ ( 2Φ F + VSB − 2Φ F ) effect”
2qε si N sub • Note, it also works in reverse,
Body effect coefficient, γ =
Cox as if you increase VB w.r.t. VS,
then VT lowers
γ typically ranges from 0.3 to 0.4V1 2

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TAMU-474-08 J. Silva-Martinez

MOS MODEL: SPICE LEVEL-II

W
NMOS : I DS = µ nCOX (VGS − VTn − 0.5VDS )VDS
L
•Drain current, Triode region
PMOS : I SD =
W
L
(
µ pCOX VSG − VTp − 0.5VSD VSD)
W
NMOS : I DS = µ nCOX (VGS − VTn )
2
•Drain Current, Saturation region 2L
PMOS : I SD =
W
2L
(
µ pCOX VSG − VTp
2
)
•Threshold voltage (zero bias) VT 0 = Φ MS + 2Φ F + γ 2Φ F

•Threshold voltage VT = VT 0 + γ [ ]
2Φ F + VSB − 2Φ F ⇒ VT 0 VSB =0

2qε si N sub
•KP and γ (Spice Model) KP = µCOX ; γ =
COX

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Subthreshold Region
• So far we have assumed that ID=0 when VGS<VT
• However, in reality an exponentially decreasing current
exists for VGS<VT

V q 
In subthreshold region : I D = I 0 exp GS 
 ζkT 
where I 0 is a scale current

ζ > 1 is a nonideality factor

The steepest subthreshold slope is 1dec./60mV with ζ = 1 [Razavi]

• VT values are often set by extrapolating above threshold

data to current values of zero or infinite Ron
• A rough value often used is the VGS which yields
ID/W=1µA/µm
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Subthreshold Current & VT Scaling
• This subthreshold current prevents lowering VT excessively
• Assuming VT=300mV and has an 80mV subthreshold
slope, then the Ion/Ioff ratio is only on the order of
10^(300/80)=5.6e3
• Reducing VT to 200mV drops the Ion/Ioff ratio to near 316
• If we have a large number of “off” transistors on our chip
these subthreshold currents add up quickly, resulting in
significant power dissipation
• This is a huge barrier in CMOS technology scaling and one
of the main reasons Vdd scaling has slowed

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Next Time
• MOS Transistor Modeling
• Small-Signal Model
• Spice Models

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