La-E541p Diuya - Yb - Sa - SB - SD (KBL-R)

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A B C D E

1 1

Compal Confidential
2
DIUYA/YB/SA/SB/SD (KBL-R) 2

DIS M/B Schematics Document


Intel KabyLake U/KabyLake R Processor with DDR4

N16S-GTR(940) (23x23mm)
N16V-GMR1(920) (23x23mm)
3 3

2017-06-05
LA-E541P
REV:2.A
FAB: JB501

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


2017/06/05 2018/06/05 Title
Issued Date Deciphered Date Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 2.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E541P
Date: Wednesday, June 21, 2017 Sheet 1 of 51
A B C D E
A B C D E

nVIDIA N16V-GMR1 / N16S-GTR PCIe x4 Memory Bus CH-A DDR4 SODIMM/LPDIMM x1


1 1
VRAM(GDDR5)*2 2GB N16V-GMR1 (Cruze) DDR4 2133MHz (1.2V)
N16S-GTR (Alpine/Cruze) ( 2400 MHz )

eDP Panel eDP x1 USB3.0 x3 Type-C Connector


4 Lanes (Alpine)
2 Lanes (Cruze) (CC+MUX)
USB3.0 repeater
Periom PI3EQX7502A USB3.0 Connector
HDMI Conn. DDI Intel KBL-U 15W/28W
USB3.0 Connector Alpine I/O Board
1356pin BGA

Card Reader USB Charger USB 2.0 Connector


SD Card Connector TI TPS2546RTER
Realtek RTS5220-GR USB2.0 x6
Cruze I/O Board
I/O Board PCIe x6 Camera
2 2

Wireless LAN (WIFI + BT combo)


NGFF Half Blue Tooth (WIFI + BT combo)
NGFF Half

PCIE SSD (2242/2280) x4 Finger Printer


M.2 NGFF (Option)

SPI ROM (8MB) SPI I2C (SPI) Touch Panel Int. Speaker
W25Q64FVSSIQ

HDA Audio Codec Int. Array Mic x2


REV:2.A Realtek ALC3240

Touch Pad I2C x1 FAB: JB501


Combo Jack
SATA x1 HDD Conn.
3 3

LPC
Hall sensor x1
(For Cruze)
Alpine Sub-borad Cruze Sub-borad I/O Board
EC
Nuvoton NPCE388NB0DX
I/O Board I/O Board Hall sensor x2
(For Alpine)
I2C x1 I2C x1
Sensor Board
(G sensor)
Int. KBD G Sensor x1 G Sensor x1
(For Alpine) (For Alpine)
Sensor Board

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


2017/06/05 2018/06/05 Title
Issued Date Deciphered Date Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 2.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E541P
Date: Wednesday, June 21, 2017 Sheet 2 of 51
A B C D E
1 2 3 4 5

Voltage Rails BOM Structure Table USB 2.0 Port Table


External
Item BOM Structure Item BOM Structure Port USB Port
For DIS DIS@
For KBL U22 CPU U22@ 1 USB3 Type-C Port
+5VS
For UMA UMA@
power
2 USB2/3 Port (MB)
+3VS
For Touch Panel with SPI TS_SPI@ For KBL U42 CPU U42@
plane 3 USB2/3 Port (IO/B)
+1.35VS
For Touch Panel with I2C TS_I2C@ N16S_R1@
4 USB3 Type-C Port
+5VALW +1.2V +VCC_CORE
For Keyboard backlight KBL@ N16S_R3@
For GPU Type 5 Camera
B+ +VGA_CORE
No Keyboard backlight NOKBL@ N16V_R1@
6 Finger Printer (Option)
+3VALW +VCC_GFXCORE_AXG
For Samsung VRAM S2G@ N16V_R3@
A 7 NGFF WLAN+BT A

+1.8VS
For Micron VRAM M2G@
U22_EMI@
State +0.6VS
For Hynix VRAM H2G@ For EMI
U42_EMI@
+1.0VALW
For UHD Panel UHD@ USB 3.0 Port Table
For Finger Printer FP@
For Thermal sensor EX_THM@
For SSD SSD@ Port
For EMI EMI@ For ESD FP_ESD@ 1 USB3 Type-C (MUX)
For ESD ESD@ 2 USB2/3 Port (MB) PCIE Port Table
For RF RF@ 3 USB2/3 Port (IO/B)
S0
No EMI @EMI@ 4 Lane Port
O O O O No ESD @ESD@ 5 1
No RF @RF@ 6 2
1 GPU
S3
Connector ME@ 3
O O O X For VARM X76 X76@ 4
SATA Port Table
S5 S4/AC
For Test Point TP@ 5 Card Reader
O O X X For Debug @DCI@ Port 6 NGFF WLAN+BT
S5 S4/ Battery only
For S series only S_AL@ 0 HDD 7
O X X X For S IMR series only S_IMR@ 1 8
S5 S4/AC & Battery
For YOGA series only YOGA@ 9
don't exist X X X X i7_7500U_R1@ 10
3 SSD
i5_7200U_R1@ 11
i3_7100U_R1@ 12
B B
i7_7500U_R3@
For CPU Type
i5_7200U_R3@
i3_7100U_R3@
pt_4415U_R1@
pt_4415U_R3@
i3_6006U_R3@

EC SM Bus1 address EC SM Bus2 address EC SM Bus4 address


X4E HDMI Logo
Device Address Device Address Device Address
NCT7718W 1001 100x 98h BMA250E 0001 100X 18h ZZZ 45@
Smart Battery 0001 011x 16h Yoga Series S Series
ZZZ4 X4E_YA@ ZZZ3 X4E_YA_FP@ ZZZ5 X4E_YB@ ZZZ6 X4E_YB_FP@ ZZZ8 X4E_S@ ZZZ7 X4E_S_FP@

PCH SM Bus address GPU SM Bus address


HDMI Logo
Device Address Device Address RO0000003HM
X4E Y Series X4E Y Series FP SKU X4E Y Series UHD SKU X4E Y Series UHD&FP SKU X4E S Series X4E S Series FP SKU
DDR_JDIMM1 1010 000x A0h Internal thermal sensor 1001 111x 9Eh X4EA5R38LA1 X4EA5R38LA2 X4EA5R38LE2 X4EA5R38LE1 X4EA5R38L01 X4EA5R38L02
Touch Pad

SMBUS Control Table Yoga Series (U42) S Series (U42) PCB part
ZZZ X4E_U42_YA@ ZZZ X4E_U42_YA_FP@ ZZZ1 X4E_U42_YB@ ZZZ2 X4E_U42_YB_FP@ ZZZ X4E_U42_S@ ZZZ X4E_U42_S_FP@ ZZZ YOGA@

Thermal G-
SOURCE VGA BATT CHARGER NECP388 SODIMM Sensor DGPU TP PCH SENSOR

SMB_EC_CK1
X V V X X X X X X X X X
C X4E Y Series X4E Y Series FP SKU X4E Y Series UHD SKU X4E Y Series UHD&FP SKU X4E S Series X4E S Series FP SKU PCB Y Series C
NECP388 X4EA5R38LL2 X4EA5R38LL1 X4EA5R38LO2 X4EA5R38LO1 X4EA5R38LR1 X4EA5R38LR2 DA80019S02A
SMB_EC_DA1 +3VALW +3VALW +19V_VIN
SMB_EC_CK2
V X X V X V X X X X V X
ZZZ S_AL@
NECP388
SMB_EC_DA2 +3VGS +3VS +3VS +3VS
+3VS GDDR5 VRAM * 2
SMB_EC_CK4
SMB_EC_DA4
NECP388
+3VALW
X X X X X X X X X X X V
+3VS X7671138L03 X7671138L02 X7671138L01 PCB S Series
DA80019S12A
PCH_SMBCLK
X X X X V X X X X V X X
UV6 S2G@ UV7 S2G@ UV6 M2G@ UV7 M2G@ UV6 H2G@ UV7 H2G@
PCH
PCH_SMBDATA +3VALW +3VS +3VS ZZZ S_IMR@

SML0CLK
SML0DATA
PCH
+3VALW
X X X X X X X X V
+3VS
X X X K4G80325FB-HC03 K4G80325FB-HC03 MT51J256M32HF MT51J256M32HF H5GC8H24MJR-T2C H5GC8H24MJR-T2C
SA000094R20 SA000094R20 SA000096K20 SA000096K20 SA00009ZG10 SA00009ZG10
SML1CLK
X X X V X X V X X X X X
PCB S Series
PCH RV65 RV65 RV65 DA80019S12A
SML1DATA +3VALW +3VS +3VS SD034499180
4.99K_0402_1%
SD034100280
10K_0402_1%
SD034301280
30.1K_0402_1%
S2G@ M2G@ H2G@

SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock GPU part CPU part
Full ON HIGH HIGH HIGH HIGH ON ON ON ON
UV1 N16S_R1@ UV1 N16V_R1@
KBL U22 (= U22@) SKL U22 (= U22@) KBL U42 (= U42@)
UC1 i3_7100U_R1@ UC1 i5_7200U_R1@ UC1 i7_7500U_R1@ UC1 pt_4415U_R1@ UC1 i3_6006U_R3@ UC1 i5_QNEF_R1@ UC1 i7_QNBF_R1@
S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW

S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF


N16S-GTR-S-A2 BGA 595P N16V-GMR1-S-A2 BGA 595P
SA00009FP00 SA00009IT00 QLYK H0 2.4G QLYJ H0 2.5G QLYH H0 2.7G QLYM H0 2.3G SR2JG K1 i3-6006U 2.0G C38! QNEF Y0 1.6G FCBGA QNBF Y0 1.8G FCBGA
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF SA0000A38A0 SA0000A37A0 SA0000A3490 SA0000ADV00 SA0000ACN10 SA0000AWB00 SA0000AWC00
D UV1 N16S_R3@ UV1 N16V_R3@ D
UC1 i3_7100U_R3@ UC1 i5_7200U_R3@ UC1 i7_7500U_R3@ UC1 pt_4415U_R3@ UC1 i5_QNEF_R3@ UC1 i7_QNBF_R3@
S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF

N16S-GTR-S-A2 BGA 595P N16V-GMR1-S-A2 BGA 595P


SA00009FP30 SA00009IT30 SR343 H0 2.4G SR342 H0 2.5G SR341 H0 2.7G SR348 H0 2.3G QNEF Y0 1.6G FCBGA QNBF Y0 1.8G FCBGA
SA0000A38B0 SA0000A37B0 SA0000A34A0 SA0000ADV20 SA0000AWB50 SA0000AWC50

Security Classification Compal Secret Data


Title
Compal Electronics, Inc.
Issued Date 2017/06/05 Deciphered Date 2018/06/05
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Notes List
Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 2.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-E541P
Wednesday, June 21, 2017 Sheet 3 of 51
1 2 3 4 5
5 4 3 2 1

-PowerMap_KBL_DDR4_Volume_NON CS]

B+

D D

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2017/06/05 Deciphered Date 2018/06/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power MAP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
LA-C071P 2.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 21, 2017 Sheet 4 of 51
5 4 3 2 1
5 4 3 2 1

G3->S0 S0->S3/DS3 S0/ DS3 ->S0 S0->S5


+3VL_RTC +3VL_RTC
tPCH01_Min : 9 ms
SOC_RTCRST# SOC_RTCRST#

B+ B+
D D
+3VLP/+5VLP +3VLP/+5VLP

EC_ON EC_ON
tPCH04_Min : 9 ms
+5VALW/+3VALW/+3VALW_DSW +5VALW/+3VALW/+3VALW_DSW
Pull-up to DSW well if not implemented.
PM_BATLOW# PM_BATLOW#

PCH_PWR_EN (SLP_SUS#) PCH_PWR_EN (SLP_SUS#)

+3V_PRIM +3V_PRIM

+1.8V_PRIM +1.8V_PRIM

EXT_PWR_GATE# If EXT_PWR_GATE# Toffmin is too small, Pwr EXT_PWR_GATE#


gate may choose to completely ignore it

+1.0V_MPHYPLL +1.0V_MPHYPLL

+1.0V_PRIM_CORE +1.0V_PRIM_CORE
tPCH34_Max : 20 ms
+1.0V_PRIM tPCH06_Min : 200 us +1.0V_PRIM

SUSACK# SUSACK#
tPCH02_Min : 10 ms
PCH_DPWROK PCH_DPWROK
tPCH03_Min : 10 ms
EC_RSMRST# EC_RSMRST#
tPLT02_Min : 0 ms Max : 90 ms
C C
AC_PRESENT AC_PRESENT

ON/OFF ON/OFF
tPCH43_Min : 95 ms
PBTN_OUT# PBTN_OUT#
Minimum duration of PWRBTN# assertion = 16mS. PWRBTN# can assert before or after RSMRST#

PM_SLP_S5# PM_SLP_S5#
tPCH18_Min : 90 us
ESPI_RST# ESPI_RST#

PM_SLP_S4# PM_SLP_S4#

SYSON SYSON

+1.0V_VCCST/+1.0V_VCCSFR +1.0V_VCCST/+1.0V_VCCSFR

+1.35V_VDDQ/+1.35V_VCCSFR_OC +1.35V_VDDQ/+1.35V_VCCSFR_OC

PM_SLP_S3# PM_SLP_S3#

SUSP# SUSP#
tCPU04 Min : 100 ns
+1.0VS_VCCSTG +1.0VS_VCCSTG
tCPU10 Min : 1 ms
B
+1.0VS_VCCIO +1.0VS_VCCIO B

T <=10msec
+5VS/+3VS/+1.5VS/+1.05VS
+5VS/+3VS/+1.5VS/+1.05VS
T = 10msec
EC_VCCST_PG EC_VCCST_PG

VR_ON VR_ON
tCPU19 Max : 100 ns
SM_PG_CTRL SM_PG_CTRL
tCPU18 Max : 35 us
+0.675VS_VTT +0.675VS_VTT
tCPU09 Min : 1 ms
+VCC_SA +VCC_SA

+VCC_CORE +VCC_CORE

+VCC_GT +VCC_GT

VR_PWRGD VR_PWRGD
tCPU16 Min : 0 ns
PCH_PWROK PCH_PWROK

H_CPUPWRGD H_CPUPWRGD

SYS_PWROK SYS_PWROK
A A

SUS_STAT# SUS_STAT#

SOC_PLTRST#
SOC_PLTRST#

Security Classification Compal Secret Data Compal Electronics, Inc.


2017/06/05 2018/06/05 Title
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power Sequence
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 2.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 21, 2017 Sheet 5 of 51
5 4 3 2 1
A B C D E

1 1

UC1A SKL-U
Rev_1.0
E55 C47
F55 DDI1_TXN[0] EDP_TXN[0] C46 EDP_TXN0 <26>
DDI1_TXP[0] EDP_TXP[0] EDP_TXP0 <26>
E58 D46
F58 DDI1_TXN[1] EDP_TXN[1] C45 EDP_TXN1 <26>
DDI1_TXP[1] EDP_TXP[1] EDP_TXP1 <26>
F53 A45 <eDP>
G53 DDI1_TXN[2] EDP_TXN[2] B45 EDP_TXN2 <26>
F56 DDI1_TXP[2] EDP_TXP[2] A47 EDP_TXP2 <26>
DDI1_TXN[3] EDP_TXN[3] EDP_TXN3 <26>
G56 B47
DDI1_TXP[3] EDP_TXP[3] EDP_TXP3 <26>
C50 E45 EDP_AUXN <26>
<27> HDMI_TX2-_CK D50 DDI2_TXN[0] DDI EDP EDP_AUXN F45
<27> HDMI_TX2+_CK DDI2_TXP[0] EDP_AUXP EDP_AUXP <26>
C52
<27> HDMI_TX1-_CK DDI2_TXN[1]
D52 B52
<27> HDMI_TX1+_CK DDI2_TXP[1] EDP_DISP_UTIL
<HDMI> A50
<27> HDMI_TX0-_CK DDI2_TXN[2]
B50 G50
<27> HDMI_TX0+_CK DDI2_TXP[2] DDI1_AUXN
D51 F50
<27> HDMI_CLK-_CK DDI2_TXN[3] DDI1_AUXP
C51 E48
<27> HDMI_CLK+_CK DDI2_TXP[3] DDI2_AUXN F48
DDI2_AUXP G46
DISPLAY SIDEBANDS RSVD F46
L13 RSVD
L12 GPP_E18/DDPB_CTRLCLK L9
GPP_E19/DDPB_CTRLDATA GPP_E13/DDPB_HPD0 L7
N7 GPP_E14/DDPC_HPD1 L6
TMDS_B_HPD <27> From HDMI
<27> HDMICLK_NB GPP_E20/DDPC_CTRLCLK GPP_E15/DDPD_HPD2
HDMI DDC (Port C) N8 N9
<27> HDMIDAT_NB GPP_E21/DDPC_CTRLDATA GPP_E16/DDPE_HPD3 EC_SCI# <10,32>
L10
N11 GPP_E17/EDP_HPD EDP_HPD <26> From eDP
N12 GPP_E22 R12
<26> TS_I2C_RST# GPP_E23 EDP_BKLTEN ENBKL <26,32>
R11
EDP_COMP EDP_BKLTCTL INVPWM <26>
E52 1 OF 20 U13
2 EDP_RCOMP EDP_VDDEN PCH_ENVDD <26> 2
SKL-U_BGA1356 @

< Compensation PU For eDP >

+1.0VS_VCCIO

1 2 EDP_COMP
RC3 24.9_0402_1%

Trace width=20 mils, Spacing=25mil, Max length=100mils


+1.0VS_VCCIO
1

If routed MS, PECI requires 18 mils spacing to other signals


+1.0V_VCCST RC4 UC1D SKL-U
1K_0402_5% Rev_1.0
SOC_CATERR# D63
T99 TP@ H_PECI A54 CATERR# < PU/PD for CMC Debug > +1.0VS_VCCIO
<32> H_PECI
2

1 2 H_THERMTRIP# 1 2 H_PROCHOT#_R C65 PECI


<32> H_PROCHOT# H_THERMTRIP# PROCHOT# JTAG
RC5 1K_0402_5% RC6 499_0402_1% C63
SOC_OCC# A65 THERMTRIP# SOC_XDP_TMS RC11 1 @ 2 51_0402_5%
T100 TP@ SKTOCC# CPU_XDP_TCK0
CPU MISC B61
XDP_BPM#0 C55 PROC_TCK D60 SOC_XDP_TDI SOC_XDP_TDI RC12 1 @ 2 51_0402_5%
T103 TP@ XDP_BPM#1 BPM#[0] PROC_TDI SOC_XDP_TDO
T105 TP@ D55 A61
3 XDP_BPM#2 B54 BPM#[1] PROC_TDO C60 SOC_XDP_TMS SOC_XDP_TDO RC13 1 @DCI@ 2 51_0402_5% 3
T107 TP@ XDP_BPM#3 BPM#[2] PROC_TMS SOC_XDP_TRST#
T109 TP@ C56 B59
BPM#[3] PROC_TRST#
A6 B56 PCH_JTAG_TCK1
A7 GPP_E3/CPU_GP0 PCH_JTAG_TCK D59 SOC_XDP_TDI CPU_XDP_TCK0 RC14 1 @DCI@ 2 51_0402_5%
<26> TS_INT# GPP_E7/CPU_GP1 PCH_JTAG_TDI SOC_XDP_TDO
BA5 A56
AY5 GPP_B3/CPU_GP2 PCH_JTAG_TDO C59 SOC_XDP_TMS PCH_JTAG_TCK1 RC15 1 @ 2 51_0402_5%
GPP_B4/CPU_GP3 PCH_JTAG_TMS C61 SOC_XDP_TRST#
CPU_POPIRCOMP PCH_TRST# CPU_XDP_TCK0 T116 TP@
RC7 2 1 49.9_0402_1% AT16 A59
RC8 2 1 49.9_0402_1% PCH_OPIRCOMP AU16 PROC_POPIRCOMP JTAGX
RC9 2 @ 1 49.9_0402_1% EDRAM_OPIO_RCOMP H66 PCH_OPIRCOMP
RC10 2 @ 1 49.9_0402_1% EOPIO_RCOMP H65 OPCE_RCOMP
OPC_RCOMP SOC_XDP_TRST# RC23 1 @ 2 51_0402_5%
4 OF 20
SKL-U_BGA1356 @

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2017/06/05 Deciphered Date 2018/06/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(1/12)DDI,EDP,MISC,CMC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 2.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E541P
Date: Wednesday, June 21, 2017 Sheet 6 of 51
A B C D E
5 4 3 2 1

Interleaved Memory

D D

SKL-U
UC1C
UC1B SKL-U Rev_1.0
Rev_1.0
<18> DDR_A_D[0..15] DDR_A_D0 DDR_A_CLK#0 Interleave / Non-Interleaved
AL71 AU53 AF65 AN45
DDR_A_D1 DDR0_DQ[0] DDR0_CKN[0] DDR_A_CLK0 DDR_A_CLK#0 <18> DDR1_DQ[0]/DDR0_DQ[16] DDR1_CKN[0]
AL68 AT53 AF64 AN46
DDR_A_D2 DDR0_DQ[1] DDR0_CKP[0] DDR_A_CLK#1 DDR_A_CLK0 <18> DDR1_DQ[1]/DDR0_DQ[17] DDR1_CKN[1]
AN68 AU55 DDR_A_CLK#1 <18> AK65 AP45
DDR_A_D3 AN69 DDR0_DQ[2] DDR0_CKN[1] AT55 DDR_A_CLK1 AK64 DDR1_DQ[2]/DDR0_DQ[18] DDR1_CKP[0] AP46
DDR_A_D4 DDR0_DQ[3] DDR0_CKP[1] DDR_A_CLK1 <18> DDR1_DQ[3]/DDR0_DQ[19] DDR1_CKP[1]
AL70 AF66
DDR_A_D5 AL69 DDR0_DQ[4] BA56 DDR_A_CKE0 AF67 DDR1_DQ[4]/DDR0_DQ[20] AN56
DDR_A_D6 DDR0_DQ[5] DDR0_CKE[0] DDR_A_CKE1 DDR_A_CKE0 <18> DDR1_DQ[5]/DDR0_DQ[21] DDR1_CKE[0]
AN70 BB56 AK67 AP55
DDR_A_D7 DDR0_DQ[6] DDR0_CKE[1] DDR_A_CKE1 <18> DDR1_DQ[6]/DDR0_DQ[22] DDR1_CKE[1]
AN71 AW56 TP@ T119
AK66 AN55
DDR_A_D8 AR70 DDR0_DQ[7] DDR0_CKE[2] AY56 AF70 DDR1_DQ[7]/DDR0_DQ[23] DDR1_CKE[2] AP53
DDR_A_D9 DDR0_DQ[8] DDR0_CKE[3] TP@ T118 DDR1_DQ[8]/DDR0_DQ[24] DDR1_CKE[3]
AR68 AF68
DDR_A_D10 AU71 DDR0_DQ[9] AU45 DDR_A_CS#0 AH71 DDR1_DQ[9]/DDR0_DQ[25] BB42
DDR_A_D11 DDR0_DQ[10] DDR0_CS#[0] DDR_A_CS#1 DDR_A_CS#0 <18> DDR1_DQ[10]/DDR0_DQ[26] DDR1_CS#[0]
AU68 AU43 AH68 AY42
DDR_A_D12 DDR0_DQ[11] DDR0_CS#[1] DDR_A_ODT0 DDR_A_CS#1 <18> DDR1_DQ[11]/DDR0_DQ[27] DDR1_CS#[1]
AR71 AT45 DDR_A_ODT0 <18>
AF71 BA42
DDR_A_D13 AR69 DDR0_DQ[12] DDR0_ODT[0] AT43 DDR_A_ODT1 AF69 DDR1_DQ[12]/DDR0_DQ[28] DDR1_ODT[0] AW42
DDR_A_D14 DDR0_DQ[13] DDR0_ODT[1] DDR_A_ODT1 <18> DDR1_DQ[13]/DDR0_DQ[29] DDR1_ODT[1]
AU70 AH70
DDR_A_D15 AU69 DDR0_DQ[14] AH69 DDR1_DQ[14]/DDR0_DQ[30]
DDR0_DQ[15] DDR3L / LPDDR3 / DDR4 DDR_A_MA5 DDR1_DQ[15]/DDR0_DQ[31] DDR3L / LPDDR3 / DDR4
BA51 AT66 AY48
DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDR_A_MA9 DDR_A_MA5 <18> DDR1_DQ[16]/DDR0_DQ[48] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]
BB54 DDR_A_MA9 <18> AU66 AP50
<18> DDR_A_D[16..31] DDR_A_D16 Interleave / Non-Interleaved DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDR_A_MA6 DDR1_DQ[17]/DDR0_DQ[49] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]
BB65 BA52 DDR_A_MA6 <18> AP65 BA48
DDR_A_D17 AW65 DDR0_DQ[16]/DDR0_DQ[32] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] AY52 DDR_A_MA8 AN65 DDR1_DQ[18]/DDR0_DQ[50] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] BB48
DDR_A_D18 DDR0_DQ[17]/DDR0_DQ[33] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] DDR_A_MA7 DDR_A_MA8 <18> DDR1_DQ[19]/DDR0_DQ[51] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]
AW63 AW52 AN66 AP48
DDR_A_D19 DDR0_DQ[18]/DDR0_DQ[34] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] DDR_A_BG0 DDR_A_MA7 <18> DDR1_DQ[20]/DDR0_DQ[52] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]
AY63 AY55 AP66 AP52
DDR_A_D20 DDR0_DQ[19]/DDR0_DQ[35] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDR_A_MA12 DDR_A_BG0 <18> DDR1_DQ[21]/DDR0_DQ[53] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]
BA65 AW54 DDR_A_MA12 <18> AT65 AN50
DDR_A_D21 AY65 DDR0_DQ[20]/DDR0_DQ[36] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] BA54 DDR_A_MA11 AU65 DDR1_DQ[22]/DDR0_DQ[54] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] AN48
DDR_A_D22 DDR0_DQ[21]/DDR0_DQ[37] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] DDR_A_MA11 <18> DDR1_DQ[23]/DDR0_DQ[55] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]
BA63 BA55 M_A_ACT# <18> AT61 AN53
DDR_A_D23 BB63 DDR0_DQ[22]/DDR0_DQ[38] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# AY54 AU61 DDR1_DQ[24]/DDR0_DQ[56] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# AN52
DDR_A_D24 DDR0_DQ[23]/DDR0_DQ[39] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] DDR_A_MA13 DDR_A_BG1 <18> DDR1_DQ[25]/DDR0_DQ[57] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]
BA61 AU46 AP60 BA43
DDR_A_D25 DDR0_DQ[24]/DDR0_DQ[40] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] DDR_A_MA15 DDR_A_MA13 <18> DDR1_DQ[26]/DDR0_DQ[58] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]
AW61 AU48 DDR_A_MA15 <18>
AN60 AY43
C DDR_A_D26 BB59 DDR0_DQ[25]/DDR0_DQ[41] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] AT46 DDR_A_MA14 AN61 DDR1_DQ[27]/DDR0_DQ[59] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] AY44 C
DDR_A_D27 DDR0_DQ[26]/DDR0_DQ[42] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] DDR_A_MA16 DDR_A_MA14 <18> DDR1_DQ[28]/DDR0_DQ[60] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]
AW59 AU50 DDR_A_MA16 <18> AP61 AW44
DDR_A_D28 BB61 DDR0_DQ[27]/DDR0_DQ[43] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] AU52 DDR_A_BA0 AT60 DDR1_DQ[29]/DDR0_DQ[61] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] BB44
DDR_A_D29 DDR0_DQ[28]/DDR0_DQ[44] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] DDR_A_MA2 DDR_A_BA0 <18> DDR1_DQ[30]/DDR0_DQ[62] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]
AY61 AY51 AU60 AY47
DDR_A_D30 DDR0_DQ[29]/DDR0_DQ[45] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] DDR_A_BA1 DDR_A_MA2 <18> DDR1_DQ[31]/DDR0_DQ[63] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]
BA59 AT48 DDR_A_BA1 <18> AU40 BA44
DDR_A_D31 AY59 DDR0_DQ[30]/DDR0_DQ[46] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] AT50 DDR_A_MA10 AT40 DDR1_DQ[32]/DDR1_DQ[16] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] AW46
<18> DDR_A_D[32..47] DDR_A_D32 DDR0_DQ[31]/DDR0_DQ[47] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] DDR_A_MA1 DDR_A_MA10 <18> DDR1_DQ[33]/DDR1_DQ[17] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]
AY39 BB50 DDR_A_MA1 <18> AT37 AY46
DDR_A_D33 AW39 DDR0_DQ[32]/DDR1_DQ[0] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] AY50 DDR_A_MA0 AU37 DDR1_DQ[34]/DDR1_DQ[18] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] BA46
DDR_A_D34 DDR0_DQ[33]/DDR1_DQ[1] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] DDR_A_MA0 <18> DDR1_DQ[35]/DDR1_DQ[19] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]
AY37 AR40
DDR_A_D35 AW37 DDR0_DQ[34]/DDR1_DQ[2] BA50 DDR_A_MA3 AP40 DDR1_DQ[36]/DDR1_DQ[20] BB46
DDR_A_D36 DDR0_DQ[35]/DDR1_DQ[3] DDR0_MA[3] DDR_A_MA4 DDR_A_MA3 <18> DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[3]
BB39 BB52 DDR_A_MA4 <18>
AP37 BA47
DDR_A_D37 BA39 DDR0_DQ[36]/DDR1_DQ[4] DDR0_MA[4] AM70 DDR_A_DQS#0 AR37 DDR1_DQ[38]/DDR1_DQ[22] DDR1_MA[4]
DDR_A_D38 DDR0_DQ[37]/DDR1_DQ[5] DDR0_DQSN[0] DDR_A_DQS0 DDR_A_DQS#0 <18> DDR1_DQ[39]/DDR1_DQ[23]
BA37 AM69 AT33
DDR_A_D39 DDR0_DQ[38]/DDR1_DQ[6] DDR0_DQSP[0] DDR_A_DQS#1 DDR_A_DQS0 <18> DDR1_DQ[40]/DDR1_DQ[24] Interleave / Non-Interleaved
BB37 AT69 AU33 AH66
DDR_A_D40 DDR0_DQ[39]/DDR1_DQ[7] DDR0_DQSN[1] DDR_A_DQS1 DDR_A_DQS#1 <18> DDR1_DQ[41]/DDR1_DQ[25] DDR1_DQSN[0]/DDR0_DQSN[2]
AY35 AT70 DDR_A_DQS1 <18>
AU30 AH65
DDR_A_D41 AW35 DDR0_DQ[40]/DDR1_DQ[8] DDR0_DQSP[1] AT30 DDR1_DQ[42]/DDR1_DQ[26] DDR1_DQSP[0]/DDR0_DQSP[2] AG69
DDR_A_D42 AY33 DDR0_DQ[41]/DDR1_DQ[9] AR33 DDR1_DQ[43]/DDR1_DQ[27] DDR1_DQSN[1]/DDR0_DQSN[3] AG70
DDR_A_D43 DDR0_DQ[42]/DDR1_DQ[10] Interleave / Non-Interleaved DDR_A_DQS#2 DDR1_DQ[44]/DDR1_DQ[28] DDR1_DQSP[1]/DDR0_DQSP[3]
AW33 BA64 AP33 AR66
DDR_A_D44 DDR0_DQ[43]/DDR1_DQ[11] DDR0_DQSN[2]/DDR0_DQSN[4] DDR_A_DQS2 DDR_A_DQS#2 <18> DDR1_DQ[45]/DDR1_DQ[29] DDR1_DQSN[2]/DDR0_DQSN[6]
BB35 AY64 AR30 AR65
DDR_A_D45 DDR0_DQ[44]/DDR1_DQ[12] DDR0_DQSP[2]/DDR0_DQSP[4] DDR_A_DQS#3 DDR_A_DQS2 <18> DDR1_DQ[46]/DDR1_DQ[30] DDR1_DQSP[2]/DDR0_DQSP[6]
BA35 AY60 DDR_A_DQS#3 <18> AP30 AR61
DDR_A_D46 BA33 DDR0_DQ[45]/DDR1_DQ[13] DDR0_DQSN[3]/DDR0_DQSN[5] BA60 DDR_A_DQS3 DDR1_DQ[47]/DDR1_DQ[31] DDR1_DQSN[3]/DDR0_DQSN[7] AR60
DDR_A_D47 DDR0_DQ[46]/DDR1_DQ[14] DDR0_DQSP[3]/DDR0_DQSP[5] DDR_A_DQS#4 DDR_A_DQS3 <18> DDR1_DQSP[3]/DDR0_DQSP[7]
BB33 BA38 DDR_A_DQS#4 <18> AU27 AT38
<18> DDR_A_D[48..63] DDR_A_D48 AY31 DDR0_DQ[47]/DDR1_DQ[15] DDR0_DQSN[4]/DDR1_DQSN[0] AY38 DDR_A_DQS4 AT27 DDR1_DQ[48] DDR1_DQSN[4]/DDR1_DQSN[2] AR38
DDR_A_D49 DDR0_DQ[48]/DDR1_DQ[32] DDR0_DQSP[4]/DDR1_DQSP[0] DDR_A_DQS#5 DDR_A_DQS4 <18> DDR1_DQ[49] DDR1_DQSP[4]/DDR1_DQSP[2]
AW31 AY34 AT25 AT32
DDR_A_D50 DDR0_DQ[49]/DDR1_DQ[33] DDR0_DQSN[5]/DDR1_DQSN[1] DDR_A_DQS5 DDR_A_DQS#5 <18> DDR1_DQ[50] DDR1_DQSN[5]/DDR1_DQSN[3]
AY29 BA34 DDR_A_DQS5 <18>
AU25 AR32
DDR_A_D51 AW29 DDR0_DQ[50]/DDR1_DQ[34] DDR0_DQSP[5]/DDR1_DQSP[1] BA30 DDR_A_DQS#6 AP27 DDR1_DQ[51] DDR1_DQSP[5]/DDR1_DQSP[3]
DDR_A_D52 DDR0_DQ[51]/DDR1_DQ[35] DDR0_DQSN[6]/DDR1_DQSN[4] DDR_A_DQS6 DDR_A_DQS#6 <18> DDR1_DQ[52]
BB31 AY30 DDR_A_DQS6 <18> AN27 AR25
DDR_A_D53 BA31 DDR0_DQ[52]/DDR1_DQ[36] DDR0_DQSP[6]/DDR1_DQSP[4] AY26 DDR_A_DQS#7 AN25 DDR1_DQ[53] DDR1_DQSN[6] AR27
DDR_A_D54 DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQSN[7]/DDR1_DQSN[5] DDR_A_DQS7 DDR_A_DQS#7 <18> DDR1_DQ[54] DDR1_DQSP[6]
BA29 BA26 AP25 AR22
DDR_A_D55 DDR0_DQ[54]/DDR1_DQ[38] DDR0_DQSP[7]/DDR1_DQSP[5] DDR_A_DQS7 <18> DDR1_DQ[55] DDR1_DQSN[7]
BB29 AT22 AR21
DDR_A_D56 AY27 DDR0_DQ[55]/DDR1_DQ[39] AW50 AU22 DDR1_DQ[56] DDR1_DQSP[7] AN43
DDR_A_D57 DDR0_DQ[56]/DDR1_DQ[40] DDR0_ALERT# DDR_A_ALERT# <18> DDR1_DQ[57] DDR1_ALERT#
AW27 AT52 DDR_A_PARITY <18>
AU21 AP43 TP@ T123
DDR_A_D58 AY25 DDR0_DQ[57]/DDR1_DQ[41] DDR0_PAR AT21 DDR1_DQ[58] DDR1_PAR AT13 DDR_DRAMRST#
DDR_A_D59 DDR0_DQ[58]/DDR1_DQ[42] DDR1_DQ[59] DRAM_RESET# DDR_DRAMRST# <18>
AW25 DDR CH - A AY67 AN22 DDR CH - B AR18
DDR_A_D60 DDR0_DQ[59]/DDR1_DQ[43] DDR_VREF_CA +0.6V_VREFCA <18> DDR1_DQ[60] DDR_RCOMP[0]
BB27 AY68 +0.6V_A_VREFDQ <18> Trace width/Spacing >= 20mils AP22 AT18
B DDR_A_D61 BA27 DDR0_DQ[60]/DDR1_DQ[44] DDR0_VREF_DQ BA67 AP21 DDR1_DQ[61] DDR_RCOMP[1] AU18 SM_RCOMP0 RC16 1 2 121_0402_1% B
DDR_A_D62 BA25 DDR0_DQ[61]/DDR1_DQ[45] DDR1_VREF_DQ AN21 DDR1_DQ[62] 3 OF 20 DDR_RCOMP[2] SM_RCOMP1 RC17 1 2 80.6_0402_1%
DDR_A_D63 BB25 DDR0_DQ[62]/DDR1_DQ[46] 2 OF 20 AW67 DDR_PG_CTRL DDR1_DQ[63] SM_RCOMP2 RC18 1 2 100_0402_1%
DDR0_DQ[63]/DDR1_DQ[47] DDR_VTT_CNTL SKL-U_BGA1356 @
SKL-U_BGA1356 @

+1.2V
+1.2V

1
+3VS
RC20
@ 470_0402_5%
CC101 2 1 0.1U_0201_10V6K
1

2
UC7
1 5 RC54 DDR_DRAMRST#
NC VCC 220K_0402_5%
DDR_PG_CTRL 2 1
2

A 4 CC96
3 Y DDR_VTT_PG_CTRL <42>
100P_0402_50V8J
GND ESD@
1

74AUP1G07GW_TSSOP5 2
SA00007WE00 RC19 Close to CPU
2M_0402_5%
A @ A
2

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2017/06/05 Deciphered Date 2018/06/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(2/12)DDR3L
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 2.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E541P
Date: Wednesday, June 21, 2017 Sheet 7 of 51
5 4 3 2 1
5 4 3 2 1

SML0ALERT# (Internal Pull Down):

eSPI or LPC

0 = LPC is selected for EC ==> Default


+3VALW
1 = eSPI is selected for EC
D D

RC21 1 @ 2 1K_0402_5% SOC_SPI_IO2 +3VS

RPC12
SOC_SML0CLK 1 8
SOC_SML0DATA 2 7
RC22 1 @ 2 1K_0402_5% SOC_SPI_IO3 3 6
4 5
RC24 1 @ 2 1K_0402_5%
499_0804_8P4R_1%

+3VS
UC1E SKL-U
Rev_1.0
SPI - FLASH
SMBUS, SMLINK
SOC_SML1ALERT# RC113 1 @ 2 150K_0402_5%
+3VS SOC_SPI_CLK AV2 R7 PCH_SMB_CLK
SOC_SPI_SO AW3 SPI0_CLK GPP_C0/SMBCLK R8 PCH_SMB_DATA PCH_SMB_CLK <18> SMB
PCH_SMB_DATA <18> RPC2
SOC_SPI_SI AV3 SPI0_MISO GPP_C1/SMBDATA R10 SOC_SMBALERT# (Link to DDR) PCH_SMB_CLK 1 8
SOC_SPI_IO2 SPI0_MOSI GPP_C2/SMBALERT# TP@ T124 PCH_SMB_DATA
AW2 2 7
RC112 1 2 10K_0402_5% KB_RST# SOC_SPI_IO3 AU4 SPI0_IO2 R9 SOC_SML0CLK EC_SMB_CK2 3 6
SOC_SPI_CS#0 AU3 SPI0_IO3 GPP_C3/SML0CLK W2 SOC_SML0DATA EC_SMB_DA2 4 5
AU2 SPI0_CS0# GPP_C4/SML0DATA W1 SOC_SML0ALERT#
SPI0_CS1# GPP_C5/SML0ALERT# TP@ T125
AU1 1K_0804_8P4R_5%
SPI0_CS2# W3
+1.8VS_3VS_PGPPA GPP_C6/SML1CLK V3
EC_SMB_CK2 <22,32,36> SML1
SPI - TOUCH GPP_C7/SML1DATA SOC_SML1ALERT# EC_SMB_DA2 <22,32,36>
AM7 (Link to EC,DGPU,Thermal Sensor) +1.8VS_3VS_PGPPA
TS_SPI_CLK M2 GPP_B23/SML1ALERT#/PCHHOT#
<26> TS_SPI_CLK TS_SPI_SO GPP_D1/SPI1_CLK
RC25 1 2 8.2K_0402_5% SERIRQ M3
<26> TS_SPI_SO TS_SPI_SI GPP_D2/SPI1_MISO PM_CLKRUN#
J4 RC31 1 @ 2 8.2K_0402_5%
<26> TS_SPI_SI GPP_D3/SPI1_MOSI
V1
V2 GPP_D21/SPI1_IO2 AY13 LPC_AD0
C TS_SPI_CS#0 GPP_D22/SPI1_IO3 GPP_A1/LAD0/ESPI_IO0 LPC_AD1 LPC_AD0 <32> C
M1 LPC BA13
<26> TS_SPI_CS#0 GPP_D0/SPI1_CS# GPP_A2/LAD1/ESPI_IO1 LPC_AD2 LPC_AD1 <32>
BB13 Follow 543016_SKL_U_Y_PDG_0_9
GPP_A3/LAD2/ESPI_IO2 LPC_AD3 LPC_AD2 <32>
AY12
C LINK GPP_A4/LAD3/ESPI_IO3 LPC_FRAME# LPC_AD3 <32>
BA12
GPP_A5/LFRAME#/ESPI_CS# LPC_FRAME# <32>
G3 BA11
G2 CL_CLK GPP_A14/SUS_STAT#/ESPI_RESET#
G1 CL_DATA
CL_RST# AW9 LPC_CLK0 RC26 1 EMI@ 2 22_0402_5%
GPP_A9/CLKOUT_LPC0/ESPI_CLK AY9 CLK_LPC_EC <32>
KB_RST# AW13 GPP_A10/CLKOUT_LPC1 AW11 PM_CLKRUN#
GPP_A0/RCIN# GPP_A8/CLKRUN#
SERIRQ AY11
<32> SERIRQ GPP_A6/SERIRQ 5 OF 20

SKL-U_BGA1356 @

RPC1, RPC3 and RC30 are close to UC3


RPC1
SOC_SPI_SO 1 8 SOC_SPI_SO_0_R
SOC_SPI_CLK 2 7 SOC_SPI_CLK_0_R
SOC_SPI_SI 3 6 SOC_SPI_SI_0_R
B SOC_SPI_IO3 4 5 SOC_SPI_IO3_0_R B

From SOC 33_0804_8P4R_5%


EMI@
SOC_SPI_IO2 1 2 SOC_SPI_IO2_0_R
RC30 EMI@ 33_0402_5%

RPC3
EC_SPICLK 1 8 SOC_SPI_CLK_0_R
<32> EC_SPI_CLK EC_MOSI SOC_SPI_SI_0_R
2 7
<32> EC_SPI_MOSI EC_SPICS# SOC_SPI_CS#0
3 6
From EC <32> EC_SPI_CS0# EC_MISO 4 5 SOC_SPI_SO_0_R
<32> EC_SPI_MISO
33_0804_8P4R_5%
EMI@

< SPI ROM - 8M >


+3VALW
@
UC3 CC2 1 2 0.1U_0201_10V K X5R
SOC_SPI_CS#0 1 8
SOC_SPI_SO_0_R 2 /CS VCC 7 SOC_SPI_IO3_0_R
SOC_SPI_IO2_0_R 3 DO(IO1) /HOLD(IO3) 6 SOC_SPI_CLK_0_R
4 /WP(IO2) CLK 5 SOC_SPI_SI_0_R
GND DI(IO0)
1
A W25Q64FVSSIQ_SO8 A
CC3
10P_0402_50V8J
2 @EMI@

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2017/06/05 Deciphered Date 2018/06/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(3/12)SPI,SMB,LPC,ESPI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 2.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E541P
Date: Wednesday, June 21, 2017 Sheet 8 of 51
5 4 3 2 1
5 4 3 2 1

D D

UC1G SKL-U
Rev_1.0
< HD AUDIO >
AUDIO
RPC4
1 8 HDA_BIT_CLK HDA_SYNC BA22
<28> HDA_BITCLK_AUDIO HDA_SYNC HDA_BIT_CLK HDA_SYNC/I2S0_SFRM
2 7 AY22
<28> HDA_SYNC_AUDIO HDA_SDOUT HDA_BLK/I2S0_SCLK
3 6 BB22 SDIO / SDXC
4 5 HDA_SDOUT BA21 HDA_SDO/I2S0_TXD
<28> HDA_SDOUT_AUDIO <28> HDA_SDIN0 HDA_SDI0/I2S0_RXD
AY21 AB11
33_0804_8P4R_5% AW22 HDA_SDI1/I2S1_RXD GPP_G0/SD_CMD AB13
EMI@ J5 HDA_RST#/I2S1_SCLK GPP_G1/SD_DATA0 AB12
AY20 GPP_D23/I2S_MCLK GPP_G2/SD_DATA1 W12
AW20 I2S1_SFRM GPP_G3/SD_DATA2 W11
I2S1_TXD GPP_G4/SD_DATA3 W10
< To Enable ME Override > AK7 GPP_G5/SD_CD# W8
AK6 GPP_F1/I2S2_SFRM GPP_G6/SD_CLK W7
AK9 GPP_F0/I2S2_SCLK GPP_G7/SD_WP
AK10 GPP_F2/I2S2_TXD BA9
GPP_F3/I2S2_RXD GPP_A17/SD_PWR_EN#/ISH_GP7 BB9
GPP_A16/SD_1P8_SEL
H5 AB7 RC76 1 @ 2 200_0402_1%
D7 GPP_D19/DMIC_CLK0 SD_RCOMP
GPP_D20/DMIC_DATA0
D8 AF13
C8 GPP_D17/DMIC_CLK1 GPP_F23
RC116 1 2 0_0402_5% HDA_SDOUT GPP_D18/DMIC_DATA1
<32> ME_EN HDA_SPKR AW5
<28> HDA_SPKR GPP_B14/SPKR
C C
7 OF 20

SKL-U_BGA1356 @

UC1I SKL-U
Rev_1.0
+3VS CSI-2

A36 C37
RC33 1 @ 2 2.2K_0402_5% HDA_SPKR B36 CSI2_DN0 CSI2_CLKN0 D37
C38 CSI2_DP0 CSI2_CLKP0 C32
D38 CSI2_DN1 CSI2_CLKN1 D32
C36 CSI2_DP1 CSI2_CLKP1 C29
SPKR (Internal Pull Down): D36 CSI2_DN2 CSI2_CLKN2 D29
A38 CSI2_DP2 CSI2_CLKP2 B26
TOP Swap Override B38 CSI2_DN3 CSI2_CLKN3 A26
B CSI2_DP3 CSI2_CLKP3 B
C31 E13 RC80 1 @ 2 100_0402_1%
0 = Disable TOP Swap mode. ==> Default D31 CSI2_DN4 CSI2_COMP B7
C33 CSI2_DP4 GPP_D4/FLASHTRIG
D33 CSI2_DN5
1 = Enable TOP Swap Mode. CSI2_DP5 EMMC
A31
B31 CSI2_DN6 AP2
A33 CSI2_DP6 GPP_F13/EMMC_DATA0 AP1
B33 CSI2_DN7 GPP_F14/EMMC_DATA1 AP3
CSI2_DP7 GPP_F15/EMMC_DATA2 AN3
A29 GPP_F16/EMMC_DATA3 AN1
B29 CSI2_DN8 GPP_F17/EMMC_DATA4 AN2
C28 CSI2_DP8 GPP_F18/EMMC_DATA5 AM4
D28 CSI2_DN9 GPP_F19/EMMC_DATA6 AM1
A27 CSI2_DP9 GPP_F20/EMMC_DATA7
B27 CSI2_DN10 AM2
C27 CSI2_DP10 GPP_F21/EMMC_RCLK AM3
D27 CSI2_DN11 GPP_F22/EMMC_CLK AP4
CSI2_DP11 GPP_F12/EMMC_CMD
9 OF 20 AT1 RC129 1 @ 2 200_0402_1%
EMMC_RCOMP
SKL-U_BGA1356 @

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2017/06/05 Deciphered Date 2018/06/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(4/12)HDA,EMMC,SDIO,CSI2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 2.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E541P
Date: Wednesday, June 21, 2017 Sheet 9 of 51
5 4 3 2 1
5 4 3 2 1

U22_EMI@
SOC_XTAL24_IN RC154 1 2 33_0402_1% XTAL24_IN

U22_EMI@
SOC_XTAL24_OUT RC155 1 2 33_0402_1% XTAL24_OUT
U22@
RC34 1 2 1M_0402_5%

+3VS
D D
YC1 U22@
UC1J SKL-U 24MHZ_18PF_XRCGB24M000F2P51R0
Rev_1.0 SJ10000UJ00
RPC5 CLOCK SIGNALS
8 1 CLKREQ_PCIE#4 1 3
7 2 CLKREQ_PCIE#5 D42 1 3
6 3 <19> CLK_PEG_VGA# C42 CLKOUT_PCIE_N0 NC NC
DGPU <19> CLK_PEG_VGA VGA_CLKREQ# CLKOUT_PCIE_P0
5 4 AR10
<19> VGA_CLKREQ# GPP_B5/SRCCLKREQ0# 2 4
U22@ U22@

27P_0402_50V8J

27P_0402_50V8J
10K_0804_8P4R_5% B42 1 1
<31> CLK_PCIE_SSD# A42 CLKOUT_PCIE_N1 F43
@ SSD <31> CLK_PCIE_SSD SSDCLK_REQ# CLKOUT_PCIE_P1 CLKOUT_ITPXDP_N

CC4

CC5
<31> SSDCLK_REQ#
AT7 E43
GPP_B6/SRCCLKREQ1# CLKOUT_ITPXDP_P
RPC6 D41 BA17 SUSCLK 2 2
CR_CLKREQ# <30> CLK_PCIE_WLAN# CLKOUT_PCIE_N2 GPD8/SUSCLK SUSCLK <30>
8 1 NGFF WL+BT C41
7 2 WLANCLK_REQ# <30> CLK_PCIE_WLAN WLANCLK_REQ# AT8 CLKOUT_PCIE_P2 E37 SOC_XTAL24_IN
<30> WLANCLK_REQ# GPP_B7/SRCCLKREQ2# XTAL24_IN SOC_XTAL24_OUT
6 3 EC_SCI# <6,32> E35
5 4 SSDCLK_REQ# D40 XTAL24_OUT
<35> CLK_PCIE_CR# CLKOUT_PCIE_N3 XCLK_BIASREF
Card Reader RTS5220 C40 E42
<35> CLK_PCIE_CR CLKOUT_PCIE_P3 XCLK_BIASREF
10K_0804_8P4R_5% <35> CR_CLKREQ#
AT10
GPP_B8/SRCCLKREQ3# AM18 SOC_RTCX1 +1.0V_CLK5_F24NS
+3VS B40 RTCX1 AM20 SOC_RTCX2
A40 CLKOUT_PCIE_N4 RTCX2
CLKREQ_PCIE#4 AU8 CLKOUT_PCIE_P4 AN18 SOC_SRTCRST# XCLK_BIASREF RC35 1 2 2.7K_0402_1%
RC134 GPP_B9/SRCCLKREQ4# SRTCRST# AM16 SOC_RTCRST#
1 2 VGA_CLKREQ# E40 RTCRST# RC110 1 @ 2 60.4_0402_1%
E38 CLKOUT_PCIE_N5
10K_0402_5% CLKREQ_PCIE#5 AU7 CLKOUT_PCIE_P5
GPP_B10/SRCCLKREQ5#

10 OF 20

SKL-U_BGA1356 @

+3VL_RTC
C C

RC36 1 2 20K_0402_5% SOC_SRTCRST#

CC6 1 2 1U_0402_6.3V6K
< PCH PLTRST Buffer >
RC42 1 2 0_0402_5%

RC37 1 2 20K_0402_5% SOC_RTCRST# RC38 1 2 0_0402_5% EC_CLEAR_CMOS# <32> +3VS


CC7 1 2 1U_0402_6.3V6K
SOC_RTCX2
CLRP2 1 2 SHORT PADS CLR CMOS

5
UC4 @
SOC_PLTRST# 1

P
RC39 1 2 1M_0402_5% SM_INTRUDER# B 4 SOC_RTCX1
2 Y PCI_RST# <19,30,31,32,35>
A

100K_0402_5%

100P_0402_50V8J
RC41 1 2 10M_0402_5%

1
TC7SH08FUF_SSOP5

1
RC44
SA007080100 ESD@

CC8
2
YC2

2
1 2

+3VALW 32.768KHZ_9PF_9H03280012
SJ10000Q400

6.8P_0402_50V8C

6.8P_0402_50V8C
RPC7 1 1
8 1 PCH_PWROK
EC_RSMRST#

CC9

CC10
7 2
6 3
5 4 SYS_RESET# 2 2
B B
10K_0804_8P4R_5% UC1K SKL-U
Rev_1.0
SYSTEM POWER MANAGEMENT
AT11 PM_SLP_S0#
GPP_B12/SLP_S0# PM_SLP_S3# TP@T130
AP15
SOC_PLTRST# AN10 GPD4/SLP_S3# BA16 PM_SLP_S4# PM_SLP_S3# <32>
SYS_RESET# B5 GPP_B13/PLTRST# GPD5/SLP_S4# AY16 PM_SLP_S5# PM_SLP_S4# <32,40,42>
SYS_RESET# EC_RSMRST# SYS_RESET# GPD10/SLP_S5# TP@T131
ESD@ 1 2
<32> EC_RSMRST#
AY17
CC97 100P_0402_50V8J RSMRST# AN15
ESD@ 1 2 EC_RSMRST# H_CPUPWRGD A68 SLP_SUS# AW15
Only For Power Sequence Debug T132 TP@ EC_VCCST_PG PROCPWRGD SLP_LAN# SLP_WLAN#
CC94 100P_0402_50V8J B65 BB17 TP@T133
ESD@ 1 2 SYS_PWROK VCCST_PWRGD GPD9/SLP_WLAN# AN16 PM_SLP_A#
SYS_PWROK GPD6/SLP_A# TP@T134
CC95 100P_0402_50V8J B6
<32> SYS_PWROK PCH_PWROK SYS_PWROK PBTN_OUT#
<32> PCH_PWROK BA20 BA15 PBTN_OUT# <32>
EC_RSMRST# BB20 PCH_PWROK GPD3/PWRBTN# AY15 AC_PRESENT RC103 1 2 0_0402_5%
DSW_PWROK GPD1/ACPRESENT PM_BATLOW# EC_VCIN1_AC_BYPASS <22,32>
AU13
AR13 GPD0/BATLOW#
AP11 GPP_A13/SUSWARN#/SUSPWRDNACK +3VALW
GPP_A15/SUSACK# AU11
WAKE# BB15 GPP_A11/PME# AP16 SM_INTRUDER#
+3VALW AM15 WAKE# INTRUDER# PM_BATLOW# RC46 1 2 8.2K_0402_5%
AW17 GPD2/LAN_WAKE# AM10
1 2 WAKE# AT15 GPD11/LANPHYPC GPP_B11/EXT_PWR_GATE# AM11 SOC_VRALERT# AC_PRESENT RC48 1 @ 2 10K_0402_5%
RC47 1K_0402_5% GPD7/RSVD 11 OF 20 GPP_B2/VRALERT#
SOC_VRALERT# RC50 1 @ 2 10K_0402_5%
SKL-U_BGA1356 @
+1.0V_VCCST
From EC (Open-Drain)
1

RC52
1K_0402_5%
2

A A
RC53 1 2 60.4_0402_1% EC_VCCST_PG
<32> VCCST_PWRGD

1
CC117
100P_0402_50V8J
2 ESD@

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2017/06/05 Deciphered Date 2018/06/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(5/12)CLK,PM,GPIO
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 2.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E541P
Date: Wednesday, June 21, 2017 Sheet 10 of 51
5 4 3 2 1
5 4 3 2 1

GSPI0_MOSI (Internal Pull Down):

No Reboot

0 = Disable No Reboot mode. ==> Default


+3VS
1 = Enable No Reboot Mode. (PCH will disable the TCO RC206 1 @ 2 10K_0402_5% STORAGE_PRSNT1
D
Timer system reboot feature). This funct i oni s us ef ul D
when running ITP/XDP. RC205 1 @ 2 10K_0402_5%

GSPI1_MOSI (Internal Pull Down):


RC208 1 @ 2 10K_0402_5% STORAGE_PRSNT2

Boot BIOS Strap Bit RC207 1 @ 2 10K_0402_5%

0 = SPI Mode ==> Default


1 = LPC Mode
+3VS
DGPU_PRSNT
Funct i on (GPP_C15)
RC59 1 @ 2 4.7K_0402_5% GSPI0_MOSI
DIS 0
RC60 1 @ 2 150K_0402_5% GSPI1_MOSI UMA Only 1
+3VS

RC61 1 UMA@ 2 10K_0402_5% DGPU_PRSNT

RC62 1 DIS@ 2 10K_0402_5%

C C
UC1F SKL-U
Rev_1.0
LPSS ISH

RPC10 AN8 P2
+3VS 1 8 AP7 GPP_B15/GSPI0_CS# GPP_D9 P3
2 7 SOC_GPIOB17 AP8 GPP_B16/GSPI0_CLK GPP_D10 P4 STORAGE_PRSNT2
3 6 UART0_RX GSPI0_MOSI AR7 GPP_B17/GSPI0_MISO GPP_D11 P1 STORAGE_PRSNT1
UART0_TX GPP_B18/GSPI0_MOSI GPP_D12 Funct i on MB_ID
4 5
AM5 M4
49.9K_0804_8P4R_1% AN7 GPP_B19/GSPI1_CS# GPP_D5/ISH_I2C0_SDA N3
AP5 GPP_B20/GSPI1_CLK GPP_D6/ISH_I2C0_SCL YOGA series 0
<32> SENSOR_EC_INT GSPI1_MOSI GPP_B21/GSPI1_MISO
AN5 N1 RC146 S_IMR@
GPP_B22/GSPI1_MOSI GPP_D7/ISH_I2C1_SDA N2
S series 1 10K_0402_5%
+3VS AB1 GPP_D8/ISH_I2C1_SCL
<33> TP_INT# GPP_C8/UART0_RXD
AB2 AD11
RPC8 SOC_GPIOC10 W4 GPP_C9/UART0_TXD GPP_F10/I2C5_SDA/ISH_I2C2_SDA AD12 +3VS
8 1 DGPU_PWR_EN AB3 GPP_C10/UART0_RTS# GPP_F11/I2C5_SCL/ISH_I2C2_SCL
DGPU_HOLD_RST# <30> WLBT_OFF# GPP_C11/UART0_CTS# MB_ID
7 2 RC146 1 S_AL@ 2 10K_0402_5%
6 3 <30> UART0_RX
AD1 U1
5 4 WLBT_OFF# AD2 GPP_C20/UART2_RXD GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA U2 RC147 1 YOGA@ 2 10K_0402_5%
<30> UART0_TX AD3 GPP_C21/UART2_TXD GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL U3
10K_0804_8P4R_5% AD4 GPP_C22/UART2_RTS# GPP_D15/ISH_UART0_RTS# U4
GPP_C23/UART2_CTS# GPP_D16/ISH_UART0_CTS#/SML0BALERT#
AC1 DGPU_PWR_EN
GPP_C12/UART1_RXD/ISH_UART1_RXD DGPU_HOLD_RST# DGPU_PWR_EN <24,32>
U7 AC2
<33> I2C0_SDA_TP U6 GPP_C16/I2C0_SDA GPP_C13/UART1_TXD/ISH_UART1_TXD AC3 GPU_ALL_PGOOD DGPU_HOLD_RST# <19>
Touch PAD <33> I2C0_SCL_TP GPP_C17/I2C0_SCL GPP_C14/UART1_RTS#/ISH_UART1_RTS# DGPU_PRSNT GPU_ALL_PGOOD <24>
AB4
U8 GPP_C15/UART1_CTS#/ISH_UART1_CTS#
<26> I2C1_SDA_TS GPP_C18/I2C1_SDA
Touch Panel U9 AY8 MB_ID
<26> I2C1_SCL_TS GPP_C19/I2C1_SCL GPP_A18/ISH_GP0 BA8
AH9 GPP_A19/ISH_GP1 BB7 DGPU_SEL
<32> I2C2_SDA_SEN GPP_F4/I2C2_SDA GPP_A20/ISH_GP2 Funct i on DGPU_SEL
EC Sensor AH10 BA7 RC210 N16S_R3@
<32> I2C2_SCL_SEN GPP_F5/I2C2_SCL GPP_A21/ISH_GP3 AY7 10K_0402_5%
B AH11 GPP_A22/ISH_GP4 AW7 B
AH12 GPP_F6/I2C3_SDA GPP_A23/ISH_GP5 AP13 TP_PRSNT
N16V-GRM1(920) 0
GPP_F7/I2C3_SCL Sx_EXIT_HOLDOFF# / GPP_A12 / BM_BUSY# / ISH_GP6 RC209 N16V_R3@
AF11
N16S-GTR-S(940) 1 10K_0402_5%
+3VS AF12 GPP_F8/I2C4_SDA
RPC11 GPP_F9/I2C4_SCL 6 OF 20
8 1 I2C1_SCL_TS +3VS
7 2 I2C1_SDA_TS SKL-U_BGA1356 @ N16S_R1@
6 3 I2C0_SCL_TP RC210 1 2 10K_0402_5% DGPU_SEL
5 4 I2C0_SDA_TP
N16V_R1@
2.2K_0804_8P4R_5% RC209 1 2 10K_0402_5%

SOC_GPIOC10 RC204 1 2 0_0402_5% GPU_EVENT#


GPU_EVENT# <22>
+3VS
TO DGPU
SOC_GPIOB17 RC195 1 2 0_0402_5% GC6_FB_EN RC212 1 @ 2 10K_0402_5% TP_PRSNT
GC6_FB_EN <22,23>

A RC211 1 @ 2 10K_0402_5% A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2017/06/05 Deciphered Date 2018/06/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(6/12)GPIO,I2C,GSPI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 2.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E541P
Date: Wednesday, June 21, 2017 Sheet 11 of 51
5 4 3 2 1
5 4 3 2 1

D D

UC1H @ SKL-U
Rev_1.0

SSIC / USB3
PCIE / USB3 / SATA
H8 USB3_RX1_N <34>
USB3_1_RXN G8 USB3_RX1_P <34>
<19> PCIE_PRX_DTX_N1 H13 USB3_1_RXP C13 USB3 Type-C (MUX)
PCIE1_RXN/USB3_5_RXN USB3_1_TXN USB3_TX1_N <34>
<19> PCIE_PRX_DTX_P1 G13 D13
PCIE_PTX_DRX_N1 PCIE1_RXP/USB3_5_RXP USB3_1_TXP USB3_TX1_P <34>
CC11 DIS@ 1 2 0.22U_0402_6.3V6K B17
<19> PCIE_PTX_C_DRX_N1 PCIE_PTX_DRX_P1 PCIE1_TXN/USB3_5_TXN
<19> PCIE_PTX_C_DRX_P1 CC14 DIS@ 1 2 0.22U_0402_6.3V6K A17 J6 USB3_RX2_N <35>
PCIE1_TXP/USB3_5_TXP USB3_2_RXN / SSIC_RXN H6
USB3_2_RXP / SSIC_RXP USB3_RX2_P <35>
G11 B13 USB2/3 Port (MB)
<19> PCIE_PRX_DTX_N2 PCIE2_RXN/USB3_6_RXN USB3_2_TXN / SSIC_TXN USB3_TX2_N <35>
F11 A13
<19> PCIE_PRX_DTX_P2 PCIE_PTX_DRX_N2 PCIE2_RXP/USB3_6_RXP USB3_2_TXP / SSIC_TXP USB3_TX2_P <35>
CC15 DIS@ 1 2 0.22U_0402_6.3V6K D16
<19> PCIE_PTX_C_DRX_N2 CC16 DIS@ 1 2 0.22U_0402_6.3V6K PCIE_PTX_DRX_P2 C16 PCIE2_TXN/USB3_6_TXN J10
<19> PCIE_PTX_C_DRX_P2 PCIE2_TXP/USB3_6_TXP USB3_3_RXN USB3_RX3_N <35>
dGPU H10 USB3_RX3_P <35>
H16 USB3_3_RXP B15
<19> PCIE_PRX_DTX_N3
G16 PCIE3_RXN USB3_3_TXN A15 USB3_TX3_N <35> USB2/3 Port (IO/B)
<19> PCIE_PRX_DTX_P3 PCIE_PTX_DRX_N3 PCIE3_RXP USB3_3_TXP USB3_TX3_P <35>
CC12 DIS@ 1 2 0.22U_0402_6.3V6K D17
<19> PCIE_PTX_C_DRX_N3 PCIE_PTX_DRX_P3 PCIE3_TXN
CC13 DIS@ 1 2 0.22U_0402_6.3V6K C17 E10
<19> PCIE_PTX_C_DRX_P3 PCIE3_TXP USB3_4_RXN F10
G15 USB3_4_RXP C15
<19> PCIE_PRX_DTX_N4 F15 PCIE4_RXN USB3_4_TXN D15
<19> PCIE_PRX_DTX_P4 CC17 DIS@ 1 2 0.22U_0402_6.3V6K PCIE_PTX_DRX_N4 B19 PCIE4_RXP USB3_4_TXP
<19> PCIE_PTX_C_DRX_N4 PCIE_PTX_DRX_P4 PCIE4_TXN USB20_N1
CC18 DIS@ 1 2 0.22U_0402_6.3V6K A19 AB9
<19> PCIE_PTX_C_DRX_P4 PCIE4_TXP USB2N_1 USB20_P1 USB20_N1 <34>
AB10 USB3 Type-C Port
USB2P_1 USB20_P1 <34>
F16
<35> PCIE_PRX_DTX_N5 E16 PCIE5_RXN AD6 USB20_N2
<35> PCIE_PRX_DTX_P5 PCIE5_RXP USB2N_2 USB20_N2 <35>
Card Reader CC19 1 2 0.1U_0201_10V K X5R PCIE_PTX_DRX_N5 C19 AD7 USB20_P2
USB2/3 Port (MB)
C <35> PCIE_PTX_C_DRX_N5 1 2 0.1U_0201_10V K X5R PCIE_PTX_DRX_P5 PCIE5_TXN USB2P_2 USB20_P2 <35> C
CC20 D19
<35> PCIE_PTX_C_DRX_P5 PCIE5_TXP AH3 USB20_N3
USB2N_3 USB20_P3 USB20_N3 <35>
G18 AJ3 USB2/3 Port (IO/B)
<30> PCIE_PRX_DTX_N6 PCIE6_RXN USB2P_3 USB20_P3 <35>
F18
<30> PCIE_PRX_DTX_P6 PCIE_PTX_DRX_N6 PCIE6_RXP
NGFF WLAN+BT CC102 1 2 0.1U_0201_10V K X5R D20 AD9
<30> PCIE_PTX_C_DRX_N6 1 2 0.1U_0201_10V K X5R PCIE_PTX_DRX_P6 PCIE6_TXN USB2N_4
CC103 C20 AD10
<30> PCIE_PTX_C_DRX_P6 PCIE6_TXP USB2P_4
F20 AJ1 USB20_N5
<29> SATA_PRX_DTX_N0 E20 PCIE7_RXN/SATA0_RXN USB2N_5 AJ2 USB20_P5 USB20_N5 <26>
<29> SATA_PRX_DTX_P0 B21 PCIE7_RXP/SATA0_RXP USB2P_5 USB20_P5 <26> Camera
HDD <29> SATA_PTX_DRX_N0 PCIE7_TXN/SATA0_TXN
USB2
USB20_N6
A21 AF6
<29> SATA_PTX_DRX_P0 PCIE7_TXP/SATA0_TXP USB2N_6 USB20_P6 USB20_N6 <29>
AF7 Finger Printer
G21 USB2P_6 USB20_P6 <29>
F21 PCIE8_RXN/SATA1A_RXN AH1 USB20_N7
PCIE8_RXP/SATA1A_RXP USB2N_7 USB20_P7 USB20_N7 <30>
D21 AH2 NGFF WLAN+BT
PCIE8_TXN/SATA1A_TXN USB2P_7 USB20_P7 <30>
C21
PCIE8_TXP/SATA1A_TXP AF8
E22 USB2N_8 AF9
<31> PCIE_PRX_DTX_N9 PCIE9_RXN USB2P_8
<31> PCIE_PRX_DTX_P9 E23
CC110 SSD@ 1 2 0.22U_0402_6.3V6K PCIE_PTX_DRX_N9 B23 PCIE9_RXP AG1
<31> PCIE_PTX_C_DRX_N9 PCIE_PTX_DRX_P9 PCIE9_TXN USB2N_9
<31> PCIE_PTX_C_DRX_P9 CC109 SSD@ 1 2 0.22U_0402_6.3V6K A23 AG2
PCIE9_TXP USB2P_9
F25 AH7
<31> PCIE_PRX_DTX_N10 E25 PCIE10_RXN USB2N_10 AH8 +3VALW
<31> PCIE_PRX_DTX_P10 PCIE_PTX_DRX_N10 PCIE10_RXP USB2P_10
CC114 SSD@ 1 2 0.22U_0402_6.3V6K D23
<31> PCIE_PTX_C_DRX_N10 PCIE_PTX_DRX_P10 PCIE10_TXN USB2_COMP RPC9
CC113 SSD@ 1 2 0.22U_0402_6.3V6K C23 AB6 RC70 1 2 113_0402_1%
<31> PCIE_PTX_C_DRX_P10 PCIE10_TXP USB2_COMP AG3 RC104 1 2 1K_0402_5% USB_OC1# 8 1
RC71 1 2 100_0402_1% PCIE_RCOMPN F5 USB2_ID AG4 RC105 1 2 1K_0402_5% USB_OC3# 7 2
PCIE_RCOMPP E5 PCIE_RCOMPN USB2_VBUSSENSE USB_OC0# 6 3
PCIE_RCOMPP A9 USB_OC2# 5 4
SSD XDP_PRDY# GPP_E9/USB2_OC0# USB_OC0# <34>
T147 TP@ D56 C9 USB_OC1# <35>
XDP_PREQ# D61 PROC_PRDY# GPP_E10/USB2_OC1# D9 10K_0804_8P4R_5%
T148 TP@ PROC_PREQ# GPP_E11/USB2_OC2# USB_OC3# USB_OC2# <35>
BB11 B9
GPP_A7/PIRQA# GPP_E12/USB2_OC3#
E28 J1
B
<31> PCIE_PRX_DTX_N11 E27 PCIE11_RXN/SATA1B_RXN GPP_E4/DEVSLP0 J2 B
<31> PCIE_PRX_DTX_P11 PCIE_PTX_DRX_N11 PCIE11_RXP/SATA1B_RXP GPP_E5/DEVSLP1 WL_OFF# <30>
CC116 SSD@ 1 2 0.22U_0402_6.3V6K D24 J3
<31> PCIE_PTX_C_DRX_N11 PCIE_PTX_DRX_P11 PCIE11_TXN/SATA1B_TXN GPP_E6/DEVSLP2
CC115 SSD@ 1 2 0.22U_0402_6.3V6K C24
<31> PCIE_PTX_C_DRX_P11 E30 PCIE11_TXP/SATA1B_TXP H2 +3VS
<31> PCIE_PRX_DTX_N12 F30 PCIE12_RXN/SATA2_RXN GPP_E0/SATAXPCIE0/SATAGP0 H3
<31> PCIE_PRX_DTX_P12 CC112 SSD@ 1 2 0.22U_0402_6.3V6K PCIE_PTX_DRX_N12 A25 PCIE12_RXP/SATA2_RXP GPP_E1/SATAXPCIE1/SATAGP1 G4
<31> PCIE_PTX_C_DRX_N12 PCIE_PTX_DRX_P12 PCIE12_TXN/SATA2_TXN GPP_E2/SATAXPCIE2/SATAGP2
CC111 SSD@ 1 2 0.22U_0402_6.3V6K B25
<31> PCIE_PTX_C_DRX_P12 PCIE12_TXP/SATA2_TXP H1 WL_OFF# RC139 1 @ 2 10K_0402_5%
8 OF 20 GPP_E8/SATALED#

SKL-U_BGA1356

When PCIE8/SATA1A is used as SATA Port 1 (ODD), then


PCIE11/SATA1B (M.2 SSD) cannot be used as SATA Port 1.

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2017/06/05 Deciphered Date 2018/06/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(7/12)PCIE,USB,SATA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 2.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E541P
Date: Wednesday, June 21, 2017 Sheet 12 of 51
5 4 3 2 1
5 4 3 2 1

+1.2V +1.0VS_VCCIO
UC1N @ SKL-U
Rev_1.0
+VL +1.0VALW CPU POWER 3 OF 4
AU23 AK28
+1.0V_VCCST AU28 VDDQ_AU23 VCCIO AK30
AU35 VDDQ_AU28 VCCIO AL30
D VDDQ_AU35 VCCIO D

1U_0402_6.3V6K

1U_0402_6.3V6K
I(Max) : 0.16 A(+1.0V_VCCST) AU42 AL42
+1.0VALW TO +1.0V_VCCST 1 1 VDDQ_AU42 VCCIO

CC21

CC22

0.1U_0201_10V K X5R
RON(Max) : 25 mohm BB23 AM28
+1.0V_VCCST_R 2 1 BB32 VDDQ_BB23 VCCIO AM30
@
V drop : 0.004 V RC136 0_0402_5% BB41 VDDQ_BB32 VCCIO AM42 +VCCSA
2 2 +1.0VS_VCCIO BB47 VDDQ_BB41 VCCIO
1 VDDQ_BB47

CC23
BB51 AK23
VDDQ_BB51 VCCSA AK25
UC5 VCCSA G23
1 14 2 +1.0V_VCCST AM40 VCCSA G25
2 VIN1 VOUT1 13 VDDQC VCCSA G27
VIN1 VOUT1 A18 VCCSA G28
RC74 2 1 0_0402_5% EN_1.0V_VCCSTU 3 12 1 2 VCCST VCCSA J22
<32,42> SYSON ON1 CT1 A22 VCCSA J23
CC24 Follow 543977_SKL_PDDG_Rev0_91 VCCSTG_A22 VCCSA
4 11 8200P_0402_25V7K CC24 10PF ->22us(Spec:<= 65us) J27
VBIAS GND AL23 VCCSA K23
RC75 2 1 0_0402_5% EN_1.8VS 5 10 1 2 VCCPLL_OC VCCSA K25
<32,37,42> SUSP# ON2 CT2 CC25 K20 VCCSA K27
6 9 1000P_0402_50V7K K21 VCCPLL_K20 VCCSA K28
+1.8VALW 7 VIN2 VOUT2 8 +1.8VS VCCPLL_K21 VCCSA K30
VIN2 VOUT2 VCCSA
15 AM23
GPAD +1.8VS_R VCCIO_SENSE

0.1U_0201_10V K X5R
2 1 AM22
EM5209VF DFN 14P DUAL LOAD SW RC137 0_0402_5% VSSIO_SENSE
+1.8VALW TO +1.8VS VSSSA_SENSE

1U_0402_6.3V6K
1 H21
VSSSA_SENSE VCCSA_SENSE VSSSA_SENSE <46>

CC26
1 H20
VCCSA_SENSE VCCSA_SENSE <46>

CC27
14 OF 20
@
2 SKL-U_BGA1356 Trace Length Match < 25 mils
I(Max) : 0.2 A(+1.8VS) 2
RON(Max) : 25 mohm
V drop : 0.005 V

C C

+1.0VALW TO +1.0VS_VCCIO
+VL +1.0VALW
+1.0V_VCCST +1.0VS_VCCIO
I(Max) : 3.04 A(+1.0VS_VCCIO)
RON(Max) : 6.2 mohm PSC Side BSC Side
0.1U_0201_10V K X5R

1U_0402_6.3V6K

V drop : 0.019 V
1 1
CC30

CC32

@ UC6
2 2 +1.0VS_VCCIO

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1
2 VIN1
VIN2

CC28

CC34

CC35
7 6 +1.0VS_VCCIO_STG RC79 1 2 0_0805_5% @
VIN thermal VOUT 2 2 2
1
3
VBIAS CC33
SUSP# RC81 2 1 0_0402_5% 4 5 @ 0.1U_0201_10V K X5R
ON GND 2
B B
AOZ1334DI-01_DFN 8P Close to A18 Close to K20 Close to A22

+1.0VS_VCCIO +1.2V

BSC Side PSC Side BSC Side PSC Side BSC Side
10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

22U_0603_6.3V6M

22U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CC36

CC37

CC38

CC39

CC40

CC41

CC42

CC29

CC43

CC44

CC45

CC46

CC47

CC48

CC49

CC50
@ @ @ @ @ @
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

Underneath CPU Close to CPU Close to AL23 Close to AM40 Close to CPU Underneath CPU
A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2017/06/05 Deciphered Date 2018/06/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(8/12)Power
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 2.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E541P
Date: Wednesday, June 21, 2017 Sheet 13 of 51
5 4 3 2 1
5 4 3 2 1

D D
+1.0VALW +1.8VALW
UC1O SKL-U
Rev_1.0 +3VALW
CPU POWER 4 OF 4

Follow 543016_SKL_U_Y_PDG_1_0 CC51 1 2 1U_0402_6.3V6K AB19


AB20 VCCPRIM_1P0 AK15
+1.0VALW +1.0V_APLL P18 VCCPRIM_1P0 VCCPGPPA AG15
@
VCCPRIM_1P0 VCCPGPPB Y16
LC1 CC54 1 2 1U_0402_6.3V6K AF18 VCCPGPPC Y15
MURATA BLM15EG221SN1D AF19 VCCPRIM_CORE VCCPGPPD T16
1 2
Imax : 2.57A V20 VCCPRIM_CORE VCCPGPPE AF16
@
VCCPRIM_CORE VCCPGPPF
VCCPGPPF support 1.8V only

0.1U_0201_10V K X5R
SM01000HC00 RF@ V21 AD15
VCCPRIM_CORE VCCPGPPG
R_0402 2

CC31
RF@
CC55 1 2 1U_0402_6.3V6K DCPDSW AL1 V19
DCPDSW_1P0 VCCPRIM_3P3_V19
CC56 1 2 1U_0402_6.3V6K K17 T1 +1.0VALW
1 L1 VCCMPHYAON_1P0 VCCPRIM_1P0_T1
Close to K17 VCCMPHYAON_1P0 AA1 CC57 1 2 1U_0402_6.3V6K
CC60 1 2 22U_0603_6.3V6M N15 VCCATS_1P8
N16 VCCMPHYGT_1P0_N15 AK17
@
Imax : 1.54A N17 VCCMPHYGT_1P0_N16 VCCRTCPRIM_3P3
CC61 1 2 1U_0402_6.3V6K P15 VCCMPHYGT_1P0_N17 AK19
Follow 543016_SKL_U_Y_PDG_1_0 VCCMPHYGT_1P0_P15 VCCRTC_AK19 +3VL_RTC
Close to P15 P16 BB14
+1.0V_AMPHYPLL VCCMPHYGT_1P0_P16 VCCRTC_BB14
+1.0V_AMPHYPLL K15 BB10 DCPRTC CC62 1 2 0.1U_0201_10V K X5R
L15 VCCAMPHYPLL_1P0 DCPRTC
VCCAMPHYPLL_1P0 A14
VCCCLK1 +1.0V_CLK6_24TBT
RC148 1 2 0_0603_5%
+1.0V_APLL
V15
VCCAPLL_1P0
22U_0603_6.3V6M

1U_0402_6.3V6K

K19
AB17 VCCCLK2
1 1 VCCPRIM_1P0_AB17
CC58

CC59

Y18 L21 +1.0V_APLL


VCCPRIM_1P0_Y18 VCCCLK3
@ @ AD17 N20
2 2 +3VALW VCCDSW_3P3_AD17 VCCCLK4 +1.0V_CLK4_F100OC
AD18
AJ17 VCCDSW_3P3_AD18 L19
C VCCDSW_3P3_AJ17 VCCCLK5 +1.0V_CLK5_F24NS C

+3V_1.8V_HDA AJ19 A10 +1.0V_CLK6_24TBT


VCCHDA VCCCLK6
AJ16 AN11
VCCSPI GPP_B0/CORE_VID0 AN13
+1.0V_CLK5_F24NS 1 2 AF20 GPP_B1/CORE_VID1
AF21 VCCSRAM_1P0
Follow 543016_SKL_U_Y_PDG_1_0 CC65 1U_0402_6.3V6K
VCCSRAM_1P0
@ Close to AF20 T19
RC85 1 2 0_0603_5% +3VALW +3V_1.8V_HDA T20 VCCSRAM_1P0
LC2 VCCSRAM_1P0
22U_0603_6.3V6M

22U_0603_6.3V6M

MURATA BLM15EG221SN1D 1 2 AJ21


1 2 CC67 1U_0402_6.3V6K VCCPRIM_3P3_AJ21
1 1
CC63

CC64

0.1U_0201_10V K X5R
SM01000HC00 RF@ @ Close to AJ21 AK20
VCCPRIM_1P0_AK20
R_0402
@ @ 1 1 2 N18
2 2 VCCAPLLEBB_1P0

CC66
CC68 1U_0402_6.3V6K 15 OF 20
Close to N18
RF@

SKL-U_BGA1356
2 @

+1.0V_CLK4_F100OC
Follow 543016_SKL_U_Y_PDG_1_0
RC87 1 2 0_0603_5%
22U_0603_6.3V6M

22U_0603_6.3V6M

1 1
CC69

CC70

@ @
2 2

B B

+1.0V_CLK6_24TBT RTC Battery


Follow 543016_SKL_U_Y_PDG_1_0
+3VL_RTC +RTCBATT
RC91 1 2 0_0603_5% +3VS +1.8VS_3VS_PGPPA
+1.0VALW +3VALW +1.8VALW +3VALW W=20mils
1U_0402_6.3V6K

1U_0402_6.3V6K

22U_0603_6.3V6M

22U_0603_6.3V6M

LPC 3.3V
1 1 1 1 RC90 1 2 0_0402_5%
CC83

CC84

CC85

CC86

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
1 2
RC93 0_0402_5%
1 1 1 1 1 1 1
CC71

CC72

CC73

CC74

CC75

CC76

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0201_10V K X5R
@ @ @ @ 1 1 1 1 1 CC82
2 2 2 2 1U_0402_6.3V6K

CC80

CC77

CC78

CC81

CC79
@ @ @ @ @ @ @ @ @
2 2 2 2 2 2 2
2 2 2 2 2

Safty suggestion remove EE side, Keep PWR side


Close to AG15 Close to Y16 Close to T16 Close to AK17

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2017/06/05 Deciphered Date 2018/06/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(9/12)Power
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 2.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E541P
Date: Wednesday, June 21, 2017 Sheet 14 of 51
5 4 3 2 1
5 4 3 2 1

U22/U42 co-lay

+VCCGT_VCCCORE +VCCCORE

R418 U42@
1 2
1 2
SOLDER_PREFORMS_0603

R414 U42@
1 2
1 2
D
SOLDER_PREFORMS_0603 +VCCGT D

R419 U22@
1 2
1 2
SOLDER_PREFORMS_0603

+VCCGT +VCCGT
UC1M SKL-U
Rev_1.0
+VCCGT_VCCCORE CPU POWER 2 OF 4
N70
A48 VCCGT N71
A53 VCCGT VCCGT R63
+VCCCORE +VCCCORE A58 VCCGT VCCGT R64
A62 VCCGT VCCGT R65
UC1L SKL-U A66 VCCGT VCCGT R66
Rev_1.0 AA63 VCCGT VCCGT R67
CPU POWER 1 OF 4 VCCGT VCCGT
AA64 R68
A30 G32 AA66 VCCGT VCCGT R69
A34 VCC_A30 VCC_G32 G33 AA67 VCCGT VCCGT R70
A39 VCC_A34 VCC_G33 G35 AA69 VCCGT VCCGT R71
A44 VCC_A39 VCC_G35 G37 AA70 VCCGT VCCGT T62
AK33 VCC_A44 VCC_G37 G38 AA71 VCCGT VCCGT U65
AK35 VCC_AK33 VCC_G38 G40 AC64 VCCGT VCCGT U68
AK37 VCC_AK35 VCC_G40 G42 AC65 VCCGT VCCGT U71
AK38 VCC_AK37 VCC_G42 J30 AC66 VCCGT VCCGT W63
AK40 VCC_AK38 VCC_J30 J33 AC67 VCCGT VCCGT W64
AL33 VCC_AK40 VCC_J33 J37 AC68 VCCGT VCCGT W65
AL37 VCC_AL33 VCC_J37 J40 AC69 VCCGT VCCGT W66
AL40 VCC_AL37 VCC_J40 K33 AC70 VCCGT VCCGT W67
AM32 VCC_AL40 VCC_K33 K35 AC71 VCCGT VCCGT W68
AM33 VCC_AM32 VCC_K35 K37 J43 VCCGT VCCGT W69
C AM35 VCC_AM33 VCC_K37 K38 J45 VCCGT VCCGT W70 C
AM37 VCC_AM35 VCC_K38 K40 J46 VCCGT VCCGT W71
AM38 VCC_AM37 VCC_K40 K42 J48 VCCGT VCCGT Y62 +VCCGT_VCCCORE
G30 VCC_AM38 VCC_K42 K43 J50 VCCGT VCCGT
VCC_G30 VCC_K43
Trace Length Match < 25 mils VCCGT
J52
K32 E32 J53 VCCGT AK42
RSVD VCC_SENSE VCCCORE_SENSE <46> VCCGT VCCGTX_AK42
E33 J55 AK43
VSS_SENSE VSSCORE_SENSE <46> VCCGT VCCGTX_AK43
AK32 J56 AK45
RSVD B63 SOC_SVID_ALERT# J58 VCCGT VCCGTX_AK45 AK46 +VCCGT
AB62 VIDALERT# A63 VR_SVID_CLK J60 VCCGT VCCGTX_AK46 AK48
P62 VCCOPC_AB62 VIDSCK D64 VR_SVID_DATA VR_SVID_CLK <46> K48 VCCGT VCCGTX_AK48 AK50
V62 VCCOPC_P62 VIDSOUT K50 VCCGT VCCGTX_AK50 AK52 R417 1 U22@ 2 0_0402_5%
VCCOPC_V62 G20 R416 1 U22@ 2 0_0603_5% +VCCGT_K52 K52 VCCGT VCCGTX_AK52 AK53
VCCSTG_G20
ALERT signal must be routed between CLK and DATA signals VCCGT VCCGTX_AK53
H63 K53 AK55
VCC_OPC_1P8_H63 +1.0VS_VCCIO K55 VCCGT VCCGTX_AK55 AK56
G61 K56 VCCGT VCCGTX_AK56 AK58
VCC_OPC_1P8_G61 K58 VCCGT VCCGTX_AK58 AK60
VCCOPC_SENSE AC63 K60 VCCGT VCCGTX_AK60 AK70
T157 TP@ VSSOPC_SENSE VCCOPC_SENSE VCCGT VCCGTX_AK70
AE63 L62 AL43
T158 TP@ VSSOPC_SENSE VCCGT VCCGTX_AL43
L63 AL46
AE62 L64 VCCGT VCCGTX_AL46 AL50
AG62 VCCEOPIO L65 VCCGT VCCGTX_AL50 AL53
VCCEOPIO L66 VCCGT VCCGTX_AL53 AL56
AL63 L67 VCCGT VCCGTX_AL56 AL60
AJ62 VCCEOPIO_SENSE L68 VCCGT VCCGTX_AL60 AM48
VSSEOPIO_SENSE 12 OF 20 L69 VCCGT VCCGTX_AM48 AM50
L70 VCCGT VCCGTX_AM50 AM52
SKL-U_BGA1356 L71 VCCGT VCCGTX_AM52 AM53
@ M62 VCCGT VCCGTX_AM53 AM56
N63 VCCGT VCCGTX_AM56 AM58
N64 VCCGT VCCGTX_AM58 AU58
N66 VCCGT VCCGTX_AU58 AU63
N67 VCCGT VCCGTX_AU63 BB57
N69 VCCGT VCCGTX_BB57 BB66
VCCGT VCCGTX_BB66
B VCCGT_SENSE J70 AK62 VCCGTX_SENSE B
<46> VCCGT_SENSE VSSGT_SENSE VCCGT_SENSE VCCGTX_SENSE VSSGTX_SENSE T161 TP@
J69 AL61 T162 TP@
<46> VSSGT_SENSE VSSGT_SENSE VSSGTX_SENSE
13 OF 20

Trace Length Match < 25 mils SKL-U_BGA1356


@
SVID ALERT
+1.0V_VCCST
Place the PU
resistors close to CPU
1

RC94
56_0402_5%
2

SOC_SVID_ALERT# 1 2 (To VR)


VR_ALERT# <46>
RC95 220_0402_5%

+1.0V_VCCST

SVID DATA Place the PU


resistors close to CPU
1

RC96
100_0402_1%

A A
2

VR_SVID_DATA
VR_SVID_DATA <46> (To VR)

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2017/06/05 Deciphered Date 2018/06/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(10/12)Power,SVID
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 2.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E541P
Date: Wednesday, June 21, 2017 Sheet 15 of 51
5 4 3 2 1
5 4 3 2 1

D D

UC1Q SKL-U
UC1P SKL-U Rev_1.0 UC1R SKL-U
Rev_1.0 GND 2 OF 3 Rev_1.0
GND 1 OF 3 GND 3 OF 3
AT63 BA49 F8 L18
A5 AL65 AT68 VSS VSS BA53 G10 VSS VSS L2
A67 VSS VSS AL66 AT71 VSS VSS BA57 G22 VSS VSS L20
A70 VSS VSS AM13 AU10 VSS VSS BA6 G43 VSS VSS L4
AA2 VSS VSS AM21 AU15 VSS VSS BA62 G45 VSS VSS L8
AA4 VSS VSS AM25 AU20 VSS VSS BA66 G48 VSS VSS N10
AA65 VSS VSS AM27 AU32 VSS VSS BA71 G5 VSS VSS N13
AA68 VSS VSS AM43 AU38 VSS VSS BB18 G52 VSS VSS N19
AB15 VSS VSS AM45 AV1 VSS VSS BB26 G55 VSS VSS N21
AB16 VSS VSS AM46 AV68 VSS VSS BB30 G58 VSS VSS N6
AB18 VSS VSS AM55 AV69 VSS VSS BB34 G6 VSS VSS N65
AB21 VSS VSS AM60 AV70 VSS VSS BB38 G60 VSS VSS N68
AB8 VSS VSS AM61 AV71 VSS VSS BB43 G63 VSS VSS P17
AD13 VSS VSS AM68 AW10 VSS VSS BB55 G66 VSS VSS P19
AD16 VSS VSS AM71 AW12 VSS VSS BB6 H15 VSS VSS P20
AD19 VSS VSS AM8 AW14 VSS VSS BB60 H18 VSS VSS P21
AD20 VSS VSS AN20 AW16 VSS VSS BB64 H71 VSS VSS R13
AD21 VSS VSS AN23 AW18 VSS VSS BB67 J11 VSS VSS R6
AD62 VSS VSS AN28 AW21 VSS VSS BB70 J13 VSS VSS T15
AD8 VSS VSS AN30 AW23 VSS VSS C1 J25 VSS VSS T17
AE64 VSS VSS AN32 AW26 VSS VSS C25 J28 VSS VSS T18
AE65 VSS VSS AN33 AW28 VSS VSS C5 J32 VSS VSS T2
AE66 VSS VSS AN35 AW30 VSS VSS D10 J35 VSS VSS T21
AE67 VSS VSS AN37 AW32 VSS VSS D11 J38 VSS VSS T4
C AE68 VSS VSS AN38 AW34 VSS VSS D14 J42 VSS VSS U10 C
AE69 VSS VSS AN40 AW36 VSS VSS D18 J8 VSS VSS U63
AF1 VSS VSS AN42 AW38 VSS VSS D22 K16 VSS VSS U64
AF10 VSS VSS AN58 AW41 VSS VSS D25 K18 VSS VSS U66
AF15 VSS VSS AN63 AW43 VSS VSS D26 K22 VSS VSS U67
AF17 VSS VSS AP10 AW45 VSS VSS D30 K61 VSS VSS U69
AF2 VSS VSS AP18 AW47 VSS VSS D34 K63 VSS VSS U70
AF4 VSS VSS AP20 AW49 VSS VSS D39 K64 VSS VSS V16
AF63 VSS VSS AP23 AW51 VSS VSS D44 K65 VSS VSS V17
AG16 VSS VSS AP28 AW53 VSS VSS D45 K66 VSS VSS V18
AG17 VSS VSS AP32 AW55 VSS VSS D47 K67 VSS VSS W13
AG18 VSS VSS AP35 AW57 VSS VSS D48 K68 VSS VSS W6
AG19 VSS VSS AP38 AW6 VSS VSS D53 K70 VSS VSS W9
AG20 VSS VSS AP42 AW60 VSS VSS D58 K71 VSS VSS Y17
AG21 VSS VSS AP58 AW62 VSS VSS D6 L11 VSS VSS Y19
AG71 VSS VSS AP63 AW64 VSS VSS D62 L16 VSS VSS Y20
AH13 VSS VSS AP68 AW66 VSS VSS D66 L17 VSS VSS Y21
AH6 VSS VSS AP70 AW8 VSS VSS D69 VSS VSS
AH63 VSS VSS AR11 AY66 VSS VSS E11
AH64 VSS VSS AR15 B10 VSS VSS E15 18 OF 20
AH67 VSS VSS AR16 B14 VSS VSS E18
AJ15 VSS VSS AR20 B18 VSS VSS E21 SKL-U_BGA1356
AJ18 VSS VSS AR23 B22 VSS VSS E46 @
AJ20 VSS VSS AR28 B30 VSS VSS E50
AJ4 VSS VSS AR35 B34 VSS VSS E53
AK11 VSS VSS AR42 B39 VSS VSS E56
AK16 VSS VSS AR43 B44 VSS VSS E6
AK18 VSS VSS AR45 B48 VSS VSS E65
AK21 VSS VSS AR46 B53 VSS VSS E71
AK22 VSS VSS AR48 B58 VSS VSS F1
AK27 VSS VSS AR5 B62 VSS VSS F13
AK63 VSS VSS AR50 B66 VSS VSS F2
AK68 VSS VSS AR52 B71 VSS VSS F22
AK69 VSS VSS AR53 BA1 VSS VSS F23
AK8 VSS VSS AR55 BA10 VSS VSS F27
B AL2 VSS VSS AR58 BA14 VSS VSS F28 B
AL28 VSS VSS AR63 BA18 VSS VSS F32
AL32 VSS VSS AR8 BA2 VSS VSS F33
AL35 VSS VSS AT2 BA23 VSS VSS F35
AL38 VSS VSS AT20 BA28 VSS VSS F37
AL4 VSS VSS AT23 BA32 VSS VSS F38
AL45 VSS VSS AT28 BA36 VSS VSS F4
AL48 VSS VSS AT35 F68 VSS VSS F40
AL52 VSS VSS AT4 BA45 VSS VSS F42
AL55 VSS VSS AT42 VSS VSS BA41
AL58 VSS VSS AT56 VSS
AL64 VSS VSS AT58
VSS VSS
17 OF 20
16 OF 20
SKL-U_BGA1356
SKL-U_BGA1356 @
@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2017/06/05 Deciphered Date 2018/06/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(11/12)GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 2.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E541P
Date: Wednesday, June 21, 2017 Sheet 16 of 51
5 4 3 2 1
5 4 3 2 1

D D

UC1S SKL-U
Rev_1.0
RESERVED SIGNALS-1

E68 BB68
B67 CFG[0] RSVD_TP_BB68 BB69
D65 CFG[1] RSVD_TP_BB69
D67 CFG[2] AK13
CFG4 E70 CFG[3] RSVD_TP_AK13 AK12
C68 CFG[4] RSVD_TP_AK12
D68 CFG[5] BB2
C67 CFG[6] RSVD_BB2 BA3
F71 CFG[7] RSVD_BA3
G69 CFG[8]
F70 CFG[9] AU5
CFG[10] TP5 U42_EMI@
G68 AT5 SOC_XTAL24_IN_U42 RC106 1 2 33_0402_1% XTAL24_IN_U42
H70 CFG[11] TP6
G71 CFG[12]
H69 CFG[13] D5
G70 CFG[14] RSVD_D5 D4
CFG[15] RSVD_D4 B2
RSVD_B2 U42_EMI@
E63 C2 SOC_XTAL24_OUT_U42 RC107 1 2 33_0402_1% XTAL24_OUT_U42
F63 CFG[16] RSVD_C2
CFG[17] U42@
B3 RC40 1 2 1M_0402_5%
E66 RSVD_B3 A3
F66 CFG[18] RSVD_A3
C CFG[19] AW1 C
CFG_RCOMP E60 RSVD_AW1
CFG_RCOMP E1
RSVD_E1 U42@
E8 E2 YC3
ITP_PMODE RSVD_E2
24MHZ_18PF_XRCGB24M000F2P51R0
AY2 BA4 UC1T SKL-U SJ10000UJ00
AY1 RSVD_AY2 RSVD_BA4 BB4 Rev_1.0
RSVD_AY1 RSVD_BB4 SPARE 1 3
D1 A4 1 3
D3 RSVD_D1 RSVD_A4 C4 NC NC
AW69 F6
RSVD_D3 RSVD_C4 RSVD_AW69 RSVD_F6 SOC_XTAL24_IN_U42
AW68 E3
K46 BB5 RSVD_AW68 RSVD_E3 2 4

27P_0402_50V8J

27P_0402_50V8J
AU56 C11
K45 RSVD_K46 TP4 RSVD_AU56 RSVD_C11
AW48 B11 2 2
RSVD_K45 A69 SOC_XTAL24_OUT_U42 RSVD_AW48 RSVD_B11

CC126

CC52
+1.8VALW C7 A11
AL25 RSVD_A69 B69 RSVD_C7 RSVD_A11
RC98 1 @ 2 0_0402_5% U12 D12 U42@ U42@
AL27 RSVD_AL25 RSVD_B69 RSVD_U12 RSVD_D12
1 @ 2 U11 C12
RSVD_AL27 AY3 1 2 0_0402_5% RSVD_U11 RSVD_C12 1 1

1U_0402_6.3V6K
RC97 @ H11 F52
RSVD_AY3 1 RSVD_H11 RSVD_F52
C71 RC102
B70 RSVD_C71 D71

CC98
RSVD_B70 RSVD_D71 0_0402_5% 20 OF 20
C70 @
F60 RSVD_C70 2
RSVD_F60 SKL-U_BGA1356
C54 @
A52 RSVD_C54 D54
RSVD_A52 RSVD_D54
BA70 AY4
BA68 RSVD_TP_BA70 TP1 BB3
RSVD_TP_BA68 TP2
J71 AY71 RC213 1 @ 2 0_0402_5%
J68 RSVD_J71 VSS_AY71 AR56
RSVD_J68 ZVM#
F65 AW71
G65 VSS_F65 RSVD_TP AW70 +1.0V_VCCST
VSS_G65 RSVD_TP
F61 AP56 PM_MSM# T185 TP@
E61 RSVD_F61 MSM# C64 SKL_CNL# 1 2
B RSVD_E61 PROC_SELECT# RC99 @ 100K_0402_5% B
19 OF 20

SKL-U_BGA1356
@ Follow 544669_SKL_U_DDR3L_RVP7_schematic_rev1.0

Stuff 100k(RC99) for CannonLake-U

Un-stuff 100k(RC99) for SkyLake-U

1 2 CFG_RCOMP
RC100 49.9_0402_1%

1 2 CFG4
RC101 1K_0402_5%

Display Port Presence Strap


A A
1 : Disabled;
No Physical Display Port attached to Embedded Display Port
CFG4
0 : Enabled;
An external Display Port device is connected to the Embedded Display Port

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2017/06/05 Deciphered Date 2018/06/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(12/12)CFG,RSVD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 2.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E541P
Date: Wednesday, June 21, 2017 Sheet 17 of 51
5 4 3 2 1
A B C D E

<7> DDR_A_DQS#[0..7]
Reverse Type
<7>
<7> DDR_A_D[0..63]

DDR_A_DQS[0..7]
Interleaved Memory 2-3A to 1 DIMMs/channel
+1.2V +1.2V
<7> DDR_A_MA[0..16]
JDIMM1
<7> DDR_A_BA0 +1.2V
1 2
<7> DDR_A_BA1 DDR_A_D4 VSS VSS DDR_A_D1
3 4
<7> DDR_A_BG0 DQ5 DQ4
5 6
<7> DDR_A_BG1 DDR_A_D5 VSS VSS DDR_A_D0
7 8
9 DQ1 DQ0 10
DDR_A_DQS#0 11 VSS VSS 12 +DIMM_VREF_DQ
DDR_A_DQS0 13 DQS0_C DM0*/DBI0* 14
DQS0_T VSS

1
15 16 DDR_A_D6
1 <7> DDR_A_CLK0 DDR_A_D7 VSS DQ6 +0.6V_VREFCA_R 1
17 18 RD21 1 2 0_0402_5% RD19
<7> DDR_A_CLK#0 DQ7 VSS DDR_A_D2 <7> +0.6V_VREFCA
19 20 1K_0402_1%
<7> DDR_A_CLK1
<7> DDR_A_CLK#1
DDR_A_D3 21 VSS DQ2 22 20mil RD10
23 DQ3 VSS 24 DDR_A_D9 2_0402_1%

2
DDR_A_D11 25 VSS DQ12 26 RD22 1 @ 2 0_0402_5% 1 2
DQ13 VSS DDR_A_D8 <7> +0.6V_A_VREFDQ
27 28
<7> DDR_A_CKE0 DDR_A_D12 VSS DQ8
29 30
<7> DDR_A_CKE1 DQ9 VSS DDR_A_DQS#1
31 32 1
33 VSS DQS1_C 34 DDR_A_DQS1
<7> DDR_A_CS#0 DM1*/DBI1* DQS1_T
35 36 CD21
<7> DDR_A_CS#1 DDR_A_D13 VSS VSS DDR_A_D14
37 38 0.022U_0402_16V7K
39 DQ15 DQ14 40 2
DDR_A_D15 41 VSS VSS 42 DDR_A_D10
DQ10 DQ11

1
43 44
DDR_A_D16 45 VSS VSS 46 DDR_A_D17 RD12 RD20
47 DQ21 DQ20 48 24.9_0402_1% 1K_0402_1%
DDR_A_D20 49 VSS VSS 50 DDR_A_D21
51 DQ17 DQ16 52

2
DDR_A_DQS#2 53 VSS VSS 54
DDR_A_DQS2 55 DQS2_C DM2*/DBI2* 56
<8> PCH_SMB_DATA DQS2_T VSS DDR_A_D23
57 58
<8> PCH_SMB_CLK DDR_A_D22 VSS DQ22
59 60
61 DQ23 VSS 62 DDR_A_D19
DDR_A_D18 63 VSS DQ18 64
<7> DDR_A_ODT0 DQ19 VSS DDR_A_D29
65 66
<7> DDR_A_ODT1 DDR_A_D24 VSS DQ28
67 68
69 DQ29 VSS 70 DDR_A_D25
DDR_A_D28 71 VSS DQ24 72
73 DQ25 VSS 74 DDR_A_DQS#3
75 VSS DQS3_C 76 DDR_A_DQS3
77 DM3*/DBI3* DQS3_T 78
DDR_A_D30 79 VSS VSS 80 DDR_A_D31
Note: DQ30 DQ31
Layout Note: 81 82
Check voltage tolerance of DDR_A_D26 83 VSS VSS 84 DDR_A_D27
Place near JDIMM1 VREF_DQ at the DIMM socket 85 DQ26 DQ27 86
87 VSS VSS 88
89 CB5_NC CB4_NC 90
91 VSS VSS 92
93 CB1_NC CB0_NC 94
95 VSS VSS 96
+1.2V 97 DQS8_C DM8*/DBI8* 98
99 DQS8_T VSS 100
2 VSS CB6_NC 2
101 102
103 CB2_NC VSS 104
VSS CB7_NC
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

105 106
107 CB3_NC VSS 108 DDR_DRAMRST#_R CD34 1 2 100P_0201_25V8J
1 1 1 1 1 1 1 1 DDR_A_CKE0 VSS RESET* DDR_A_CKE1
109 110
CKE0 CKE1
CD4

CD5

CD6

CD7

CD8

CD9

CD17

CD18

111 112 ESD@


@ @ @ @ DDR_A_BG1 113 VDD1 VDD2 114
2 2 2 2 2 2 2 2 DDR_A_BG0 BG1 ACT* M_A_ACT# <7>
115 116
BG0 ALERT* DDR_A_ALERT# <7>
117 118
DDR_A_MA12 119 VDD3 VDD4 120 DDR_A_MA11
DDR_A_MA9 121 A12 A11 122 DDR_A_MA7
123 A9 A7 124
DDR_A_MA8 125 VDD5 VDD6 126 DDR_A_MA5
4 as near side of the DIMM close to VDD pins DDR_A_MA6 A8 A5 DDR_A_MA4
127 128
129 A6 A4 130
+1.2V DDR_A_MA3 131 VDD7 VDD8 132 DDR_A_MA2
DDR_A_MA1 133 A3 A2 134
135 A1 EVENT* 136
DDR_A_CLK0 VDD9 VDD10 DDR_A_CLK1
10U_0603_6.3V6M

137 138
DDR_A_CLK#0 CK0_T CK1_T DDR_A_CLK#1
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

330U_D3_2.5VY_R6M

139 140
141 CK0_C CK1_C 142
1 VDD11 VDD12 DDR_A_MA0
1 1 1 1 1 1 1 1 143 144
<7> DDR_A_PARITY PARITY A0
CD10

CD11

CD12

CD13

CD14

CD19

CD15

CD20

CD35

@ @ @ DDR_DRAMRST#_R RD11 1 2 0_0402_5%


2 2 2 2 2 2 2 2 2 DDR_A_BA1 DDR_A_MA10 DDR_DRAMRST# <7>
145 146
147 BA1 A10_AP 148
DDR_A_CS#0 149 VDD13 VDD14 150 DDR_A_BA0
DDR_A_MA14 151 S0* BA0 152 DDR_A_MA16
153 A14_WE* A16_RAS* 154 +DIMM_VREF_DQ
DDR_A_ODT0 155 VDD15 VDD16 156 DDR_A_MA15
DDR_A_CS#1 157 ODT0 A15_CAS* 158 DDR_A_MA13
159 S1* A13 160
DDR_A_ODT1 161 VDD17 VDD18 162
163 ODT1 S2*/C0 164
165 VDD19 VREFCA 166
Place these caps on the VTT plane close to DIMM S3*/C1 SA2
167 168
DDR_A_D37 169 VSS VSS 170 DDR_A_D36
+0.6VS 171 DQ37 DQ36 172
DDR_A_D32 173 VSS VSS 174 DDR_A_D33
175 DQ33 DQ32 176
DDR_A_DQS#4 177 VSS VSS 178
3 3
DDR_A_DQS4 DQS4_C DM4*/DBI4*
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0603_6.3V6M

10U_0603_6.3V6M

179 180
181 DQS4_T VSS 182 DDR_A_D39
1 1 1 1 1 1 DDR_A_D38 VSS DQ39
CD30

CD31

CD32

CD33

CD22

CD23

183 184
185 DQ38 VSS 186 DDR_A_D35
DDR_A_D34 187 VSS DQ35 188
2 2 2 2 2 2 189 DQ34 VSS 190 DDR_A_D44
DDR_A_D41 191 VSS DQ45 192
193 DQ44 VSS 194 DDR_A_D45
DDR_A_D40 195 VSS DQ41 196
197 DQ40 VSS 198 DDR_A_DQS#5
199 VSS DQS5_C 200 DDR_A_DQS5
201 DM5*/DBI5* DQS5_T 202
DDR_A_D43 203 VSS VSS 204 DDR_A_D47
205 DQ46 DQ47 206
DDR_A_D42 207 VSS VSS 208 DDR_A_D46
209 DQ42 DQ43 210
DDR_A_D52 211 VSS VSS 212 DDR_A_D48
213 DQ52 DQ53 214 +3VS +3VS
DDR_A_D49 215 VSS VSS 216 DDR_A_D53
217 DQ49 DQ48 218
VSS VSS

2
DDR_A_DQS#6 219 220
DDR_A_DQS6 221 DQS6_C DM6*/DBI6* 222 RD14 RD13
223 DQS6_T VSS 224 DDR_A_D54
10K_0402_5% 10K_0402_5%
+3VS DDR_A_D55 225 VSS DQ54 226
+2.5V DQ55 VSS DDR_A_D51 @ @
227 228

1
DDR_A_D50 229 VSS DQ50 230
231 DQ51 VSS 232 DDR_A_D63
DDR_A_D58 233 VSS DQ60 234 DDR_A_SA1 DDR_A_SA0
235 DQ61 VSS 236 DDR_A_D62
+3VS_DIMM DDR_A_D56 237 VSS DQ57 238
239 DQ56 VSS 240 DDR_A_DQS#7
VSS DQS7_C

1
+2.5V DDR_A_DQS7
2.2U_0402_6.3V6M

0.1U_0201_10V6K

241 242
DM7*/DBI7* DQS7_T +0.6VS
10U_0603_6.3V6M

1U_0402_6.3V6K

1 1 243 244 RD16 RD15


DDR_A_D57 VSS VSS DDR_A_D60
CD37

CD28

1 1 245 246 0_0402_5% 0_0402_5%


DQ62 DQ63
CD36

CD29

247 248
DDR_A_D59 249 VSS VSS 250 DDR_A_D61
DQ58 DQ59

2
2 2 251 252
2 2 PCH_SMB_CLK 253 VSS VSS 254 PCH_SMB_DATA
+3VS_DIMM 255 SCL SDA 256 DDR_A_SA0
257 VDDSPD SA0 258
259 VPP1 VTT 260 DDR_A_SA1
close to DIMM VPP2 SA1
4 4

261
GND 262
GND
DEREN_40-42271-26001RHF
SP07001CW00
ME@

Security Classification
2017/06/05
Compal Secret Data
2018/06/05 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR4_DIMM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 2.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E541P
Date: Wednesday, June 21, 2017 Sheet 18 of 51
A B C D E
1 2 3 4 5

UV1A
COMMON
1/14 PCI_EXPRESS

Place near Place near BGA +1.0VS_DGPU


AB6 PEX_WAKE#
balls
1.0V
PEX_IOVDD AA22
PLT_RST_VGA_MON# PLT_RST_VGA#

1U_0402_6.3V6K

1U_0402_6.3V6K

4.7U_0402_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
RV379 1 2 0_0402_5% AC7 PEX_RST# PEX_IOVDD AB23

CV202

CV205

CV2

CV199

CV204
NOGC6@ PEX_IOVDD AC24 1 1 1 1 1 1 1
CLKREQ_PCIE#0_R

CV9

CV7
AC6 PEX_CLKREQ# PEX_IOVDD AD25
PEX_IOVDD AE26
AE8 PEX_REFCLK PEX_IOVDD AE27
<10> CLK_PEG_VGA 2 2 2 2 2 2 2

DIS@

DIS@

@
PCIE CLK AD8 PEX_REFCLK#
<10> CLK_PEG_VGA#
PCIE_PRX_DTX_P1 CV11 DIS@ 1 2 0.22U_0402_6.3V6K PCIE_PRX_C_DTX_P1 AC9
<12> PCIE_PRX_DTX_P1 PEX_TX0
PCIE_PRX_DTX_N1 CV12 DIS@ 1 2 0.22U_0402_6.3V6K PCIE_PRX_C_DTX_N1 AB9
A <12> PCIE_PRX_DTX_N1 PEX_TX0# A
PCIE_PTX_C_DRX_P1 AG6
<12> PCIE_PTX_C_DRX_P1 PEX_RX0
PCIE_PTX_C_DRX_N1 AG7 PEX_IOVDDQ AA10
<12> PCIE_PTX_C_DRX_N1 PEX_RX0#
PEX_IOVDDQ AA12 Place near Place near BGA
PCIE_PRX_DTX_P2 CV13 DIS@ 1 2 0.22U_0402_6.3V6K PCIE_PRX_C_DTX_P2 AB10 PEX_IOVDDQ AA13 +1.0VS_DGPU
<12> PCIE_PRX_DTX_P2 PCIE_PRX_DTX_N2 CV14 DIS@ 1 2 0.22U_0402_6.3V6K PCIE_PRX_C_DTX_N2 AC10
PEX_TX1
AA16
balls
<12> PCIE_PRX_DTX_N2 PEX_TX1# PEX_IOVDDQ 1.0V
PEX_IOVDDQ AA18
PCIE_PTX_C_DRX_P2

1U_0402_6.3V6K

1U_0402_6.3V6K

4.7U_0402_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
AF7 PEX_RX1 PEX_IOVDDQ AA19
<12> PCIE_PTX_C_DRX_P2 PCIE_PTX_C_DRX_N2

CV201

CV200

CV3

CV198

CV203
AE7 PEX_RX1# PEX_IOVDDQ AA20 1 1 1 1 1 1 1
<12> PCIE_PTX_C_DRX_N2

CV10 @

CV8
PEX_IOVDDQ AA21
PCIE_PRX_DTX_P3 CV15 DIS@ 1 2 0.22U_0402_6.3V6K PCIE_PRX_C_DTX_P3 AD11 AB22
PCIE X4 Bus <12> PCIE_PRX_DTX_P3 PCIE_PRX_DTX_N3 PCIE_PRX_C_DTX_N3 PEX_TX2 PEX_IOVDDQ
CV16 DIS@ 1 2 0.22U_0402_6.3V6K AC11 PEX_TX2# PEX_IOVDDQ AC23
<12> PCIE_PRX_DTX_N3 2 2 2 2 2 2 2

DIS@

DIS@
PEX_IOVDDQ AD24
PCIE_PTX_C_DRX_P3 AE9 PEX_IOVDDQ AE25
<12> PCIE_PTX_C_DRX_P3 PEX_RX2
PCIE_PTX_C_DRX_N3 AF9 PEX_IOVDDQ AF26
<12> PCIE_PTX_C_DRX_N3 PEX_RX2#
PEX_IOVDDQ AF27
PCIE_PRX_DTX_P4 CV17 DIS@ 1 2 0.22U_0402_6.3V6K PCIE_PRX_C_DTX_P4 AC12
<12> PCIE_PRX_DTX_P4 PEX_TX3
PCIE_PRX_DTX_N4 CV18 DIS@ 1 2 0.22U_0402_6.3V6K PCIE_PRX_C_DTX_N4 AB12
<12> PCIE_PRX_DTX_N4 PEX_TX3#
PCIE_PTX_C_DRX_P4 AG9
<12> PCIE_PTX_C_DRX_P4 PEX_RX3
PCIE_PTX_C_DRX_N4 AG10
<12> PCIE_PTX_C_DRX_N4 PEX_RX3#

AB13
Near UV1 AC13
PEX_TX4
PEX_TX4#

AF10 PEX_RX4
AE10 PEX_RX4#

AD14 NC FOR GF119


PEX_TX5
AC14 PEX_TX5# PEX_PLL_HVDD AA8
PEX_PLL_HVDD AA9

NC FOR GM108
AE12 +3VS_DGPU_AON
PEX_RX5
AF12 PEX_RX5# Place near BGA
PEX_SVDD_3V3 AB8
AC15 PEX_TX6
B B

0.1U_0201_10V6K

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M
AB15 PEX_TX6#

CV207

CV5

CV4
1 1 1
AG12 PEX_RX6
AG13 PEX_RX6#
2 2 2

DIS@

DIS@

DIS@
AB16 PEX_TX7
AC16 PEX_TX7#

AF13 PEX_RX7
AE13 PEX_RX7#

AD17 PEX_TX8
AC17 PEX_TX8#
Reset Control +3VS AE15 PEX_RX8
AF15 PEX_RX8#
UV12
5

MC74VHC1G08DFT2G_SC70-5 AC18 F2 VDD_SENSE_GPU


PEX_TX9 VDD_SENSE VDD_SENSE_GPU <49>
AB18 PEX_TX9# To POWER
VCC

1
<10,30,31,32,35> PCI_RST# IN1 4 GND_SENSE_GPU
(From PCH) AG15 PEX_RX9 GND_SENSE F1
OUT PLT_RST_VGA_MON# <22> GND_SENSE_GPU <49>
2 AG16 trace width: 16mils
GND

<11> DGPU_HOLD_RST# IN2 PEX_RX9#


+3VS_DGPU_AON
differential voltage sensing.
AB19 PEX_TX10
DIS@ AC19
differential signal routing.
PEX_TX10#
3

UV15
5

MC74VHC1G08DFT2G_SC70-5 AF16 PEX_RX10


AE16 PEX_RX10#
VCC

NC FOR GF117/GK208/GM108
1
IN1 4 PLT_RST_VGA# AD20
OUT PEX_TX11
2 AC20
GND

<22> PLT_RST_VGA_HOLD# IN2 PEX_TX11#


1

(From GPU)
AE18 PEX_RX11
GC6@ RV378 AF18 PEX_RX11#
3

10K_0402_5%
C DIS@ AC21 PEX_TX12 C
2

AB21 PEX_TX12#

AG18 AF22 PEX_PLL_CLK_OUT RV4 2 @ 1200_0402_1%


PEX_RX12 PEX_TSTCLK_OUT
AG19 AE22 PEX_PLL_CLK_OUT#
PEX_RX12# PEX_TSTCLK_OUT#

AD23
CLK_REQ +3VS_DGPU AE23
PEX_TX13
PEX_TX13#
+1.0VS_DGPU

PEX_PLLVDD_GPU
1.0V
AF19 PEX_RX13 PEX_PLLVDD AA14 RV377 1 2 0_0402_5%
AE19 PEX_RX13# PEX_PLLVDD AA15
1

0.1U_0201_10V6K

1U_0402_6.3V6K

4.7U_0402_6.3V6M
Place near BALL Place near BGA

CV206

CV6
RV17 AF24 PEX_TX14 1 1 1

CV208 DIS@
10K_0402_5% AE24 PEX_TX14#
DIS@
AE21 PEX_RX14
2

2 2 2

DIS@

DIS@
AF21 PEX_RX14#
RV16 1 @ 2 0_0402_5% AD9 GPU_TESTMODE
<23,24,49> DGPU_PWROK TESTMODE GPU_TESTMODE <22>
AG24 PEX_TX15
AG25 PEX_TX15#
+3VS_DGPU_AON
1U_0402_6.3V6K
CV121 @

1
AG21 PEX_RX15
AG22 PEX_RX15#
1

RV68 2
10K_0402_5% AF25 PEX_TERMP
PEX_TERMP
2

DIS@ QV3

1
G

2N7002K_SOT23-3
2

N16S-GT-S-A2_BGA595 RV376
CLKREQ_PCIE#0_R 3 1 VGA_CLKREQ# @
VGA_CLKREQ# <10> 2.49K_0402_1%
S

DIS@
DIS@ (To SOC)

2
1

VGS(Max) : 2.5 V RV18


10K_0402_5%
D @ D
2

RV375 1 @ 2 0_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2017/06/05 Deciphered Date 2018/06/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NV(1/5)-PCIE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 2.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E541P
Date: Wednesday, June 21, 2017 Sheet 19 of 51
1 2 3 4 5
1 2 3 4 5

UV1G
IFPA/B
UV1H
COMMON IFPC
COMMON 5/14 IFPC
4/14 IFPAB IFPC
T6 IFPC_RSET GF119/GK208
IFPA_TXC# AC4
IFPA_TXC AC3 DVI/HDMI DP

AA6 M7 N5

NC FOR GF117/GM108
IFPAB_RSET IFPC_PLLVDD I2CW_SDA IFPC_AUX#
IFPA_TXD0# Y3 N7 IFPC_PLLVDD I2CW_SCL IFPC_AUX N4
Y4

NC FOR GF117/GM108
A IFPA_TXD0 A

V7 IFPAB_PLLVDD IFPC_L3# N3
TXC
IFPA_TXD1# AA2 IFPC_L3 N2
TXC
W7 IFPA_TXD1 AA3
IFPAB_PLLVDD
DAC_A
NC FOR GF117/GM108
IFPC_L2# R3
TXD0
UV1K IFPC_L2 R2
TXD0
IFPA_TXD2# AA1 COMMON
IFPA_TXD2 AB1 3/14 DACA TXD1 IFPC_L1# R1
TXD1 IFPC_L1 T1

NC FOR GF117/GM108
GF117/GM108 GF117 GM108/GK208
IFPA_TXD3# AA5 W5 B7 I2CA_SCL T3
DACA_VDD NC NC I2CA_SCL I2CA_SCL <22> TXD2 IFPC_L0#
AA4 A7 I2CA_SDA T2
IFPA_TXD3 NC I2CA_SDA I2CA_SDA <22> TXD2 IFPC_L0
AE2 DACA_VREF TSEN_VREF

IFPB_TXC# AB4 AF2 DACA_RSET DACA_HSYNC AE3 GF117


NC NC
IFPB_TXC AB5 DACA_VSYNC AE4 P6 IFPC_IOVDD GPIO15 C3
NC NC

W6 IFPA_IOVDD IFPB_TXD4# AB2 DACA_RED AG3


NC
IFPB_TXD4 AB3 N16S-GT-S-A2_BGA595
Y6 IFPB_IOVDD DACA_GREEN AF4 @
NC

IFPB_TXD5#
IFPB_TXD5
AD2
AD3
NC DACA_BLUE AF3 UV1I
COMMON IFPD
GM108 6/14 IFPD
GK208
GF117
IFPB_TXD6# AD1
AE1 N16S-GT-S-A2_BGA595 U6 GF119/GK208
IFPB_TXD6 IFPD_RSET
@
DVI/HDMI DP
IFPB_TXD7# AD5
IFPB_TXD7 AD4 T7 IFPD_PLLVDD I2CX_SDA IFPD_AUX# P4
P3

NC FOR GF117/GM108
I2CX_SCL IFPD_AUX
R7 IFPD_PLLVDD

NC FOR GF117/GM108
B R5 B
GF117 TXC IFPD_L3#
IFPD_L3 R4
TXC
GPIO14 B3
NC
IFPAB TXD0
IFPD_L2#
IFPD_L2
T5
T4
TXD0
N16S-GT-S-A2_BGA595
@ TXD1 IFPD_L1# U4
+1.0VS_DGPU IFPD TXD1 IFPD_L1 U3

1V DIS@ IFPD_L0# V4
GPU_PLLVDD TXD2
LV5 1 2 PBY160808T-300Y-N 0603 IFPD_L0 V3
TXD2

22U_0603_6.3V6M

0.1U_0201_10V K X5R
Place near balls
GF117
1 1

CV32 DIS@

CV31 DIS@
R6 IFPD_IOVDD GPIO17 D4
NC
UV1J
COMMON IFPE/F 2 2

7/14 IFPEF
GF119/GK208
N16S-GT-S-A2_BGA595
DVI-DL DVI-SL/HDMI DP @
I2CY_SDA I2CY_SDA IFPE_AUX# J3
I2CY_SCL I2CY_SCL IFPE_AUX J2
J7 IFPEF_PLLVDD

IFPE_L3# J1
TXC TXC K1
IFPE_L3
NC FOR GF117/GM108

TXC TXC
K7 IFPEF_PLLVDD
NC FOR GF117/GK208/GM108

IFPE_L2# K3
TXD0 TXD0 K2
IFPE_L2
TXD0 TXD0
K6 IFPEF_RSET IFPE_L1# M3
TXD1 TXD1
IFPE_L1 M2
C TXD1 TXD1 C

TXD2
TXD2
TXD2
TXD2
IFPE_L0#
IFPE_L0
M1
N1
UV1M
COMMON
9/14 XTAL_PLL
X'TAL
IFPE NC FOR GK208 L6 PLLVDD
+1.0VS_DGPU Place near BGA Place near balls M6 +3VS_DGPU_AON
SP_PLLVDD
RV23 @
C2 LV6 1 2 0_0603_5% VID_PLLVDD N6 10K_0402_1%
HPD_E HPD_E GPIO18 VID_PLLVDD NC XTAL_OUTBUFF 1 2
22U_0603_6.3V6M

22U_0603_6.3V6M

10U_0603_6.3V6M

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R
NC FOR GF117
1V GF119/GK208 GF117/GM108
1 1 1 1 1
CV61 DIS@

CV35 DIS@

CV30 DIS@

CV34 DIS@

CV60 DIS@
RV21 DIS@ RV20 DIS@
H6 IFPE_IOVDD 10K_0402_1% 10K_0402_1%
GF119/GK208 2 1 A10 XTALSSIN XTALOUTBUFF C10 XTAL_OUTBUFF 1 2
J6 2 2 2 2 2
IFPF_IOVDD DVI-DL DVI-SL/HDMI DP
IFPF_AUX# H4 C11 XTALIN XTALOUT B10
I2CZ_SDA
I2CZ_SCL IFPF_AUX H3
N16S-GT-S-A2_BGA595
@
TXC IFPF_L3# J5 90-OHM DIFF Impedance for XTALIN & XTALOUT.

2
J4
NC FOR GF117/GM108

TXC IFPF_L3
YV1 RV110 DIS@
IFPF_L2# K5 27MHZ_10PF_XRCGB27M000F2P18R0 1.5K_0402_1%
TXD3 TXD0
IFPF_L2 K4 SJ10000UI00
TXD3 TXD0

1
TXD4 TXD1 IFPF_L1# L4 1 3
1 3
IFPF TXD4 TXD1 IFPF_L1 L3
NC NC
1 1
IFPF_L0# M5 DIS@
TXD5 TXD2 2 4
IFPF_L0 M4 CV210 DIS@ CV209 DIS@
TXD5 TXD2
18P_0402_50V8J 18P_0402_50V8J
2 2
NC FOR GK208

D D
GPIO19 F7
HPD_F

NC FOR GF117

N16S-GT-S-A2_BGA595
@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2017/06/05 Deciphered Date 2018/06/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NV(2/5)-IFP_ABCDEF_DAC_XTAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 2.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E541P
Date: Wednesday, June 21, 2017 Sheet 20 of 51
1 2 3 4 5
1 2 3 4 5

UV1D UV1F
+1.35VS_VRAM COMMON COMMON
Place under GPU
GPU_Decoupling
12/14 FBVDDQ 13/14 GND
A2 GND GND M13
B26 FBVDDQ AB17 GND GND M15
C25 FBVDDQ AB20 GND GND M17

CAPs @ Power

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0201_10V6K

0.1U_0201_10V6K
E23 FBVDDQ AB24 GND GND N10

CV217

CV38
1 1 1 1 1 1 E26 FBVDDQ AC2 GND GND N12

CV218

CV221

CV222

CV215
A
F14 FBVDDQ AC22 GND GND N14 A

2 2 2 2 2 2
F21
G13
FBVDDQ
FBVDDQ Page AC26
AC5
GND
GND
GND
GND
N16
N18

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@
G14 FBVDDQ AC8 GND GND P11
G15 FBVDDQ AD12 GND GND P13
G16 FBVDDQ AD13 GND GND P15
G18 FBVDDQ A26 GND GND P17
G19 +VGA_CORE UV1E AD15 P2
FBVDDQ GND GND
G20 FBVDDQ COMMON AD16 GND GND P23
G21 FBVDDQ Voltage by GPU SKU 11/14 NVVDD AD18 GND GND P26
L22 FBVDDQ K10 VDD AD19 GND GND P5
L24 FBVDDQ K12 VDD AD21 GND GND R10
L26 FBVDDQ K14 VDD AD22 GND GND R12
M21 FBVDDQ K16 VDD AE11 GND GND R14
N21 FBVDDQ K18 VDD AE14 GND GND R16
R21 FBVDDQ L11 VDD AE17 GND GND R18
T21 FBVDDQ L13 VDD AE20 GND GND T11
V21 FBVDDQ L15 VDD AB11 GND GND T13
W21 FBVDDQ L17 VDD AF1 GND GND T15
M10 VDD AF11 GND GND T17
M12 VDD AF14 GND GND U10
GF117 M14 AF17 U12
GF119
VDD GND GND
M16 VDD AF20 GND GND U14
GK208
M18 VDD AF23 GND GND U16
H24 FBVDDQ_AON N11 VDD AF5 GND GND U18
FBVDDQ
H26 FBVDDQ_AON N13 VDD AF8 GND GND U2
FBVDDQ

22U_0603_6.3V6M

10U_0603_6.3V6M
J21 FBVDDQ_AON N15 VDD AG2 GND GND U23
FBVDDQ
1 1 K21 FBVDDQ_AON N17 VDD AG26 GND GND U26
FBVDDQ

CV45

CV44
P10 VDD AB14 GND GND U5
P12 VDD B1 GND GND V11
P14 VDD B11 GND GND V13
2 2
DIS@

DIS@
P16 VDD B14 GND GND V15
P18 VDD B17 GND GND V17
R11 VDD B20 GND GND Y2
R13 VDD B23 GND GND Y23
R15 VDD B27 GND GND Y26
B R17 B5 Y5 B
VDD GND GND
Place near GPU T10 VDD B8 GND
T12 VDD E11 GND
CIZ00 22uF x1 change to 10uF x2 T14 VDD E14 GND
T16 VDD E17 GND
T18 VDD E2 GND
U11 VDD E20 GND
U13 VDD E22 GND
U15 VDD E25 GND
Near Ball +1.35VS_VRAM U17 VDD E5 GND
V10 VDD E8 GND
V12 VDD H2 GND
FB_CAL_PD_VDDQ D22 RV41 1 DIS@ 2 40.2_0402_1% V14 VDD H23 GND
V16 VDD H25 GND
V18 VDD H5 GND
FB_CAL_PU_GND C24 RV42 2 DIS@ 1 40.2_0402_1% K11 GND
K13 GND
N16S-GT-S-A2_BGA595 K15 GND
FB_CALTERM_GND B25 RV43 2 DIS@ 1 60.4_0402_1% @ K17 GND
L10 GND
L12 GND
N16S-GT-S-A2_BGA595 L14 GND
@ L16 GND
L18 GND
L2 GND
L23 GND
L25 GND
L5 GND GND AA7
M11 GND GND AB7

N16S-GT-S-A2_BGA595
@

C UV1C C
COMMON
14/14 XVDD/VDD33
+3VS_DGPU
Under GPU Near GPU
AD10 NC VDD33 G8
AD7 NC GM108 VDD33 G9
0.1U_0201_10V6K

0.1U_0201_10V6K

1U_0402_6.3V6K

4.7U_0402_6.3V6M

VDD33 G10
3V3_AON
CV216

VDD33 G12 1 1 1 1
3V3_AON
CV220

CV211

CV219

F11 3V3AUX_NC

2 2 2 2
DIS@

DIS@

DIS@

DIS@

V5 FERMI_RSVD1_NC
V6 FERMI_RSVD2_NC
+3VS_DGPU_AON

Under GPU Near GPU


CONFIGURABLE
POWER CHANNELS
0.1U_0201_10V6K

1U_0402_6.3V6K

4.7U_0402_6.3V6M

* nc on substrate
CV213

1 1 1
CV214

CV212

G1 XPWR_G1
G2 XPWR_G2
G3 XPWR_G3
2 2 2
DIS@

DIS@

G4 XPWR_G4
DIS@

G5 XPWR_G5
G6 XPWR_G6
G7 XPWR_G7

V1 XPWR_V1
V2 XPWR_V2
** XPWR pins are configurable.
These pins are not connected on the substrate.
D D
W1 XPWR_W1 Therefore, XPWR pins can be assigned as needed,
W2 XPWR_W2
W3 XPWR_W3 to improve Top layer routing, power delivery.
W4 XPWR_W4

N16S-GT-S-A2_BGA595
@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2017/06/05 Deciphered Date 2018/06/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NV(3/5)-POWER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 2.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E541P
Date: Wednesday, June 21, 2017 Sheet 21 of 51
1 2 3 4 5
1 2 3 4 5

+3VS_DGPU_AON

UV1N
COMMON
8/14 MISC1
GPIO +3VS_DGPU_AON
PLT_RST_VGA_HOLD#
DGPU_MAIN_EN
1
2
RPV5
8
7
D9 I2CS_SCL RV203 1 DIS@ 2 2.2K_0402_5% PSI 3 6
I2CS_SCL
I2CS_SDA D8 I2CS_SDA RV204 1 DIS@ 2 2.2K_0402_5% I2CS SMBUS: 0x96 VGA_AC_DET 4 5

I2CC_SCL A9 I2CC_SCL RV205 1 @ 2 2.2K_0402_5% and 0x9E(Default) 10K_0804_8P4R_5%


B9 I2CC_SDA RV206 1 @ 2 2.2K_0402_5% DIS@
I2CC_SDA

E12 GF117 GPU_EVENT#_D RV72 1 GC6@ 2 10K_0402_5%


THERMDN
C9 I2CB_SCL
NC I2CB_SCL I2CB_SDA GPIO8_OVERT#
F12 THERMDP I2CB_SDA C8 RV69 1 DIS@ 2 100K_0402_5%
NC

GPU_JTAG_TCK AE5
T231 TP@ JTAG_TCK
GPU_JTAG_TMS AD6 RPV6
T232 TP@ JTAG_TMS
GPU_JTAG_TDI AE6 GPIO9_ALERT# 1 8
T242 TP@ JTAG_TDI
A GPU_JTAG_TDO AF6 2 7 A
T243 TP@ JTAG_TDO
GPU_JTAG_TRST# AG4 C6 GPIO0_GC6_FB_EN RV202 1 2 0_0402_5% GPU_JTAG_TRST# 3 6
JTAG_TRST# GPIO0 GC6_FB_EN <11,23>
B2 FB_CLAMP 4 5
GPIO1 <23> FB_CLAMP
D6
GPIO2
GPIO3 C7
F9
For GC6 2.0 10K_0804_8P4R_5%
GPIO4 DIS@
A3 DGPU_MAIN_EN
GPIO5 GPU_EVENT#_D DGPU_MAIN_EN <24,49>
GK208 GPIO6 A4 DV1 GC6@ 2 1 RB751V-40_SOD323-2 RPV3
GPU_EVENT# <11> I2CA_SCL
GM108 GPIO7 B6 1 8
GPIO8_OVERT# <20> I2CA_SCL I2CA_SDA
OVERT GPIO8 A6 2 7
GPIO9_ALERT# <20> I2CA_SDA I2CB_SCL
GPIO9 F8 DV5 DIS@ 2 1 RB751V-40_SOD323-2 To EC 3 6
MEM_VREF GPU_PROHOT# <32> I2CB_SDA
GPIO10 C5 4 5
GPU_VID0 MEM_VREF <25>
E7
GPIO11
D7 VGA_AC_DET GPU_VID0 <49> To DGPU VR 2.2K_0804_8P4R_5%
GPIO12 From EC
B4 PSI @
GPIO13 PSI <49> To DGPU VR
GM108 GK208 GF117 GF119 GPU_BUFRST RV67 1 @ 2 10K_0402_5%
GPIO16 GPIO16 GPIO16 D5
NC GPU_TESTMODE
GPIO20 GPIO20 NC GPIO20 E6 RV71 1 DIS@ 2 10K_0402_5%
PLT_RST_VGA_HOLD# <19> GPU_TESTMODE
GPIO21 GPIO8 NC GPIO21 C4
PLT_RST_VGA_HOLD# <19> MEM_VREF RV102 1 DIS@ 2 100K_0402_5%
E9 PLT_RST_VGA_MON#
GPIO8 NC NC NC PLT_RST_VGA_MON# <19>
PLT_RST_VGA_MON# RV70 1 @ 2 10K_0402_5%

N16S-GT-S-A2_BGA595 GC6_FB_EN RV88 1 GC6@ 2 10K_0402_5%


@

UV1L
COMMON
STRAP STRAP STRAP0 : PU 49.9K (50K)
STRAP[1:5] : Reserved
10/14 MISC2
+3VS_DGPU_AON

+3VS_DGPU

E10 VMON_IN0_NC
F10 VMON_IN1_NC ROM_CS# D12

1
45.3K_0402_1%

4.99K_0402_1%

4.99K_0402_1%

49.9K_0402_1%
B B

1
ROM_SI

14.7K_0402_1%

10K_0402_1%

4.99K_0402_1%

10K_0402_1%

RV384
ROM_SI B12
ROM_SO

RV61

RV389

RV382

RV51

DIS@
ROM_SO A12 @ @ @ @
ROM_SCLK

RV84

RV81

RV80
STRAP0 D1 STRAP0 ROM_SCLK C12
STRAP1 D2 STRAP1 @ @ @

2
STRAP2 E4 STRAP2
NC FOR

2
STRAP3 E3 GM108
STRAP3
STRAP4 D3 ROM_SI STRAP0
STRAP4
ROM_SO STRAP1
ROM_SCLK STRAP2
STRAP3
+3VS_DGPU_AON C1 STRAP5_NC STRAP4

1
GPU_BUFRST

4.99K_0402_1%

4.99K_0402_1%

4.99K_0402_1%
RV265 BUFRST# D11

1
@

RV65

DIS@

RV64

DIS@

RV381

45.3K_0402_1%

4.99K_0402_1%

4.99K_0402_1%

4.99K_0402_1%

4.99K_0402_1%
0_0402_5%

RV385

RV387

RV388

RV390

RV383
1 @ 2 STRAPREF0 F6 MULTISTRAP_REF0_GND PGOOD D10
NC
GF117 @ @ @ @ @
GK208 GF117 GF119

2
1

GM108 GK208

2
RV380 F4 MULTISTRAP_REF1_GND GM108
NC
40.2K_0402_1%
DIS@ F5 MULTISTRAP_REF2_GND NC
2

N16S-GT-S-A2_BGA595
@
Internal Thermal Sensor

+3VS Reserve for +3VS_DGPU_AON


leakage issue

+3VS +3VS
Link to PCH SML1

5
G
DIS@ PU @ PCH SIDE
2

QV2B
RV15 @ RV26 @
10K_0402_5% I2CS_SCL 4 3
10K_0402_5%

S
EC_SMB_CK2 <8,32,36>

D
DV4 @ 2N7002KDW_SOT363-6
1

C RB751V-40_SOD323-2 C
VGA_AC_DET 2 1 EC_VCIN1_AC_BYPASS
EC_VCIN1_AC_BYPASS <10,32>

2
G
DIS@
QV2A
RV126 1 @ 2 0_0402_5%
I2CS_SDA 1 6

S
EC_SMB_DA2 <8,32,36>

D
2N7002KDW_SOT363-6

D D

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2017/06/05 Deciphered Date 2018/06/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NV(4/5)-GPIO/Strap
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 2.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E541P
Date: Wednesday, June 21, 2017 Sheet 22 of 51
1 2 3 4 5
1 2 3 4 5

+3VS

UV1B
For GC6
COMMON
2/14 FBA 1
<25> FBA_D[0..31] FBA_D0 FB_CLAMP
E18 FBA_D0 FB_CLAMP F3 CV223 @
FBA_D1 NC FB_CLAMP <22>
F18 FBA_D1 0.1U_0201_10V K X5R
FBA_D2 E16 FBA_D2 GF119
FBA_D3 F17 2
FBA_D3
FBA_D4 D20 UV23 GC6@
FBA_D4

5
FBA_D5 D21 MC74VHC1G32DFT2G SC70-5
A FBA_D5 A
FBA_D6 F20 GC6_FB_EN 2
FBA_D6

G Vcc
FBA_D7 <11,22> GC6_FB_EN B
E21 FBA_D7 4
FBA_D8 E15 1 Y 1.35V_PWR_EN <24,49>
FBA_D8 <19,24,49> DGPU_PWROK A
FBA_D9 D15 FBA_D9
FBA_D10 F15 FBA_D10

3
FBA_D11 F13 FBA_D11
FBA_D12 C13 FBA_D12
FBA_D13 B13 FBA_D13
FBA_D14 E13 RV201 1 2 0_0402_5%
FBA_D14
FBA_D15 D13 NOGC6@
FBA_D15
FBA_D16 B15 FBA_D16
FBA_D17 C16 Stuff RV201 if not support GC6
FBA_D17
FBA_D18 A13 FBA_D18
FBA_D19 A15 FBA_D19
FBA_D20 B18 FBA_D20
FBA_D21 A18 FBA_D21
FBA_D22 A19 FBA_D22
FBA_D23 C19 FBA_D23
FBA_D24 B24 FBA_D24
FBA_D25 C23 FBA_D25
FBA_D26 A25 FBA_D26
FBA_D27 A24 FBA_D27
FBA_D28 A21 FBA_D28
FBA_D29 B21 FBA_D29 FBA_CMD[0..31] <25>
FBA_D30 C20 FBA_D30
FBA_D31 C21
<25> FBA_D[32..63] FBA_D31
FBA_D32 R22 FBA_D32
FBA_D33 R24 C27 FBA_CMD0
FBA_D33 FBA_CMD0
FBA_D34 T22 C26 FBA_CMD1
FBA_D34 FBA_CMD1
FBA_D35 R23 E24 FBA_CMD2 +1.35VS_VRAM +1.35VS_VRAM
FBA_D35 FBA_CMD2
FBA_D36 N25 F24 FBA_CMD3
FBA_D36 FBA_CMD3
FBA_D37 FBA_CMD4

10K_0402_5%

10K_0402_5%
N26 FBA_D37 FBA_CMD4 D27

2
FBA_D38 N23 D26 FBA_CMD5
FBA_D38 FBA_CMD5
FBA_D39 FBA_CMD6

DIS@

RV255

DIS@

RV256
N24 FBA_D39 FBA_CMD6 F25
FBA_D40 V23 F26 FBA_CMD7
FBA_D40 FBA_CMD7
B FBA_D41 V22 F23 FBA_CMD8 B
FBA_D41 FBA_CMD8
FBA_D42 T23 G22 FBA_CMD9
FBA_D42 FBA_CMD9

1
FBA_D43 U22 G23 FBA_CMD10
FBA_D43 FBA_CMD10
FBA_D44 Y24 G24 FBA_CMD11 FBA_CKE_L FBA_CMD14
FBA_D44 FBA_CMD11
FBA_D45 AA24 F27 FBA_CMD12
FBA_D45 FBA_CMD12
FBA_D46 Y22 G25 FBA_CMD13 FBA_CKE_H FBA_CMD30
FBA_D46 FBA_CMD13
FBA_D47 AA23 G27 FBA_CMD14
FBA_D47 FBA_CMD14
FBA_D48 AD27 G26 FBA_CMD15 FBA_RST_L FBA_CMD13
FBA_D48 FBA_CMD15
FBA_D49 AB25 M24 FBA_CMD16
FBA_D49 FBA_CMD16
FBA_D50 AD26 FBA_CMD17 M23 FBA_CMD17 FBA_RST_H FBA_CMD29
FBA_D50
FBA_D51 AC25 K24 FBA_CMD18
FBA_D51 FBA_CMD18
FBA_D52 FBA_CMD19

10K_0402_5%

10K_0402_5%
AA27 FBA_D52 FBA_CMD19 K23

2
FBA_D53 AA26 M27 FBA_CMD20
FBA_D54 FBA_D53 FBA_CMD20
FBA_CMD21 GDDR5 design

DIS@

RV253

DIS@

RV254
W26 FBA_D54 FBA_CMD21 M26
FBA_D55 Y25 FBA_CMD22 M25 FBA_CMD22
FBA_D55
FBA_D56 R26 K26 FBA_CMD23
FBA_D56 FBA_CMD23
FBA_D57 T25 K22 FBA_CMD24
FBA_D57 FBA_CMD24

1
FBA_D58 N27 J23 FBA_CMD25
FBA_D58 FBA_CMD25
FBA_D59 R27 J25 FBA_CMD26
FBA_D59 FBA_CMD26
FBA_D60 V26 FBA_CMD27 J24 FBA_CMD27
FBA_D60
FBA_D61 V27 K27 FBA_CMD28
FBA_D61 FBA_CMD28
FBA_D62 W27 K25 FBA_CMD29
FBA_D62 FBA_CMD29
FBA_D63 W25 J27 FBA_CMD30
FBA_D63 FBA_CMD30
J26 FBA_CMD31
FBA_CMD31
<25> FBA_DBI[3..0] FBA_DBI0 D19 FBA_DQM0
FBA_DBI1 D14 FBVDDQ_GPU
FBA_DQM1
FBA_DBI2 C17 FBA_DQM2 GF117/GF119
FBA_DBI3 C22 +1.35VS_VRAM
<25> FBA_DBI[7..4] FBA_DQM3 GK208
FBA_DBI4 P24 FBA_DQM4
FBA_DBI5 W24 B19
FBA_DBI6
FBA_DQM5 NC
FBA_CMD32 1.35V
AA25 FBA_DQM6
FBA_DBI7 U25 FBA_CMD34 F22 RV82 1 @ 2 60.4_0402_1%
FBA_DQM7 FBA_DEBUG0
FBA_CMD35 J22 RV83 1 @ 2 60.4_0402_1%
FBA_DEBUG1
C
<25> FBA_EDC[3..0] FBA_EDC0 E19 C
FBA_DQS_WP0
FBA_EDC1 C15 FBA_DQS_WP1
FBA_EDC2 B16 FBA_CLK0 D24 FBA_CLK0
FBA_DQS_WP2 FBA_CLK0 <25>
FBA_EDC3 B22 FBA_CLK0# D25 FBA_CLK0#
<25> FBA_EDC[7..4] FBA_DQS_WP3 FBA_CLK0# <25>
FBA_EDC4 R25 FBA_CLK1 N22 FBA_CLK1
FBA_DQS_WP4 FBA_CLK1 <25>
FBA_EDC5 W23 FBA_CLK1# M22 FBA_CLK1#
FBA_DQS_WP5 FBA_CLK1# <25>
FBA_EDC6 AB26 FBA_DQS_WP6
FBA_EDC7 T26 FBA_DQS_WP7

F19 FBA_WCK01 D18 FBA_WCK0


FBA_DQS_RN0 FBA_WCK0 <25>
C14 FBA_WCK01# C18 FBA_WCK0#
FBA_DQS_RN1 FBA_WCK0# <25>
A16 FBA_WCK23 D17 FBA_WCK1
FBA_DQS_RN2 FBA_WCK1 <25>
A22 FBA_WCK23# D16 FBA_WCK1#
FBA_DQS_RN3 FBA_WCK1# <25>
P25 FBA_WCK45 T24 FBA_WCK2
FBA_DQS_RN4 FBA_WCK2 <25>
W22 FBA_WCK45# U24 FBA_WCK2#
FBA_DQS_RN5 FBA_WCK2# <25>
AB27 FBA_WCK67 V24 FBA_WCK3
FBA_DQS_RN6 FBA_WCK3 <25>
T27 FBA_WCK67# V25 FBA_WCK3#
FBA_DQS_RN7 FBA_WCK3# <25>

GF119
FB_PLLAVDD F16
+1.0VS_PLLAVDD +1.0VS_PLLAVDD +1.0VS_DGPU
NC
FB_PLLAVDD P22
Close to P22 Close to F16 1.0V LV7 DIS@
FB_DLLAVDD H22 1 2
FB_PLLAVDD
PBY160808T-300Y-N 0603
0.1U_0201_10V K X5R
CV55

0.1U_0201_10V K X5R
CV52

0.1U_0201_10V K X5R
CV53

22U_0603_6.3V6M
CV51
GF117
1 2 1 1
DIS@

DIS@

DIS@

DIS@

2 1 2 2
For VRAM DEBUG using
FB_VREF D23
T2401 TP@ FB_VREF_PROBE
D D
Close to H22 Near GPU
N16S-GT-S-A2_BGA595
@

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2017/06/05 Deciphered Date 2018/06/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NV(5/5)-MEMORY FBA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 2.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E541P
Date: Wednesday, June 21, 2017 Sheet 23 of 51
1 2 3 4 5
5 4 3 2 1

D D

I_Continuous(Max) : 0.79 A(+1.0VS_DGPU)


RON(Max) : 22 mohm
+1.0V_PRIM to +1.0VS_DGPU V drop : 0.0175 V
+3VS to +3VS_DGPU +5VALW +3VS +3VS_DGPU Rising : ~ 208us
QV26 DIS@
ME2301DC-G_SOT23-3

2
+5VALW +1.35VS_VRAM +5VALW +1.0VALW +1.0VS_DGPU
3 1

D
RV261 QV5 DIS@
47K_0402_5% ME2320D-G 1N SOT-23-3

1
470_0603_5%
RV260
DIS@

1
100K_0402_1%
RV252

22_0603_1%
RV251
RV262 DIS@ 1 3

S
1

2
10K_0402_5%
DGPU_MAIN_EN# DGPU_MAIN_EN#_GATE

0.1U_0201_10V6K
CV133

1U_0402_6.3V6K
CV314
1 1

2
@

47K_0402_5%
RV266

G
2

2
@

@
2

2
6
RV263
2 2

DIS@
0_0402_5% 1 1 2

3
D

DIS@
D QV145B @

1
DGPU_MAIN_EN DGPU_MAIN_EN# 1.35V_PWR_EN#

0.1U_0201_10V K X5R
CV320

4.7U_0402_6.3V6M
CV319

1U_0402_6.3V6K
CV318
1 2 2 QV30A DIS@ 2 5 2N7002KDW_SOT363-6
<22,49> DGPU_MAIN_EN G
L2N7002DW1T1G 2N SC88-6 G
2 2 1 S QV25 @
1

6
1U_0402_6.3V6K
CV321

1 @ 2N7002K_SOT23-3 D QV145A @ S

4
DIS@

@
2 2N7002KDW_SOT363-6
<23,49> 1.35V_PWR_EN G
DGPU_MAIN_EN 1 @ 2 DGPU_MAIN_EN_GATE 2 DIS@ 1 DGPU_MAIN_EN_R_GATE
2
@

S RV128 0_0402_5% RV85 47K_0402_5%

1
D

0.047U_0402_16V4Z
QV146 DIS@
DGPU_MAIN_EN#

CV315

0.1U_0201_10V K X5R
CV316
2 2N7002K_SOT23-3 1

2
G
C S C

1
2

DIS@

DIS@
+3VS to +3VS_DGPU_AON +5VALW +3VS +3VS_DGPU_AON

QV20 DIS@
ME2301DC-G_SOT23-3
2

3 1
S

RV258 D
47K_0402_5%

1
DIS@
G
1

470_0603_5%
RV257
RV259 DIS@
10K_0402_5%
DGPU_PWR_EN# DGPU_PWR_EN#_GATE

@
3

RV264 1 1 2

1
0_0402_5% D
DGPU_PWR_EN#
0.1U_0201_10V K X5R
CV313

4.7U_0402_6.3V6M
CV312

1U_0402_6.3V6K
CV311 @
QV30B DIS@ 2
DGPU_PWR_EN 1 2 5 L2N7002DW1T1G 2N SC88-6 G
<11,32> DGPU_PWR_EN 2 2 1 S QV19 @

3
@ 2N7002K_SOT23-3
4

DIS@
1U_0402_6.3V6K
CV317

2
@

B +3VS_DGPU_AON B
2

RG82
10K_0402_5%
DIS@
DIS@
1

DGPU_PWROK DG4 1 2 RB751V-40_SOD323-2


<19,23,49> DGPU_PWROK

+1.35VGS_PGOOD RG83 1 2 0_0402_5% GPU_ALL_PGOOD


<49> +1.35VGS_PGOOD GPU_ALL_PGOOD <11>

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2017/06/05 Deciphered Date 2018/06/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DGPU_DC/DC Interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 2.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E541P
Date: Wednesday, June 21, 2017 Sheet 24 of 51
5 4 3 2 1
5 4 3 2 1

Memory Partition A
UV6 MF=0 UV7 MF=0
MF=0 MF=1 MF=1 MF=0 MF=0 MF=1 MF=1 MF=0

A4 FBA_D0 A4 FBA_D32
FBA_D[0..63] FBA_EDC0 C2 DQ24 DQ0 A2 FBA_D1 FBA_EDC4 C2 DQ24 DQ0 A2 FBA_D33
<23> FBA_D[0..63] FBA_EDC1 EDC0 EDC3 DQ25 DQ1 FBA_D2 FBA_EDC5 EDC0 EDC3 DQ25 DQ1 FBA_D34
C13 B4 C13 B4
FBA_EDC[7..0] FBA_EDC2 R13 EDC1 EDC2 DQ26 DQ2 B2 FBA_D3 FBA_EDC6 R13 EDC1 EDC2 DQ26 DQ2 B2 FBA_D35
<23> FBA_EDC[7..0] FBA_EDC3 EDC2 EDC1 DQ27 DQ3 FBA_D4 FBA_EDC7 EDC2 EDC1 DQ27 DQ3 FBA_D36 BYTE4
R2 E4 BYTE0 R2 E4
EDC3 EDC0 DQ28 DQ4 E2 FBA_D5 EDC3 EDC0 DQ28 DQ4 E2 FBA_D37
DQ29 DQ5 F4 FBA_D6 DQ29 DQ5 F4 FBA_D38
FBA_DBI0 D2 DQ30 DQ6 F2 FBA_D7 FBA_DBI4 D2 DQ30 DQ6 F2 FBA_D39
<23> FBA_DBI0 FBA_DBI1 DBI0# DBI3# DQ31 DQ7 FBA_D8 <23> FBA_DBI4 FBA_DBI5 DBI0# DBI3# DQ31 DQ7 FBA_D40
D13 A11 D13 A11
<23> FBA_DBI1 FBA_DBI2 DBI1# DBI2# DQ16 DQ8 FBA_D9 <23> FBA_DBI5 FBA_DBI6 DBI1# DBI2# DQ16 DQ8 FBA_D41
P13 A13 P13 A13
D <23> FBA_DBI2 FBA_DBI3 DBI2# DBI1# DQ17 DQ9 FBA_D10 <23> FBA_DBI6 FBA_DBI7 DBI2# DBI1# DQ17 DQ9 FBA_D42 D
P2 B11 P2 B11
<23> FBA_DBI3 DBI3# DBI0# DQ18 DQ10 FBA_D11 <23> FBA_DBI7 DBI3# DBI0# DQ18 DQ10 FBA_D43
B13 BYTE1 B13
FBA_CLK0 J12 DQ19 DQ11 E11 FBA_D12 FBA_CLK1 J12 DQ19 DQ11 E11 FBA_D44
<23> FBA_CLK0 FBA_CLK0# CK DQ20 DQ12 FBA_D13 <23> FBA_CLK1 FBA_CLK1# CK DQ20 DQ12 FBA_D45 BYTE5
J11 E13 J11 E13
Samsung_X7668738L05 <23>
<23>
FBA_CLK0#
FBA_CMD14
FBA_CMD14 J3 CK#
CKE#
DQ21
DQ22
DQ13
DQ14
F11 FBA_D14
FBA_D15
<23>
<23>
FBA_CLK1#
FBA_CMD30
FBA_CMD30 J3 CK#
CKE#
DQ21
DQ22
DQ13
DQ14
F11 FBA_D46
FBA_D47
F13 F13
DQ23 DQ15 U11 FBA_D16 DQ23 DQ15 U11 FBA_D48
Micron_X7668738L06 <23> FBA_CMD2
FBA_CMD2
FBA_CMD4
H11
BA0/A2 BA2/A4
DQ8
DQ9
DQ16
DQ17
U13 FBA_D17
FBA_D18 <23> FBA_CMD18
FBA_CMD18
FBA_CMD20
H11
BA0/A2 BA2/A4
DQ8
DQ9
DQ16
DQ17
U13 FBA_D49
FBA_D50
K10 T11 K10 T11
<23> FBA_CMD4 FBA_CMD3 BA1/A5 BA3/A3 DQ10 DQ18 FBA_D19 <23> FBA_CMD20 FBA_CMD19 BA1/A5 BA3/A3 DQ10 DQ18 FBA_D51
K11 T13 BYTE2 K11 T13
<23> FBA_CMD3 FBA_CMD1 BA2/A4 BA0/A2 DQ11 DQ19 FBA_D20 <23> FBA_CMD19 FBA_CMD17 BA2/A4 BA0/A2 DQ11 DQ19 FBA_D52
H10 N11 H10 N11 BYTE6
<23> FBA_CMD1 BA3/A3 BA1/A5 DQ12 DQ20 FBA_D21 <23> FBA_CMD17 BA3/A3 BA1/A5 DQ12 DQ20 FBA_D53
N13 N13
DQ13 DQ21 M11 FBA_D22 DQ13 DQ21 M11 FBA_D54
FBA_CMD6 K4 DQ14 DQ22 M13 FBA_D23 FBA_CMD22 K4 DQ14 DQ22 M13 FBA_D55
<23> FBA_CMD6 FBA_CMD11 A8/A7 A10/A0 DQ15 DQ23 FBA_D24 <23> FBA_CMD22 FBA_CMD27 A8/A7 A10/A0 DQ15 DQ23 FBA_D56
H5 U4 H5 U4
<23> FBA_CMD11 FBA_CMD10 A9/A1 A11/A6 DQ0 DQ24 FBA_D25 <23> FBA_CMD27 FBA_CMD26 A9/A1 A11/A6 DQ0 DQ24 FBA_D57
H4 U2 H4 U2
<23> FBA_CMD10 FBA_CMD7 A10/A0 A8/A7 DQ1 DQ25 FBA_D26 <23> FBA_CMD26 FBA_CMD23 A10/A0 A8/A7 DQ1 DQ25 FBA_D58
K5 T4 K5 T4
<23> FBA_CMD7 FBA_CMD9 A11/A6 A9/A1 DQ2 DQ26 FBA_D27 <23> FBA_CMD23 FBA_CMD25 A11/A6 A9/A1 DQ2 DQ26 FBA_D59
J5 T2 BYTE3 J5 T2
<23> FBA_CMD9 A12/RFU/NC DQ3 DQ27 FBA_D28 <23> FBA_CMD25 A12/RFU/NC DQ3 DQ27 FBA_D60
N4 N4 BYTE7
A5 DQ4 DQ28 N2 FBA_D29 A5 DQ4 DQ28 N2 FBA_D61
U5 VPP/NC DQ5 DQ29 M4 FBA_D30 U5 VPP/NC DQ5 DQ29 M4 FBA_D62
VPP/NC DQ6 DQ30 M2 FBA_D31 VPP/NC DQ6 DQ30 M2 FBA_D63
DQ7 DQ31 DQ7 DQ31
RV116 2 DIS@ 1 1K_0402_1% J1 +1.35VS_VRAM RV117 2 DIS@ 1 1K_0402_1% J1 +1.35VS_VRAM
RV118 2 DIS@ 1 1K_0402_1% J10 MF RV119 2 DIS@ 1 1K_0402_1% J10 MF
RV120 2 DIS@ 1 121_0402_1% J13 SEN B1 RV121 2 DIS@ 1 121_0402_1% J13 SEN B1
ZQ VDDQ D1 ZQ VDDQ D1
VDDQ F1 VDDQ F1
FBA_CMD8 J4 VDDQ M1 FBA_CMD24 J4 VDDQ M1
<23> FBA_CMD8 FBA_CMD12 ABI# VDDQ <23> FBA_CMD24 FBA_CMD28 ABI# VDDQ
G3 P1 G3 P1
<23> FBA_CMD12 FBA_CMD0 RAS# CAS# VDDQ <23> FBA_CMD28 FBA_CMD16 RAS# CAS# VDDQ
G12 T1 G12 T1
<23> FBA_CMD0 FBA_CMD15 CS# WE# VDDQ <23> FBA_CMD16 FBA_CMD31 CS# WE# VDDQ
L3 G2 L3 G2
<23> FBA_CMD15 FBA_CMD5 CAS# RAS# VDDQ <23> FBA_CMD31 FBA_CMD21 CAS# RAS# VDDQ
L12 L2 L12 L2
<23> FBA_CMD5 WE# CS# VDDQ <23> FBA_CMD21 WE# CS# VDDQ
B3 B3
VDDQ D3 VDDQ D3
VDDQ F3 VDDQ F3
FBA_WCK0# D5 VDDQ H3 FBA_WCK2# D5 VDDQ H3
<23> FBA_WCK0# FBA_WCK0 WCK01# WCK23# VDDQ <23> FBA_WCK2# FBA_WCK2 WCK01# WCK23# VDDQ
D4 K3 D4 K3
<23> FBA_WCK0 WCK01 WCK23 VDDQ <23> FBA_WCK2 WCK01 WCK23 VDDQ
M3 M3
FBA_WCK1# P5 VDDQ P3 FBA_WCK3# P5 VDDQ P3
<23> FBA_WCK1# FBA_WCK1 WCK23# WCK01# VDDQ <23> FBA_WCK3# FBA_WCK3 WCK23# WCK01# VDDQ
P4 T3 P4 T3
<23> FBA_WCK1 WCK23 WCK01 VDDQ <23> FBA_WCK3 WCK23 WCK01 VDDQ
E5 E5
C VDDQ VDDQ C
N5 N5
A10 VDDQ E10 A10 VDDQ E10
U10 VREFD VDDQ N10 U10 VREFD VDDQ N10
+FBA_VREFC0 J14 VREFD VDDQ B12 +FBA_VREFC0 J14 VREFD VDDQ B12
VREFC VDDQ D12 VREFC VDDQ D12
VDDQ F12 VDDQ F12
VDDQ H12 VDDQ H12
FBA_CMD13 J2 VDDQ K12 FBA_CMD29 J2 VDDQ K12
<23> FBA_CMD13 RESET# VDDQ <23> FBA_CMD29 RESET# VDDQ
M12 M12
VDDQ P12 VDDQ P12
VDDQ T12 VDDQ T12
VDDQ G13 VDDQ G13
H1 VDDQ L13 H1 VDDQ L13
K1 VSS VDDQ B14 K1 VSS VDDQ B14
B5 VSS VDDQ D14 B5 VSS VDDQ D14
G5 VSS VDDQ F14 G5 VSS VDDQ F14
L5 VSS VDDQ M14 L5 VSS VDDQ M14
T5 VSS VDDQ P14 T5 VSS VDDQ P14
B10 VSS VDDQ T14 B10 VSS VDDQ T14
D10 VSS VDDQ D10 VSS VDDQ
G10 VSS G10 VSS
L10 VSS A1 L10 VSS A1
P10 VSS VSSQ C1 P10 VSS VSSQ C1
T10 VSS VSSQ E1 T10 VSS VSSQ E1
H14 VSS VSSQ N1 H14 VSS VSSQ N1
+1.35VS_VRAM K14 VSS VSSQ R1 K14 VSS VSSQ R1
+1.35VS_VRAM VSS VSSQ U1 +1.35VS_VRAM VSS VSSQ U1
VSSQ H2 VSSQ H2
VSSQ VSSQ
1

G1 K2 G1 K2
RV125 L1 VDD VSSQ A3 L1 VDD VSSQ A3
549_0402_1% G4 VDD VSSQ C3 G4 VDD VSSQ C3
DIS@ L4 VDD VSSQ E3 L4 VDD VSSQ E3
C5 VDD VSSQ N3 C5 VDD VSSQ N3
2

R5 VDD VSSQ R3 R5 VDD VSSQ R3


RV200 1 DIS@ 2 931_0402_1% +FBA_VREFC0 C10 VDD VSSQ U3 C10 VDD VSSQ U3
R10 VDD VSSQ C4 R10 VDD VSSQ C4
W=16mils D11 VDD
VDD
VSSQ
VSSQ
R4 D11 VDD
VDD
VSSQ
VSSQ
R4
G11 F5 G11 F5
VDD VSSQ VDD VSSQ
1

D
1.33K_0402_1%
RV127

820P_0402_25V7
CV158

820P_0402_25V7
CV159

1 1 L11 M5 L11 M5
2 QV50 P11 VDD VSSQ F10 P11 VDD VSSQ F10
<22> MEM_VREF VDD VSSQ VDD VSSQ
G 2N7002W-T/R7_SOT323-3 G14 M10 RV123 DIS@ G14 M10
DIS@ L14 VDD VSSQ C11 80.6_0402_1% L14 VDD VSSQ C11
B S B
3

2 2 VDD VSSQ FBA_CLK0 1 FBA_CLK0# VDD VSSQ


DIS@

DIS@

DIS@

R11 2 R11
2

VSSQ A12 VSSQ A12


VSSQ C12 VSSQ C12
VSSQ
VSSQ
E12
N12
Near to VRAM VSSQ
VSSQ
E12
N12
VSSQ R12 RV175 DIS@ VSSQ R12
VSSQ U12 VSSQ U12
Place near pin J14 of each vram 170-BALL
VSSQ FBA_CLK1
80.6_0402_1%
FBA_CLK1#
170-BALL
VSSQ
H13 2 1 H13
SGRAM GDDR5 VSSQ K13 SGRAM GDDR5 VSSQ K13
VSSQ A14 VSSQ A14
VSSQ
VSSQ
C14 Near to VRAM VSSQ
VSSQ
C14
E14 E14
VSSQ N14 VSSQ N14
VSSQ R14 VSSQ R14
VSSQ U14 VSSQ U14
VSSQ VSSQ
K4G80325FB-HC03_FBGA170~D @ K4G80325FB-HC03_FBGA170~D @

+1.35VS_VRAM
+1.35VS_VRAM
10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R

1U_0402_6.3V6K

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CV373

CV160

CV161

CV162

CV163

CV164

CV165

CV166

CV167

CV374

CV375

CV376

CV377

CV378

CV379

CV380

CV389

CV381

CV168

CV169

CV170

CV171

CV172

CV173

CV174

CV175

CV382

CV383

CV384

CV385

CV386

CV387

CV388
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

@DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@
DIS@

DIS@

DIS@

DIS@
A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2017/06/05 Deciphered Date 2018/06/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N16P_GDDR5_A
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 2.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E541P
Date: Wednesday, June 21, 2017 Sheet 25 of 51
5 4 3 2 1
5 4 3 2 1

W=60mils +3VS Camera +3VS_CMOS

+3VS LCD Power Circuit +LCDVDD_CONN

W=60mils U202
5 1 +LCDVDD R211 1 2 0_0805_5%
IN OUT
2
W=20mils R212 1 2 0_0603_5%
W=20mils
GND 1
1 1 1
C217 4 3 C201 @
1U_0402_6.3V6K EN OC 4.7U_0402_6.3V6M Q201 @ C202 C203
EM5203AJ-20 SOT23 5P 2 ME2301DC-G_SOT23-3 0.1U_0201_10V K X5R 10U_0603_6.3V6M
2 SA00008R900 2 2
D D
3

D
1
<6> PCH_ENVDD

G
2
R202 @ R201
100K_0402_5% 150K_0402_5%
@ CMOS_ON#_R
<32> CMOS_ON#

2
1
@
C204
0.1U_0201_10V K X5R
2

+3VS

U203 eDP CONN.

5
TC7SH08FUF_SSOP5
2 B+ +LEDVDD
From PCH

P
<6,32> ENBKL B 4 DISPOFF#
1 Y R203 1 2 0_0805_5%
From EC <32> BKOFF# A

4.7U_0805_25V6-K
@ W=100mils

3
2

R205

C205
R210 100K_0402_5% 1
100K_0402_5%
@

1
JEDP1
1

2 40 45
R204 1 2 0_0402_5% 39 40 G5 44
38 39 G4 43
C 37 38 G3 42 C
36 37 G2 41
<6> INVPWM 36 G1
DISPOFF# 35
EDP_HPD_R 34 35
W=60mils 33 34
+LCDVDD_CONN 33
32
C206 1 2 0.1U_0201_10V K X5R EDP_AUXN_C 31 32
<6> EDP_AUXN EDP_AUXP_C 31
<6> EDP_AUXP C207 1 2 0.1U_0201_10V K X5R 30
29 30
C208 1 2 0.1U_0201_10V K X5R EDP_TXP0_C 28 29
eDP <6> EDP_TXP0
C209 1 2 0.1U_0201_10V K X5R EDP_TXN0_C 27 28
<6> EDP_TXN0 27
26
R207 1 2 0_0402_5% EDP_HPD_R C210 1 2 0.1U_0201_10V K X5R EDP_TXP1_C 25 26
<6> EDP_HPD <6> EDP_TXP1 EDP_TXN1_C 25
C211 1 2 0.1U_0201_10V K X5R 24
<6> EDP_TXN1 24
1

1 23
UHD_ESD@ C213 1 2 0.1U_0201_10V K X5R UHD@ EDP_TXP2_C 22 23
<6> EDP_TXP2 EDP_TXN2_C 22
R209 C391 C212 1 2 0.1U_0201_10V K X5R UHD@ 21
<6> EDP_TXN2 21
100K_0402_5% 0.1U_0201_10V K X5R 20
2 C214 1 2 0.1U_0201_10V K X5R UHD@ EDP_TXP3_C 19 20
<6> EDP_TXP3
2

C215 1 2 0.1U_0201_10V K X5R UHD@ EDP_TXN3_C 18 19


<6> EDP_TXN3 17 18
+3VS_CMOS USB20_N5_R 17
@EMI@ 16
W=20mils
EMI C216 1 2 10P_0402_50V8J USB20_P5_R 15
14
16
15
Camera +3VS
13 14
DMIC <28> DMIC_CLK 12 13
<28> DMIC_DAT 12
+3VS 11
EMI G sensor <29,32>
<29,32>
EC_SMB_DA4
EC_SMB_CK4
10
9
8
11
10
9
+3VS +3VS +3VS TS_I2C_RST# 8
7
<6> TS_I2C_RST# TS_DISABLE# 6 7
<32> TS_DISABLE# TS_SPI_CLK_C 6
R206 1 2 0_0402_5% 5
5
1

1
TS_SPI_CS#0_C 4
R286 R285
Touch Panel TS_SPI_SI_C 3 4
B @ 100K_0402_5% @ 4.7K_0402_5% TS_INT# 2 3 B
USB20_P5_R <6> TS_INT# TS_SPI_SO_C 2
1
<12> USB20_P5 1
2

2
TS_I2C_RST# TS_INT# ACES_50398-04041-001
USB20_N5_R SP010013I00
<12> USB20_N5

2
ME@
R135
@ 10K_0402_5%

R208 1 2 0_0402_5%
1

TS_SPI_CLK R218 1 2 33_0402_5%


<8> TS_SPI_CLK TS_SPI_CLK_C
TS_SPI@
I2C1_SCL_TS R214 1 2 0_0402_5%
<11> I2C1_SCL_TS

TS_SPI_CS#0 R217 1 2 33_0402_5%


<8> TS_SPI_CS#0 TS_SPI_CS#0_C
TS_SPI@
I2C1_SDA_TS R213 1 2 0_0402_5%
<11> I2C1_SDA_TS

TS_SPI_SI R219 1 2 33_0402_5% TS_SPI_SI_C


A A
<8> TS_SPI_SI
TS_SPI@
TS_SPI_SO R220 1 2 33_0402_5% TS_SPI_SO_C
<8> TS_SPI_SO
TS_SPI@

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2017/06/05 Deciphered Date 2018/06/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
eDP / Camera
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 2.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E541P
Date: Wednesday, June 21, 2017 Sheet 26 of 51
5 4 3 2 1
5 4 3 2 1

EMI
EMI
CH13 1 2 0.1U_0201_10V K X5R HDMI_CLK+_CK_C RH11 1 EMI@ 2 8.2_0402_1% HDMI_CLK+_CONN HDMI_CLK+_CONN RH12 1 EMI@ 2 150_0402_5% HDMI_CLK-_CONN
<6> HDMI_CLK+_CK

CH14 1 2 0.1U_0201_10V K X5R HDMI_CLK-_CK_C RH15 1 EMI@ 2 8.2_0402_1% HDMI_CLK-_CONN HDMI_TX0+_CONN RH13 1 EMI@ 2 150_0402_5% HDMI_TX0-_CONN
<6> HDMI_CLK-_CK
D D
HDMI_TX1+_CONN RH14 1 EMI@ 2 150_0402_5% HDMI_TX1-_CONN

HDMI_TX2+_CONN RH16 1 EMI@ 2 150_0402_5% HDMI_TX2-_CONN

For HDMI
CH15 1 2 0.1U_0201_10V K X5R HDMI_TX0+_CK_C RH17 1 EMI@ 2 8.2_0402_1% HDMI_TX0+_CONN
<6> HDMI_TX0+_CK +5VS +5V_Display

CH16 1 2 0.1U_0201_10V K X5R HDMI_TX0-_CK_C RH18 1 EMI@ 2 8.2_0402_1% HDMI_TX0-_CONN UH11


<6> HDMI_TX0-_CK
3
W=40mils
OUT
1 1
IN CH11
1
@ 2 0.1U_0201_10V K X5R
CH12 GND
0.1U_0201_10V K X5R 2
2 G5250Q1T73U_SC59-3
CH17 1 2 0.1U_0201_10V K X5R HDMI_TX1+_CK_C RH19 1 EMI@ 2 8.2_0402_1% HDMI_TX1+_CONN
<6> HDMI_TX1+_CK

CH18 1 2 0.1U_0201_10V K X5R HDMI_TX1-_CK_C RH20 1 EMI@ 2 8.2_0402_1% HDMI_TX1-_CONN


<6> HDMI_TX1-_CK

+3VS
CH19 1 2 0.1U_0201_10V K X5R HDMI_TX2+_CK_C RH21 1 2 8.2_0402_1% HDMI_TX2+_CONN
C <6> HDMI_TX2+_CK C
EMI@

1
CH20 1 2 0.1U_0201_10V K X5R HDMI_TX2-_CK_C RH22 1 2 8.2_0402_1% HDMI_TX2-_CONN
<6> HDMI_TX2-_CK
EMI@ RH23
1M_0402_5%
QH14

2
G
2N7002K_SOT23-3

2
JHDMI1
3 1 HDMI_DET 19
<6> TMDS_B_HPD HP_DET
18

D
Near JHDMI1 +5V_Display +5V

1
17
RH24 HDMIDAT_R 16 DDC/CEC_GND
RPH11 20K_0402_5% HDMICLK_R 15 SDA
5 4 14 SCL
6 3 13 Utility

2
7 2 HDMI_CLK-_CONN 12 CEC
8 1 11 CK-
HDMI_CLK+_CONN 10 CK_shield
470 +-5% 8P4R HDMI_TX0-_CONN 9 CK+
8 D0-
HDMI_TX0+_CONN 7 D0_shield
RPH12 HDMI_TX1-_CONN 6 D0+
5 4 5 D1-
6 3 HDMI_TX1+_CONN 4 D1_shield 23
7 2 HDMI_TX2-_CONN 3 D1+ GND1 22
8 1 2 D2- GND2 21
HDMI_TX2+_CONN 1 D2_shield GND3 20
470 +-5% 8P4R +3VS D2+ GND4
ACON_HMRBL-AK120D
1

D DC232004700
2 ME@
G
S QH17
3

2N7002K_SOT23-3

B B

+3VS +3VS +5V_Display


2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%
1

1
RH26

RH25

RH27

RH28

QH15A DH11 @ESD@ DH12 @ESD@ DH13 @ESD@


2

2N7002KDW 2N SC88-6 HDMICLK_R 9 10 1 HDMICLK_R HDMI_TX1-_CONN 9 10 1 HDMI_TX1-_CONN HDMI_TX0-_CONN 9 10 1 HDMI_TX0-_CONN


1 1 1
2

1 6 HDMICLK_R HDMIDAT_R 8 9 2 HDMIDAT_R HDMI_TX1+_CONN 8 9 2 HDMI_TX1+_CONN HDMI_TX0+_CONN 8 9 2 HDMI_TX0+_CONN


<6> HDMICLK_NB 2 2 2
5

HDMI_DET 7 7 4 HDMI_DET HDMI_TX2-_CONN 7 7 4 HDMI_TX2-_CONN HDMI_CLK-_CONN 7 7 4 HDMI_CLK-_CONN


4 4 4

4 3 HDMIDAT_R +5V_Display 6 6 5 +5V_Display HDMI_TX2+_CONN 6 6 5 HDMI_TX2+_CONN HDMI_CLK+_CONN 6 6 5 HDMI_CLK+_CONN


<6> HDMIDAT_NB 5 5 5

QH15B 3 3 3 3 3 3
2N7002KDW 2N SC88-6
8 8 8

L05ESDL5V0NA-4 SLP2510P8 ESD L05ESDL5V0NA-4 SLP2510P8 ESD L05ESDL5V0NA-4 SLP2510P8 ESD

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2017/06/05 Deciphered Date 2018/06/05 Title
HDMI
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 2.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E541P
Date: Wednesday, June 21, 2017 Sheet 27 of 51
5 4 3 2 1
A B C D E

place close audio codec


ALC3240 +5VS_PVDD
+5VS
Input
RA2 1 2 0_0805_5% +3VDD_CODEC

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M
0.1U_0201_10V K X5R

0.1U_0201_10V K X5R
+3VDD_CODEC
2 1 2 1 Combo Jack

2
+1.8VS

CA53
(Normal Open)

CA1

CA66

CA49
RA51
4.7U_0402_4V6M 1 2 1 2 100K_0402_1%
2
CA40

1
@ PLUG_IN_R RA23 1 2 200K_0402_1% PLUG_IN

1 EMI

29

34
39
1
UA1 EXT_MIC_SLEEVE EMI@ RA42 2 1 FBMA-L11-160808-121LMT 0603 HGNDB
W=40mils EXT_MIC_RING2 EMI@ RA31 2 1 FBMA-L11-160808-121LMT 0603 HGNDA
Headphone W=40mils

CPVDD
DVDD

PVDD1
PVDD2
1 HDA_SDIN0_AUDIO HP_OUTL HPOUT_L 1
<9> HDA_SDIN0 33_0402_5% 2 1 RA52 7 EMI@ RA45 1 2 47_0402_5%
4 SDATA-IN 25 HP_OUTL HP_OUTR EMI@ RA56 1 2 47_0402_5% HPOUT_R
<9> HDA_SDOUT_AUDIO SDATA-OUT HPOUT-L(PORT-I-L) HP_OUTR
26
HPOUT-R(PORT-I-R)
PC_BEEP 11 CA68 1 2 1U_0402_6.3V6K
PCBEEP GNDA
22 For Universal Audio Jack EMI@ EMI@ EMI@ EMI@

470P_0402_50V7K

470P_0402_50V7K

220P_0402_50V7K

220P_0402_50V7K
VREF

2
5 27 CPVEE CA70 2 1 1U_0402_6.3V6K

10K_0402_5%

10K_0402_5%
<9> HDA_BITCLK_AUDIO BCLK CPVEE 1 1

2
LINE1-L CA46 2 1 1U_0402_6.3V6K

RA57

RA44

CA56

CA59
@EMI@
33_0402_5% 2 @EMI@ 1 RA50

CA65

CA50
22P_0402_50V8J CA52 @ @
LINE1-R CA54 2 1 1U_0402_6.3V6K

1
RA58 1 2 2.2K_0402_5% EXT_MIC_RING2 13 17 LINE1-R 2 2

1
RA54 1 2 2.2K_0402_5% EXT_MIC_SLEEVE 14 MIC2-L(PORT-F-L)/RING LINE1-R(PORT-C-R) 18 LINE1-L
MIC2-R(PORT-F-R)/SLEEVE LINE1-L(PORT-C-L)
GNDA

CA63 2 1 2.2U_0402_6.3V6M 15 24
+LINE1-VREFO-R
23 MIC2-CAP LINE1-VREFO-L 12 PLUG_IN_R RA36 1 2 4.7K_0402_5% GNDA GNDA GNDA GNDA GNDA GNDA
wide 40MIL +MIC2-VREFO MIC2-VREFO HP/ LINE1-JD(JD1) External DMIC
SPK_L2+ 35 2 RA49 1 2 4.7K_0402_5%
SPK_L1- SPK-OUT-LP GPIO0/DMIC-DATA12 DMIC_CLK_R DMIC_DAT <26> +LINE1-VREFO-R
36 3 LA9 2 EMI@ 1 220_0402_5%
SPK_R1-
SPK_R2+
37
38
SPK-OUT-LN
SPK-OUT-RN
GPIO1/DMIC-CLK
8
DMIC_CLK <26>
Combo Jack
SPK-OUT-RP DVDD-IO +IOVDD_CODEC
EMI (Normal Open)
GNDA GNDA

2.2U_0402_6.3V6M1 2 CA61 1
LDO1 21 28 CA57
2.2U_0402_6.3V6M1 2 CA64 LDO2 32 LDO1-CAP CBN 30
HGNDA / HGNDB , W=60mils JHP1 ME@
LDO2-CAP CBP 1U_0402_6.3V6K
LDO3 6 HGNDB 3
2.2U_0402_6.3V6M1 2 CA51 LDO3-CAP 2 HPOUT_L RA63 1 @ 2 0_0402_5% HPOUT_L1 1
40 PDB RA46 1 2 0_0402_5% EC_MUTE# <32>
10 PDB

VD33STB
DC DET

2
9 41 5

AVDD1
AVDD2
AVSS1
AVSS2
<9> HDA_SYNC_AUDIO SYNC THERMAL PAD RA43 @
10K_0402_5%
PLUG_IN 6
ALC3240-VA3-CG_MQFN40_5X5 HPOUT_R RA64 1 @ 2 0_0402_5% HPOUT_R1 2

20
33
19
31

16

1
HGNDA 4
7
2 2

L03ESDL5V0CC3-2_SOT23-3
DA8 SCA00002900

L03ESDL5V0CC3-2_SOT23-3
DA9 SCA00002900
3

33K_0402_5%
SINGA_2SJ3095-067111F

1
DC23000DY00

@ESD@

RA62
GNDA +3VALW
+5VDDA_CODEC +1.8VS

@ESD@

ESD@

2
RA53 1 2 0_0402_5%
Place RA53 on GNDA moat

1
CA60 1 2 1U_0402_6.3V6K
GNDA

Place near Pin33


Output
SPEAK 4 ohm : 40MIL JSPK1 ME@
6
SPEAK 8 ohm : 20MIL 5 GND2
GND1
+5VS to +5VDDA_CODEC :
Each Platform Power Net Support List: SPK_R1-
SPK_R2+
LA5
LA6
1
1
2
2
0_0603_5%
0_0603_5%
SPK_R1-_CONN
SPK_R2+_CONN
4
3 4
SPK_L1- LA7 1 2 0_0603_5% SPK_L1-_CONN 2 3
SPK_L2+ LA8 1 2 0_0603_5% SPK_L2+_CONN 1 2
1
+1.5VS +1.8VS +3VS +5VS +3VALW

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K
+5VS +5VDDA_CODEC ACES_50271-0040N-001
1 1 1 1 SP02000TS00
2 1 0_0603_5%

EMI@ CA45

EMI@ CA67

EMI@ CA71

EMI@ CA47
RA48 1.5V(S0) 1.8V(S0) 3.3V(S0) 5V(S0) 3.3V(S0~S5)
Intel Broadwell V X V V V
0.1U_0201_10V K X5R

2 2 2 2
1 1
1U_0402_6.3V6K
CA58

CA55

Intel Skylake X V V V V
3
Place RA48 on GNDA moat
2 2
EMI 3

ESD protection needs to be placed near connector side

GNDA

Each Platform HDA Link Voltage Support (Pin 8): DA3 @ESD@
SPK_R1-_CONN 6 3 SPK_L2+_CONN
Place near Pin20 I/O4 I/O2
3.3V 1.5V
+5VS
Intel Broadwell V (default) V
5 2
VDD GND
Intel Skylake V (default) V
SPK_R2+_CONN 4 1 SPK_L1-_CONN
I/O3 I/O1
AZC099-04S.R7G_SOT23-6
ESD
+3VS to +IOVDD_CODEC +3VS to +3VDD_CODEC PC Beep place close audio codec EMI CA41
EMI@
1 2 0.1U_0201_10V K X5R

RA41 1 2 47K_0402_5% BEEP_N CA69 2 1 0.1U_0402_10V7K PC_BEEP


+3VS +IOVDD_CODEC +3VS +3VDD_CODEC EC Beep <32> BEEP#
RA60 1 2 0_0402_5%
RA55 1 2 47K_0402_5%
APU Beep <9> HDA_SPKR
100P_0402_50V8J
CA43 @ESD@

1
1

RA61 1 2 0_0402_5%
RA6 2 1 0_0603_5% RA59 2 1 0_0603_5% RA47
4 27K_0402_5% EMI@ 4
1U_0402_6.3V6K
0.1U_0201_10V K X5R

2 CA42 1 2 0.1U_0201_10V K X5R


1
0.1U_0201_10V K X5R

1
CA62

CA44

1
2
CA48

2 GND GNDA
Place near Pin8 2
Place near Pin1 GNDA

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2017/06/05 Deciphered Date 2018/06/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HD Audio Codec_ ALC3240
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 2.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E541P
Date: Wednesday, June 21, 2017 Sheet 28 of 51
A B C D E
A B C D E F G H

HDD
1 1

SATA HDD Conn.


Near Connector JHDD1

1
C233 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_P0 2 GND
<12> SATA_PTX_DRX_P0 SATA_PTX_C_DRX_N0 A+
C234 1 2 0.01U_0402_16V7K 3
<12> SATA_PTX_DRX_N0 A-
4
1 2 SATA_PRX_C_DTX_N0 5 GND
Near HDD <12> SATA_PRX_DTX_N0
C235 0.01U_0402_16V7K
SATA_PRX_C_DTX_P0 B-
C236 1 2 0.01U_0402_16V7K 6
<12> SATA_PRX_DTX_P0 7 B+
GND
+5V_HDD
R232 1 @ 2 0_0805_5% +3V_HDD 8
+3VS V33
9
10 V33
V33

1000P_0402_50V7K

0.1U_0201_10V K X5R

10U_0603_6.3V6M
11
12 GND
1 1 1
GND

C237

C232

C238
13
R233 1 2 0_0805_5% +5V_HDD 14 GND
@ +5VS V5
15
2 2 2 16 V5
17 V5
18 GND
19 Reserved

ESD 1 20 GND
V12

1
2 21 24 2
C239 22 V12 GND 23
R420
0.1U_0201_10V K X5R V12 GND
0_0402_5%
@ESD@ 2
SDAN_603006-022041

2
DC01000CE00
ME@

(G-Sensor for 360-degree reverse) Finger Printer


+3VS

1
R234
3 0_0402_5% 3

2
+3VS
+3VS
U231 YOGA@ D202 FP_ESD@ JFP1
R231 1 2 0_0402_5% +3VS_GS_R 7 3 9 10 +3VS_FP
1 1 1
VDD VDDIO USB20_N6 1
0.1U_0201_10V K X5R

10 11 2
CSB PS <12> USB20_N6 USB20_P6 2
0.1U_0201_10V K X5R

2 8 9 2 2 3
<12> USB20_P6 3
@

2 5 4 4 9
INT1 NC USB20_P6 USB20_P6 4 GND
YOGA@

C240

6 7 7 4 4 5 10
INT2 5 GND
C231

1 6
2 SDO 9 1 USB20_N6 6 5 USB20_N6 7 6
6 5
1 <26,32> EC_SMB_DA4 12 SDx GND 8 8 7
<26,32> EC_SMB_CK4 SCx GNDIO 8
3 3
BMA250E_LGA12 ACES_51580-00841-P01
8 SP01002GM00
ME@
L05ESDL5V0NA-4 SLP2510P8 ESD

SMB Address: 0001 1000

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2017/06/05 Deciphered Date 2018/06/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD/FP/G-Sensor
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 2.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E541P
Date: Wednesday, June 21, 2017 Sheet 29 of 51
A B C D E F G H
A B C D E

NGFF for WLAN / BT (E- KEY)


1 1

+3VS +3VS_WLAN

R242 1 2 0_0805_5%

@
1 1
C243 C244

4.7U_0402_6.3V6M 0.1U_0201_10V K X5R


2 2

2 2

+3VS_WLAN

JWLAN1
1 2
3 GND 3.3VAUX 4
<12> USB20_P7 USB_D+ 3.3VAUX
BT 5 6
<12> USB20_N7 7 USB_D- LED1# 8
9 GND PCM_CLK 10
11 SIDO_CLK PCM_SYNC 12
13 SDIO_CMD PCM_IN 14
15 SDO_DAT0 PCM_OUT 16
17 SDO_DAT1 LED2# 18
19 SDO_DAT2 GND 20
21 SDO_DAT3 UART_WAKE# 22 WL_UART_RX RP241 @
UART for intel debugging in WIN7
23 SDIO_WAKE# UART_RX 1 8
SDIO_RESET# UART0_TX <11>
2 7
UART0_RX <11>
3 6
4 5
32 WL_UART_TX
33 UART_TX 34 0_0804_8P4R_5%
35 GND UART_CTS 36
<12> PCIE_PTX_C_DRX_P6 37 PETP0 UART_RTS 38 R243 1 2 0_0402_5%
<12> PCIE_PTX_C_DRX_N6 PETN0 RESERVED EC_TX <32>
39 40 R244 1 2 0_0402_5%
41 GND RESERVED 42 EC_RX <32>
<12> PCIE_PRX_DTX_P6 PERP0 RESERVED
43 44
WLAN <12> PCIE_PRX_DTX_N6
45 PERN0 COEX3 46
47 GND COEX2 48
<10> CLK_PCIE_WLAN 49 REFCLKP0 COEX1 50 SUSCLK_R 1 2 0_0402_5%
R245
<10> CLK_PCIE_WLAN# REFCLKN0 SUSCLK WL_RST# SUSCLK <10>
51 52
R246 1 2 0_0402_5% WLANCLK_REQ#_R 53 GND PERST0# 54 BT_DISABLE_R R247 1 2 0_0402_5%
<10> WLANCLK_REQ# WAKE#_R CLKEQ0# W_DISABLE2# WLBT_OFF# <11>
<32> PCIE_WAKE# R249 1 @ 2 0_0402_5% 55 56 R248 1 2 0_0402_5%
3 57 PEWAKE0# W_DISABLE1# 58 WL_OFF# <12> 3
59 GND I2C_DATA 60
61 RSRVD/PETP1 I2C_CLK 62
63 RSRVD/PETN1 ALERT 64
Note: The real behavior of BT_DISABLE are
65 GND RESERVED 66 BT_DISABLE=LOW, BT=OFF
67 RSRVD/PERP1 RESERVED 68 BT_DISABLE=HIGH, BT=ON
69 RSRVD/PERN1 RESERVED 70
71 GND RESERVED 72
73 RESERVED 3.3VAUX 74
75 RESERVED 3.3VAUX
GND

77 76
MTG77 MTG76

LOTES_APCI0128-P005A
SP070011H00
ME@

2
R251 R252 WL_RST# R250 1 2 0_0402_5% PCI_RST# <10,19,31,32,35>
100K_0402_5% 100K_0402_5%
1 @

4 4

Security Classification
2017/06/05
Compal Secret Data
2018/06/05
Compal Electronics, Inc.
Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NGFF WLAN / BT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
2.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E541P
Date: Wednesday, June 21, 2017 Sheet 30 of 51
A B C D E
A B C D E

NGFF for SSD (M-KEY)


1 1

+3VS +3VS_SSD

R261 1 2 0_0805_5%

10U_0603_6.3V6M

10U_0603_6.3V6M

0.1U_0201_10V6K

0.01U_0402_16V7K
1 1 1 1

C261

C263

C262

C264
2 @ 2 2 2

SSD@

SSD@

@
2 +3VS_SSD 2

JSSD1
1 2
3 GND 3P3VAUX 4
5 GND 3P3VAUX 6
<12> PCIE_PRX_DTX_N9 PERn3 NC
7 8
<12> PCIE_PRX_DTX_P9 PERp3 NC
9 10
11 GND DAS/DSS# 12
<12> PCIE_PTX_C_DRX_N9 PETn3 3P3VAUX
<12> PCIE_PTX_C_DRX_P9 13 14
15 PETp3 3P3VAUX 16
17 GND 3P3VAUX 18
<12> PCIE_PRX_DTX_N10 PERn2 3P3VAUX
19 20
<12> PCIE_PRX_DTX_P10 PERp2 NC
21 22
23 GND NC 24
<12> PCIE_PTX_C_DRX_N10 PETn2 NC
<12> PCIE_PTX_C_DRX_P10 25 26
27 PETp2 NC 28
29 GND NC 30
<12> PCIE_PRX_DTX_N11 PERn1 NC
<12> PCIE_PRX_DTX_P11 31 32
33 PERp1 NC 34
35 GND NC 36
<12> PCIE_PTX_C_DRX_N11 PETn1 NC
<12> PCIE_PTX_C_DRX_P11 37 38
39 PETp1 DEVSLP 40
41 GND NC 42
<12> PCIE_PRX_DTX_P12 PERn0/SATA-B+ NC
<12> PCIE_PRX_DTX_N12
43 44
45 PERp0/SATA-B- NC 46
47 GND NC 48
<12> PCIE_PTX_C_DRX_N12 PETn0/SATA-A- NC PCI_RST#
<12> PCIE_PTX_C_DRX_P12 49 50
PETp0/SATA-A+ PERST# PCI_RST# <10,19,30,32,35>
51 52 SSDCLK_REQ# <10>
53 GND CLKREQ# 54
<10> CLK_PCIE_SSD# REFCLKN PEWake#
<10> CLK_PCIE_SSD 55 56
57 REFCLKP NC 58
GND NC

3 3

67 68
69 NC SUSCLK(32kHz) 70
PEDET(NC-PCIE/GND-SATA) 3P3VAUX +3VS_SSD
71 72
73 GND 3P3VAUX 74
75 GND 3P3VAUX
GND 76
GND1 77
GND2
LOTES_APCI0079-P005A
SP07001EZ00
ME@

4 4

Security Classification
2017/06/05
Compal Secret Data
2018/06/05
Compal Electronics, Inc.
Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NGFF SSD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
2.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E541P
Date: Wednesday, June 21, 2017 Sheet 31 of 51
A B C D E
+5VALW

USB_EN# R105 1 2 10K_0402_5%


+3VL +3VL
L101
BLM15AX601SN1D _2P VCIN1_BATT_TEMP C111 1 2 100P_0402_50V8J
1 2 R102 1 2 0_0603_5% 1
+3VALW_EC +EC_VCCA VCIN1_AC_IN
SM01000KL00 1 1 C101 C112 1 2 100P_0402_50V8J
C107 @ +3VALW_EC 100P_0402_50V8J
C106 1 1 1 1 @ R110 1 @ 2 4.7K_0402_5%
2

0.1U_0201_10V K X5R
C102

0.1U_0201_10V K X5R
C103

1000P_0402_50V7K
C104

1000P_0402_50V7K
C105
0.1U_0201_10V K X5R 1000P_0402_50V7K
1 2 2 ECAGND 2
L102
BLM15AX601SN1D _2P 2 2 @ 2 @ 2 +EC_VCCA
SM01000KL00 +3VS
ECAGND 1K_0804_8P4R_5%
4 5

111
125
+3VL 3 6

22
33
96

67
9
U11 EC_SMB_CK4 2 7
EC_SMB_DA4 1 8

VSBY
VCC1/LPC

VCC5/SPI

AVCC
VCC2
VCC3
VCC4
R125 2 1 100K_0402_5% RP101
YOGA@
1 21
<35> NOVO# 2 GPIO85/GA20 GPIO15/A_PWM 23 VCCST_PWRGD <10> +1.8VS
BEEP#
<34> CC_LINK GPIO86/KBRST# GPIO21/B_PWM BEEP# <28>

100P_0402_50V8J
C120 @ESD@
3 PWM Output 26 1 1K_0804_8P4R_5%
<8> SERIRQ 4 SERIRQ/GPIOF0 GPIO32/D_PWM 27 EC_VCIN1_AC_BYPASS EC_FAN_PWM1 <36> I2C2_SCL_SEN 4 5
<8> LPC_FRAME# LFRAME#/GPIOF6 GPIO45/E_PWM I2C2_SDA_SEN
5 3 6
EMI
@EMI@ @EMI@
<8> LPC_AD3
<8> LPC_AD2
<8> LPC_AD1
7
8
10
LAD3/GPIOF4
LAD2/GPIOF3
LAD1/GPIOF2 GPIO90/AD0
63
64 VCIN1_BATT_TEMP <39,40>
2
2
1
7
8

2 1 R103 2 1 10_0402_1% <8> LPC_AD0 LAD0/GPIOF1 LPC & MISC GPIO91/AD1 65 VCIN1_BATT_DROP <41> RP102
GPIO92/AD2 ADP_I <40>
C108 22P_0402_50V8J 12 AD Input 66 7/26 update YOGA@
<8> CLK_LPC_EC LCLK/GPIOF5 GPIO93/AD3
13 75
1 2 <10,19,30,31,35> PCI_RST# EC_RST# 37 LRESET#/GPIOF7 GPIO05/AD4 76
+3VALW_EC R104 47K_0402_5% EC_SCI# 20 ECRST# GPIO04/AD5 CUST_TEMP2 <36>
<6,10> EC_SCI# GPIO54/ECSCI# +3VALW
2 38
<35,37,41,43> 3V/5VALW_PG GPIO11/CLKRUN# 68 YOGA only
GPIO94/DA0 TAB_SW# <33>

0.1U_0402_16V7K
C109 70
GPIO95/DA1 TS_DISABLE# <26>
1
0.1U_0201_10V K X5R DA Output 71
GPIO96/DA2 DGPU_PWR_EN <11,24>

1
1

C110

10K_0402_5%
KSI0 55 72
KBSIN0/GPIOA0 GPIO97/DA3 USB_EN# <35>
ESD@

YOGA@

R130
KSI1 56
2

KSI2 57 KBSIN1/GPIOA1
KSI3 58 KBSIN2/GPIOA2 83
KBSIN3/GPIOA3 GPIO31/SCL3/PSCLK1 I2C2_SCL_SEN <11>
KSI4 59 84 YOGA only
I2C2_SDA_SEN <11>

2
KSO[0..15] KSI5 60 KBSIN4/GPIOA4/N2TCK GPIO23/SDA3/PSDAT1 85 EC_SMB_CK4_R R123 1 2 0_0402_5%
<33> KSO[0..15] KBSIN5/GPIOA5/N2TMS GPIO47/SCL4/PSCLK2 EC_SMB_DA4_R EC_SMB_CK4 <26,29>
KSI6 61 PS2 InterfaceGPIO53/SDA4/PSDAT2 86 R124 1 2 0_0402_5% YOGA only
KSI[0..7] KBSIN6/GPIOA6 EC_SMB_DA4 <26,29>
KSI7 62 87
<33> KSI[0..7]
ESD KSO0
KSO1
KSO2
39
40
41
KBSIN7/GPIOA7
KBSOUT0/GPIOB0/SOUT_CR/JENK#
KBSOUT1/GPIOB1/TEST#
GPIO50/PSCLK3
GPIO52/PSDAT3
88
DIR_SET <34>
KB_MUTLI_KEY <33>

KSO3 42 KBSOUT2/GP(I)OB2/TRIST# 97
KBSOUT3/GP(I)OB3/XORTR# GPIO02 ENBKL <6,26>
KSO4 43 98
KBSOUT4/GPIOB4/SDP_VIS# GPIO75 SYS_PWROK <10>
+3VALW_EC KSO5 44 GPIO 99
KBSOUT5/GPIOB5/TDO GPIO76 ME_EN <9>
KSO6 45 109
KBSOUT6/GPIOB6/RDY# VCIN1/GPIO16 VCIN0_PH1 <39>
R108 KSO7 46 Int. K/B
1 2 EC_SMB_CK1 KSO8 47 KBSOUT7/GPIOB7
2.2K_0402_5% KSO9 48 KBSOUT8/GPIOC0 Matrix 119
KBSOUT9/GPIOC1 F_SDI&F_SDIO1/GPO80 EC_SPI_MISO <8>
R109 KSO10 49 120
1 2 EC_SMB_DA1
2.2K_0402_5%
KSO11
KSO12
KSO13
50
51
52
KBSOUT10&P80_CLK/GPIOC2
KBSOUT11&P80_DAT/GPIOC3
KBSOUT12/GPIO64/TCK
F_SDIO&F_SDIO0/GPIOC6
F_CLK/GPIOC4
SPI Flash ROM F_CS0#/GPIOC5
126
128
EC_SPI_MOSI <8>
EC_SPI_CLK <8>
EC_SPI_CS0# <8> +3VALW KBL_SELECT
KSO14 53 KBSOUT13/GPIO63/TMS Funct i on KBL_ID
KSO15 54 KBSOUT14/GPIO62/TDI 73 R107 1 @ 2 10K_0402_5%
81 KBSOUT15/GPIO61/XOR_OUT GPIO03/AD6/CIRRXM 74 CUST_TEMP1 <36> KBL 1
<34> TYPEC_PWR_DIS# GPIO60/KBSOUT16 GPIO07/AD7/CIRTX1 TP_DISABLE# <33>
82 89
<41> 5VLDO_EN GPIO57/KBSOUT17 GPIO67/N2TMS 90 EC_MUTE# <28> NO KBL 0
GPIO51/N2TCK BATT_CHG_LED# <36>
+3VALW 91
EC_SMB_CK1 GPIO36 CAPS_LED# <33> KB_BL_PWM
77 GPIO 92
<39,40> EC_SMB_CK1 EC_SMB_DA1 GPIO17/SCL1/N2TCK GPIO40/F_PWM PWR_LED# <33,35,36>
78 93
<39,40> EC_SMB_DA1 GPIO22/SDA1/N2TMS GPIO35 BATT_LOW_LED# <36>

1
EC_SMB_CK2

100P_0402_50V8J
C117 @ESD@

100P_0402_50V8J
C118 @ESD@
79 95 SYSON 1 1
<8,22,36> EC_SMB_CK2 EC_SMB_DA2 GPIO73/SCL2 GPIO06/IOX_DOUT USB_CHG_ILIM_SEL SYSON <13,42>
R117 80 SM Bus 121 R121
PCIE_WAKE# <8,22,36> EC_SMB_DA2 GPIO74/SDA2 GPIO81/F_WP# SENSOR_EC_INT USB_CHG_ILIM_SEL <35>
1 2 127 10K_0402_5%
GPIO84/IOX_SCLK SENSOR_EC_INT <11>
1K_0402_5% YOGA only 2 2 NOKBL@

2
R106 6 100
1 2 PBTN_OUT# <35> USB_CHG_STATUS# GPIO24 GPIO26/RSMRST# EC_RSMRST# <10>
14 101
ESD 10K_0402_5%
@
<35> USB_CHG_CTL1
<10> EC_CLEAR_CMOS#
<35> USB_CHG_CTL3
15
16
17
GPIO10/LPCPD#
GPIO65/SMI#
GPIO34/1_WIRE/CIRRXL
GPIO20/TA2/IOX_DIO
VC_IN2/GPIO72
VC_OUT2/GPIO37
102
103
104
VCOUT1_PROCHOT# GPU_PROHOT# <22>
VCOUT1_PROCHOT# <40> +3VL
1 <35> USB_CHG_EN GPIO01/TB2 VC_OUT1/GPIO25 VCOUT0_MAIN_PWR_ON <41>
@ R101 18 GPIO 105 BKOFF# ON/OFF# R282 1 2 100K_0402_5%
1 2 <35> USB_CHG_CTL2 EC_PCIE_WAKE# 19 GPIO43 GPIO77 106 BKOFF# <26>
C116 GPIO
<30> PCIE_WAKE# GPIO42/CIRTX2 GPIO44 PM_SLP_S3# <10>
0.1U_0201_10V K X5R 0_0402_5% 25 107 +1.0V_VCCST
2 <33> KB_BL_PWM GPIO13/C_PWM GPIO12 VR_PWRGD <46>
28 108
<36> EC_FAN_SPEED1 GPIO56/TA1 GPIO30/F_WP# VR_ON <46> NUVOTON_VTT R116 1

100P_0402_50V8J
C119 @ESD@
29 1 2 0_0402_5%
<40> VCIN1_AC_IN 30 GPIO14/TB1
<30> EC_TX GPIO83/SOUT_CR/P80_DATA EC_VCIN1_AC_BYPASS
31 110
<30> EC_RX PCH_PWROK 32 GPIO87/SIN_CR/P80_CLK AC_IN/GPIO41/F_WP# 112 EC_ON EC_VCIN1_AC_BYPASS <10,22>
SUSP# R128 1 2 100K_0402_5%
<10> PCH_PWROK GPIO27/RSMRST# EC_ON/GPIO71 EC_ON <35,41> 2
34 GPIO 114 ON/OFF# <33,35>
GPIO66/G_PWM ON_OFFBTN#/GPIO70 LID_SW#
100P_0402_50V8J
C121 @ESD@

1 36 115
1 <26> CMOS_ON# GPIO33/H_PWM GPO82/IOX_LDSH/LIDIN LID_SW# <33,35>
R113 2 116 SUSP#
GPIO46/CIRRXM/PLCIN 117 NUVOTON_VTT SUSP# <13,37,42>
10K_0402_5%
@ VTT 118 PECI 1 R114 2 43_0402_1%
2 PECI PECI H_PECI <6>
+3VS 122
<10> PBTN_OUT# 123 GPIO00/EXTCLK 124
Share ROM +V18R R115 1 @ 2 0_0402_5% +3VALW_EC
<10,40,42> PM_SLP_S4# GPIO55/CLKOUT/IOX_DIO VCORF
1
AGND
GND1
GND2
GND3
GND4
GND5

4.7U_0402_6.3V6M

C114
1 2 EC_FAN_SPEED1
R118 10K_0402_5%
2
11
24
35
94
113

69

NPCE388NA1DX LQFP 128P KBC


ECAGND

Testing Only

@
ESD VCOUT1_PROCHOT# R111 1 2 0_0402_5%

2 1 ON/OFF# SYSON
JP1 R112 1 2 0_0402_5% H_PROCHOT# <6>
<46> VR_HOT#

C115
SHORT PADS

0.1U_0201_10V K X5R
ESD@
1
1
ESD@
@ C113
2 1 ON/OFF# 2 100P_0402_50V8J
JP2 2
SHORT PADS

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2017/06/05 Deciphered Date 2018/06/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EC NPCE388
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 2.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E541P
Date: Wednesday, June 21, 2017 Sheet 32 of 51
Keyboard Backlight Keyboard +5VALW

JKB1
1
R271 2 1 866_0402_1% 2 1
<32> CAPS_LED# 3 2
KSO15
3

0.1U_0201_10V K X5R
KSO10 4
KSO11 5 4
KSO14 6 5
1 6
+5VS +5VALW +5VS +VCC_KB_LED

@ESD@

C271
KSO13 7
KSO12 8 7
KSO3 9 8
2 KSO6 10 9
10

1
KSO8 11
R275 R276 Q271 JKBL1 KSO7 12 11
10K_0402_5% 10K_0402_5% KSO4 13 12
3 KSI[0..7] 13

D
KBL@ @ 1 1 KSO2 14
2 1 KSI[0..7] <32> 15 14
KSI0
2

2
2 15

10U_0603_6.3V6M

0.1U_0201_10V K X5R
ME2301DC-G_SOT23-3 3 KSO[0..15] KSO1 16
3 KSO[0..15] <32> 16
KBL@ 4 KSO5 17

G
1 1

2
4 17

C277

C279
R277 KSI3 18
1 2 KSI2 19 18
19

KBL@
KSO0 20
2 2 20

0.01U_0402_16V7K
30K_0402_1% 5 KSI5 21
R278 KBL@ 6 GND KSI4 22 21
1 GND 22

C278
1 2 KSO9 23
KSI6 24 23
24

KBL@
0_0402_5% KSI7 25
25

1
2 CVILU_CF5004FD0RD-10-NH @ESD@ KSI1 26
LTCX007VP00 C272 2 1 0.1U_0201_10V K X5R 27 26 33

OUT
ME@ 28 27 GND 34
29 28 GND
2 R272 2 S_IMR@ 1 866_0402_1% 30 29
<32> KB_BL_PWM IN <32,35,36> PWR_LED# 30
1 2 31
GND

<32> KB_MUTLI_KEY 31
@ R284 YOGA@ 0_0402_5% 32
Q272 1 2 32
<32,35> ON/OFF#

2
DTC124EKAT146_SC59-3 R283 S_IMR@ 0_0402_5%
3

D303 JXT_FP257H-032S10M
ESD@ SP01002FA00

L03ESDL5V0CC3-2_SOT23-3
R283 R272 ME@
0_0402_5% 866_0402_1%
SD028000080 SD034866080
S_AL@ S_AL@

KB_MUTLI_KEY SELECT

1
Funct i on BOM control
Power Key S_IMR@
(Cruze )
S_AL@
Funct i on Key
(Alpine) YOGA@

Hall -Sensor for 0-deg reverse (TOP) Touch Pad


R273 only for 520S R273
1 2 R273
+3VALW +3VS
100K_0402_5% 100K_0402_5%
S_AL@ S_IMR@
2

R279 1 2 0_0402_5%
+3VS
1
VDD

0.1U_0201_10V K X5R
C273
0.1U_0201_10V K X5R 3
2 OUTPUT LID_SW# <32,35>

C280
YOGA@

1
GND

1 R280 @
C274 4.7K_0402_5%
U281 10P_0402_50V8J ME@
1

APX8132 SOT-23F 3P YOGA@ SP01001AE00

2
SA00008K800 2 ACES_51522-00801-001
YOGA@
TP_VCC 8
7 8 10
<11> I2C0_SCL_TP 6 7 G2 9
<11> I2C0_SDA_TP 6 G1
5
4 5
3 4
TP_INT# 2 3
<11> TP_INT# 2
1
<32> TP_DISABLE# 1
JTP1
1 1

Hall -Sensor for 360-deg reverse (BOT) C281


100P_0402_50V8J
C282
100P_0402_50V8J

2
@ 2 2@
D281
PSOT24C_SOT23-3
R274
1 2
+3VALW
100K_0402_5%

1
@ @ESD@
2

1
VDD

C275
0.1U_0201_10V K X5R 3
ESD
2 OUTPUT TAB_SW# <32>
YOGA@
GND

1
C276
U282 10P_0402_50V8J
1

APX8132 SOT-23F 3P YOGA@


SA00008K800 2
YOGA@
Security Classification Compal Secret Data Compal Electronics, Inc.
2017/06/05 2018/06/05 Title
Issued Date Deciphered Date KBL/KBD/Hall Sensor/TP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 2.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E541P
Date: Wednesday, June 21, 2017 Sheet 33 of 51
5 4 3 2 1

USB Type-C Port +USBC_VBUS +VCONN


+USBC_VBUS +USBC_VBUS

10U_0603_6.3V6M
F11 PD11 JUSBCX1
1 2 2 1 1 A1 B12
GND GND

CT22
0.2A_9V_PICOSMDC020S-2 RB551V-30_SOD323-2 USBCTXDP1_C CT63 1 2 0.1U_0201_10V K X5R USBCTXDP1 A2 B11 USBCRXDP1
USBCTXDN1_C CT64 1 2 0.1U_0201_10V K X5R USBCTXDN1 A3 SSTXP1 SSRXP1 B10 USBCRXDN1
RT69 2 SSTXN1 SSRXN1
1 2 CT27 1 2 0.1U_0201_10V K X5R A4 B9 CT30 1 2 0.1U_0201_10V K X5R
0_0402_5% VBUS VBUS
@ CC1 A5 B8
CC1 SBU2
D USB20_P1_CONN USB20_N1_CONN D
A6 B7
USB20_N1_CONN A7 DP1 DN2 B6 USB20_P1_CONN
DN1 DP2
A8 B5 CC2
+3VALW SBU1 CC2
CT28 1 2 0.1U_0201_10V K X5R A9 B4 CT29 1 2 0.1U_0201_10V K X5R
VBUS VBUS
USBCTXDN2_C

0.1U_0201_10V K X5R
USBCRXDN2 A10 B3 USBCTXDN2 CT61 1 2 0.1U_0201_10V K X5R
+3VALW USBCRXDP2 A11 SSRXN2 SSTXN2 B2 USBCTXDP2 CT62 1 2 0.1U_0201_10V K X5R USBCTXDP2_C
SSRXP2 SSTXP2
USB3 MUX 1 A12
GND GND
B1

CT19
+3VALW

0.1U_0201_10V K X5R
1 6
2 GND GND 7
2 3 GND GND 8
1 GND GND

CT21
4 9
GND GND

0.1U_0201_10V K X5R
UT12 5 10
12 GND GND
3 V33C 2 LOTES_AUSB0372-P001A
HC_EN 1

CT20
4 20 LTCX007XY00
5 MC_EN VCC3A ME@
<32> CC_LINK EN_VCONN CC_EN
6 29
7 VCONN_EN V33B 2
<32> DIR_SET DIR_SET
11
3A/Active High
VCONN +VCONN +5VALW +USBC_VBUS
RT33 1 2 5.1K_0402_1% 30
REXT
1 CU_MODE_0
USBCTXDP1_C 25 SR0_IN 32 TYPEC_CC_ILIM_ADJ#
USBCTXDN1_C 26 TXP_0 SR1_IN
TXN_0 CC1_Z_MODE W=120mils W=120mils
31 UT13
USBCRXDP1
USBCRXDN1
16
15 RXP_0
EJ179V ZCC1_IN
ZCC2_IN
2 CC2_Z_MODE
Intel_PCH_USB3.0 5
IN OUT
1
RXN_0 TYPEC_OC0#

220U_6.3V_ESR18M

470P_0402_50V7K
RT50 1 @ 2 0_0402_5% 3 1
USBCTXDP2_C <12> USB_OC0# CC_LINK FLAG
27 23 RT42 1 2 10K_0402_5% CC_LINK_EN 4 2 1
C USBCTXDN2_C TXP_1 TXP USB3_TX1_P <12> EN(#EN) GND C

CT60

CT24
28 22 +
TXN_1 TXN USB3_TX1_N <12>

0.1U_0201_10V K X5R

10P_0402_50V8J

0.1U_0201_10V K X5R
@ G517G1TO1U_TSOT23-5
USBCRXDP2 14 19 RT51 1 2 1 1 SA0000A9700
RXP_1 RXP USB3_RX1_P <12> 2 @ 2

CT25

CT23
USBCRXDN2 13 18 QT1 1
RXN_1 RXN

1
USB3_RX1_N <12> D

CT26
0_0402_5%

@RF@
2
<32> TYPEC_PWR_DIS# 2 2
8 CC1 G
9 CC1_IN 10 CC2 2
S

3
17 VSSA CC2_IN 2N7002K_SOT23-3
21 VCCSA @
24 VCCSA 33
VSSA EP

EJ179V_QFN32_4X4
SA00009EK00

EMI LT12 EMI@


USB20_P1 2 1 USB20_P1_CONN
<12> USB20_P1

USB20_N1 3 4 USB20_N1_CONN
<12> USB20_N1
MCM1012B900F06BP_4P
+3VALW +3VALW +3VALW +3VALW +3VALW
1

RT31 RT34 RT36 RT38 RT40


10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
@ @ @
B B
2

EN_VCONN CU_MODE_0 TYPEC_CC_ILIM_ADJ# CC1_Z_MODE CC2_Z_MODE

ESD
1

RT32 RT35 RT37 RT39 RT41 DT14 ESD@ DT13 ESD@


10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 3 6 USB20_P1_CONN CC1 9 10 1 CC1
1
@ @ I/O2 I/O4
+USBC_VBUS CC2 8 9 2 2 CC2
2

2 5 7 7 4 4
GND VDD
6 6 5 5

1 4 USB20_N1_CONN 3
I/O1 I/O3 3
8
AZC099-04S.R7G_SOT23-6

Profile Selection L05ESDL5V0NA-4 SLP2510P8 ESD

DT12 ESD@ DT11 ESD@


USBCRXDN2 9 10 1 1 USBCRXDN2 USBCTXDP1 9 10 1 1 USBCTXDP1
EN_VCONN CU_MODE_0 TYPEC_CC_ILIM_ADJ# CC[1:2]_Z_MODE CURRNET SELECT
USBCRXDP2 8 9 2 2 USBCRXDP2 USBCTXDN1 8 9 2 2 USBCTXDN1
1 0 0 00 DFP 900mA
USBCRXDN1 7 7 4 4 USBCRXDN1 USBCTXDP2 7 7 4 4 USBCTXDP2
1 1 0 00 DFP 1.5A
USBCRXDP1 6 6 5 5 USBCRXDP1 USBCTXDN2 6 6 5 5 USBCTXDN2
Currently setting 1 0 1 00 DFP 3A
3 3
3 3
0 1 1 00 UFP
8 8
0 X X 01 10 11 EXTERNAL RESISTER
A L05ESDL5V0NA-4 SLP2510P8 ESD L05ESDL5V0NA-4 SLP2510P8 ESD A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2017/06/05 Deciphered Date 2018/06/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Type-C
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 2.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E541P
Date: Wednesday, June 21, 2017 Sheet 34 of 51
5 4 3 2 1
5 4 3 2 1

USB Charge +5VALWP

IO CONN

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

47U_0805_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
JIO1
PCI_RST# 1
1 1 1 1 1 1 1 1 1 1 <10,19,30,31,32> PCI_RST# 1

C337

C338

C339

C340

C341

C342

C343

C344

C345

C346
2
<12> USB3_RX3_P 3 2
@ @ <12> USB3_RX3_N 4 3
2 2 2 2 2 2 2 2 2 2 USB3 with Charge 5 4
<12> USB3_TX3_P 5
<12> USB3_TX3_N 6
7 6
D PCIE_PRX_DTX_N5 7 D
8
<12> PCIE_PRX_DTX_N5 PCIE_PRX_DTX_P5 9 8
<12> PCIE_PRX_DTX_P5 10 9
CLK_PCIE_CR# 11 10
+5VALW_CHG +5V_CHGUSB <10> CLK_PCIE_CR# CLK_PCIE_CR 11
12
For USB Charger to improve +5VALWP power ripple Card Reader <10> CLK_PCIE_CR
13 12
+3VL PCIE_PTX_C_DRX_N5 14 13
<12> PCIE_PTX_C_DRX_N5 PCIE_PTX_C_DRX_P5 14
15
<12> PCIE_PTX_C_DRX_P5 15
22U_0603_6.3V6M

22U_0603_6.3V6M

0.1U_0201_10V K X5R

16
+5VALW USB20_N3_R 16
1 1 1 17
17
1

1
USB20_P3_R
10K_0402_5%

10K_0402_5%
USB2 18
18

1
C330

C333

C332

R343

R339

10K_0402_5%
+3VALW
19
LID_SW# 19

R338
@ @ 20
2 2 2
USB Charge switch <32,33> LID_SW#
+CHGRTC_R
21
22
20
21
U331 +3VS
2

23 22
80mil

2
1 12 Novo# 24 23
IN OUT +5VALW_CHG +5VALW
Lid/Novo/PWR <32> Novo#
ON/OFF# 25 24
<32,33> ON/OFF# 25
R332 2 @ 1 0_0402_5% USB_OC2#_U331 13 9 PWR_LED# 26
<12> USB_OC2# FAULT# STATUS# USB_CHG_STATUS# <32> <32,33,36> PWR_LED# 26
27
2 11 USB20_N3_C +VL 28 27
<12> USB20_N3 DM_OUT DM_IN USB20_P3_C 28
3 10 29
<12> USB20_P3 DP_OUT DP_IN +5V_CHGUSB 29
30
4 15 R333 1 2 51.1K_0402_1% 31 30 33
<32> USB_CHG_ILIM_SEL ILIM_SEL ILIM_LO W=100mils 31 GND

22U_0603_6.3V6M
5 16 R334 1 2 22.1K_0402_1% R336 32 34
<32> USB_CHG_EN EN ILIM_HI 1 2 3 32 GND

D
1 1

C334
6 1 0_0603_5% Q332
<32> USB_CHG_CTL1 CTL1
7 14 C335 ACES_51547-03201-P01

ME2301DC-G_SOT23-3
<32> USB_CHG_CTL2 CTL2 GND
8 17 22U_0603_6.3V6M SP01001PC00

G
<32> USB_CHG_CTL3

2
CTL3 GPAD 2 ME@
1

2
10K_0402_5%

TPS2546RTER_QFN16_3X3
R341

SA000064O00
@
+VL
2

C C
R331
1 2

100K_0402_5%
1

1
D

2N7002K_SOT23-3
EC_ON_R

Q331
R337 1 2 470K_0402_1% 2 C331
<32,41> EC_ON <10> CR_CLKREQ#
G @ 0.1U_0201_10V K X5R
@ S 2

2
0.1U_0201_10V K X5R
R342
EMI <32,37,41,43> 3V/5VALW_PG
R340 2 1 0_0402_5% 0_0402_5%
@
1

1
USB20_P3_C R345 2 1 0_0402_5% USB20_P3_R

C336
@
USB20_N3_C R344 2 1 0_0402_5% USB20_N3_R 2

Close to CPU RPC6

USB3.0_Port Intel_PCH_USB2.0

L301 EMI@
B 1 4 U2DN2 B
<12> USB20_N2 1 4

+5VALW +USB3_VCCA 2 3 U2DP2


<12> USB20_P2 2 3
2A/Active Low +USB3_VCCA
W=80mils MCM1012B900F06BP_4P
W=80mils U301
1
5 OUT
IN 2
W=80mils
USB_EN# 4 GND Intel_PCH_USB3.0
<32> USB_EN# R301
EN 3 USB_OC1#_U301 1 2 R302 1 2 0_0402_5% JUSB1
1 OCB USB_OC1# <12>
0_0402_5% @ U3TXDP2 9
C305 SY6288D20AAC_SOT23-5 @ 1 SSTX+
0.1U_0201_10V K X5R U3RXDN2 U3TXDN2 8 VBUS
2 <12> USB3_RX2_N SSTX-
470P_0402_50V7K

1 U2DP2 3
D+
220U_6.3V_M

1 7
GND
C304

C303

+ U3RXDP2 U2DN2 2 10
<12> USB3_RX2_P U3RXDP2 6 D- GND 11
@ 4 SSRX+ GND 12
2 2 U3RXDN2 5 GND GND 13
R303 1 2 0_0402_5% SSRX- GND
@ ACON_TARBA-9U1393
DC23300N800
ME@
R304 1 2 0_0402_5%
C301 @
0.1U_0201_10V K X5R
<12> USB3_TX2_N 1 2 U3TXDN2_L U3TXDN2
C302
D301 ESD@ D302 ESD@ 0.1U_0201_10V K X5R
U3RXDN2 9 10 1 1U3RXDN2 U2DP2 3 6 <12> USB3_TX2_P 1 2 U3TXDP2_L U3TXDP2
I/O2 I/O4
U3RXDP2 8 9 2 2U3RXDP2

A U3TXDN2 7 7 4 4U3TXDN2 2 5 +USB3_VCCA R305 1 2 0_0402_5% A


GND VDD @
U3TXDP2 6 6 5 5U3TXDP2

3 1 4 U2DN2
Place TX AC coupling Cap (C172,173). Close to connector
3
I/O1 I/O3
8
L30ESDL5V0C6-4_SOT23-6

L05ESDL5V0NA-4 SLP2510P8 ESD


Security Classification Compal Secret Data
Issued Date 2017/06/05 Deciphered Date 2018/06/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB2 / USB3 / FP / IO Board
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 2.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E541P
Date: Wednesday, June 21, 2017 Sheet 35 of 51
5 4 3 2 1
5 4 3 2 1

Thermal Sensor DDR VRAM


+EC_VCCA +EC_VCCA

+3VS_DGPU +3VS

16.5K_0402_1%

16.5K_0402_1%
1

1
R364

R365
1

1
DIS@
R362 R361
0_0402_5% 0_0402_5%

2
EX_THM@ @
D D

2
<32> CUST_TEMP1 <32> CUST_TEMP2
GPU

1
Close to U361 R366 R367
U361 EX_THM@ 100K +-1% 0402 B25/50 4250K DIS@ 100K +-1% 0402 B25/50 4250K
+3V_Thermal 1 8 EC_SMB_CK2
1 VDD SCL EC_SMB_CK2 <8,22,32>
C361 SL200002H00 SL200002H00

2
2200P_0402_50V7K REMOTE1+ 2 7 EC_SMB_DA2
D+ SDA EC_SMB_DA2 <8,22,32>
EX_THM@
2 REMOTE1- 3 6
D- ALERT# ECAGND ECAGND
R363 1 2 4.7K_0402_5% 4 5
+3V_Thermal T_CRIT# GND
EX_THM@

NCT7718W_MSOP8
REMOTE1+/-:
Trace width/space:10/10 mil SMB Address: 1001100x
Trace length:<8"

REMOTE1+
Close to CPU
1
1

C
@ C362 2 Q361 @
100P_0402_50V8J B MMST3904-7-F_SOT323-3
2 E
3

REMOTE1-

C C

Power LED & Battery LED


FAN
Power (White)
LED2
PWR_LED# 1 2 R377 1 2 412_0402_1%
<32,33,35> PWR_LED# +5VALW
S_AL@
LTW-C193TS5-C_WHITE
+5VS SC50000BB10
S_AL@

LED5 R377
R371 1 2 0_0603_5% 1K_0402_1%
1 1 2 S_IMR@

C371
10U_0603_6.3V6M LTW-C193TS5-C_WHITE
2 SC50000BB10
S_IMR@

ME@
SP02001C500
B CVILU_CI1804M1VRA-NH B
6
Battery ( White )
5 GND LED3
GND
4 BATT_CHG_LED# 1 2 R376 1 2 412_0402_1%
3 4 <32> BATT_CHG_LED# +VL
<32> EC_FAN_PWM1 3
2 YOGA@
<32> EC_FAN_SPEED1 +5VS_FAN 1 2 LTW-C193TS5-C_WHITE
1 SC50000BB10 LED3 R376
JFAN1 YOGA@ LTW-C193TS5-C_WHITE 412_0402_1%
SC50000BB10 S_AL@
LED6 S_AL@

1 2 R376
1K_0402_1%
S_IMR@
LTW-C193TS5-C_WHITE
SC50000BB10
S_IMR@

Battery (amber)
LED4
BATT_LOW_LED# 1 2 R378 1 2 442_0402_1%
<32> BATT_LOW_LED#
A +VL
YOGA@
LTST-C191KFKT-2CA_ORANGE
SC500005930 LED4 R378
LTST-C191KFKT-2CA_ORANGE 182_0402_%
YOGA@ SC500005930 S_AL@ Power (White) Battery(White) Battery(amber)
S_AL@ LED / Res. LED / Res.
LED7
LED / Res.
R378 YOGA R376 R378
A 1 2 412_0402_1% TOP (YOGA@) IO Board LED3 412 Ω LED4 A
A S_IMR@
442 Ω
S series R377 R376 R378
LTST-C191KFKT-2CA_ORANGE TOP (S_AL@) LED2 412 Ω LED3 412 Ω LED4 182 Ω
SC500005930
S_IMR@ S IMR R377 R376 R378
BOT (S_IMR@) LED5 1K Ω LED6 1K Ω LED7 412 Ω

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2017/06/05 Deciphered Date 2018/06/05 Title
FAN / LED / Thermal Senser
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 2.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E541P
Date: Wednesday, June 21, 2017 Sheet 36 of 51
5 4 3 2 1
A B C D E

DC to DC

1
+3VALW
J4
+3VS RF 1

2 1
+VL 2 1

0.1U_0201_10V K X5R

10U_0603_6.3V6M
JUMP_43X79 +3VS +3VS +5VALW +VGA_CORE +3VS +VCCGT

10U_0603_6.3V6M

0.1U_0201_10V K X5R
1 1 1 1
+3VALW to +3VS

C381

C382

C384

C385

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R
@ @ 2 2 2 2 2 2

@RF@

CC53

@RF@

CC99

@RF@

CC100
@RF@

CC104

@RF@

CC105

@RF@

CC121
2 2 2 2
U381
1 14 +3VALW_3VS 1 1 1 1 1 1
2 VIN1 VOUT1 13
VIN1 VOUT1
3 12 C383 1 2
ON1 CT1 470P_0402_50V7K
4 11 +VCCGT
<13,32,42> SUSP# VBIAS GND +5VS
5 10 1 2 220P_0402_50V7K
+5VALW ON2 CT2 C386 J5 +1.0VALW +1.0VALW +VCCSA +VCCGT +VGA_CORE +VCCGT +VGA_CORE
6 9 +5VALW_5VS 2 1
VIN2 VOUT2 2 1

10U_0603_6.3V6M

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R
7 8
VIN2 VOUT2
10U_0603_6.3V6M

0.1U_0201_10V K X5R
JUMP_43X79 1 1 2 2 2 2
0.1U_0201_10V K X5R

C389

C390

@RF@

CC122

@RF@

CC123

@RF@

CC124

@RF@

CC125
1 1 15 2 2 2
GPAD
C387

C388

@RF@

CC118

@RF@

CC119

@RF@

CC120
@
@ EM5209VF_DFN14_3X2
SA00007PM00 2 2 1 1 1 1
2 2 1 1 1

+5VALW to +5VS
+3VS +3VS +1.0VALW +VCCCORE +1.0VALW +1.0VALW

2 2

Discharge Screw Hold


CPU VGA NGFF Shielding Clip
Larger
H1 H2 H3 H4 H5 H6 H7 CLIP1 CLIP10 CLIP11 CLIP12
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA

@ @ @ @
For +1.8VALW Discharge For +0.6VS Discharge

1
H_3P3 H_3P3 H_3P3 H_3P3 H_3P3 H_3P2 H_3P2
3 3
+5VALW +1.8VALW Smaller
CLIP2 CLIP3 CLIP4 CLIP5 CLIP6 CLIP7 CLIP8 CLIP9 CLIP14
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
1

+0.6VS
R401 R402
100K_0402_1% 22_0603_1% +5VALW @ @ @ @ @ @ @ @ @
KB

1
1
2

R411
1

@
3

D R412 470_0402_5% H8 H9 H10 H11 H12 H13


1.8VALW_PWR_EN# 5 @ HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
1 2

G 100K_0402_5%
2

S D
LASER BARCODE
4

1
Q401B SUSP 2 Q411
2N7002KDW_SOT363-6 G 2N7002K_SOT23-3
1

S @
D H_4P6X6P1 H_4P6X6P6 H_2P5-G H_2P5-G H_2P5-G H_2P5-G
3

SUSP# 2 Q412 CODE1 @ CODE2 @


6

D G 2N7002K_SOT23-3
2 S @
<32,35,41,43> 3V/5VALW_PG G
3

S
1

Q401A BARCODE_8X8 BARCODE_12X4


2N7002KDW_SOT363-6

H17 H15 H16


FD1 FD2 FD3 FD4 HOLEA HOLEA HOLEA CODE3 @ CODE4 @

4 4
1

1
H_3P5X2P5N H_2P0N H_3P5X2P5N
BARCODE_20X4 BARCODE_10X10

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2017/06/05 Deciphered Date 2018/06/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC to DC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 2.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E541P
Date: Wednesday, June 21, 2017 Sheet 37 of 51
A B C D E
5 4 3 2 1

D D

ACES_50278-00401-001 PL101 EMI_90W@


6
G2 5 PF101
5A_Z120_25M_0805_2P
1 2
+19V_VIN
G1 4 APDIN 7A_32VDC_0437007.WRML
4 3 1 2 +19V_APDIN
3 2
2 1 EMI@
1

1000P_0402_50V7K

1000P_0402_50V7K
100P_0402_50V8J

100P_0402_50V8J
1 2
@ JDCIN1
PL102

1
EMI@ PC101

EMI@ PC102

EMI@ PC103

EMI@ PC104
5A_Z120_25M_0805_2P

2
C C

2
PR101
+CHGRTC
45.3K_0603_1%

PR102
1.5K_0603_5%
1

1 2
PD101
+3VLP
S SCH DIO BAS40CW SOT-323
2
+RTCBATT 1
3 PR103
1K_0603_5%
1 2
B +CHGRTC_R B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR- DCIN / Vin Detector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. KBL
Date: Wednesday, June 21, 2017 Sheet 38 of

5 4 3 2 1
5 4 3 2 1

D D

EMI@

VMB2 +8.4V_VMB PL201 5A_Z120_25M_0805_2P


1 2
PF201
JBAT1
1 1 2
1 2 +12.6V_BATT+
EMI@
2 3 EC_SMCA PL202
3 4 EC_SMDA 15A_24V_F1206HB15V024TM 1 2
4
5
5 +EC_VCCA
6 5A_Z120_25M_0805_2P
6
1

7 1

16.5K_0402_1%
7

1
100_0402_1%

100_0402_1%
8

1
8 9 PC201 EMI@ PC202 EMI@

PR206
C GND C
10 1000P_0402_50V7K 0.01U_0402_25V7K

2
GND
PR201

PR202

11
2

GND 12
GND

2
SUYIN_125022HB008M200ZL <32> VCIN0_PH1
CONN@

1
EC_SMB_CK1 <32,40>
PH201
EC_SMB_DA1 <32,40> 100K +-1% 0402 B25/50 4250K
1 2
+3VLP
PR203

2
1 2 200K_0402_1% +3VALW
PR204
@ 200K_0402_1%
1 2
PR205
VCIN1_BATT_TEMP <32,40> PH201 under CPU botten side :
10K_0402_5%
CPU thermal protection at 93 +-3 degree C
Recovery at 56 +-3 degree C ECAGND

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2017/06/05 Deciphered Date 2018/06/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR- BATTERY CONN/OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 2.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. KBL
Date: Wednesday, June 21, 2017 Sheet 39 of 51
5 4 3 2 1
5 4 3 2 1

Module model information


ISL95520_Hybrid_Boost_V2.mdd
D D

Protection for reverse input

Vgs = 20V
Vds = 60V
Id = 250mA

1
D
2 PQ707
G L2N7002WT1G_SC70-3
S max Power loss 0.22W for 90W;0.12W for 65W system;0.05W for 45W B+

3
Rds(on) = 15.8mohm max CSR rating: 1W
1 2 1 2
Vgs = 20V VCSIP-VCSIN spec < 81mV
PR738 PR737 Vds = 30V
1M_0402_1% 3M_0402_5% ID = 10.5A (Ta=70C)
PQ740 +19V_P1 PQ712
Need check the SOA for inrush EMB04N03H 1N EDFN5X6-8 AON7506_DFN33-8-5 PR913 EMI@ PL704
1 1 +19V_P2 0.01_1206_1% 1UH_2.8A_30%_4X4X2_F +19VB_CHG
2 2
5 3 3 5 1 4 1 2
+19V_VIN

PC765 @EMI@

EMI@
2200P_0402_25V7K
2 3 Isat: 10A

10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V7K
DCR: 14mohm

1
CSIN_CHG_R
CSIP_CHG_R

PC760

PC762

PC1236
2

2
1
2_0402_5%
1

PR740
0_0402_5%
PR772
C C

1
392K_0402_1%
PR729

2
ASGATE_CHG_R @

2
PC747
2 PQ705

4.02K_0402_1%

4.02K_0402_1%
1 2
AON7506_DFN33-8-5
1

1
0.1U_0402_25V6 2
5 3

PR745
PR729 and PR732 are ACDET set t i ng base on your proj ect to set

PC750 0.22U_0603_25V7K
100_0402_1%

4
PR762

PR763
1 2 +12.6V_BATT+ Rds(on) = 32mohm max
Vgs = 20V
Vds = 30V
1

CMSRC_CHG
2200P_0402_50V7K
49.9K_0402_1%

ID = 8A (Ta=70C) @ PC779
1
PR732

PC715

1
ASGATE_CHG 1 2
2

BGATE_CHG
2

OPCN_CHG 2
0.1U_0402_25V7K

CSIN_CHG
CSIP_CHG

OPCP_CHG

VBAT_CHG
0x3CH <BIT9> PSYS current gain
Rs1 = 10mΩ and Rs2 = 5mΩ o r Rs 1 = 10m Ω a nd R s2 = 10m
Ω Rds(on) = 32mohm max
1 VDD_CHG

BIT0 = 1.14uA/W Vgs = 20V


BIT1 = 0.285uA/W Vds = 30V

5
=========================================================
Rs1 = 20mΩ and Rs2 = 10mΩ or Rs1 = 20mΩ and Rs2 = 20 m
Ω PU703
ID = 8A (Ta=70C) PQ305
100K_0402_1%

support Turbo boost : 2200P Support max charge 3.5A

32

31

30

29

28

27

26

25
BIT0 = 2.28uA/W no support Turbo boost : 0.1u IC_ISL88739HRZ-T_QFN_32P_CHARGER
BIT1 = 0.57uA/W AON7408L_DFN8-5 Power loss: 0.245W
PR741

7X7X3

CSIP

ASGATE

QPCP

BGATE
CSIN

CMSRC

OPCN

VBAT
PC721 4 CSR rating: 1W
PR771 2.2_0603_5% 0.22U_0603_25V7K
Isat: 6.5A VCSPP-VCSON spec < 81mV
ACIN_CHG 1 24 BST_CHG 1 2 BST_CHG_R 1 2 DCR: 28mohm
2

ACIN BOOT
Ipsys = KPSYS  x VAD P x IAD P + VBA T
( T
x IBA ) PL700 PR765
2 23 UG_CHG 0.01_1206_1%
R_Psys = 1.2V / Ipsys

3
2
1
KPSYS = 1.14uA/W <32> VCIN1_AC_IN @ ACOK UGATE 4.7UH_5.5A_20%_7X7X3_M +12.6V_BATT+
1

B LX_CHG +17.4V_BATT_CHG B
158K_0402_1%

adapter wattage = 45W PR769 1 2 0_0402_5% 3 22 1 2 1 4


<32,39> EC_SMB_DA1 SDA PHASE
PR731

Battery wattage = 40Wh @


LG_CHG

680P_0603_50V7K 4.7_1206_5%
PR770 1 2 0_0402_5% 4 21 2 3
Ipsys = 1.14 x (45+40) = 96.9uA <32,39> EC_SMB_CK1 SCL LGATE

10U_0603_25V6M
EMI@ PR766

10U_0805_25V6K

10U_0805_25V6K
@
R_Psys = 1.2V / 96.9uA = 12.3K-ohm.

5
PR777 1 2 0_0402_5% 5 20 VDDP_CHG PQ706
2

===================================== <32> VCOUT1_PROCHOT# PROCHOT# VDDP

AON7752_DFN3X3EP8-5
@

1
adapter wattage = 65W 2 0_0402_5% AMON_ISL95520 6 VDD_CHG

PC775

PC776

PC761
PR780 1 19 1 2
Battery wattage = 40Wh <32> ADP_I AMON VDD

2
Ipsys = 1.14 x (65+40) = 119.7uA 7 18 PR760 4.7_0402_5%

2
BMON DCIN

1
R_Psys = 1.2V / 96.9uA = 10K-ohm. 4

BATGONE
Close to EC. 8 17 PC768 PC769
<46> PMON_SKYLAKE PSYS NTC

EMI@ PC767
1U_0402_16V6K 1U_0402_16V6K

CCLIM

2
ACLIM
COMP
PROG
AGND

CSON

CSOP
FSET
PR757

1
10K_0402_1%

100K_0402_1%

3
2
1

2
1

1
PR727

PC748
1000P_0402_25V8J PD703
33

10

11

12

13

14

15

16
**Design Notes** Follow adapter and PR743 10_1206_5% 3
+19V_VIN
2

battery wattage in @ 1 2 1
For 45W/65W /90W system, 2S/3S/4S battery

3
Close to Vsys current source. 2 PQ710
2

Maximum Charging current 3.5A

2
FSET_CHG

EC.

PC757
1U_0603_25V6K
Base on CPU Core VR design. VF = 0.38V
Maximum Battery discharge power 55W The resistor is pop on CPU VR schematic. SCH DIO BAS40CW SOT-323 LMUN5113T1G_SOT323-3
1

2
#Register Setting

1
PR778
1. 0X3DH bit10 set 0 (default 1) to enable turbo boost function 10K_0402_1%

1
2. Disable turbo when AC only VDD_CHG
VDD=5V
#Circuit Design @ PR1446
2

1 2
1. ACLIM and CCLIM are devider voltage control. BA

1
CCLIM_CHG
2. Use 7X7 choke and 3X3 H/L side MOSFET
200K_0402_1%

0_0603_5% <10,32,42> PM_SLP_S4# 2


A31 connect to BA
1

ACLIM_CHG
Charge current 3A Other team connect to bat t c onn
PR749

PR750
Power loss : 1.79W (H/S=0.227W,L/S=1.2738W,Choke=0.297W) PROG_CHG CSOP_CHG 1 2 CSOP_CHG_R PQ711
200K_0402_1%

BA
Power density : 0.61 (23X16)

3
COMP_CHG
#Protect function PR742 2_0402_5% LTC015EUBFS8TL_UMT3F
2

1
100_0402_1%

1. ACOVP : VCC voltage > 24V


38.3K_0402_1%

@ PR779 Fs=729KHZ ~ +/- 15% PC708


2. SMBus timeout : 0X3DH bit15 set 0 (default 0) to enable 175s(default). BA
1

2 PR755 1

76.8K_0402_1% 0.1U_0402_25V6

2
3. ACOC : OX3CH bit4 set1 release adapter limit function (default:Enable).
PR754

1 2
1

CSON_CHG CSON_CHG_R
182K_0402_1%

560P_0402_50V7K

4. CHGOCP : based on charge current setting 1 2


1
PR753

A A
5. BATOVP : 4.6V/Cell
PC751

@ PQ741 PR776
2
1

6. BATLOWV : No. D
76.8K_0402_1%

@ 0_0402_5%
2
1

VCIN1_AC_IN
0.015U_0402_25V7K

7. TSHUT : 150C 2 PR752 For A31 only.


2

G 154K_0402_1% @ VCIN1_BATT_TEMP <32,39> Turn off Charger IC on battery only.


1
PR751

PC752

S Depend on customer design for


3

L2N7002WT1G_SC70-3 BATGONE(BATT_TEMP) system power consumption.


2

logic high: above 2.4V


2

Battery current limimed by CCLIm Hybrid boost power mode


~ 3.89A. logic low: under 0.8V
Adapter current limimed by ACLIm Cell = 3s
~ 4.33A. PC224
(Rs1 = 10mΩ and Rs2 = 5mΩ or Rs1 = 20mΩ and Rs2 = 10mΩ). (PR779 and PQ741 are for change ACLIm when AC in) 10P_0402_25V8J
1

CC_LIM = VccLIM / 64 x Rs2


=============================================================
Security Classification Compal Secret Data Compal Electronics, Inc.
(Rs1 = 10mΩ and Rs2 = 10mΩ or Rs1 = 20mΩ and Rs2 = 20mΩ). Issued Date 2017/06/05 2018/06/05 Title
CC_LIM = VccLIM / 32 x Rs2
Deciphered Date
PWR_CHARGER
============================================================= THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AC_LIM = Vac_LIM / 32 x Rs1 2.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. KBL
Date: Wednesday, June 21, 2017 Sheet 40 of 51
5 4 3 2 1
A B C D E

Module model information


SY8286B_V3_single.mdd
SY8286B_V3_dual.mdd
keep short pad,
snubber is for EMI only.

B+ PU501
EMI@ SY8286BRAC_QFN20_3X3 @ PR502 PC504
PL503
0_0402_5% 0.1U_0201_10V6K
+19VB_3V BST_3V BST_3V_R

2200P_0402_50V7K
1 1 2 1 2 1 2 1
Use 7x7x3 size when the layout space is enough.

10U_0805_25V6K

10U_0805_25V6K
@EMI@ PC501

EMI@ PC502
0.1U_0402_25V6
5A_Z120_25M_0805_2P

1
PL501

PC529

PC503
1.5UH_6A_20%_5X5X3_M

BS
IN

IN

IN

IN
@RF@

2
PC11192 LX_3V6 20 LX_3V 1 4
+3VALWP

2
22P_0402_50V8J LX LX
7 19 2 3
GND LX

22P_0402_50V8J
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

@RF@ PC531
4.7_1206_5%
1

1
PR503
RF@
8 18
+3VL GND GND

PC505

PC506

PC507

PC508
9 17
+3VLP

2
PG LDO

1
10 16

3V_SN2
NC NC

1
Check pull up resistor of SPOK at HW side PC509

OUT
EN2

EN1
21

NC
4.7U_0603_6.3V6M

FF

2
GND

680P_0603_50V7K
PR501
100K_0402_5%

11

12

13

14

15

1
RF@
2
3.3V LDO 150mA~300mA Vout is 3.234V~3.366V

PC510
<32,35,37,43> 3V/5VALW_PG

2
ENLDO_3V5V PC511 PR504
Iocp=10A
1000P_0402_25V8J 1K_0402_1%
TDC=6A
5V_3V_EN 3V_FB 1 2 3V_FB_1 1 2
PR510
2.2K_0402_5%
1 2 EN1 and EN2 dont't be floating.
<32,35> EC_ON @ PR511 EN :H>0.8V ; L<0.4V Fsw : 600K Hz @ PJ502
0_0402_5% 1 2
1 2 +3VALWP 1 2 +3VALW
2 <32> VCOUT0_MAIN_PWR_ON JUMP_43X118 2

@ PJP502
5V_3V_EN JUMP_43X39
1 2
+3VLP 1 2 +3VL
1M_0402_1%

4.7U_0402_6.3V6M

EN1 and EN2 dont't be floating.


1

EN :H>0.8V ; L<0.4V
1
PR513

PC527

Fsw : 600K Hz
2
2

keep short pad,


2 Cell battery : Cin=10uF*2pcs snubber is for EMI only.
3 Cell ~ 4 Cell battery : Cin=10uF*1pcs
B+ +19VB_5V
PR506 EMI@ @ PR505 PC512
PL504
499K_0402_1% PU502 SY8288CRAC_QFN20_3X3 0_0402_5% 0.1U_0201_10V6K
1 2 ENLDO_3V5V 1 2 +19VB_5V BST_5V1 2 BST_5V_R 1 2
B+
1

1
PR508 5A_Z120_25M_0805_2P
1

PL502

BS
IN

IN

IN

IN
150K_0402_1% PC532
LX_5V 6
2200P_0402_50V7K
10U_0805_25V6K

10U_0805_25V6K

1U_0402_16V6K
0.1U_0402_25V6

20 3.3UH_PIMB104T-3R3MS_10A_20%
2

LX LX
2

7 19 LX_5V 1 2
GND LX +5VALWP
1

1
PC513

PC514

EMI@ PC515

@EMI@ PC516

8 18
GND GND PC517

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
2

1
3 9 17 VCC_5V 1 2 3
PG VCC

4.7_1206_5%
PR507

PC519

PC520

PC518

PC521
RF@
10 16

2
NC NC 4.7U_0603_6.3V6M
OUT

LDO

+3VLP
EN2

EN1

21
FF

GND

2
11

12

13

14

15
1

+5VLP

1 5V_SN
4.7U_0603_6.3V6M

@ PR509 3V/5VALW_PG
1

680P_0603_50V7K
PC524

@ PR516 100K_0402_5%
0_0402_5%
2

ENLDO_3V5V 1

PC525
RF@
2
2

2
PR517 5V_3V_EN
0_0402_5%
Vout is 4.998V~5.202V
1 2
1

<32> 5VLDO_EN
100K_0402_5%
4.7U_0402_6.3V6M

TDC=6A Iocp=10A
PR518

PC526 PR512
1

PC530

1000P_0402_25V8J 1K_0402_1%
5V_FB 1 2 5V_FB_1 1 2
@
2

+19VB_5V @ PJ504
1 2
+5VALWP 1 2 +5VALW
JUMP_43X118
1

@ PJP504
4 PR514 JUMP_43X39 4
1 2
560K_0402_5% +5VLP 1 2 +VL
2

VCIN1_BATT_DROP <32>
1

PR515 PC528
1000P_0402_25V8J
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2017/06/05 Deciphered Date 2018/06/05 Title
2

105K_0402_1%
+3VALW/+5VALW
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 2.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. KBL
Date: Wednesday, June 21, 2017 Sheet 41 of 51
A B C D E
5 4 3 2 1

Pin19 need pull separate from +1.35VP.


EMI@ PL601
If you have +1.35V and +0.675V sequence question, 0.675Volt +/- 5%
5A_Z120_25M_0805_2P you can change from +1.35VP to +1.35VS. TDC 0.7A
B+ +12.6VB_DDR Peak Current 1A
1 2 PR601
2.2_0603_5%
BST_DDR_R 1 2 BST_DDR

2200P_0402_50V7K

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
+1.2VP

1
PC601

PC602

PC603

PC604
UG_DDR +0.6VSP

2
EMI@
@EMI@
D D
LX_DDR

10U_0603_6.3V6M

10U_0603_6.3V6M
1

1
PC605

5
0.1U_0603_25V7K

PC606

PC607
16

17

18

19

20
2
PU601

2
VLDOIN
PHASE

UGATE

BOOT

VTT
21
PAD
PQ601 4 LG_DDR 15 1
LGATE VTTGND
AON7408L_DFN8-5
PL603 14 2
1UH_11A_20%_7X7X3_M PR602 PGND VTTSNS

1
2
3
13K_0402_1%
1 4 1 2 CS_DDR 13 3
+1.2VP PQ602
PC608 CS RT8207PGQW _W QFN20_3X3 GND

1
2 3 1U_0402_10V6K

5
AON7506_DFN33-8-5 1 2 12 4 VTTREF_DDR
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

RF@ PR603 PR604 VDDP VTTREF


1

4.7_1206_5% 5.1_0603_5%
PC609

PC610

PC611

PC612

PC613

PC614

1 2 VDD_DDR 11 5
+5VALW +1.2VP

1 2
VDD VDDQ

1
PGOOD
2

4 PC616
+5VALW PR605

TON
1
RF@ PC615 0.033U_0402_16V7K

FB
S5

S3

2
680P_0402_50V7K PC617 1 2

2
1U_0402_10V6K 5.1_0603_5%

10

6
1
2
3
C C

EN_DDR

EN_0.675VSP

FB_DDR
TON_DDR
PR607
MOSFET: 3x3 DFN 1 2 +1.2VP
PR608 470K_0402_1%
H/S Rds(on): 27mohm(Typ), 34mohm(Max) +12.6VB_DDR1 2
Idsm: 7.5A@Ta=25C, 5.5A@Ta=70C 6.04K_0402_1%

1
L/S Rds(on): 19mohm(Typ), 23.5mohm(Max) PR609
Idsm: 11A@Ta=25C, 8.8A@Ta=70C @
PR610
0_0402_5% 10K_0402_1%
1 2
<13,32> SYSON

2
Mode Level +0.675VSP VTTREF_1.35V Choke: 7x7x3
S5 L off off Rdc=6.7mohm(Typ), 7.4mohm(Max)

1
@ PC618
S3 L off on 0.1U_0402_10V7K
S0 H on on Switching Frequency:540kHz

2
Ipeak=8A
Note: S3 - sleep ; S5 - power off Iocp~9.6A @
PR611
OVP: 113%~120% 0_0402_5%
VFB=0.75V, Vout=1.3545V 1 2 @ PJ601
<13,32,37> SUSP# +1.2VP 1 2 +1.2V
1 2
PR606
+3VALW +5VALW @ 0_0402_5% JUMP_43X118
1 2
<7> DDR_VTT_PG_CTRL

1
@ PC619
1

B 0.1U_0402_10V7K B

2
1

PC620 @ PJ604
1

1U_0402_6.3V6K 1 2
JUMP_43X79 +0.6VSP 1 2 +0.6VS
2

@ PJ603
2

JUMP_43X39
Vout=0.8V* (1+Rup/Rdown)
2

PU602
APL5930KAI-TRG_SO8
1

PC621 6
4.7U_0603_6.3V6K 5 VCNTL 3
9 VIN VOUT 4
PR612
2

@ 0_0402_5% VIN VOUT


+2.5VP PJ605
1

1 2 8 @
3.4K_0402_1%

0.01U_0402_25V7K

<10,32,40> PM_SLP_S4# EN
1

7 2 +2.5VP 1 2 +2.5V
GND

POK FB 1 2
PR614

PC622

22U_0603_6.3V6M
1

JUMP_43X79
Rup
0.1U_0402_16V7K

PR615
PC623

47K_0402_5% PC624
2

2
2

1.6K_0402_1%
PR616

Rdown
2

A Ultra Low Dropout 0.23V(typical) at 3A Output Current A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2018/06/05 Title
2017/06/05 Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RT8207P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 2.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. KBL
Date: Wednesday, June 21, 2017 Sheet 42 of 51
5 4 3 2 1
5 4 3 2 1

Module model information


APL5930_V2.mdd

D D

+3VALW +5VALW

Ultra Low Dropout 0.23V(typical) at 3A Output Current

1
PC701

1
1U_0402_6.3V6K
JUMP_43X79

2
@ PJ701

2
2
PU701
APL5930KAI-TRG_SO8

1
C PC702 6 C
4.7U_0603_6.3V6K 5 VCNTL 3
9 VIN VOUT 4 PJ702
@
PR701
+1.8VALWP

2
@ 0_0402_5% VIN VOUT 1 2
+1.8VALWP 1 2 +1.8VALW

1
1 2 8

12.7K_0402_1%

0.01U_0402_25V7K
<32,35,37,41> 3V/5VALW_PG
7 EN

1
2 JUMP_43X79

GND
POK FB

PR703

PC703

22U_0603_6.3V6M
1

0.1U_0402_16V7K
Rup

1
PC704
PR704

2
2

PC705
1M_0402_5%

2
@ PR702
2

100K_0402_5%

10K_0402_1%
1

PR705
Rdown

2
+3VALW
PGOOD <44>
Vout=0.8V* (1+Rup/Rdown)

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2017/06/05 Deciphered Date 2018/06/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
APL5930
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 2.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. KBL
Date: Wednesday, June 21, 2017 Sheet 43 of 51
5 4 3 2 1
A B C D E

Module model information


SY8286_V1_single.mdd
SY8286_V1_dual.mdd

+3VALW
Confirm HW side

1
+19VB_1V @ PR803 keep short pad, RF@ PR802 RF@ PC802
1 1
10K_0402_5% snubber is for EMI only. 4.7_1206_5% 680P_0603_50V7K
1 2 SNUB_1V 1 2
EMI@
PL802 PU801

2
+19VB_1V
B+ 1 2 2
IN PG
9 @ PR804
0_0402_5%
PC805
0.1U_0201_10V6K
Use 7x7x3 size when the layout space is enough.

10U_0805_25V6K
0.1U_0402_25V6
5A_Z120_25M_0805_2P 3 1 BST_1V 1 2 BST_1V_R 1 2

2200P_0402_50V7K
IN BS PL801

1
EMI@ PC801

@EMI@ PC803

PC804
LX_1V
4
IN LX
6 1 2
+1.0VALWP

2
5 19 1UH_6.6A_20%_5X5X3_M

14.3K_0402_1%

330P_0402_50V7K

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
IN LX

1
7 20

PR805

PC806

PC807

PC808

PC809

PC810

PC814

PC815
GND LX
8 14 FB_1V R1

2
GND FB @ @

2
18 17 LDO_3V
PR801 GND VCC
@ 0_0402_5%

1
1 2 EN_1V 11 10
<43> PGOOD EN NC PC811 FB=0.6V

1
ILMT_1V 13 12 2.2U_0402_6.3V6M

2
ILMT NC
1

@ PC812
PR806 15 16 PR807
1M_0402_1%
0.1U_0402_25V6 +3VALW BYP NC Vout=0.6V* (1+R1/R2) R2 20K_0402_1%
2

+3VALW
21 =0.6*(1+(14.3/20)) @ PJ802

2
PAD JUMP_43X118
2

EN :H>0.8V ; L<0.4V SY8286RAC_QFN20_3X3 1 2


Vout=1.029V +1.0VALWP 1 2 +1.0VALW

1
PC813
EN pin don't floating
1

@ 1U_0402_6.3V6K

2
If have pull down resistor at HW side, PR808
please delete PR601. 0_0402_5%
2

2 2

The current limit is set to 6A, 9A or 12A when this pin


is pull low, floating or pull high.

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2017/06/05 Deciphered Date 2018/06/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SY8286
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 2.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. KBL
Date: Wednesday, June 21, 2017 Sheet 44 of 51
A B C D E
5 4 3 2 1

CPU CORE

PSYS:
OCP for VCCSA Please confirm charger pull low resistance.
PMON_SKYLAKE <40>
D Charger side should be unpop. D

U42@ PRI5
19.1K_0402_1% PRI1
PCI1
1.5K_0402_1%
1 2 1 2
PRI2, PRI8 place near CPU side.
If the resisters are at HW side and POP. PRI2, PRI8 can be canceled. 8200P_0402_25V7K
PCI3 COMP_1b_CPU 1 2 PCI2
1000P_0402_50V7K 15P_0402_50V8J
+VCCSA PRI2 1 2 PRI69

1000P_0402_50V7K
100_0402_1% 10_0402_5%
1 2 PRI4 1 2
PRI3

1
@ 0_0402_5% 1.78K_0402_1% CSN_1b_VCCSA <47>

U22@ PRI5
24K_0402_1%

1
1 2 VSPP_1b_CPU_R 1 2 VSP_1b_CPU
<13> VCCSA_SENSE

2200P_0402_50V7K
PHI1

PCI4
Close to SA choke

1200P_0402_50V7K
2
1
RDRPSP

PCI36
100K_0402_1%_B25/50 4250K

0.01U_0402_25V7K

1
PCI5 PRI7
PRI6

2
@ 0_0402_5% 1000P_0402_50V7K 1K_0402_1%

PCI7
2

1 2
1

1
1 2 VSNN_1b_CPU_R 1 2 VSN_1b_CPU CSN_1b_VCCSA_NTC

PCI6
<13> VSSSA_SENSE

2
1 2 1 2 PRI9

2
PRI8 100_0402_1% PCI8 2200P_0402_25V7K 12K_0402_1%
+VCCCORE PRI10 CSP_1b_VCCSA +3VS
1 2 CSP_1b_VCCSA_R <47>

2
1 2 20K_0402_1% U22@ PRI14 1 2
PRI13

1
PRI11 100_0402_1% @ 0_0402_5% 68.1K_0402_1% 7.5K_0603_1%
1 2 VSP_2ph_CPU 1 2 U42@ PRI14 PRI12 PRI15
<15> VCCCORE_SENSE
57.6K_0402_1% 10K_0402_1%

1
1 2
<15> VSSCORE_SENSE PCI9 PRI18 PCI10 470P_0402_50V7K
PRI17

2
@ 0_0402_5% 1000P_0402_50V7K 806_0402_1% VR_PWRGD <32>

100P_0402_50V8J
2
1 2 1 2 VSN_2ph_CPU_R 1 2 VSN_2ph_CPU
PRI16 100_0402_1%
1 2 IMVP8_EN

PCI35
1
U42@ PRI20
Upper Threshold > 0.8V +1.0V_VCCST ESD@
909_0402_1% PCI11 3300P_0402_25V7K
Lower Threshold < 0.3V

1
C C

2
PRI19

1
PRI11, PRI16 place near CPU side. 49.9_0402_1% U22@ U22_SKL@ PRI23 U42@ PRI23
If the resisters are at HW side and POP. PRI11, PRI16 can be canceled. PRI20 28.7K_0402_1% 23.2K_0402_1% @ PRI21 0_0402_5%
RIOUT@CORE 1 2

110_0402_1%

100_0402_1%
45.3_0402_1%
1 2
VR_ON <32>

IOUT_1b_CPU
ILIM_1b_CPU
604_0402_1%

470P_0402_50V7K
2
PCI12

EN_CPU
PWM_1b_CPU <47>

1
470P_0402_50V7K

2
CSCOMP_2ph_CPU_R

Close to CORE choke DRVON <47>

1
PRI23 U22_KBL@ PRI24 @

PCI13
25.5K_0402_1% PCI14 110_0402_1% PRI34

1
1

4.75K_0402_1%
PHI2 7.5K_0603_1%

49

48
47
46
45
44
43
42
41
40
39
38
37
0.1U_0402_25V6

2
220K_0402_5%_B25/50 4700K @ 1 2
CSP1_VGT1 <47>

PRI25

1
1
1 2

VSN_2ph
VSP_2ph

VSP_1b
VSN_1b
COMP_1b
ILIM_1b
CSN_1b
CSP_1b
IOUT_1b

EN
TAB

PSYS

VR_RDY

2
U42@ PRI39 PCI15 PUI1 VR_HOT# <32> PRI29

PRI26

PRI27

PRI33
16.9K_0402_1% 15P_0402_50V8JIC NCP81218MNTXG QFN 48P 12K_0402_1% Close to GT choke
2

1 2
PRI31 PRI32 IOUT_2ph_CPU 1 36 PCI17 1 2

0.01U_0402_25V7K
165K_0402_1% 75K_0402_1% DIFFOUT_2ph_CPU 2 IOUT_2ph PWM_1b 35 PRI36 49.9_0402_1% 470P_0402_50V7K CSN1_VGT_NTC

0.022U_0402_16V7K
1 2 1 2 1 2 U22@ PRI39 PCI16 FB_2ph_CPU 3 DIFFOUT_2ph DRVON 34 SCLK_CPU 1 2 1 2
<47> CSP_1a_VCORE_R FB_2ph SCLK VR_SVID_CLK <15>
1

1
PRI30 100K_0603_1% 9.76K_0402_1% 2200P_0402_50V7K COMP_2ph_CPU 4 33 ALERT#_CPU PRI37 1 2 @ 0_0402_5%

PCI20
VR_ALERT# <15>
ILIM_2ph_CPU 2 COMP_2ph ALERT# SDIO_CPU

100K_0402_1%_B25/50 4250K
1 2 PCI18 PCI19 1 2 5 32 PRI40 1 2 10_0402_1% PRI42 PHI3

PCI21
<47> CSP_2a_VCORE_R ILIM_2ph SDIO VR_SVID_DATA <15>

1
PRI38 U42@ 100K_0603_1% 1000P_0402_50V7K 100P_0402_50V8J CSCOMP_2ph_CPU 6 31 VR_HOTL# PRI41 1 2 100_0402_1% 61.9K_0402_1%
2

CSSUM_2ph_CPU 7 CSCOMP_2ph VR_HOT# 30 IOUT_1a_CPU 1 2 PRI70


1 2 CSREF_2ph_CPU 8 CSSUM_2ph IOUT_1a 29 CSP_1a_VCORE 10_0402_5%
<47> CSN_2a_VCORE

2
PRI43 U42@ 10_0402_1% CSP2_2ph_CPU 9 CSREF_2ph CSP_1a 28 1 2
CSP2_2ph CSN_1a
1

1 2 CSP1_2ph_CPU 10 27 ILIM_1a_CPU

ROSC_COREGT
<47> CSN_1a_VCORE
0.1U_0402_25V6

0.1U_0402_25V6

2200P_0402_50V7K
PRI44 10_0402_1% TSENSE_2ph_CPU_R 1 2 TSENSE_2ph_CPU 11 CSP1_2ph ILIM_1a 26 COMP_1a_CPU

ADDR_VBOOT
TSENSE_2ph COMP_1a
1

TSENSE_1ph
RSOC_SAUS

ICCMAX_2ph
1 2 12 25
PCI22

U42@ PCI23

PCI37
ICCMAX_1a
ICCMAX_1b
PCI24
2

VRMP VSN_1a

PWM1_2ph
PWM2_2ph

1
PCI26 @ PRI45 0_0402_5% PRI46 3300P_0402_50V7-K

VRMP_CPU
+19VB_CPU 1K_0402_1%

PWM_1a
1

1 2 VSN_1a_CPU_R PCI25 PCI29

VSP_1a
2

0.22U_0402_25V6K PRI48 15P_0402_50V8J 1500P_0402_50V7K

VCC

1 2

2
1

1
PHI4 61.9K_0402_1% PCI28 PRI49 @ PRI50 PRI51 <47> CSN1_VGT1
1000P_0402_50V7K 909_0402_1% 0_0402_5% 100_0402_1%

1
CSP_1a_VCORE_R 1 2 PCI30 VSN_1a_CPU
1 2 1 2 1 2 PRI52
2

13
14
1ROSC_SAUS_CPU 15
16
17
18
19
20
21
22
23
24

2
PRI47 2.15K_0402_1% 100K_0402_1%_B25/50 4250K 0.01U_0402_50V7K 2.49K_0402_1%

1
CSP_2a_VCORE_R 1 2 PCI31 PCI27
VSSGT_SENSE <15>

2
PRI54 U42@ 2.15K_0402_1% 1000P_0402_50V7K

ICCMAX_2ph_CPU

2
VCC_CPU

ADDR_VBOOT_CPU
B B

ICCMAX_1a_CPU
ICCMAX_1b_CPU
1000P_0402_50V7K

1
+5VS PRI55 PRI56 @ PRI57
1 2 2_0402_1% 2.94K_0402_1% 0_0402_5% +VCCGT PRI53
+5VS U22@ PRI118 1 2 1 2VSP_1a_CPU_R 1 2 36.5K_0402_1%
VCCGT_SENSE <15>
1K_0402_1%
VSP_1a_CPU 1

1ROSC_COREGT_CPU
2 1 2 1 2

24K_0402_1%

2
2.94K_0402_1% PRI58 100_0402_1%
1

PCI32 PRI115 OCP for GT

PRI60
PCI33 1000P_0402_50V7K @ PRI61
1U_0603_10V6K 0_0402_5%
2

TSENSE_1ph_CPU 1 2 TSENSE_1ph_CPU_R

1000P_0402_50V7K
33.2K_0402_1%

61.9K_0402_1%
1

1
Fsw for SA

2
PWM_1a_CPU <47> PHI5
PRI59

PCI34
100K_0402_1%_B25/50 4250K

PRI62
51.1K_0402_1%

97.6K_0402_1%

15.8K_0402_1%

35.7K_0402_1%
Fsw for CORE & GT
2

2
1

1
472mV/120uA=3.933K
Active Point110 degreeC = 4.206K
PRI63

PRI64

PRI65

PRI66
U22_KBL@
2

U42@ PRI63
100K_0402_1%
U22@

VBOOT:
Debug setting=51.1K
U22_SKL@ PRI63
45.3K_0402_1%
A A
PWM2_2ph_CPU <47>

PWM1_2ph_CPU <47>

U42@ PRI65
19.1K_0402_1%

Title
NCP81218
Size Document Number Rev
2.A

Date: Wednesday, June 21, 2017 Sheet 46 of 51


5 4 3 2 1
5 4 3 2 1

EMI@ PLI1
CPU POWER STAGES 5A_Z120_25M_0805_2P
1 2
InputCapacitor:
EMI@ PLI2
+19VB_CPU 10uF_0805_X5R_25V 5A_Z120_25M_0805_2P B+
1 2

2200P_0402_50V7K
10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6
@EMI@ PCI40

EMI@ PCI41
1 1

33U_25V_NC_6.3X4.5

33U_25V_NC_6.3X4.5
1

1
+ +

PCI38

PCI39

PC135

PC136
2

2
2 2

5
PRI68 PCI42
2.2_0603_5% 0.22U_0603_16V7K PQI6
1 2BST1_VCORE1_R 1 2

BST1_VCORE1
D AON6380 1N DFN5X6-8 D

UG_VCORE1 4

PUI2 VCC_CORE

3
2
1
NCP81151MNTBG_DFN8_2X2 FSW=450kHz
1 8 PLI3 +VCCCORE DCR = 1.19 mohm +/- 5%
BST DRVH
2 7 LX_VCORE1
0.22UH_24A_20%_ 7X7X4_M
1 4
TYP MAX
<46> PWM1_2ph_CPU PWM SW H/S Rds(on) :11.7mohm , 14mohm
DRVON 3 6 2 3
+5VS EN GND L/S Rds(on) :2.7mohm , 3.3mohm

330U_B2_2.5VM_R9M
4 5
PAD

VCC DRVL PQI7 @U42@


1

1
AON6314 1N DFN5X6-8 RF@ PCI94
1

PRI71 CSN_1a_VCORE <46> +


9

PCI43 4.7_1206_5%
2.2U_0603_16V6K LG_VCORE1 4
2

2
SNB_VCORE1 CSP_1a_VCORE_R <46>

3
2
1

1
RF@
PCI45
680P_0603_50V7K

2
+19VB_CPU
C C

2200P_0402_50V7K

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6

PCI55 U42@

PCI56 U42@
@U42_EMI@ PCI53

PCI54
1

1
+19VB_CPU

U42_EMI@
2

2
2200P_0402_50V7K
10U_0805_25V6K

10U_0805_25V6K
PRI73

0.1U_0402_25V6
@EMI@ PCI46

PCI47
1 U42@ PRI74

33U_25V_NC_6.3X4.5
2.2_0603_5% 2.2_0603_5%
BST_VCORE2 2 BST_VCORE2_R

5
+

PCI50

PCI51
1 U42@
BST_VGT1_R

PC148
1 2 PQI9

EMI@
AON6380 1N DFN5X6-8

2
2

1
U42@
BST_VGT1 PCI60 4
1

0.22U_0603_16V7K

2
PCI57 U42@
0.22U_0603_16V7K PQI2 PUI4
2

PUI3 NCP81151MNTBG_DFN8_2X2

3
2
1
NCP81253MNTBG_DFN8_2X2 1 9
BST FLAG
2

1 9 U42@ PLI5
<46> PWM_1a_CPU BST FLAG <46> PWM2_2ph_CPU UG_VCORE2
PLI4 2 8 0.22UH_24A_20%_ 7X7X4_M
D1

G1

2 8 UG_VGT1 0.22UH_24A_20%_ 7X7X4_M +VCCGT PWM DRVH +VCCCORE


PWM DRVH DRVON 3 7 LX_VCORE2 LX_VCORE2 1 4
3 7 LX_VGT1 7 LX_VGT1 1 4 EN SW
<46> DRVON EN SW D2/S1
+5VS 4 6 2 3
VCC GND

4.7_1206_5%
U42_RF@ PRI78
4 6 2 3
RF@

330U_D1_2VY_R9M
VCC GND LG_VCORE2

5
+5VS 5 U42@
G2
S2

S2

S2

LG_VGT1 DRVL 1
1

4.7_1206_5%

5 1 PQI10 PCI93
DRVL

1
AON6992_DFN5X6D-8-7 +

330U_D1_2VY_R9M
U42@ AON6314 1N DFN5X6-8
3

6
1

+ PCI92
PRI77

PCI59 U42@

2
PCI58 2.2U_0603_16V6K

2
2.2U_0603_16V6K 4 CSN_2a_VCORE <46> 2
B B
2

2
LG_VGT1

SNUB_VCORE2 CSP_2a_VCORE_R <46>

3
2
1
SNUB_VGT1

1
1

680P_0603_50V7K

680P_0603_50V7K
2
PCI64 RF@
2

CSN1_VGT1 <46>

U42_RF@ PCI63
CSP1_VGT1 <46>

+19VB_CPU
2200P_0402_50V7K
10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6
@EMI@ PCI67

PCI68
1

1
PCI65

PCI66

EMI@

PRI83 PCI69
2

2.2_0603_5% 0.22U_0603_16V7K
1 2 BST_VCCSA_R 1 2
BST_VCCSA

UG_VCCSA
AON7934
Rds(on)=12.4~15.8m ohm
PUI5 PQI1
4

NCP81253MNTBG_DFN8_2X2 AON7934_DFN3X3A8-10
PLI6
D1

D1

D1

G1

1 8 0.47UH_NA__12.2A_20% +VCCSA
BST DRVH
2 7 10 9 LX_VCCSA 1 4
<46> PWM_1b_CPU PWM SW D1 D2/S1
A A
PRI84

DRVON 3 6 2 3
+5VS EN GND
4.7_1206_5%
G2
S2

S2

S2

4 5
PAD

VCC DRVL
5

RF@
1

9
2.2U_0603_16V6K
PCI70

CSN_1b_VCCSA <46>
2

SNB_VCCSA
680P_0603_50V7K
PCI71
1

LX_VCCSA CSP_1b_VCCSA_R <46> Title


Power Stage
2

LG_VCCSA
RF@

Size Document Number Rev


2.A

Date: Wednesday, June 21, 2017 Sheet 47 of 51


5 4 3 2 1
A
B
C
D
+VCCCORE

5
5

2 1 2 1 2 1
2
1

PC1197 PC1171 PC1153 PC1101


1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
2
1

PC1198 PC1172 PC1154 PC1102


1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
2
1

PC1199 PC1173 PC1155 PC1103


1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
2
1

PC1200 PC1174 PC1156 PC1104


1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
2
1

PC1201 PC1175 PC1157 PC1105


1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
2
1

PC1202 PC1176 PC1158 PC1106


1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
2
1
22U_0603 * 36pcs +1U_0201*35 pcs

PC1203 PC1177 PC1159 PC1107


1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
2
1
VCC_CORE Place on CPU Back Side @ V09

PC1204 PC1178 PC1160 PC1108


1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
2
1

PC1205 PC1179 PC1161 PC1109


1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 2 1

4
4

2
1

PC1180 PC1162 PC1110


1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M

2
1
+VCCSA
2 1 2 1
PC1208
22U_0603_6.3V6M PC1181 PC1163
2
1

1U_0201_6.3V6M 1U_0201_6.3V6M
2 1 2 1 PC1111
22U_0603_6.3V6M
PC1182 PC1164
2
1

1U_0201_6.3V6M 1U_0201_6.3V6M

2
1
2 1 2 1 PC1112
PC1209 22U_0603_6.3V6M
22U_0603_6.3V6M PC1183 PC1165
2
1

1U_0201_6.3V6M 1U_0201_6.3V6M

2
1
PC1113
PC1210 22U_0603_6.3V6M
22U_0603_6.3V6M
2
1

2
1
PC1114
PC1211 22U_0603_6.3V6M
22U_0603_6.3V6M
2
1

2
1
2
1

PC1115
PC1224 PC1166 22U_0603_6.3V6M
U42@

22U_0603_6.3V6M 22U_0603_6.3V6M
2
1

2
1
2
1
2
1

PC1116
PC1212 PC11193 PC1167 22U_0603_6.3V6M
U42@

22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M


2
1

2
1
2
1
2
1

PC1117
PC1213 PC11194 PC1168 22U_0603_6.3V6M
U42@

22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M


2
1

2
1
2
1

PC1118
PC11195 PC1169 22U_0603_6.3V6M
U42@

22U_0603_6.3V6M 22U_0603_6.3V6M
2
1
2
1

22U_0603 * 9 pcs + 1U_0201*7

2
1

PC1214 PC1119

3
3

22U_0603_6.3V6M PC1170 22U_0603_6.3V6M


22U_0603_6.3V6M
2
1
2
1

PC1215 PC1120
VCC_SA Place on CPU Back Side @ V09

22U_0603_6.3V6M 22U_0603_6.3V6M
2
1
2
1

PC1216 PC11196
U42@

22U_0603_6.3V6M 22U_0603_6.3V6M
2
1

PC11197

Issued Date
U42@

22U_0603_6.3V6M
2 1
2
1

Security Classification
PC1217 PC11198
U42@

1U_0201_6.3V6M 22U_0603_6.3V6M
+VCCGT_VCCCORE

2 1
2
1

PC1218 PC11199
U42@

1U_0201_6.3V6M 22U_0603_6.3V6M
2 1
2
1

PC1219
1U_0201_6.3V6M PC1121
2 1 22U_0603_6.3V6M
2
1

PC1220
1U_0201_6.3V6M PC1122

2017/06/05
+VCCGT

2 1 22U_0603_6.3V6M
2
1

PC1221 2 1
1U_0201_6.3V6M PC1123
2 1 PC1206 22U_0603_6.3V6M
1U_0201_6.3V6M
PC1222 2 1 2 1
2
1

1U_0201_6.3V6M
2 1 PC1207 PC1184 PC1137
1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
PC1223 2 1

2
2

2
1

1U_0201_6.3V6M
PC1185 PC1138
Compal Secret Data 1U_0201_6.3V6M 22U_0603_6.3V6M
Deciphered Date
2
1

2 1
2
1

PC1124
PC1186 PC1139 22U_0603_6.3V6M
1U_0201_6.3V6M 22U_0603_6.3V6M
2
1

2 1
2
1

PC1125
PC1187 PC1140 22U_0603_6.3V6M
1U_0201_6.3V6M 22U_0603_6.3V6M
2
1

2 1
2
1

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PC1126
PC1188 PC1141 22U_0603_6.3V6M
1U_0201_6.3V6M 22U_0603_6.3V6M
2
1

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

2 1
2
1

PC1127
2018/06/05
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

PC1189 PC1142 22U_0603_6.3V6M


1U_0201_6.3V6M 22U_0603_6.3V6M 2 1
2 1
2
1

PC1128
PC1190 PC1143 22U_0603_6.3V6M
1U_0201_6.3V6M 22U_0603_6.3V6M
2
1

2 1
C
2
1

PC1129
PC1191 PC1144 22U_0603_6.3V6M
Size
Title

Date:

1U_0201_6.3V6M 22U_0603_6.3V6M
2
1

2 1 2 1
PC1130
PC1192 PC1145 22U_0603_6.3V6M
1U_0201_6.3V6M 22U_0603_6.3V6M
KBL
2
1

2 1
2
1

PC1131
PC1193 PC1235 22U_0603_6.3V6M
1U_0201_6.3V6M 22U_0603_6.3V6M
Document Number
2
1

2
1
2
1

PC1132
PC1194 PC1147 22U_0603_6.3V6M
22U_0603_6.3V6M 22U_0603_6.3V6M
Wednesday, June 21, 2017
2
1
22U_0603 * 32 pcs +1U_0201*12 pcs

1
1

2
1
2
1

PC1133
VCC_GT Place on CPU Back Side @ V09

PC1195 PC1148 22U_0603_6.3V6M


22U_0603_6.3V6M 22U_0603_6.3V6M
2
1

2
1
2
1

PC1134
PC1196 PC1149 22U_0603_6.3V6M
Sheet

22U_0603_6.3V6M 22U_0603_6.3V6M
2
1

2
1

PC1135
Compal Electronics, Inc.

48

PC1150 22U_0603_6.3V6M
22U_0603_6.3V6M
2
1

2
1

of

PC1136
PC1151 22U_0603_6.3V6M
22U_0603_6.3V6M
51
2
1

PC1152
PWR-PROCESSOR_DECOUPLING
Rev

22U_0603_6.3V6M
2.A
A
B
C
D
5 4 3 2 1

3.PWM-VID Spec and component Values

PWM-VID Spec Config A Config B Config C


D D
Vmin 0.6V 0.6V 0.65V
Vmax 1.2V 1.2V 1.15V
Vboot 0.875V 0.9V 0.9V
Voltage step 6.25mV 6.25mV 25mV
N of 96 96 20
Voltage
Rrefadj
level PR8 39K 20K 39K
Rref1 PR7 39K 20K 30K
Module model information:
Rboot PR10 1.5K 2K 3K RT8812A-2P_V1A.mdd for IC portion
PR20 30K 18K 24K RT8812A-2P_V1B.mdd for SW portion
Rref2=PR20+PR21
PR21 1.5K 0 3K
C PC9 1.5nf 2.7nf 1.8nf

Vboot=Vvref*Rref2/(Rref1+Rref2+Rboot)
Rt=Rrefadj // (Rboot+Rref2)
PWM VID and Output voltage control PL903 VGA_EMI@
Vmin= Vvref*[Rref2/(Rref2+Rboot)]*[Rt/(Rref1+Rt)] 1.Boot mode HCB2012KF-121T50_2P
2.Standby mode (don't support) VGA_B+ 2 1
Vmax=Vvref*Rref2/[(Rref1//Rrefadj)+Rboot+Rref2] B+
3.Normal mode

2200P_0402_50V7K
Vout=Vmin+N*Vstep

10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6
VGA_EMI@ PC1480

@VGA_EMI@ PC1491
1

1
PC1473

PC1474
Vstep=(Vmax-Vmin)/Nmax @VGA@
PR1463 VGA@ PR1468 Pull DH1_VGA_1
high on HW side
PSI Pull high on HW side 0_0402_1% 1K_0402_5%

2
1 2 1 2
<22> PSI DGPU_MAIN_EN <22,24>
VGA@

1
PR1458 @VGA@ PR1464 @VGA@ VGA@
VGA@ VGA@

1
Rref1 20K_0402_1% 0_0402_1% PC1481 EN High Threshold = 1.6V PQ1401
<22> GPU_VID0 1 2 .1U_0402_16V7K

D1

G1
2
Rboot VGA@ PL904
C
PR1451 Rrefadj 0.24UH_22A_+-20%_ 7X7X3_M +VGA_CORE C

2
2K_0402_1% LX1_VGA 7 LX1_VGA 1 4
DH1_VGA_1 D2/S1

GPU_PSI
1 2 1 2

GPU_EN
VGA@ PR1455 2 3
18K_0402_1%
1

1
VGA@ PR1448 2.2_0603_1%

G2
0.01U_0402_16V7K

S2

S2

S2
BST1_VGA 1 2BST1_VGA-1
PR1466

2700P_0402_50V7K 20K_0402_1%

1SNUB_VGA1
VGA@ AON6992_DFN5X6D-8-7

330U_B2_2.5VM_R9M
1 1 1 1

330U_D1_2VY_R9M

330U_D1_2VY_R9M
VGA@

6
1
@VGA@ PC1494

1 PR1452 VGA_RF@
+ + +
PC1482

PC1475

PC1476
Rref2 VGA@ VGA@ 4.7_1206_5%
1 2

2
REFADJ

PC1478
PU1002 PC1495
2

2
0_0402_5%
PR1469

@VGA@ C 0.22U_0603_25V7K

UGATE1

BOOT1
VID

PSI

EN
2 PC1479VGA_RF@ 2 2 2
DL1_VGA 680P_0603_50V7K
6 20 LX1_VGA VGA@ VGA@
VGA@

2
REFADJ PHASE1
Rocset
2

1
RGND

10.7K_0402_1%
DL1_VGA VGA@
7 19

PR1457
REFIN
REFIN LGATE1 VGA@ PR1454
1_0603_1%
VREF_VGA 8 18 GPU_PVCC 1 2
+5VS

2
VREF RT8812AGQW_WQFN20_3X3 PVCC
1

1
VGA@ VGA@ PR1467 VGA@
PC1484 VGA_B+ 1 2 TON 9 17 DL2_VGA PC1477 VGA@
1U_0402_6.3V6K 499K_0402_1% TON LGATE2 1U_0603_10V6K
2

2
Rton 10 16 LX2_VGA VGA_B+

UGATE2
RGND PHASE2

PGOOD

BOOT2
VSNS
RGND

10U_0805_25V6K

10U_0805_25V6K
GND

1 DH2_VGA-2
@VGA@ PR1461 VGA@
SS

1
PC1488

PC1489
0_0402_1% PC1492
1 2 0.22U_0603_25V7K
<19> GND_SENSE_GPU
21

11

12

13

14

15
VGA@ PR1460 2

2
2.2_0603_1% VGA@
1 2 BST2_VGA 1 2BST2_VGA-2 VGA@ VGA@

1
PR1453 PQ1402
0.01U_0402_16V7K

10_0402_1%
1000P_0402_50V7K

D1

G1
PC1493

VGA@ VGA@ PL905


DH2_VGA-2 +VGA_CORE
@VGA@

Css 0.24UH_22A_+-20%_ 7X7X3_M


1

LX2_VGA 7 LX2_VGA 1 4
PC1483

2 VGA@ PR1456 D2/S1


+VGA_CORE

1
VGA@ 10K_0402_5% 2 3
EDP-Continuous 26.5A
2

1 2 +3VS_DGPU_AON
@VGA@

PR1449

G2
S2

S2

S2

1SNUB_VGA2
B 10_0402_1% EDP-Peak 53A B
1 2 GPU_VSENSE
+VGA_CORE AON6992_DFN5X6D-8-7 PR1459 VGA_RF@ OCP min 66.4A

6
DGPU_PWROK <19,23,24> 4.7_1206_5%

2
1 2 VGA_RF@
PR1444 <19> VDD_SENSE_GPU
@VGA@ 0_0402_5% PC1490
EN_1.35V 1 2 1.35V_PWR_EN @VGA@ PR1462 DL2_VGA 680P_0603_50V7K
1.35V_PWR_EN <23,24>
0_0402_1%

2
1

@VGA@ PC1472
VGA@ PR1445
+3VS +VGA_CORE Near GPU Core
0.22U_0402_10V6K Confirm HW side
2

1M_0402_1%

22U_0603_6.3V6M

22U_0603_6.3V6M
2

B+_1.35V
1

VGA@ PC11191

VGA@ PC835

VGA@ PC836

VGA@ PC837

VGA@ PC838

VGA@ PC839

VGA@ PC840

VGA@ PC841

VGA@ PC842

VGA@ PC847
@VGA@ keep short pad, VGA_RF@ PR1067 VGA_RF@ PC1238

10U_0402_6.3V6M

10U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M
PR1060 snubber is for EMI only. 4.7_1206_5% 680P_0603_50V7K

1
100K_0402_5% 1 2 SNUB_1.35V 1 2
VGA_EMI@ PL906 VGA@
PU1001
HCB2012KF-121T50_0805 @VGA@ VGA@
2

2
+19VB_1.35V
B+ 1 2 2
IN PG
9 +1.35VGS_PGOOD <24> PR1061
0_0402_5%
PC1237
0.1U_0201_10V6K
Use 7x7x3 size when the layout space is enough.
10U_0805_25V6K
0.1U_0402_25V6

3 1 BST_1.35V 1 2 BST_1.35V_R 1 2
2200P_0402_50V7K

IN BS PL602
1

1
PC1242

@EMI@ PC1248

VGA@ PC1249

LX_1.35V
4
IN LX
6 1 2
+1.35VGSP
2

5 19
VGA_EMI@

1UH_6.6A_20%_5X5X3_M

330P_0402_50V7K
12.4K_0402_1%

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
1
IN LX
VGA@
LDO_3V_1.35V
1

1
7 20
PR1062

PC1243

PC1239

PC1244

PC1247

PC1245
GND LX
FB_1.35V R1
8 14 +VGA_CORE Under GPU Core GB4-128 package
2

2
GND FB
1

@VGA@
2

PR1440 18 17 LDO_3V_1.35V
0_0402_5% GND VCC VGA@

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M
1

EN_1.35V 11 10 VGA@ VGA@ VGA@ VGA@ VGA@

VGA@ PC821

VGA@ PC822

VGA@ PC823

VGA@ PC824

VGA@ PC825

VGA@ PC826

VGA@ PC827

VGA@ PC828

VGA@ PC829

VGA@ PC830
VGA@

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M
EN NC PC1246 FB=0.6V
2

1
ILMT_1.35V ILMT_1.35V 13 12 2.2U_0402_6.3V6M
2

ILMT NC
15 16 PR1063
+3VALW Vout=0.6V* (1+R1/R2) R2

2
BYP NC
21 =0.6*(1+(12.4/10))
10K_0402_1% +VGA_CORE
2

PAD
VGA@
SY8286RAC_QFN20_3X3
Vout=1.344V
1

VGA@

1U_0402_16V6K

1U_0402_16V6K

1U_0402_16V6K

1U_0402_16V6K
A A

PC831

PC832

PC833

PC834

VGA@ PC843

VGA@ PC844

VGA@ PC845

VGA@ PC846
PC1240

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6
1

1
1U_0402_6.3V6K
2

1
@ PJ902

2
EN :H>0.8V ; L<0.4V JUMP_43X118

2
1 2

@VGA_RF@

@VGA_RF@

@VGA_RF@

@VGA_RF@
+1.35VGSP 1 2 +1.35VS_VRAM
EN pin don't floating
If have pull down resistor at HW side,
please delete PR601.
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2017/06/05 Deciphered Date 2018/06/05 Title
PWR-CPU_GFX
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
The current limit is set to 6A, 9A or 12A when this pin DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
KBL 2.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
is pull low, floating or pull high. Date: Wednesday, June 21, 2017 Sheet 49 of 51

5 4 3 2 1

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