EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021

INDEX

SI. FACULTY
DATE NAME OF THE EXPERIMETS MARKS
NO
SIGNATURE
1 Current Series (Series-Series) feedback amplifier

2 Voltage Shunt (Shunt-Shunt) feedback amplifier

3 RC Phase shift Oscillator

4 Wien Bridge Oscillator

5 LC (Hartley & Colpitt’s) Oscillator

6 Single tuned amplifier

7 RC Integrator & Differentiator

8 Astable Multivibrator

9 Monostable Multivibrator

10 Clippers and Clampers

SIMULATION EXPERIMENTS

11 Simulation of Tuned Collector Oscillator

12 Simulation of Twin T Oscillator

13 Simulation of Wien Bridge Oscillator

14 Simulation of Double Tuned Oscillator

15 Simulation of Stagger tuned amplifier

16 Simulation of Bistable Multivibrator

17 Simulation of Schmitt Trigger

18 Analysis of Power Amplifier

CONTENT BEYOND SYLLABUS

19 Simulation of Voltage Time Base Generator

20 Simulation of Current Time Base Generator

1
 EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Circuit Diagram

Series – Series Amplifier without Feedback

V5
22.5v

R6
R1
5.6k
22k C1

1u

R5 C3 Q2 V

Q2N2222
0.68k 1u R2 C4

R3 1k 0.001u
V4
50mV 3.4k R4 C2
0 1.5k 100u

Simulation Profile:

2
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Ex. No Current Series (Series-Series) Feedback Amplifier

Date:
Aim:

To design a current series feedback amplifier circuit and determine the frequency
response, gain, bandwidth, input and output impedance with and without feedback.

Apparatus Required:

Sl. Equipments / components Type Quantity

No
1 Transistor BC 107 1

22 KΩ, 5.6 KΩ, 1.5 KΩ, Each 1

2 Resistors
3.4 KΩ, 0.68KΩ

1 µF 2
3 Capacitors
100 µF 1

4 Regulated Power Supply (0 – 30) V 1

5 Function Generator (0 – 1 MHz) 1

6 CRO (0 – 20 MHz) 1

7 Bread board - 1

8 Connection Wires - As required

Design:

Assume IC = 1.8 mA , VE = 3V, R2 = 3.4 KΩ, VCC = 22.5V

To find RE:

VE = IERE

VE 3V
 RE = = = 1.67 K
IE 1.8mA

3
 EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Instead of using 1.67KΩ, we can use a standard value of RE = 1.5 KΩ

Netlist:

**** INCLUDING "current series with feedback-SCHEMATIC1.net" ****

* source CURRENT SERIES WITH FEEDBACK
R_R1 N00028 N00129 22k
R_R3 0 N00028 3.4k
R_R4 0 N00103 1.5k
R_R5 N00041 N00044 0.68k
C_C1 N00099 N00148 1u
C_C2 0 N00103 100u
C_C3 N00028 N00041 1u
R_R2 0 N00148 1k
C_C4 0 N00148 0.001u
R_R6 N00099 N00129 5.6k
Q_Q2 N00099 N00028 N00103 Q2N2222
V_V4 N00044 0 DC 0 AC 50mV
V_V5 N00129 0 22.5v

Output Waveform:

4
 EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Series – Series Amplifier with Feedback

V1

22.5v

R1 R2
22k 5.6k
C1

1u
R6 Q1
C2
V
1u
Q2N2222
0.68k

V6 R3 C3
1v
1k 0.01 u
0Vdc
R5 R4
3.4k 1.5k

Simulation Profile:
 EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-
Model Graph:
Gain (dB)

Without

0.707

With

0.707

-- f(Hz)
fL2 fL1 4 fH fH

Netlist:
**** INCLUDING "currentsries with feedback-SCHEMATIC1.net" ****
* source CURRENT SERIES WITH FEEDBACK
R_R1 N00041 N00025 22k
R_R2 N00035 N00025 5.6k
R_R4 0 N00038 1.5k
R_R5 0 N00041 3.4k
R_R6 N00060 N00063 0.68k
C_C1 N00035 N00082 1u
C_C2 N00060 N00041 1u
V_V1 N00025 GND 22.5v
Q_Q1 N00035 N00041 N00038 Q2N2222
V_V6 N00063 0 DC 0Vdc AC 1v
C_C3 0 N00082 0.01u
R_R3 0 N00082 1k

Output waveform:
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

To find R1:

drop is neglected compared to VBE and VE drops. It is this neglecting that results in β
independent voltage divider bias design. Applying KVL to the input
VR2 – VBE – VE = 0

VR2 = VBE + VE = 0.7V + 3V = 3.7 V

Instead of using 1.67KΩ, we can use a standard value of R1= 22 KΩ

To find RC :

Drop across RE is assumed to be 3V. The drop across VCE with a supply of 22.5 V is given by
22.5V – 3.0 = 19.5V, then it is equal to 19.5 / 2 = 9.75V

Now the voltage across the resistance RC is 9.75 V and IC = 1.8 mA

VC
R = =
9.75V = 5.42 KΩ
C
IC 1.8mA

Instead of using 5.42 KΩ, we can use a standard value of RC = 5.6 KΩ

Design of Input Capacitor (C):

1
f = Assume hie = 0.16 K, f = 1K Hz
2 hie C

C = 1
= 0.995 F
2 x 0.16x103 x 1000

Choose standard value of C = 1 F

- -
5
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Tabular Column

With feedback Vin = 50 mV

Frequency (Hz) V0 (volts) Gain = V0 / Vin Gain(dB) = 20 log V0 / Vin

- -
6
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Theory:

Depending on the relative polarity of the signal being feedback in to a circuit, one may
have negative or positive feedback. If feedback is of opposite polarity to input signal negative
feedback results. While negative feedback results in reduced overall gain, a number of
improvements are obtained like higher impedance, better stabilized voltage gain etc., are
obtained.

In the circuit, the feedback signal is the voltage across RE and the sampled signal is the
load current. Hence this is a case of current series feedback. This topology stabilizes the
transconductance Gm. The gain of the amplifier decreases as result of the negative feedback
applied, whereas its bandwidth is improved.

Procedure:

1. Open OrCAD capture student

2. Select file -> New -> Project
3. Give file name, and select Analog or Mixed A/D then select OK
4. Now select create blank project and select OK
5. Select “Place” to get all the circuit components
6. Connect the circuit as given in the circuit diagram
7. Assign values to all the components as given in the circuit diagram
8. Now select PSpice and then select New Simulation Profile
9. Give name to simulation and select create
10. In simulation setting select Time domain (Transient).
11. Assign run to time and select Apply
12. Now select Voltage/Level Marker and place it across the load resistor
13. Go to PSpice and select “run” to run the project
14. Output waveform is generated, note down the output.
15. Click on add plot to window in the plot icon.
16. Now place another marker across the input, to plot the input waveform
17. To view Netlist, output screen -> view -> output file

- -
7
 EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-
General Procedure for Calculation:

1. Input Impedance

a. Connect a Decade Resistance Box (DRB) between input voltage source and the base
of the transistor (series connection).
b. Connect a ac voltmeter (0-100V) across the biasing resistor R2.
c. Vary the value of DRB such that the ac voltmeter reads the voltage half of theinput
signal.
d. Note down the resistance of the DRB, which is the input impedance.

2. Output impedance

a. Measure the output voltage when the amplifier is operating in the mid-band frequency
with the load resistance connected (Vload).
b. Measure the output voltage when the amplifier is operating in the mid-band frequency
without the load resistance connected (Vno - load).

3. Bandwidth

a. Plot the frequency response.

b. Identify the maximum gain region.
c. Draw a horizontal line at -3dB.
d. The -3dB line intersects the frequency response plot at two points.
e. The lower intersecting point -3dB line with the frequency response plot gives the
lower cut-off frequency.
f. The upper intersecting point -3dB line with the frequency response plot gives the
upper cut-off frequency.
g. The difference between the upper cut-off frequency and the lower cut-off frequency is
called the Bandwidth. Thus Bandwidth = fH - fL

- -
8
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-
Tabular Column

Without feedback Vin = 50 mV

Frequency (Hz) V0 (volts) Gain = V0 / Vin Gain(dB) = 20 log V0 / Vin

- -
9
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Result:

Thus the frequency response of series – series feedback amplifier with feedback and
without feedback is plotted.

Parameters Without Feedback With Feedback

Input Impedance

Output impedance

Bandwidth

- -
10
 EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Circuit Diagram

Shunt – Shunt Amplifier without Feedback

V2 22.5v

R1

R2 5.6k
C1
22k

1u

C3 Q1

Q2N2222
1u R5
C4
1k
V1
0.0009u
50mv
0Vdc
R3 R4 C2
3.4k 1.5k 100u

Simulation Profile:

- -
11
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Ex.No Voltage Shunt (Shunt-Shunt) Feedback Amplifier

Date:
Aim:

To design a voltage shunt feedback amplifier and determine the frequency response, gain,
bandwidth, input and output impedance.

Apparatus

Sl.No Equipments / components Type Quantity

1 Transistor BC 107 1

22 KΩ, 5.6 KΩ, 1.5 KΩ, Each 1

2 Resistors
3.4 KΩ, 15KΩ

1 µF 3
3 Capacitors
100 µF 1

4 Regulated Power Supply (0 – 30) V 1

5 Function Generator (0 – 1 MHz) 1

6 CRO (0 – 20 MHz) 1

7 Bread board - 1

8 Connection Wires - As required

Design:

Assume IC = 1.8 mA , VE = 3V, R2 = 3.4 KΩ, VCC = 22.5V

To find RE:

VE = IERE

VE 3V
 RE = = = 1.67 K
IE 1.8mA

Instead of using 1.67KΩ, we can use a standard value of RE = 1.5 KΩ

- -
12
 EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Netlist:
**** INCLUDING "voltage shunt without feedback-SCHEMATIC1.net" ****
* source VOLTAGE SHUNT WITHOUT FEEDBACK
R_R1 N00025 N00130 5.6k
R_R2 N00055 N00130 22k
R_R3 0 N00055 3.4k
R_R4 0 N00028 1.5k
C_C1 N00025 N00084 1u
C_C2 0 N00028 100u
C_C3 N00055 N00041 1u
V_V1 N00041 0 DC 0Vdc AC 50mv
V_V2 N00130 0 22.5v
Q_Q1 N00025 N00055 N00028 Q2N2222
R_R5 0 N00084 1k
C_C4 0 N00084 0.0009u

Output Waveform:

- -
13
 EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Circuit Diagram

Shunt – Shunt Amplifier with Feedback

V1

22.5v

R2 R3
22k R1 C1 5.6k C2

15k 10u 100u

V
C5 Q1

Q2N2222
1u C6
R6
R4 0.005u
V2
50mv 0.1k
3.4k
0v
R5
C4
1.5k
100u

Simulation Profile:

- -
14
 EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-
Netlist:
**** INCLUDING "voltage shunt with feedback-SCHEMATIC1.net" ****
* source VOLTAGE SHUNT WITH FEEDBACK
C_C1 N00071 N00036 10u
C_C2 N00036 N00107 100u
C_C4 0 N00039 100u
C_C5 N00033 N00055 1u
C_C6 N00107 0 0.005u
R_R1 N00033 N00071 15k
R_R2 N00033 N00178 22k
R_R3 N00036 N00178 5.6k
R_R4 0 N00033 3.4k
R_R5 0 N00039 1.5k
R_R6 0 N00107 0.1k
Q_Q1 N00036 N00033 N00039 Q2N2222
V_V1 N00178 0 22.5v
V_V2 N00055 0 DC 0v AC 50mv

Output Waveform:

Model Graph:
Gain (dB)

Without
0.707 A1

With

0.707 A2

f(H

- -
15
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

To find R1:

drop is neglected compared to in VBE and VE drops. It is this neglecting that results β independent
voltage divider bias design. Applying KVL to the input

VR2 – VBE – VE = 0

VR2 = VBE + VE = 0.7V + 3V = 3.7 V

Instead of using 17.28KΩ, we can use a standard value of R1= 22 KΩ

To find RC :

Drop across RE is assumed to be 3V. The drop across VCE with a supply of 22.5 V is given by
22.5V – 3.0 = 19.5V, then it is equal to 19.5 / 2 = 9.75V

Now the voltage across the resistance RC is 9.75 V and IC = 1.8 mA

VC
R = =
9.75V = 5.42 KΩ
C
IC 1.8mA

Instead of using 5.42 KΩ, we can use a standard value of RC = 5.6 KΩ

Design of Input Capacitor (C):

1
f = Assume hie = 0.16 K, f = 1K Hz
2 hie C

C = 1
= 0.995 F
2 x 0.16x103 x 1000

Choose standard value of C = 1 F

- -
16
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Tabular Column

Without feedback Vin = 50 mV

Frequency (Hz) V0 (volts) Gain = V0 / Vin Gain(dB) = 20 log V0 / Vin

- -
17
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Theory:

Depending on the relative polarity of the signal being feedback in to a circuit, one may
have negative or positive feedback. If feedback is of opposite polarity to input signal negative
feedback results. While negative feedback results in reduced overall gain, a number of
improvements are obtained like higher impedance, better stabilized voltage gain etc., are
obtained.

The circuit given has the voltage series feedback. The feedback signal as well as the
output signal is the voltage across the emitter resistance RE, which gives rise to this type of
feedback. It increases input resistance and decreases output resistance.

Procedure:

1. Open OrCAD capture student

2. Select file -> New -> Project
3. Give file name, and select Analog or Mixed A/D then select OK
4. Now select create blank project and select OK
5. Select “Place” to get all the circuit components
6. Connect the circuit as given in the circuit diagram
7. Assign values to all the components as given in the circuit diagram
8. Now select PSpice and then select New Simulation Profile
9. Give name to simulation and select create
10. In simulation setting select Time domain (Transient).
11. Assign run to time and select Apply
12. Now select Voltage/Level Marker and place it across the load resistor
13. Go to PSpice and select “run” to run the project
14. Output waveform is generated, note down the output.
15. Click on add plot to window in the plot icon.
16. Now place another marker across the input, to plot the input waveform
17. To view Netlist, output screen -> view -> output file

- -
18
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-
General Procedure for Calculation:

1. Input Impedance

a. Connect a Decade Resistance Box (DRB) between input voltage source and the base
of the transistor (series connection).
b. Connect a ac voltmeter (0-100V) across the biasing resistor R2.
c. Vary the value of DRB such that the ac voltmeter reads the voltage half of theinput
signal.
d. Note down the resistance of the DRB, which is the input impedance.

2. Output impedance

a. Measure the output voltage when the amplifier is operating in the mid-band frequency
with the load resistance connected (Vload).
b. Measure the output voltage when the amplifier is operating in the mid-band frequency
without the load resistance connected (Vno - load).

3. Bandwidth

a. Plot the frequency response.

b. Identify the maximum gain region.
c. Draw a horizontal line at -3dB.
d. The -3dB line intersects the frequency response plot at two points.
e. The lower intersecting point -3dB line with the frequency response plot gives the
lower cut-off frequency.
f. The upper intersecting point -3dB line with the frequency response plot gives the
upper cut-off frequency.
g. The difference between the upper cut-off frequency and the lower cut-off frequency is
called the Bandwidth. Thus Bandwidth = fH - fL

- -
19
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Tabular Column

Without feedback Vin = 50 mV

Frequency (Hz) V0 (volts) Gain = V0 / Vin Gain(dB) = 20 log V0 / Vin

- -
20
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Result:

Thus the frequency response of voltage shunt feedback amplifier with feedback and
without feedback is plotted.
Parameters Without Feedback With Feedback

Input Impedance

Output impedance

Bandwidth

- -
21
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

RC PAHSE SHIFT OSCILLATOR:

Circuit Diagram:

Simulation Profile: Netlist:

Output:

- -
22
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Expt.No: RC PAHSE SHIFT OSCILLATOR

Date:

Aim:
To design a RC Phase shift oscillator and to obtain the sine wave of desired frequency
using orcad PSPICE.

Apparatus Required:
❖ Personal Computer
❖ OrCAD PSPICE Software
❖ Keyboard
❖ Mouse

Components Required:

SI.No Name of the Components Specification Quantity Required

1 Transistor Q2N2222 1

2 Resistor 100k 2
22k 1
3.9k 1

1k 1
4.7k 3
3 Capacitor 47u 1
10u 1
10n 3
4 DC Source (VDC) 12V 1

5 Voltage/Level Marker - 1
6 Ground Zero 4
7 Connecting Wires - As Required

- -
23
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Theory:
An oscillator is a device that can be used to generate an alternating voltage or current.
It is also a converter that converts DC to AC which is at 0 frequency, to higher frequency. RC
phase shift oscillator produces sinusoidal oscillations and hence a sine wave. Amplifier when
provided with a +ve feedback forms an oscillator and the phase shift between input signal and
the feedback signal must be ‘zero’ or an integral multiple of 180.
The circuit diagram the amplifier is followed by three section of RC phase shift
oscillator network. The output of the RC network produces a phase shift of 180° and the
amplifier provides another phase shift of 180°. The resistors R1, R2 combination produces
DC Emitter bias and RE, CE provides temperature stability and ac signal degeneration. The
1
component resistor and capacitor are selected to obtain the desired frequency, f =
2 RC 6
The R and C are selected in such a way that the RC combination phase angle be 60°,
so that using a ladder network of 3 RC sections a phase shift of 180° is obtained between the
input and output. This provides a total phase shift of 360° and hence a sine wave of desired
frequency is obtained. Thus, the RC phase shift oscillator serves as a frequency determining
network.

Procedure:
18. Open OrCAD capture student
19. Select file -> New -> Project
20. Give file name, and select Analog or Mixed A/D then select OK
21. Now select create blank project and select OK
22. Select “Place” to get all the circuit components
23. Connect the circuit as given in the circuit diagram
24. Assign values to all the components as given in the circuit diagram
25. Now select PSpice and then select New Simulation Profile
26. Give name to simulation and select create
27. In simulation setting select Time domain (Transient).
28. Assign run to time and select Apply
29. Now select Voltage/Level Marker and place it across the load resistor
30. Go to PSpice and select “run” to run the project
31. Output waveform is generated, note down the output.
32. Click on add plot to window in the plot icon.
33. Now place another marker across the input, to plot the input waveform
34. To view Netlist, output screen -> view -> output file - -
24
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Model Graph:

Amplitude (V)

Time (ms)

Result:
Thus, the RC phase shift oscillator is designed and the sine wave is obtained as
output.

- -
25
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Circuit Diagram
Wien Bridge Oscillator

Simulation Output

- -
26
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Simulation Profile:

NETLIST:
* source WEIN BRIDGE

R_R1 N14607 N14290 27k

R_R2 N14720 N14290 4.7k
R_R3 N14738 N14290 39k
R_R4 N14816 N14290 4.7k
R_R5 0 N14812 3.3k
R_R6 0 N14738 35k
R_R7 0 N14724 1k

R_R0 N14607 4.7k

C_C1 N14607 N14816 10n

TC=0,0C_C2

0 N14607 10n TC=0,0

X_Q1 N14720 N14607 N14724 awb2n2222 PARAMS:

X_Q2 N14816 N14738 N14812 awb2n2222 PARAMS:

C_C3 N14720 N14738 10n

TC=0,0V_V1

N14290 0 5v
- -
27
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Ex.No Wien Bridge Oscillator

Date:

Aim:
To design a Wien Bridge oscillator and to obtain the sine wave of desired frequency
using PSPICE.

Apparatus Required:

SI.No Name of the Components Specification Quantity Required

1 Transistor Q2N2222 2

2 Resistor 4.7K 3
27k 1
39k 1

1k 1
35k 1
3 Capacitor 10n 3
5 DC Source (VDC) 5V 1

6 Voltage/Level Marker - 1
7 Ground Zero 5
8 Connecting Wires - As Required

Design:

Assume C = 0.01 µF and f0 = 10 KHz

f0 = 1
2πRC

The frequency of oscillation of wien bridge oscillator is given by

10 x103 = 1

2π x R x 0,01 x 10-6

 R = 1.59 KΩ ≈ 1.5 KΩ

To avoid loading effect R1 = 10R

- -
28
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Model waveform:

Observations:

Amplitude Time Period T Frequency (1/T)

(V) (ms) (Hz)

Calculation

Practical

Frequency = 1 / Time period

 R1 = 10 x 1.5 KΩ = 15 KΩ

For the loop gain AV to be greater than 1, Rf should be equal to 2R1

Rf = 2R1 = 2 x 15 KΩ = 30 KΩ

- -
29
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Theory:

The closed loop circuit of the wien bridge oscillator gives the positive feedback. At
f0, β= 1/3 therefore for sustained oscillation, the amplifier must have a gain of precisely 3.
However, from particular point of view, AV may be slightly less or greater than 3. To
compensate the change an adaptive negative feedback is used. Since the amplifier works as a
non-inverting amplifier, the feedback network will not provide any phase shift.
The circuit can be viewed as wien bridge with a series RC network in one arm and a
parallel RC network in the adjoining arm. Resistors R1 and Rf are connected in the remaining
two arms. The condition of zero phase shift is obtained by balancing the bridge.

Procedure:

1. Open OrCAD capture student

2. Select file -> New -> Project
3. Give file name, and select Analog or Mixed A/D then select OK
4. Now select create blank project and select OK
5. Select “Place” to get all the circuit components
6. Connect the circuit as given in the circuit diagram
7. Assign values to all the components as given in the circuit diagram
8. Now select PSpice and then select New Simulation Profile
9. Give name to simulation and select create
10. In simulation setting select Time domain (Transient).
11. Assign run to time and select Apply
12. Now select Voltage/Level Marker and place it across the load resistor
13. Go to PSpice and select “run” to run the project
14. Output waveform is generated, note down the output.
15. Click on add plot to window in the plot icon.
16. Now place another marker across the input, to plot the input waveform
17. To view Netlist, output screen -> view -> output file

- -

30

Result:
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Thus wien-bridge oscillator is designed and sine wave is obtained as output.

Desired frequency (Theoretical) =

Obtained frequency (Practical) =

- -
31
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

HARTLEY OSCILLATOR:
Circuit Diagram:

Simulation Profile: Netlist:

Output:

- -
32
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

COLPITTS OSCILLATOR:
Circuit Diagram:

Simulation Profile: Netlist:

Output:

- -
33
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Expt.No: HARTLEY OSCILLATOR AND COLPITTS OSCILLATOR

Date:
Aim:
To design Hartley oscillator and Colpitts oscillator to get sine wave output of desired
frequency using OrCAD PSPICE.
Apparatus Required:
❖ Personal Computer
❖ OrCAD PSPICE Software
❖ Keyboard
❖ Mouse
Components Required:
Hartley Oscillator:
SI.No Name of the Components Specification Quantity Required

1 Transistor Q2N2222 1

2 Resistor 22k 1
10k 1
3.4k 1

1.5k 1
3 Capacitor 1u 2
100u 1
0.01u 1
4 Inductor 40uH 1

2mH 1

5 DC Source (VDC) 22.5V 1

6 Voltage/Level Marker - 1
7 Ground Zero 3
8 Connecting Wires - As Required

- -
34
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Colpitts Oscillator:

SI.No Name of the Components Specification Quantity Required

1 Transistor Q2N2222 1

2 Resistor 22k 1
5.6k 1
3.3k 1

1.5k 1
3 Capacitor 1n 1
100u 1
0.1u 2
4 Inductor 1mH 1

5 DC Source (VDC) 22.5V 1

6 Voltage/Level Marker - 1
7 Ground Zero 3
8 Connecting Wires - As Required

Theory:
The LC oscillator uses L and C as the element which forms tank circuit or oscillatory
circuit. This is also referred to as resonating tuned circuits. L and C are connected in parallel
when capacitor gets charged, the energy gets stored as electrostatic energy. After charging, it
discharges through L. When capacitor is fully discharged, maximum current flows through
the circuit.
The LC oscillator along with amplifier supplies this loss of energy at proper times.
The care of proper polarity is taken by feedback network. Thus, LC oscillator is obtained.
Due to energy which is lost, the oscillations are maintained hence called sustained
oscillations, or undamped oscillations.
The resistors R1, R2 and RE provide the necessary d.c bias to the transistor. The
feedback network consisting of capacitors C1 and C2 and an inductor L determines the
frequency of the oscillator.

- -
35
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Procedure:
35. Open OrCAD capture student
36. Select file -> New -> Project
37. Give file name, and select Analog or Mixed A/D then select OK
38. Now select create blank project and select OK
39. Select “Place” to get all the circuit components
40. Connect the circuit as given in the circuit diagram
41. Assign values to all the components as given in the circuit diagram
42. Now select PSpice and then select New Simulation Profile
43. Give name to simulation and select create
44. In simulation setting select Time domain (Transient).
45. Assign run to time and select Apply
46. Now select Voltage/Level Marker and place it across the load resistor
47. Go to PSpice and select “run” to run the project
48. Output waveform is generated, note down the output.
49. Click on add plot to window in the plot icon.
50. Now place another marker across the input, to plot the input waveform
51. To view Netlist, output screen -> view -> output file

Model Graph:

Amplitude (V)

Time (ms)

T
- -
36
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Tabulation:

Oscillator Desired Frequency Practical Frequency

(Theoretical) (Obtained)

Hartley Oscillator

Colpitts Oscillator

Result:
Thus, the Hartley oscillator and Colpitt’s oscillator are designed and the sine wave is
obtained as output.
- -
37
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Circuit Diagram

Single tuned Amplifier

V2

22.5V

L1
C4
R1 5.8mH
1u
22K

C2

1u
V
Q1
C1

1u
Q2N2222
R4
10K

V1
50mv
0v
R2
R3
3.4K C3
1.5K
100u

SIMULATION SETTINGS:

- -
38
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

NETLIST:
* source SINTUN
Q_Q1 N00027 N00105 N00030 Q2N2222
R_R1 N00119 N00062 22K
R_R2 0 N00119 3.4K
R_R3 0 N00030 1.5K
R_R4 0 N00166 10K
V_V1 N00099 0 DC 0v AC 50mv
C_C1 N00099 N00105 1u
C_C2 N00027 N00166 1u
C_C3 0 N00030 100u
C_C4 N00027 N00062 1u
L_L1 N00062 N00027 5.8mH
V_V2 N00062 0 22.5V

OUTPUT:

- -
39
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Ex. No Single tuned Amplifier

Date:
Aim:
To design and test a single tuned amplifier and determine the frequency response of
an amplifier using PSPICE.

Apparatus Required:

SI.No Name of the Components Specification Quantity Required

1 Transistor Q2N2222 1

2 Resistor 22k 1
10k 1
2.4k 1

1.5k 1
3 Capacitor 1u 3
100u 1
4 Inductor 5.8mH 1

5 AC Source (Vac) 50mv 1

6 DC Source (VDC) 22.5V 1

7 Voltage/Level Marker - 1
8 Ground Zero 3
9 Connecting Wires - As Required

Design:

Assume IC = 1.8 mA , VE = 3V, R2 = 3.4 KΩ, VCC = 22.5V

To find RE:

VE = IERE
 RE = VE = 3V = 1.67KΩ
IE 1.8mA

Instead of using 1.67KΩ, we can use a standard value of RE = 1.5 KΩ

- -
40
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

To find R1:

Applying KVL to the input

VR2 – VBE – VE = 0

VR2 = VBE + VE = 0.7V + 3V = 3.7 V

Instead of using 17.28 KΩ, we can use a standard value of R1= 22 KΩ

Theory:
Amplifiers, which amplify a specific frequency or narrow band of frequency, is called
tuned amplifier. Tuned amplifiers are used for the amplification of radio frequencies. The
tuned circuit offers very high impedance at resonant frequency and very small impedance at
other frequencies. If the signal has same frequency as resonant frequency of LC circuit, large
amplification will result. When signals of many frequencies are present at the input it will
select and strongly amplify the signals of resonant frequency while reject the others. Thus
they are used in radio receivers.
The circuit consists of transistor amplifier containing a parallel band circuit as collector load.
The values of capacitors and inductors of the tuned circuit are so selected that its resonant
frequency is the frequency to be amplified.

Model Graph:

Gain (dB)

Amax
-3 dB

Frequency ( Hz)
fL f0 fH

- -
41
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Procedure:
1. Open OrCAD capture student
2. Select file -> New -> Project
3. Give file name, and select Analog or Mixed A/D then select OK
4. Now select create blank project and select OK
5. Select “Place” to get all the circuit components
6. Connect the circuit as given in the circuit diagram
7. Assign values to all the components as given in the circuit diagram
8. Now select PSpice and then select New Simulation Profile
9. Give name to simulation and select create
10. In simulation setting select Time domain (Transient).
11. Assign run to time and select Apply
12. Now select Voltage/Level Marker and place it across the load resistor
13. Go to PSpice and select “run” to run the project
14. Output waveform is generated, note down the output.
15. Click on add plot to window in the plot icon.
16. Now place another marker across the input, to plot the input waveform
17. To view Netlist, output screen -> view -> output file

Result:
Thus the single tuned amplifier was designed and the frequency response was
obtained.

Bandwidth =
Resonant frequency =
- -
42
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-
RC Integrator

Circuit Diagram: Netlist

** INCLUDING int,diff-SCHEMATIC1.net *
* source INT,DIFF
C_C 0 N00270 0.1u
R_R N00270 N00264 10k
V_Vin N00264 0 +PULSE 5 -5 0 0 0 1m 2m

Simulation Profile:

Output:

- -
43
 EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Expt.No:2 Integrator and differentiator

Date:
Aim:
To study and simulate the operations of integrators and differentiator using orcad PSPICE.

Apparatus Required:
❖ Personal Computer
❖ OrCAD PSpice software
❖ Keyboard
❖ Mouse

Components Required:

Sl.No Name of the component Specification Quantity Required

1. Resistor 10k  1

1 1 1
2. Capacitor 0.1 F 1
3. Pulse Source (VPulse) 10V 1
4. Voltage / Level Marker - 2
5. Ground Zero source 1
6. Connecting wires - As required

Theory:

Integrator
The integrating circuit consists of a series resistor and a shunt capacitor. This passes low
frequencies of the input and attenuates high frequencies because the reactance of the capacitor C
decreases with increasing frequency. At very high frequencies the capacitor acts as a virtual short
circuit and the output falls to zero. Hence this circuit is called low-pass filter. It gives an output
waveform similar to the time integral of the input waveform. i.e.,
𝟏
𝐕𝟎 = ∫ 𝐕𝐢𝐝𝐭
𝐑𝐂

and hence, the circuit is called integrator. In general, the time constant of the integrating circuit
shall be large compared with the period of the input signal.
- -
44
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

RC Differentiator

Circuit Diagram: Netlist

**** INCLUDING int,diff-SCHEMATIC1.net ****
* source INT,DIFF
C_C N00011 N00017 0.1u
R_R 0 N00017 1k
V_Vin N00011 0 +PULSE 5 -5 0 0 0 1m 2m

Simulation Profile:

Output:

- -
45
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Differentiator
It consists of a series capacitor and a shunt resistor. Since the reactance of a capacitor is

1
𝑋𝐶 =
2𝜋𝑓𝐶

XC decreases with increasing frequency (f). Therefore, at very high frequencies the capacitor
acts as a short circuit and all the higher frequency components appear at the output with less
attenuation than the lower frequency components. Hence this circuit is called high-pass filter.

With reducing time constant, the pulse at the output becomes narrower with negligible
sag. If the time constant is reduced sufficiently, the output will be simply a series of alternate
positive and negative spikes. Mathematically, such a waveform is the first derivative of the
input waveform
𝑑𝑉𝑖
𝑉0 = 𝑅𝐶
𝑑𝑡
Design:
Assume f = 1 KHz, C = 0.1 µF
T = τ = RC ; T = 1 / f = 1 ms
𝑟 1 × 10−3
𝑅= = = 10𝑘𝛺
𝐶 1 × 10−6

- -
46
 EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Procedure:
1) Open OrCAD capture student
2) Select file -> New -> Project
3) Give file name, and select Analog or Mixed A/D then select OK
4) Now select create blank project and select OK
5) Select “Place” to get all the circuit components
6) Connect the circuit as given in the circuit diagram
7) Assign values to all the components as given in the circuit diagram
8) Now select PSpice and then select New Simulation Profile
9) Give name to simulation and select create
10) In simulation setting select Time domain(Transient).
11) Assign run to time and select Apply
12) Now select Voltage/Level Marker and place it across the load resistor
13) Go to PSpice and select “run” to run the project
14) Output waveform is generated, note down the output.
15) Click on add plot to window in the plot icon.
16) Now place another marker across the input ,to plot the input wavefo

Model Graph:

RC Integrator

- -
47
 EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

RC Differentiator

Result:
Thus, the differentiator and integrator circuits are studied and simulated using orcad PSPICE.

- -
48
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-
Astable Multivibrator

Circuit Diagram

- -
49
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Simulation profile:

- -
50
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-
Simulation Output

- -
51
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-
Ex.No Astable Multivibrator

Date:
Aim:

To design an Astable multivibrator to get a square waveform and to calculate its TON and
TOFF.

Apparatus Required:

Sl. Equipments / components Type Quantity

No
1 Transistor BC 107 2

2 Resistors 90 KΩ, 4.7 KΩ Each 2

3 Capacitors 0.01 µF 2

4 Regulated Power Supply (0 – 30) V 1

5 CRO (0 – 20 MHz) 1

6 Bread board 1

7 Connection Wires As required

Design:

Assume VCC = 12 V, hfe = 20, f = 1 KHz, IC = 2.5 mA, VCE(Sat) = 0.2 V

To find RC

Applying KVL to the outside loop we have

VCC – ICRC – VCE(Sat) = 0

- -
52
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Model Waveform

Amplitude (V)
TON
VC1

TOFF
0 t (ms)

Amplitude (V)

TON
VC2
TOFF

0 t (ms)

- -
53
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

VCC − VCE ( Sat)

 RC = I
C

12 − 0.2
= = 4.7 K
2.5 x10−3

 RC = RC1 = RC2 = 4.7 KΩ

To find R

T = 1.38 RC

T = 1 ms, Assume C = 0.01 µF

 R = R1 = R2 = 90 KΩ

Theory:

An astable multivibrator also known as free running multivibrator generates square

wave of known period. It does not have any permanent stable state. It has two quasi stable states.

The astable multivibrator may be thought of as two common emitter amplifying stages.
Each stage provides a positive feedback through a capacitor at the input of the other. Since the
amplifier stage produces a phase shift of 180°, the total phase shift is 360° or 0°. The feedback is
the positive feedback. Due to capacitive coupling none of the transistors can remain permanently
in cutoff or saturation. Instead the circuit has two quasi table state and it makes periodic
transitions between the two stages.

- -
54
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Observation

Output Amplitude (V) Time Period (ms)

TON =
VC1
TOFF =

TON =
VC2
TOFF =

- -
55
 EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Procedure:

1. Open OrCAD capture student

2. Select file -> New -> Project
3. Give file name, and select Analog or Mixed A/D then select OK
4. Now select create blank project and select OK
5. Select “Place” to get all the circuit components
6. Connect the circuit as given in the circuit diagram
7. Assign values to all the components as given in the circuit diagram
8. Now select PSpice and then select New Simulation Profile
9. Give name to simulation and select create
10. In simulation setting select Time domain (Transient).
11. Assign run to time and select Apply
12. Now select Voltage/Level Marker and place it across the load resistor
13. Go to PSpice and select “run” to run the project
14. Output waveform is generated, note down the output.
15. Click on add plot to window in the plot icon.
16. Now place another marker across the input, to plot the input waveform
17. To view Netlist, output screen -> view -> output file
.

Result:

Thus an astable multivibrator is designed to get a square wave and its TON and TOFF are
calculated and a graph is drawn.

- -
56
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-
Monostable Multivibrator

Circuit Diagram

Simulation profile:

- -
57
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-
Ex. No Monostable Multivibrator
Date:

Aim:
To design a monostable multivibrator for developing an output pulse of 140 µs duration.

Apparatus Required:

Sl. No Equipments / components Type Quantity

1 Transistor BC 107 2

2 Resistors 14 KΩ, 100 KΩ, 1KΩ Each 1

2KΩ 2

3 Capacitors 0.1µF 2

4 Diode 1N4007 1

5 Dual Regulated Power Supply (0 – 30) V 1

6 CRO (0 – 20 MHz) 1

7 AFO (0 – 1 MHz) 1

8 Bread board 1

9 Connection Wires As required

- -
58
 EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-
Model Waveform

Amplitude(Volts)

Input Trigger wave

TON TOFF t (ms)

Amplitude(Volts)
Output Pulsewave

TON

TOFF

t (ms)

- -
59
 EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-
Theory:

A monostable multivibrator has a stable state and quasi stable state. An external trigger circuit is
required to be applied to approximate point in the quasi stable state. The circuit remains in the quasi
stable state for the predetermined length of time and then changes to the stable state automatically. The
circuit of multivibrator using two NPN transistors is shown. The output of transistor Q2 is coupled to
base of transistor Q1 through R1. The output of transistor Q1 is coupled to the base of transistor Q2
through C. The output of the monostable multivibrator is available at the collector terminal of either
transistor.

Procedure:

1. Open OrCAD capture student

2. Select file -> New -> Project
3. Give file name, and select Analog or Mixed A/D then select OK
4. Now select create blank project and select OK
5. Select “Place” to get all the circuit components
6. Connect the circuit as given in the circuit diagram
7. Assign values to all the components as given in the circuit diagram
8. Now select PSpice and then select New Simulation Profile
9. Give name to simulation and select create
10. In simulation setting select Time domain (Transient).
11. Assign run to time and select Apply
12. Now select Voltage/Level Marker and place it across the load resistor
13. Go to PSpice and select “run” to run the project
14. Output waveform is generated, note down the output.
15. Click on add plot to window in the plot icon.
16. Now place another marker across the input, to plot the input waveform
17. To view Netlist, output screen -> view -> output file

- -
60
 EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-
Observation

Time Period (ms)

Waveform Amplitude (Volts)

TON (ms) TOFF (ms)

Input Trigger

Output wave put

- -
61
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Result:
Thus the monostable multivibrator is designed to get a pulse wave and its TON and TOFF is
calculated and a graph is drawn.

- -
61
 EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Positive Clipper
Circuit Diagram : Netlist:
**** INCLUDING clipper-SCHEMATIC1.net ***
* source CLIPPER
D_D1 N00049 0 D1N4148
R_R1 N00009 N00049 220
V_Vin N00009 0 +SIN 0V 10V 1kHz 0 0 0

Simulation Profile

Output

- -
62
 EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Expt.No: Clipper and Clamper

Date:
Aim:
To study and simulate the operations of various types of clippers and clampers using orcad PSPICE.

Apparatus Required:
❖ Personal Computer
❖ OrCAD PSpice software
❖ Keyboard
❖ Mouse

Components Required:

Sl.No Name of the component Specification Quantity Required

1 Diode 1N4148 1
2 Resistor 220  1

1 K 1
3 Capacitor 0.01 F 1
4 DC Source (VDC) 4V 2
5 AC Source (VAC) 10V 1
6 Voltage / Level Marker - 1
7 Ground Zero source 2
8 Connecting wires - As required

Theory:
Clippers
The circuit with which the waveform is shaped by removing (or clipping) a portion of
theinput signal without distorting the remaining part of the alternating waveform is called a
clipper. Clipping circuits are also referred to as voltage (or current) limiters, amplitude
selectors, or slicers. These circuits find extensive use in radars, digital computers, radio and
television receivers etc. The clipping circuits employ the components like diode, resistor and
dc battery. The resistor R is used to limit the current flowing through the diode when it is
forward biased. There are four general categories of clippers
(i) positive clipper (ii) negative clipper (iii) biased clipper and (iv) combinatio-n clipp-er
63
 EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Negative Clipper
Circuit Diagram : Netlist:
**** INCLUDING clipper-SCHEMATIC1.net ****
* source CLIPPER
D_D1 0 N00165 D1N4148
R_R N00009 N00165 220
V_Vin N00009 0
+SIN 0V 10V 1kHz 0 0 0

Simulation Profile

Output

- -
64
 EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-
1. Positive Clipper:
In the positive clipper circuit, when the input voltage is positive, diode conducts and acts as short-circuit
and hence there is zero signal at the output, i.e. the positive half cycle is clipped off. When the input signal
is negative, the diode does not conduct and acts as an open switch, the negative half cycle appears at the
output as shown in the figure.The positive clippers act as half wave rectifier. Thus the positive clipper
has clipped half cycle completely and allowed to pass the negative half cycle of the input signal.
2. Negative Clipper
In the negative clipping circuit, the diode is connected in a direction opposite to that of a positive clipper.
During the positive half cycle of the input signal, the diode conducts and acts as a open-circuit and hence,
the positive half cycle of the input signal will appear at the output as shown in the figure. During the
negative half cycle of the input signal, the diode conducts and acts as a closed circuit. The negative half
cycle will not appear at the output i.e. the negative half cycle is clipped off as shown in the figure.
3. Biased Clipper
In some applications, it is required to remove a small portion of positive or negative half cycle of the
signal voltage and hence biased clipper is used. The name bias is designated because the adjustment of
the clipping level is achieved by adding a biasing voltage in series with the diode or resistor.
(a) Biased positive clipper
In the biased positive clipper, the diode conducts as long as the input voltage is greater than +VR
and the output remains at +VR until the input voltage becomes less than +VR. When the input voltage is
less than +VR, the diode does not conduct and acts as an open switch. Hence the entire input signal having
less than +VR as well as negative half cycle of the input wave will appear at the output. The clipping
level can be shifted up or down by varying the bias voltage +VR.
(b) Biased positive clipper with reverse polarity of VR
The figure shows the biased clipper with reverse polarity of VR along with the input and output
voltage waveforms. Here, the entire signal above -VR is clipped off.
(c) Biased Negative clipper
In the biased negative clipper as shown in the figure, when the input voltage Vi ≤ -VR the diode
conducts and clipping takes place. The clipping level can be shifted up or down by varying the bias
voltage (-VR).
(d) Biased negative clipper with reverse polarity of VR
The figure shows the biased negative clipper with reverse polarity of VR along with the input
and output waveforms. Here, the entire signal below +VR is clipped off - -
65
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
Biased Positive clipper -

Circuit Diagram: Netlist

** INCLUDING clipper-SCHEMATIC1.net **
* source CLIPPER
D_D1 N00216 N000031 D1N4148
R_R N00009 N00216 220
V_Vin N00009 0 +SIN 0V 10V 1kHz 0 0 0
V_VR N000031 0 4Vdc
R_RL 0 N00216 1k

Simulation Profile:

Output:

- -
66
 EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-
4. Combination clipper
This is the combination of a biased positive clipper and a biased negative clipper. Figure
shows the combination clipper along with the input and output voltage waveforms. When the input
signal voltage Vi ≥ +VR1, diode D1 conducts and acts as a closed switch, while D2 is reverse biased
and D2 acts as an open switch. Hence, the outputvoltage cannot exceed the voltage level of +V R1
during the positive half cycle.
Similarly, when the input signal voltage Vi ≤ -VR2, diode D2 conducts and acts a closed
switch, while diode D1 acts as an open switch. Hence the output voltage V0 cannot go below the
voltage level of -VR2 during the negative half cycle.
The clipping levels may be changed by varying the values of VR1 and VR2. If VR1 = VR2,
the circuit will clip both the positive and negative half cycles at the same voltage levels and hence,
such a combination clipper is called symmetrical clipper.

- -
67
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Biased Negative clipper

Circuit Diagram: Netlist:

*** INCLUDING clipper-SCHEMATIC1.net ***
* source CLIPPER
D_D1 N000030 N00216 D1N4148
R_R N00009 N00216 220
V_Vin N00009 0 +SIN 0V 10V 1kHz 0 0 0
R_RL 0 N00216 1k
V_VR 0 N000030 4Vdc

Simulation Profile:

Output:

- -
68
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Biased Negative clipper with reverse polarity

Circuit Diagram: Netlist

**** INCLUDING clipper-SCHEMATIC1.als ****
.ALIASES
D_D1 D1(1=N000030 2=N00216 )
R_R R(1=N00009 2=N00216 )
V_Vin Vin(+=N00009 -=0 )
V_VR VR(+=N000030 -=0 )
R_RL RL(1=0 2=N00216 )
.ENDALIASES

Simulation Profile:

- -
69
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-
Output:

- -
70
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Biased Positive clipper with reverse polarity

Circuit Diagram: Netlist

** INCLUDING clipper-SCHEMATIC1.net **
* source CLIPPER
D_D1 N00216 N000031 D1N4148
R_R N00009 N00216 220
V_Vin N00009 0 +SIN 0V 10V 1kHz 0 0 0
V_VR 0 N000031 4Vdc
R_RL 0 N00216 1k

Simulation Profile:

Output:

- -
71
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Combinational clipper

Circuit Diagram:
Netlist
** INCLUDING clipper-SCHEMATIC1.net **
* source CLIPPER
D_D2 N01011 N00216 D1N4148
R_R N00009 N00216 220
V_Vin N00009 0 +SIN 0V 10V 1kHz 0 0 0
D_D1 N00216 N007881 D1N4148
V_VR1 N007881 0 4Vdc
R_RL 0 N00216 1k
V_VR2 0 N01011 4Vdc

Simulation Profile:

- -
72
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-
Output:

- -
73
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Positive clamper

Circuit Diagram: Netlist

**** INCLUDING clamper-SCHEMATIC1.als
****
.ALIASES
D_D1 D1(1=0 2=N00286 )
C_C1 C1(1=N00011 2=N00286 )
V_Vin Vin(+=N00011 -=0 )
.ENDALIASES

Simulation Profile:

Output:

- -
74
 EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Clampers
Clamping network shifts (clamps) a signal to a different dc level, i.e. it introduces a
dc level to an ac signal. Hence, the clamping network is also known as dc restorer. These circuits
find application in television receivers to restore the dc reference signal to the video signal.
The clamping network has the various circuit components like a diode, a capacitor
and a resistor. The time constant for the circuit τ = RC must be large so that the voltage across the
capacitor does not discharge significantly when the diode is not conducting.

(a) Positive clamper

During the negative half of the input signal, the diode conducts, and acts like a short circuit.
Now, the output voltage, V0 = 0V. The capacitor is charged to V volts and it behaves like a battery.
During the positive half of the input signal, the diode does not conduct, and acts like an open circuit.
Hence, the output voltage, V0 = 2V. This gives positively clamped voltage and the total swing of the
output is equal to the total swing of the input signal.

(b) Negative Clamper

During the positive half cycle, the diode conducts, i.e. it acts like a short circuit. The
capacitor charges to V volts. During this interval, the output which is taken acrossthe short circuit
will be V0 = 0V. During the negative half cycle, the diode is open. The output voltage is -2V. This
gives negatively clamped voltage and the total swing of the output is equal to the total swing of the
input signal.
Procedure:
1) Open OrCAD capture student
2) Select file -> New -> Project
3) Give file name, and select Analog or Mixed A/D then select OK
4) Now select create blank project and select OK
5) Select “Place” to get all the circuit components
6) Connect the circuit as given in the circuit diagram
7) Assign values to all the components as given in the circuit diagram
8) Now select PSpice and then select New Simulation Profile
9) Give name to simulation and select create
10) In simulation setting select Time domain(Transient).
- -
75
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

11) Assign run to time and select Apply

12) Now select Voltage/Level Marker and place it across the load resistor
13) Go to PSpice and select “run” to run the project
14) Output waveform is generated, note down the output.
15) Click on add plot to window in the plot icon.
16) Now place another marker across the input ,to plot the input waveform

- -
76
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Negative clamper

Circuit Diagram:
Netlist
** INCLUDING clamper-SCHEMATIC1.net **
* source CLAMPER
D_D1 N00286 0 D1N4148
C_C1 N00011 N00286 0.01u
V_Vin N00011 0 +SIN 0V 10V 1kHz 0 0 0

Simulation Profile:

Output:

- -
77
 EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Model Graph
Negative clipper
Positive clipper

clamper
Combinational clipper

- -
78
 EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Result :

Thus the various clipper and clamper circuits are studied and simulated using PSPICE

- -
79
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

SIMULATION USING PSPICE

Personal Computer Simulation Program with Integrated Circuit Emphasis (PSPICE)

- -
80
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Tuned Collector Oscillator circuit

Output Waveform

- -
81
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Ex.No Tuned Collector Oscillator

Date:
Aim:

To simulate transistor based tuned collector oscillator circuit using Pspice.

TOOLS:

Multisim Version

PROCEDURE:

❖ Select start -all programs -National Instruments - Multisim.

❖ Select place-component and place the component as required.

❖ Connect the components as per circuit diagram.

❖ Click start button to start the simulation.

❖ Verify the result with the simulation result.

NET LIST :

* source TUNED COLLECTOR OSCILLATOR

X_Q1 N02616 N02195 N02751 awb2n2222 PARAMS:

R_R1 0 N02751 1k

R_R2 0 N02682 10k

R_R3 0 N02195 9k

R_R4 N02195 N02590 14k

R_R5 0 N04482 7

- -
82
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

L_L1 N02616 N02590 1u

L_L2 N04482 N04474 9.8m

V_V1 N02590 0 7v

C_C5 N02616 N02682 70p TC=0,0

C_C6 N04474 N02195 0.026p

C_C7 0 N02195 6.3p

C_C9 N02616 N02590 220p

C_C10 0 N02751 40n

RESULT:

Thus, tuned collector oscillator circuit is simulated using Pspice.

- -
83
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Twin-T Oscillator Circuit Diagram:

Output Waveform:

- -
84
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Ex.No Twin-T Oscillator

Date:
Aim:

To simulate Twin-T Oscillator circuit using Pspice.

TOOLS:

Multisim Version

PROCEDURE:

❖ Select start -all programs -National Instruments - Multisim.

❖ Select place-component and place the component as required.

❖ Connect the components as per circuit diagram.

❖ Click start button to start the simulation.

❖ Verify the result with the simulation result.

NETLIST

* source TWIN T OSCILLATORS

Q_Q1 N00188 N00195 0 Q2N3904

R_R2 N00591 0 100

V_V1 N01044 0 9Vdc

C_C1 0 N00569 47n

C_C2 N00569 N00591 50n

C_C3 N00195 N00620 22n

- -
85
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

C_C4 N00620 N00188 22n

R_R5 0 N00620 1.5k

R_R6 N01044 N00188 3.3k

R_R7 N00569 N00188 18k

R_R8 N00195 N00569 18k

RESULT:

Thus Twin-T Oscillator circuit is simulated using Pspice.

- -
86
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Wien Bridge Oscillator Circuit Diagram

Output Waveform:

- -
87
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Ex.No Wien Bridge Oscillator

Date:
Aim:

To simulate Wien Bridge Oscillator circuit using Pspice.

TOOLS:

Multisim Version

PROCEDURE:

❖ Select start -all programs -National Instruments - Multisim.

❖ Select place-component and place the component as required.

❖ Connect the components as per circuit diagram.

❖ Click start button to start the simulation.

❖ Verify the result with the simulation result.

NETLIST

* source WEIN BRIDGE

R_R1 N14607 N14290 27k

R_R2 N14720 N14290 4.7k

R_R3 N14738 N14290 39k

R_R4 N14816 N14290 4.7k

R_R5 0 N14812 3.3k

R_R6 0 N14738 35k

- -
88
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

R_R7 0 N14724 1k

R_R8 0 N14607 4.7k

C_C1 N14607 N14816 10n TC=0,0

C_C2 0 N14607 10n TC=0,0

X_Q1 N14720 N14607 N14724 awb2n2222 PARAMS:

X_Q2 N14816 N14738 N14812 awb2n2222 PARAMS:

C_C3 N14720 N14738 10n TC=0,0

V_V1 N14290 0 5v

RESULT:

Thus, Wien Bridge Oscillator circuit is simulated using Pspice.

- -
89
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Double Tuned Amplifier Circuit

Output Waveform

- -
90
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Ex.No Double Tuned Amplifier

Date:
Aim:

To simulate transistor based double tuned amplifier circuit using Pspice.

TOOLS:

Multisim Version

PROCEDURE:

❖ Select start -all programs -National Instruments - Multisim.

❖ Select place-component and place the component as required.

❖ Connect the components as per circuit diagram.

❖ Click start button to start the simulation.

❖ Verify the result with the simulation result.

NET LIST:

* source DOUBLE TUNEDAMPLIFIER

Q_Q1 N00420 N00318 N00352 Q2N2222

R_R1 N00367 N00384 80k TC=0,0

R_R2 0 N00367 50k TC=0,0

R_R3 0 N00352 150 TC=0,0

R_R4 N00895 N00384 10 TC=0,0

R_R5 N001291 N00384 40 TC=0,0

C_C1 N00322 N00318 100n TC=0,0

- -
91
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

C_C2 0 N00352 10u TC=0,0

C_C3 N00420 N00384 125p TC=0,0

C_C4 N00514 N00384 1.25n TC=0,0

L_L1 N00514 N001291 2m

V_V1 N00384 0 12

V_V2 N00322 0 DC 1 AC 1Vac

L_L2 N00895 N00420 2m

RESULT:

Thus, double tuned amplifier circuit is simulated using Pspice.

- -
92
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Stagger Tuned Amplifier Circuit Diagram:

Output Waveform:

- -
93
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Ex.No Stagger Tuned Amplifier

Date:

Aim:

To simulate Stagger Tuned Amplifier using Pspice.

TOOLS:

Multisim Version

PROCEDURE:

❖ Select start -all programs -National Instruments - Multisim.

❖ Select place-component and place the component as required.

❖ Connect the components as per circuit diagram.

❖ Click start button to start the simulation.

❖ Verify the result with the simulation result.

NET LIST:

* source STAGGER TUNED AMPLIFIER

Q_Q1 N00476 N00472 N02750 Q2N2222

Q_Q2 N02750 N02813 N00841 Q2N2222

R_R4 N02754 N00472 19k

R_R3 N00472 N00467 55k

R_R1 N00476 N00467 1k

R_R5 0 N02754 10k

- -
94
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

R_R2 0 N00841 800

R_R6 0 N00898 55k

R_R7 N00589 N00671 1k

C_C1 0 N00472 1n

C_C2 N00589 N02813 1u

C_C6 0 N00589 0.029u

C_C4 0 N00841 1u

C_C5 0 N00898 0.009u

C_C3 N00898 N00476 1u

L_L2 0 N00589 0.88uH

L_L1 0 N00898 2.8uH

V_V2 N00671 0 DC 0Vdc AC 1Vac

V_V3 N00467 0 10Vdc

RESULT:

Thus, Stagger Tuned Amplifier is simulated using Pspice.

- -
95
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Bistable Multivibrator Circuit:

- -
96
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Ex.No Bistable Multivibrator

Date:

Aim:

To simulate transistor based Bistable multivibrator using Pspice.

TOOLS:

Multisim Version

PROCEDURE:

❖ Select start -all programs -National Instruments - Multisim.

❖ Select place-component and place the component as required.

❖ Connect the components as per circuit diagram.

❖ Click start button to start the simulation.

❖ Verify the result with the simulation result.

NETLIST:

* source BI STABLE MULTIVIBRATOR

R_R1 N00282 N00361 100k TC=0,0

R_R3 N00282 N00323 2k TC=0,0

R_R4 N00327 N00323 2k TC=0,0

R_R5 0 N05364 22k TC=0,0

C_C1 N002240 N05364 .01u

C_C2 N00282 N00361 1p

- -
97
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Output Waveform

- -
98
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

C_C3 N00379 N00327 1p

V_V1 N002240 0

+PULSE -4v 4V 0S 100ns 100ns 500us 1ms

V_V2 N00323 0 15v

Q_Q3 N01968 N016970 N01901 Q2N2222

Q_Q4 N01905 N01935 N01901 Q2N2222

R_R7 N01882 N016970 3.3k TC=0,0

R_R8 N01968 N02024 5k TC=0,0

R_R9 N01905 N02024 14k TC=0,0

R_R10 0 N01901 2k TC=0,0

R_R11 0 N01935 25k TC=0,0

R_R12 N01935 N01968 27k TC=0,0

C_C5 N01968 N01935 100uf TC=0

V_V4 N02024 0 10Vdc

V_V5 N01882 0 AC 0

+SIN 0v 5v 1Hz 0 0 0

R_R13 0 N00361 22k TC=0,0

R_R14 N00379 N00327 100k

C_C6 0 N00361 .01u

Q_Q5 N00327 N00361 0 Q2N3904

Q_Q6 N00282 N00379 0 Q2N3904

D_D2 N00379 N05364 D1N4002

RESULT:

Thus Bistable Multivibrator is simulated using Pspice.

- -
99
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Schmitt Trigger Circuit

Output Waveform

- -
100
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Ex.No Schmitt Trigger

Date:
Aim:

To simulate transistor based schmitt trigger circuit.

TOOLS:

Multisim Version

PROCEDURE:

❖ Select start -all programs -National Instruments - Multisim.

❖ Select place-component and place the component as required.

❖ Connect the components as per circuit diagram.

❖ Click start button to start the simulation.

❖ Verify the result with the simulation result.

NETLIST:

* Source SCHMITT TRIGGER – Net List

Q_Q1 N00259 N00270 N00388 Q2N2222

Q_Q2 N00384 N00441 N00388 Q2N2222

R_R1 N00259 N00441 27K

R_R2 N00263 N00270 3.3K

R_R3 N00259 N00341 5K

R_R4 N00384 N00341 14K

R_R5 0 N00388 2K

- -
101
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

R_R6 0 N00434 25K

C_C1 N00259 N00434 10fF TC=0

V_V2 N00341 0 10Vdc

V_V3 N00263 0

+SIN 0 5v 2Hz 0 0 0

RESULT:

Thus, Schmitt trigger circuit is simulated using Pspice.

- -
102
 EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-
Power Amplifier Circuit Diagram

Output Waveform:

- -
103
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Ex.No Power Amplifier

Date:
Aim:

To simulate transistor based Class A Power Amplifier circuit.

TOOLS:

Multisim Version

PROCEDURE:

❖ Select start -all programs -National Instruments - Multisim.

❖ Select place-component and place the component as required.

❖ Connect the components as per circuit diagram.

❖ Click start button to start the simulation.

❖ Verify the result with the simulation result.

NETLIST:

* source POWERAMPLIFIER

X_Q1 N00278 N00255 N00306 awb2n2222 PARAMS:

R_R1 N00278 N00282 5.6k TC=0,0

R_R2 N00255 N00282 22k TC=0,0

R_R3 0 N00255 3.4k TC=0,0

R_R4 0 N00306 1.5k TC=0,0

- -
104
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

R_R5 0 N00389 1k TC=0,0

C_C1 N00248 N00255 1n TC=0,0

C_C3 0 N00306 100u TC=0,0

V_V1 N00282 0 22Vdc

V_V2 N00248 0 DC 0Vdc AC 1Vac

C_C4 N00278 N00389 1n TC=0,0

RESULT:

Thus, Class A Power Amplifier Circuit is simulated using Pspice.

- -
105
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

CONTENT BEYOND SYLLABUS

- -
106
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Voltage Time Base Generator

Input and Output Waveform

- -
107
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Ex.No Simulation of Voltage T ime Base Genertator

Date:
Aim:

To simulate transistor based voltage time base generator circuit.

TOOLS:

Multisim Version

PROCEDURE:

❖ Select start -all programs -National Instruments - Multisim.

❖ Select place-component and place the component as required.

❖ Connect the components as per circuit diagram.

❖ Click start button to start the simulation.

❖ Verify the result with the simulation result.

RESULT:

Thus, voltage time base generator circuit is simulated using Multisim.

- -
108
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Current Time Base Generator circuit

Input and Output Waveform

- -
109
EC 8461 - Circuits Design and Simulation Lab Manual 2020 – 2021
-

Ex.No Simulation of Current Time Base Generator

Date:
Aim:

To simulate transistor based current time based generator circuit.

TOOLS:

Multisim Version

PROCEDURE:

❖ Select start -all programs -National Instruments - Multisim.

❖ Select place-component and place the component as required.

❖ Connect the components as per circuit diagram.

❖ Click start button to start the simulation.

❖ Verify the result with the simulation result.

RESULT:

Thus current time base generator circuit is simulated using Multisim.

- -
110