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    Eee4024 Computer-Architecture-And-Organization TH 1.0 37 Eee4024

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    Anbarasan Subramaniyan
    This document outlines an undergraduate course on computer architecture and organization. The course aims to help students understand computer data representation, storage and access across different media. Upon completing the course, students will be able to interpret data flow between computer modules, analyze processor performance, perform arithmetic tasks, understand floating point representation, design register transfer functions, and describe parallel and vector processing. The course consists of 8 modules covering topics like CPU organization, arithmetic, memory systems, pipelining and vector processing. Student performance will be evaluated through class tests, assignments, quizzes and a final assessment test.

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    Eee4024 Computer-Architecture-And-Organization TH 1.0 37 Eee4024

    Uploaded by

    Anbarasan Subramaniyan
    60 views3 pages
    This document outlines an undergraduate course on computer architecture and organization. The course aims to help students understand computer data representation, storage and access across different media. Upon completing the course, students will be able to interpret data flow between computer modules, analyze processor performance, perform arithmetic tasks, understand floating point representation, design register transfer functions, and describe parallel and vector processing. The course consists of 8 modules covering topics like CPU organization, arithmetic, memory systems, pipelining and vector processing. Student performance will be evaluated through class tests, assignments, quizzes and a final assessment test.

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    EEE4024_COMPUTER-ARCHITECTURE-AND-ORGANIZATION_TH_1.0_37_EEE4024

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    This document outlines an undergraduate course on computer architecture and organization. The course aims to help students understand computer data representation, storage and access across different media. Upon completing the course, students will be able to interpret data flow between computer modules, analyze processor performance, perform arithmetic tasks, understand floating point representation, design register transfer functions, and describe parallel and vector processing. The course consists of 8 modules covering topics like CPU organization, arithmetic, memory systems, pipelining and vector processing. Student performance will be evaluated through class tests, assignments, quizzes and a final assessment test.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    60 views3 pages

    Eee4024 Computer-Architecture-And-Organization TH 1.0 37 Eee4024

    Uploaded by

    Anbarasan Subramaniyan
    This document outlines an undergraduate course on computer architecture and organization. The course aims to help students understand computer data representation, storage and access across different media. Upon completing the course, students will be able to interpret data flow between computer modules, analyze processor performance, perform arithmetic tasks, understand floating point representation, design register transfer functions, and describe parallel and vector processing. The course consists of 8 modules covering topics like CPU organization, arithmetic, memory systems, pipelining and vector processing. Student performance will be evaluated through class tests, assignments, quizzes and a final assessment test.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 3

    EEE4024 Computer Architecture & Organization L T P J C

    3 0 0 0 3

    Pre-requisite EEE3002 Syllabus version

    Anti-requisite v. 1.0

    Course Objectives:

    1. To gain an understanding of computer data representation and manipulation.


    2. To understand the basic organization for data storage and access across various media.
    Expected Course Outcome:

    On the completion of this course the student will be able to:

    1. Interpret the data flow between various modules of the computer and data representation in
    various formats.
    2. Analyze the performance of processor and their interconnections.
    3. Perform the various arithmetic tasks and familiarize the various multiplication algorithms.
    4. Acquaint the knowledge about floating point and decimal arithmetic’s.
    5. Design the various register transfer functions and program in various CPU organizations.
    6. Realize the various mapping techniques and familiarize the various data transfer mechanism.
    7. Describe the functionality of parallel and vector processing and its issues.
    Student Learning Outcomes (SLO): 2,11,17

    Module:1 Fundamental Concepts 4 Hours

    Introduction- Generation of Computer, Computer families and developments, Functional units, Basic
    operational concepts, Data Representation-Fixed point and Floating point numbers.

    Module:2 Introduction to computer architecture 5 Hours

    CPU organization by Vou-Newmann model, CPU transistor count-Moore’s law, Performance


    analysis of CPU, Typical Mother board, interconnection of components.

    Module:3 Computer Arithmetic 7 Hours

    Fixed-Point Arithmetic, Addition, Subtraction, Multiplication and Division, Combinational and


    Sequential ALUs, Carry look ahead adder, Robertson algorithm, booth's algorithm, Modified booth's
    Algorithm.

    Module:4 Floating point and Decimal Arithmetic 3 Hours

    Floating Point Arithmetic, Decimal Arithmetic unit-Decimal Arithmetic operations.


    Module:5 Introduction to CPU Design 9 Hours

    Function of CPU, Register Classification and organization, ALU and control unit, instruction set with
    examples, addressing modes, stack organization, Register Transfer, Bus and memory transfers, Input
    - Output and Interrupt. Micro programmed control CPU design.

    Module:6 Memory System Design and I/O Organization 7 Hours

    Basic concepts semiconductors, RAM memories, Read-only memories- Cache memory and related
    mapping- Virtual memories. Introduction to buses and connecting I/O devices to CPU and
    memory-Programmed controlled I/O transfer- Interrupt controlled I/O transfer-DMA Controller.

    Module:7 Pipeline and Vector Processing 8 Hours

    Introduction to pipelining and pipeline hazards-design issues of pipeline architecture-Instruction level


    parallelism and advanced issues-parallel processing concepts-Vector Processing, Array Processors,
    CISC, and RISC & VLIW.

    Module:8 Contemporary issues: 2 Hours

    Total Lecture hours: 45 Hours

    Text Book(s)

    1. William Stallings, "Computer Organization and Architecture", Prentice Hall, Tenth


    Edition, 2016.

    2. Car Hamacher, ZvonksVranesic, SafeaZaky, "Computer Organization", McGraw Hill,


    Fifth Edition, 2011.

    Reference Books

    1. David A. Patterson & John L. Hennessy, "Computer Architecture: A Quantitative


    Approach", Elsevier, Fifth Edition, 2012.

    Mode of valuation: CAT I & II – 30%, DA I & II – 20%, Quiz – 10%, FAT – 40%

    Mode of assessment:

    Recommended by Board of Studies 29/05/2015


    Approved by Academic Council 37th AC Date 16/06/2015

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