High Level Digital Design

1214-0420
Anas Melhem
Computer System Engineering Department
Palestine Technical University

Today: Readings:
• VHDL Data Types • B. J. LaMeres, Quick
• VHDL Model Construction Start Guide to VHDL,
Chapter 2
Hardware Description Languages
•HDL is a specialized computer language used to program electronic and
digital logic circuits.
•The structure, operation and design of the circuits are programmable using
HDL.
•HDL includes a textual description consisting of operators, expressions,
statements, inputs and outputs.
•Example of HDL’s: ABEL, VERILOG, VHDL
•Advantages:
◦ Documentation
◦ Flexibility (easier to make design changes or mods)
◦ Portability (if HDL is standard)
◦ One language for modeling, simulation (test benches), and synthesis
VHDL
•VHSIC Hardware Description Language
◦ Very High Speed Integrated Circuit

•Standard language used to describe digital hardware devices, systems and

components
◦ Developed initially for documentation
◦ Approved as an IEEE Standard in December 1987

•Advantages:
◦ Allows the behavior of the required system to be described (modeled) and
verified (simulated) before synthesis tools translate the design into real hardware
(gates and wires).
◦ VHDL allows the description of a concurrent system. VHDL is a dataflow language
in which every statement is considered for execution simultaneously, unlike
procedural computing languages such as BASIC, C, and assembly code, where a
sequence of statements is run sequentially one instruction at a time.
What is VHDL
•A way of describing the operation of a system
◦ Example: a 2-input multiplexer
Example Synthesis Results
Introduction to VHDL
•VHDL is not case sensitive.
•Each VHDL assignment, definition, or declaration is terminated with
a semicolon (;).
• Line wraps are allowed and do not signify the end of an assignment,
definition, or declaration.
•Comments in VHDL are preceded with two dashes (i.e., --) and continue until
the end of the line.
•All user-defined names in VHDL must start with an alphabetic letter, NOT a
number.
•User-defined names are not allowed to be the same as any VHDL keyword.
•In VHDL, every signal, constant, variable, and function must be assigned a
data type.
VHDL Data Types
•The IEEE standard package provides a variety of pre-defined data types.
•The following are the most commonly used data types in the VHDL Package
standard of library std (Included by default ):
◦ Enumerated Types
◦ Range Types
◦ Physical Types
◦ Vector Types
◦ User-Defined Enumerated Types
◦ Array Type
◦ Subtypes
Enumerated Types
•An enumerated type is one in which the exact values that the type can take
on are defined.

•The individual scalar values are indicated by putting them inside single
quotes (e.g., ‘0,’ ‘a,’ ‘true’).
•The type bit is synthesizable, while Boolean and character are NOT.
Enumerated Types: example
•Example:
◦ SIGNAL x: BIT;
◦ x <= '1’;
◦ variable VAR1: boolean := 'FALSE';
Range Types
•A range type is one that can take on any value within a range.

•The integer type is a 32-bit, signed, two’s complement number and is

synthesizable.
•If the full range of integer values is not desired, this type can be bounded by
including range <min> to <max>.
•The real type is a 32-bit, floating point value and is not directly synthesizable
unless an additional package is included that defines the floating point
format.
•The values of these types are indicated by simply using the number without
quotes (e.g., 33, 3.14).
Range Types: example
•SIGNAL SUM: integer range 0 to 256 :=16;
• constant Pi : real := 3.14159;
Physical Types
•A physical type is one that contains both a value and units.
•In VHDL, time is the primary supported physical type.

•The base unit for time is fs, meaning that, if no units are provided, the value
is assumed to be in femtoseconds.
•The value of time is held as a 32-bit, signed number and is not synthesizable.
•Example: Delay: TIME := 0 ns
 Vector Types
•A vector type is one that consists of a linear array of scalar types.

•The size of a vector type is defined by including the maximum index, the keyword
downto, and the minimum index.
◦ For example, if a signal called BUS_A was given the type bit_vector(7 downto 0), it
would create a vector of 8 scalars, each of type bit. The leftmost scalar would have an
index of 7 and the rightmost scalar would have an index of 0.
•Each of the individual scalars within the vector can be accessed by providing the
index number in parentheses.
◦ For example, BUS_A(0) would access the scalar in the rightmost position. The indices
do not always need to have a minimum value of 0, but this is the most common
indexing approach in logic design.
•The type bit_vector is synthesizable, while string is not. The values of these types
are indicated by enclosing them inside double quotes (e.g., “0011,” “abcd”).
Vector Types: example
•SIGNAL y: BIT_VECTOR (3 DOWNTO 0);
•SIGNAL w: BIT_VECTOR (0 TO 7);
a user can define his/her own type in VHDL!!!

User-Defined Enumerated Types

•A user-defined enumerated type is one in which the name of the type is
specified by the user in addition to all of the possible values that the type
can assume.

•In this example, a new type is created called traffic_light.

•If we declared a new signal called Sig1 and assigned it the type traffic_light,
the signal could only take on values of red, yellow, and green.
•User-defined enumerated types are synthesizable in specific applications.
Array Type
•An array contains multiple elements of the same type {scalar or vectors}.
•In order to use an array, a new type must be declared that defines the
configuration of the array.
•Once the new type is created, signals may be declared of that type.
•The range of the array must be defined in the array-type declaration.
•The range is specified with integers (min and max) and either the keywords
downto or to.

◦ the new array type is declared with eight elements.

◦ The beginning index of the array is 0 and the ending index is 7.
◦ Each element in the array is a 16-bit vector of type bit_vector.
Subtypes
•A subtype is a constrained version or subset of another type.
•The following is the syntax for declaring a subtype and two examples of
commonly used subtypes (NATURAL and POSTIVE) that are defined in the
standard package.
VHDL Model Construction
•A VHDL design describes a single system in a single file, *.vhd.
•Within the file, there are two parts that describe the system:
◦ the entity: describes the interface to the system (i.e., the inputs and outputs)
◦ the architecture: describes the behavior.

•The functionality of VHDL (e.g., operators, signal types, functions, etc.) is

defined in the package.
•Packages are grouped within a library.
•the VHDL base set of functionality for in the standard package. This package
is contained within a library called IEEE.
•The library and package inclusion is stated at the beginning of a VHDL file
before the entity and architecture.
VHDL Model Construction
Libraries and Packages
•The keyword library is used to signify that packages are going to be added to
the VHDL design from the specified library. The name of the library follows
this keyword.
•To include a specific package from the library, a new line is used with the
keyword use followed by the package details.
•The package syntax has three fields separated with a period.
•The first field is the library name. The second field is the package name. The
third field is the specific functionality of the package to be included. If all
functionality of a package is to be used, then the keyword all is used in the
third field.
The Entity
•The entity in VHDL describes the inputs and outputs of the system. These are
called ports.
•Each port needs to have its name, mode, and type specified.
◦ The name is user-defined.
◦ The mode describes the direction data is transferred through the port and can
take on values of in, out, inout, and buffer.
◦ The type is one of the legal data types described sildes before.

•Port names with the same mode and type can be listed on the same line
separated by commas.
Example 2.1 shows multiple approaches for defining an entity
The Architecture
•The architecture in VHDL describes the behavior of a system.
•There are numerous techniques to describe behavior in VHDL that span
multiple levels of abstraction.
•The architecture is where the majority of the design work is conducted.
Signal Declarations
•A signal that is used for internal connections within a system is declared in the
architecture.
•Each signal must be declared with a type. The signal can only be used to make
connections of like types.
•A signal is declared with the keyword signal followed by a user-defined name,
colon, and the type.
•Signals of like type can be declared on the same line separated with a comma.
•All of the legal data types described in slides before can be used for signals.
•Signals represent wires within the system so they do not have a direction or
mode.
•Signals cannot have the same name as a port in the system in which they reside.
Signal Declarations
Signal Declarations
•VHDL supports a hierarchical design approach.
◦ Signal names can be the same within a sub-system as those at a higher level
without conflict.
Constant Declarations
•A constant is useful for representing a quantity that will be used multiple
times in the architecture.

•Once declared, the constant name can now be used throughout the
architecture.
•Notice that since we defined the constant to be the actual width of the
vector (i.e., 32-bits), we need to subtract one from its value when defining
the indices (i.e., 31 down to 0).
Component Declarations
•A component is the term used for a VHDL sub-system that is instantiated
within a higher-level system.
•If a component is going to be used within a system, it must be declared in
the architecture before the begin statement.

•The port definitions of the component must match the port definitions of
the sub-system’s entity exactly. As such, these lines are typically copied
directly from the lower-level systems VHDL entity description.
•Once declared, a component can be instantiated after the begin statement in
the architecture as many times as needed.
VHDL Sample Code