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Schematic Design and Layout of Flipflop using CMOS Technology

Article · July 2017

DOI: 10.14445/23488549/IJECE-V4I7P103

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SSRG International Journal of Electronics and Communication Engineering ( SSRG – IJECE ) – Volume 4 Issue 7 – July 2017

Schematic Design and Layout of Flipflop

using CMOS Technology
1
Sana Ur Rahman, 2Tarana Afrin Chandel
12
Department of ECE, Integral University Lucknow , INDIA

Abstract- current which flows directly from supply (Vdd)

In this paper the work is done on low power terminal to the ground. High leakage current plays
and high speed design of flipflop using CMOS the most significant role of contributor in the power
technology on different nanoscale technologies i.e. dissipation of CMOS circuit as the threshold voltage,
90 nm, 65nm and 45 nm. The transistor used small gate oxide thickness and channel length are reduced.
area and low power consumption. By decreasing the In this paper the work is done on
geometrical feature size of the transistors we can Multithreshold CMOS technology. There are many
achieve the low power consumption and high speed technique proposed for flip flop and latches. In
of integrated circuit in VLSI design. When the figure1 shows 11 transistor TSPC D flipflop with
technology size decreases in the result of this the positive edge triggered which later on reduces to 8
leakage power increases which is reduced by type of transistors and further reduced to 6 transistors in
CMOS technology. The comparisons are held TSPC which 4 NMOS and 2 PMOS were used. The
D-Flipflop and Multi threshold CMOS technology schematic design of TSPC filp flop is shown in figure
and among the power consumption propagation 1 in which 5 transistors where 3 NMOS and 2 PMOS
delay and power dissipation product. The work is are used.
carried out with the help of tanner EDA tool.

Keywords- CMOS technology, Nanoscale

technology, VLSI design, Tanner EDA tool.

I. INTRODUCTION
For designing IC chip the circuit consist of
many numbers of logic gates which are integrated
inside. The minimization of power dissipation in any
circuit has always been a big challenge for any circuit
designer. There are many related works which are
already carried out by different groups with different
techniques like bipolar junction transistor, CMOS
technology, BiCMOS technology etc. Designers are
able to work on more transistors onto the same die Figure 1: TSPC D Flipflop with 5 Transistor
because of the shorter size of the CMOS as per
Moore’s law. CLK IN M1 M2 M3 M4 M5 OU
P T
Latches and Flipflops are the sequential
↑ 0 ON ON OFF OFF ON 0
circuits that stores 1 and 0 state called logic states.
Latches works on level triggered while flip flops ↑ 1 OFF ON ON ON OFF 1
works on edge triggred. A Flipflop is a bistable ↓ 0 ON OFF OFF OFF OFF 0
circuit which give the output in response to a ↓ 1 OFF OFF ON OFF OFF 0
reference pulse. The data stored in flip flops on the Table 1: Truth Table of D Flipflop
rising and falling edge of the clock signal is applied
as the inputs to other sequential circuits. Those flip TSPC D Flipflop turns into a Multithreshold
flops which stores data on both the rising and falling CMOS technology when 1 PMOS transistor and
of the clock signal are termed as double edge 1NMOS transistor are connected to the circuit of
triggered flipflops and those flip flops that stores data TSPC D Flipflop which is shown in Figure2.The
either on the rising or falling edge are known single Multi Threshold CMOS Technique is very important
edge triggered flipflops. Low Power Technique which reduces the Leakage
Power effectively. This technique works in two
modes, Mode 1 and Mode 1: High Threshold Mode
II. DESIGN ANALYSIS
and Mode 2: Low Threshold Mode.. Mode 1 reduces
Basically there are three source of power the leakage power and Mode 2 improves the speed
dissipation in CMOS digital circuits. The first one is of the system.
due to signal transistor, the second one is due to the
leakage current and the last one is from short circuit

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SSRG International Journal of Electronics and Communication Engineering ( SSRG – IJECE ) – Volume 4 Issue 7 – July 2017

Figure 3 :Multithreshold CMOS Based D Flipflop on

90 nm Technology at 1V

The figure 3, 4 & 5 shows the output results

of our proposed designed Multithreshold CMOS
baesd D flip flop on 90nm, 65nm and 45 nm
respectively. All the figures contain the Clk, sleep,
Vin, Sleep bar and Vout waveforms. The voltage
range for the Vin had been checked and verified by
Figure 2: Multi Threshold CMOS providing pulse waveform whose amplitude is 1v, or
0.5v. The clock pulse is designated by clk pulse
CL I Sleep Sleep M M M M M
O M M whose amplitude is also varied from 1v or 0.5v
K N bar 1 2 3 4 5
U 6 7 (depends on the voltage range of the entire
T circuit.)There are two additional signal has been
↑ 0 0 1 ON ON OFF OFF ON ON OFF 0 provided to reduce the power dissipation of the
↑ 0 1 0 ON ON OFF OFF OFFOFF ON 0 circuit. These pulse trains are named as sleep and
sleep bar. The vin signal is shown by the green color,
↑ 1 0 1 OFF ON ON ON OFF ON OFF 1
the yellow color depicts the clk signal, the blue color
↑ 1 1 0 OFF ON ON ON OFFOFF ON 1 shows the waveforms for the sleep signal and at last
↓ 0 0 1 ON OFF OFF OFF OFF ON OFF 0 the generated output pulse i.e. Vout has been shown
↓ 0 1 0 ON OFF OFF OFF OFFOFF ON 0 by purple color.
↓ 1 0 1 OFF OFF ON OFF OFF ON OFF 0
↓ 1 1 0 OFF OFF ON ON OFFOFF ON 0
Table 2:Truth Table of Multi Threshold CMOS

III. RESULT
The performance analysis of the D Flipflop
and latches are presented there. T Spice and S-Edit
are used to carryout the work for different
technologies like 90nm, 65nm and 45nm
technologies.
Figure 4: Multithreshold CMOS based D Flip flop on 65
Parameter 90 nm 65 nm 45 nm nm Technology at 1V

0.5V 1V 0.5 1V 0.5V 1V

V

Power 0.2435 1.2847 0.2293 1.3122 0.1377 1.9015

Dissipatio
n(µW)

Delay(nS) 2.9316 0.2365 0.1963 0.02867 0.6414 0.0282

Power 0.7138 0.0304 0.0450 0.03762 0.8831 0.0537

Delay 2
Product(fJ)
Figure 5: Multithreshold CMOS Based D Flip Flop on
45 nm Technology at 1V
Table 1: Power Delay Comparison for TSPC Based D
Flipflop
The comparison between different
technologies and different scaled supply voltages is
shown in Table 1 for TSPC D Flipflop and Table 2
for Multithreshold CMOS D Flipflop respectively.

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 SSRG International Journal of Electronics and Communication Engineering ( SSRG – IJECE ) – Volume 4 Issue 7 – July 2017

Parameter 90 nm 65 nm 45 nm CMOS based D Flip-Flop has advantage of low

power delay product which is well suited for high
0.5V 1V 0.5V 1V 0.5V 1V performance applications.

Power 0.19 1.33 0.21 1.33 0.15 0.834 ACKNOWLEDGEMENT

Dissipation( 00 22 47 80 87 74 I am very thankful to my guide Ms Tarana
µW)
Afrin Chandel for her motivations and her assistance
Delay(nS) 0.23 0.10 0.24 1.15 0.26 0.106
throughout my M.Tech studies.
59 45 71 64 75 5
REFERENCES
[1] CH. DayaSagar and T. Krishna Moorthy, “Design of A Low
Power Delay 0.04 0.13 0.05 1.54 0.04 0.089 Power FlipFlop using MTCMOS”International Journal of
Product(fJ) 48 92 37 72 25 2 Computer Applications & information Technology in July
2012.
Table 2: Power Delay Comparison for MTCMOS Based [2] Rishikesh V. TambatȦ*and SonalA.LakhotiyaȦ, “Design of
D Flipflop Flip-Flops for High Performance VLSI Applications using
Deep Submicron CMOS Technology”International Journal of
Current Engineering and Technology in April 2014.
The table 1 & 2 shows the various [3] B.Chinnarao, B.Francis&Y.Apparao,”Design of A Low
parameters e.g. Power dissipation, Delay and power Power Flip-Flop Using CMOS Deep Submicron
Technology” Intrnational Journal of Electronics Signals and
delay product for TSPC and MTCMOS on various Systems in 2012.
nanometer technology scales. As the table shows the [4] Pratiksha Gupta, Dr. Rajesh Mehra,”Low Power Design of
variation in the delay and power dissipation while we SRFlipFlop Using 45nm Technology” IOSR Journal of VLSI
are changing the technology file(s) at different and Signal Processing in 2016.
various voltage levels. [5] K.Rajasri, A.Bharathi, M.Manikandan, ”Performance of
FlipFlop using 22nm CMOS Technology” International
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[6] Kaphungkui N K ,”Design of low-power, high performance
flip-flops” International Journal of Applied Sciences and
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[7] M. A. Hernandez and M. L. Aranda, “A Clock Gated Pulse –
Triggered D Flip-Flop For Low Power High Performance
VLSI Synchronous Systems,” Proceedings of the 6th
International Caribben Conference on devices, circuits and
systems, Mexico, Apr. 26-28, 2006.
[8] J.S. Wang, P.H. Yang “A Pulse Triggered TSPC FF for high
speed, low power VLSI design applications” IEEE, 1998
[9] J. Wang et al., "Design of a 3-V 300-MHz Low-Power 8-b
×8-b Pipelined Multiplier Using Pulse-Triggered TSPC Flip
Flops," IEEE J. Solid-State Circuits, vol. 35, no. 5, pp. 583-
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[10] A. Keshavarzi, K. Roy, and C. F. Hawkins, “Intrinsic leakage
in low power deep submicron CMOS ics,” in Proc. Int. Test
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Figure 6: Layout of Multi Threshold based D Flipflop

The figure 6 shows the layout diagram of the

Multi threshold D flip flop by using in which all
metal lines are drawn in Blue colors, all active layers
are by green color and the polysilicon layers are
drawn by the Red color for active region. The
complete layout has been carried out on Tanner L-
Edit tool.

IV. CONCLUSION
We had successfully designed and simulated
our CMOS based D flip flop using TANNER EDA
tool. In our design we had obtained the power
dissipation lesser than we referred. From the tables 1
& 2 listed above, it is clear that the power dissipation
decreases and propagation delay increases as the
technology is scaled down. Also as the supply
voltage is scaled down, both the power dissipation
and propagation delay decrease. When compared
with TSPC based D Flip-Flop, the Multi threshold

ISSN: 2348 – 8549 www.internationaljournalssrg.org Page 18

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