LAB 3 – Synchronous Serial

P t Design
Port D i Using
U i Verilog
V il

Spring 2011
TA : Junyoung Park
VLSI Lab Overview

VCS
„ Verilog
lab3 RTL level
‰ Hardwa re Description
p
Design Vision Language (HDL)
(Synthesis tool)
Virtuoso
Vi t
‰ Behavioral Description
p
lab2 Gate level editor ‰ Structural Description
APR ttooll ‰ Synthesizable code
Tr. level
lab1 Virtuoso
editor
Layout
VLSI Lab Overview (Con’t)
( )
„ RTL level system design using Verilog (Behavioral modeling) to design
‰ Part A: Synchronous Serial Port (SSP)

‰ Part B: Integration of SSP with ARM processor using a SoC bus

interface called “WISHBONE”
WISHBONE
„ Verilog Simulators
‰ Simulator – VCS (Synopsys), ncverilog (Cadence)

„ Tools
‰ Simulation:

„ VCS – Verilog
V il simulation
i l i tooll
„ VirSim – GUI to control simulation and view waveforms
‰ Synthesis:
„ Design Vision – Logic Synthesis
Lab3
Lab3A – SSP Design
g
„ SSP Perform
‰ Parallel-to-serial conversion on data received from a
processor
‰ Serial-to-parallel conversion on data received from a
peripheral device

„ Your design
g
‰ Your SSP provides buffering capability on both the TX
and RX logic using FIFOs to allow up to four 8-bit
words to be stored in independently in both TX and RX
module
Lab3A – SSP Block Diagram
g
Lab3A – SSP Specifications
p
„ Transmit FIFO(TxFIFO)/ Receive FIFO(RxFIFO)
‰ 8-bit wide, 4-location deep FIFO memory buffer
‰ If FIFO is full,
full generate SSPTXINTR/SSPRXINTR interrupt
signal and refuse to accept any additional data
„ Transmit and Receive Logic
‰ TX Logic:
„ read from TxFIFO and perform parallel-to-serial conversion
„ S d th
Send the serial
i l data
d t synchronously
h l
‰ RX Logic:
„ pe o serial-to-parallel
perform se op e conversion
co ve s o oon thee incoming
co g data
d
synchronously
„ Send data into RxFIFO
Lab3A – Port Descriptions
p

„ Name your top module as “ssp”

„ You should use the exact names shown below
„ SSP module port description
‰ IInput port: PCLK
PCLK, CLEAR
CLEAR_B,
B PSEL,
PSEL PWRITE,
PWRITE
PWDATA[7:0], SSPCLKIN, SSPFSSIN, SSPRXD
‰ Output port: PRDATA[7:0], SSPOE_B, SSPTXD,
SSPCLKOUT, SSPFSSOUT, SSPTXINTR,
SSPRXINTR
Lab3A – Signal
g Description
p
„ Please refer to the lab website for details
„ Si l descriptions
Signal d i ti
‰ CLEAR_B: Low active clear signal

‰ SSPCLKIN(RxLogic), SSPCLKOUT(TxLogic)
„ Synchronization clock for data transfer
„ 2 times slower than PCLK (clock for SSP)
‰ PSEL: Chip select signal for SSP
‰ PWRITE: High – Write to SSP, Low – Read from SSP
‰ SSPFSSIN(RxLogic), SSPFSSOUT(TxLogic)
„ Indicate startingg of data transfer
‰ SSPOE_B: Low active output enable signal, indicating when SSPTXD
is valid (Used only for transmission)
‰ Assume p perfect synchronization
y between SSPCLKIN and
SSPCLKOUT - testing is done with external loop back
„ Dataflow: (Written by the processor) Æ SSP TxFIFO Æ SSPTXD Æ
SSPRXD Æ SSP RxFIFO Æ (Read by the processor)
Lab3A – Timing
g Diagram
g (single
( g
transfer)
Lab3A – Timing
g Diagram
g (continuous
(
transfer)
Lab3A – Logic
g Synthesis
y
„ Regularly
egu y synthesize
sy es e youyour code by reading
e d g in your
you
design to make sure your design is synthesizable
Lab3B – WISHBONE SoC
Lab3
interconnection interface
„ Objective
‰ To design WISHBONE bus interface module to
i t
integrate
t heterogeneous
h t modules
d l
Lab3 – What is g
given to yyou
Lab3 – What y
you should do
Lab3B – Module Descriptions
p
„ ARM processor (Given)
‰ A master core of your system
„ Memory module (Given)
‰ Simple memory block used as an instruction memory
„ Synchronous Serial Port (Designed in Lab3A)
‰ Sl
Slave core off your system
t
„ WISHBONE & Clock Management Unit (Need to design
i Lab3B)
in L b3B)
‰ WISHBONE master: communicate with the ARM core
‰ WISHBONE slave:
l communicate
i t with
ith the
th SSP andd memory
module
‰ Clock Management Unit: manage all the clocks and interrupts
Lab3B – WISHBONE
„ Master:
‰ When the ARM core gets the data transfer activities,
WISHBONE master has to transfer the data from/to the
WISHBONE slave

„ Slave:
‰ Transfer the data to/from the memory of SSP according to
request from
f the
h ARM
A core, and
d then
h report the
h result
l off the
h
transfer to the WISHBONE master

„ Should be done with WISHBONE’s timing specifications

Lab3B – WISHBONE (Con’t)
( )
„ Clock Management Unit
‰ for ARM processor (phi1, phi2)
‰ for Memory (phi1, phi2)
‰ for WISHBONE and SSP (clk_o)

„ If interrupts are occurred, Clock Management Unit should

stopp the clock for ARM processor.
p
Lab3B – WISHBONE (Con’t)
( )
‰ Instruction Read
„ When ARM accesses h’00000000 – h’000FFFF
Wh
„ Generate memory access signals
„ Deliver instructions from memory
y to ARM
„ Mem Æ Slave Æ Master Æ ARM
‰ Path: Read signal (ARM) Æ master Æ slave Æ memory Æ data from
memoryy Æ slave Æ master Æ ARM ((instruction transferred to ARM))

‰ Data Read from SSP

„ When ARM access h’0010001
Wh
„ Generate SSP access signals
„ Deliver data from SSP ((RxFIFO)) to ARM
„ SSP Æ Slave Æ Master Æ ARM
‰ Path: Read signal (ARM) Æ master Æ slave Æ SSP Æ data from SSP
Æ slave Æ master Æ ARM (data transferred to ARM)
Lab3B – WISHBONE (Con’t)
( )
‰ Data Write to SSP
„ When ARM access h’0010000
„ Generate SSP access signals
„ Deliver data from ARM to SSP (TxFIFO)
„ ARM Æ Master Æ Slave Æ SSP
‰ Path: Read signal and data (from ARM) Æ master Æ slave Æ
SSP (data written to SSP)

‰ Interrupt Handling
„ S
Stop A
ARM bby hholding
ldi phi1
hi1 andd phi2
hi2 (Clock
(Cl k Management Unit)
i)
‰ E.g., SSP Overflow Interrupt
‰ SSP Æ Clock Management Unit Æ ARM (holds clocks)
Lab3B – Simulation
„ Write
W it your own assembly
bl test
t t program using
i ARM
instructions
‰ Read ARM manual ggiven to yyou

„ Compile the assembly code and save it to /image/mem.dat

(Æ t l memory image)
(Æactual i )
‰ asm_arm my_assembly_code > mem.data
‰ Template mem.data
mem data can be found in Lab3 website – you may
choose to create your own

„ R VCS
Run