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    Alpuerto Activity No. 1 HDL

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    다나
    The document provides two examples of Verilog code to implement a logic circuit with inputs A, B, C and output L. The first example uses structural style to define the circuit, breaking it down into NOT gates (Not1, Not2, Not3) that are then combined to produce the output L. The second example uses behavioral style, directly assigning the output L as the simplified logical expression of the inputs A, B, and C using bitwise operators.

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    Alpuerto Activity No. 1 HDL

    Uploaded by

    다나
    22 views1 page
    The document provides two examples of Verilog code to implement a logic circuit with inputs A, B, C and output L. The first example uses structural style to define the circuit, breaking it down into NOT gates (Not1, Not2, Not3) that are then combined to produce the output L. The second example uses behavioral style, directly assigning the output L as the simplified logical expression of the inputs A, B, and C using bitwise operators.

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    Alpuerto Activity No. 1 Hdl .Docx

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    The document provides two examples of Verilog code to implement a logic circuit with inputs A, B, C and output L. The first example uses structural style to define the circuit, breaking it down into NOT gates (Not1, Not2, Not3) that are then combined to produce the output L. The second example uses behavioral style, directly assigning the output L as the simplified logical expression of the inputs A, B, and C using bitwise operators.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    22 views1 page

    Alpuerto Activity No. 1 HDL

    Uploaded by

    다나
    The document provides two examples of Verilog code to implement a logic circuit with inputs A, B, C and output L. The first example uses structural style to define the circuit, breaking it down into NOT gates (Not1, Not2, Not3) that are then combined to produce the output L. The second example uses behavioral style, directly assigning the output L as the simplified logical expression of the inputs A, B, and C using bitwise operators.

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    © All Rights Reserved
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    Download as pdf or txt
    of 1

    ALPUERTO, DANICA MAE V.

    20160102705
    ACTIVITY 1

    (1) Write the Verilog HDL using Structural Style

    A B C L
    SOP: L = A’B’C’ + A’B’C + AB’C + ABC’
    0 0 0 1
    SIMPLIFIED: L = AB’C + ABC’
    0 0 1 1
    module struc (L, A, B, C);
    0 1 0 0 input A, B, C;
    0 1 1 0 output L;

    m
    1 0 0 0

    er as
    not Not1 (AC, A), Not2 (BC, B), Not3

    co
    1 0 1 1

    eH w
    (CC, C);

    o.
    1 1 0 1 end module
    rs e
    ou urc
    1 1 1 0

    (2) Write the Verilog HDL using Behavioral Style


    o
    aC s

    A B C L
    vi y re

    SOP: L = A’BC + AB’C + AB’C + ABC’+ ABC


    0 0 0 0
    SIMPLIFIED: L = A + BC
    ed d

    0 0 1 0
    module struc (L, A, B, C);
    ar stu

    0 1 0 0 input A, B, C;
    0 1 1 1 output L;
    is
    Th

    1 0 0 1
    assign L =(A)| (B & C);
    1 0 1 1
    sh

    end module
    1 1 0 1

    1 1 1 1

    This study source was downloaded by 100000817485283 from CourseHero.com on 09-09-2021 02:15:45 GMT -05:00

    https://www.coursehero.com/file/92655292/ALPUERTO-Activity-No-1-HDLdocx/
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