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EEE Digital Assignment (Software) : Logic Gates

This document describes a digital logic gates simulation assignment. The student was asked to simulate primary logic gates using only NAND gates in a circuit simulator. Diagrams are provided showing the simulation circuits for AND, OR, NOT, NAND and NOR gates individually, as well as implementations of AND, OR and NOT gates using only NAND gates. The student provides the procedure, model graphs of the simulated circuits, and concludes that they now have a clear understanding of using different logic gates including how NAND can be used to form other basic gates.

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72 views12 pages

EEE Digital Assignment (Software) : Logic Gates

This document describes a digital logic gates simulation assignment. The student was asked to simulate primary logic gates using only NAND gates in a circuit simulator. Diagrams are provided showing the simulation circuits for AND, OR, NOT, NAND and NOR gates individually, as well as implementations of AND, OR and NOT gates using only NAND gates. The student provides the procedure, model graphs of the simulated circuits, and concludes that they now have a clear understanding of using different logic gates including how NAND can be used to form other basic gates.

Uploaded by

bolbo na
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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EEE Digital Assignment

(Software)

Logic Gates

Name: Om Ashish Mishra

Registration Number: 16BCE0789

Slot: L11+L12

Batch: 10(B-Tech Computer Science (Core))


LOGIC GATES

AIM:
To from primary logic gates using Universal logic gate(NAND).

APPARATUS/TOOL REQUIRED:

ORCAD / PSpice simulator - > 7400 Library – 7408, 7432, 7486, 7404,7402&7400
&7400

Simulation Settings: Analysis Type - Time Domain


Run to time - 8ms

CIRCUIT DIAGRAM:
SIMULATION CIRCUIT DIAGRAM:

Fig: AND GATE

Fig: OR GATE

Fig: NOT GATE

Fig: NAND GATE


Fig: NOR GATE

Fig: ALL

Fig: AND Using NAND


Fig: OR Using NAND

Fig: NOT Using NAND


THEORY:

Rectangular
shape
Distinctive shape
(IEEE Std 91/91a- Boolean
Type (IEEE Std 91/91a- Truth table
1991 algebra between A & B
1991)
IEC 60617-12 :
1997)

INPUT OUTPUT

A B A AND B

0 0 0
AND
A.B
0 1 0

1 0 0

1 1 1

INPUT OUTPUT

A B A OR B

0 0 0
OR A+B
0 1 1

1 0 1

1 1 1
NPUT OUTPUT

A NOT A
NOT Á
0 1

1 0

INPUT OUTPUT

A NAND
A B
B

0 0 1
NAND (A.B)’

0 1 1

1 0 1

1 1 0

INPUT OUTPUT

A B A NOR B
NOR (A+B)’
0 0 1

0 1 0
1 0 0

1 1 0

PROCEDURE:
Step 1: Open Capture CIS

Step 2: Click on the File button

Step 3: Click on New Project

Step 4: Select Blank Project

Step 5: Go to Library and click on Sources

Step 6: Select 7400 Library – 7408, 7432, 7486, 7404, 7402&7400

Step 7: Click on New Simulation

Step 8: Analysis Type - Time Domain

Step 9: Run to time – 8 ms (for 2 cycles)

Step 10: Apply it

Step 11: Then we run the simulated program

Step 12: Then we get the graph as the output.


MODEL GRAPH:

Fig: AND GATE

Fig: OR GATE
Fig: NOT GATE

Fig: NAND GATE


Fig: NOR GATE

Fig: AND GATE USING NAND GATE


Fig: OR GATE USING NAND GATE

Fig: NOT GATE USING NAND GATE

RESULT:
We also learned to use NAND GATE which is one of the Universal Gates and its implementation in
formation of AND, OR, NOT Gates.

INFERENCE:
From this experiment we have got a clear picture about the use of different
gates(AND,OR,NOT,NAND,NOR).

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