Instrumentation II Chapter 1: Microprocessor Based Instrumentation System

Chapter – 1
Microprocessor Based Instrumentation System
Microprocessor: A Microprocessor is a multipurpose programmable, clock driven,
register based electronic device fabricated using signal integrations from SSI to VLSI that
reads binary instructions from a storage device called memory, accepts binary data as

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input, processes data according to those instructions and provide result s as output.

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Instrumentation System: The system which is defined as the assembly of various
instruments and other components interconnected to measure, analyze and control
physical quantities such as electrical, thermal, mechanical etc.

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Microprocessor based Instrumentation System: Any instrumentation systems centered

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around a microprocessor are known as microprocessor based system. Logical and

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computing power of microprocessor has extended the capabilities of many basic
instruments, improving accuracy and efficiency of use. Microprocessor is versatile device
for use in any instrumentation system. Examples are ATM, automatic washing machine,

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fuel control, oven etc.

Why microprocessor?
 Can be used in any system. en
 Can be used in specific applications and specific design.
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 Logical and computational power of microprocessor has been used to develop
more accurate and efficient system.
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Why, not Microprocessor?

 Complexity in interfacing.
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 Need to learn complex machine dependent language.

 Need of an expensive microprocessor development system.
But all these problems are accepted if system designed sells a number of units so that
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the development cost spreads out.

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Features for selecting microprocessor

 How fast the data has to be processed
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 Cost-amount of memory intelligence

 Complexity of work
 Field for which system is designed
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1.1 Basic Features of Microprocessor Based System

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 Three components: Microprocessor, I/O, and memory

 Decision making power based on previous entered values
 Repeatability of readings
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 User friendly (Signal readout)

 Parallel processing
 Timeshare and multiprocessing
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 Instrumentation II Chapter 1: Microprocessor Based Instrumentation System

 Data storage, retrieval and transmission

 Effective control of multiple equipments on time sharing basis
 A lot of processing capability

1.2 Open Loop and Closed Loop Microprocessor Based System

Any instrumentation system can be controlled by microprocessor in two ways

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open loop control system and closed loop control system.

Open loop control system

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 Microprocessor gives output of control variable in the form of some display to
human operator and then on the basis of displayed information, the human

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operator makes changes in the necessary control inputs.
 Example: pressure and temperature monitoring system in any chemical
processing plant

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 It is simple, low cost and used when feedback is not critical.

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Data / Address / Control Bus Microprocesor

Pressure (Analog
Signal)
ADC
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RAM
Memory
Panel
Interface
Panel
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Fig: Block diagram of pressure monitoring system - Open loop control
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 Upper and lower limit of desired pressure is set

 Pressure is converted to digital form to be fed to microprocessor
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 The microprocessor compares a sample of pressure measurement with present

pressure limits.
 If sample is beyond limits, the microprocessor indicates in form of come
alarm or lamp.
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 So, according to output signal, human operator makes necessary changes.

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Closed loop control system

 Microprocessor monitors the process variables continuously and then supplies
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the output signal to the electromechanical devices, which in turn controls the
values of process variables.
 Example: automatic temperature control system in an oven
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 Accurate and Adaptive

 No human operator required
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 Instrumentation II Chapter 1: Microprocessor Based Instrumentation System

DAC
To Heater
Control System

Port RAM

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Data / Address / Control Bus Microprocesor

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Panel
port Panel
Interface

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ADC
Temperature of
Oven
Fig: Block diagram of automatic temperature control system – Closed loop

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control

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In microprocessor, upper and lower limits of temperature are set.
Every sample of temperature measurement from transducer is compared by
the processor.
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 If temperature exceeds the preset higher limit, the microprocessor transmits an
output signal to a system which in turn turns off the supply to some of the
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heater elements.
 If temperature is less than the preset lower limit, the microprocessor transmits
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signal to system so that it turns on the supply to the heater element of the
oven.

1.3 Benefits of Microprocessor Based System

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 Complete automation

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Added intelligence
 Reduced manpower
 Flexibility to modify
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 Economic design
 Reduced circuit complexity
 Reduced operating costs (eg. Fuel savings)
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 Reduced product wearing; furnish more uniform operation; tighter control

enforce ment.
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 Improved responsiveness to changes in process: production rates, product

specifications, addition of new products.
 Incorporate strategies to minimize production upsets; resulting from plant
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equipment failures by anticipated process conditions and improved plant

safety.

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 Instrumentation II Chapter 1: Microprocessor Based Instrumentation System

 Improved timely information to plant operation and maintenance managers to

enable them to keep a plant running longer and more efficiently.
 Improved integration and interaction of plant operation through coordinated
strategy.
 Relational database management
 Statistical process control capabilities

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 Information exchange with other plant system for process synchronization.

1.4 Microcomputer on Instrumentation Design

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Process / Multiplexer

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Analog
Plant / (to sequentially feeds
Transducer
System the outputs one at atime)

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Signal Conditioner
And
Magnetic Disk Print Out ADC

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Computer Digital
Data Logger
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Produces O/P Computer Software
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Data Operator Command
Monitor
Display Through I/O
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Device
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Data
Communica-
tion
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Remote Indicator
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Fig: A typical digital computer based instrumentation system

A process or plant or system may have to simultaneously measure multiple

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variables like pressure, temperature, velocity, viscosity, flow rate etc. A computer
based measurement system has the capability of processing all inputs and present
the data in real time. A digital computer is fed with a sequential list of instructions
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termed as computer program for suitable processing and manipulation of data.

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Advantages:
 Suitably programmed to automatically carry out the mundane tasks of drift
correction, noise reduction, gain adjustments, automatic calibration etc.
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 These instruments have signal conditioning and display which are

compact, rugged and reliable and are suited for performing in wide
conditions like industrial, consumer, military, automobile etc.
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 Instrumentation II Chapter 1: Microprocessor Based Instrumentation System

 Built in diagnostic subroutines to detect only or detent and correct.

 Real time measurement, processing and display.
 Lower cost, higher accuracy, and more flexibility.

Disadvantages:
 They cannot replace the program themselves.

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 Software update
 Prone to virus problem, so may become in-operational.

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1.5 Interfacing With Microprocessor
The primary function of microprocessor is to accept data from input devices such

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as keyboard and A/D converters, read instructions from memory, process data
accordingly to the instructions, and send the results to output devices such as

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LEDs, printers and video monitors. These input and output devices are called

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peripherals or I/Os. Designing the logic circuits (hardware) and writing
instructions (software) to enable the microprocessor to communicate with these
peripherals is called interfacing, and the logic circuits are called I/O ports of

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interfacing devices.

1.5.1 PC Interfacing Techniques

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PC provides several interfaces for attaching peripherals to it. PC compatible
devices are interfaced to a PC through an internal expansion slot, a parallel
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port or a serial port. Latest PCs have USB for connecting the peripherals.
1) I/O Buses
PC brings out the system bus signals through expansion slots
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known as I/O buses on the motherboard that is an I/O bus

interfaces an external device directly to the system bus. Video
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card, sound card, network card etc. are inserted into the slots for
various applications.
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2) Parallel and Serial Ports

Basic PC configuration includes one parallel port (LPT1) and two
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serial ports (COM1 and COM2). However, additional ports can be

created by adding expansion cards. For industrial measurement and
control operations, remote data acquisition system compatible for
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serial port are used.

3) USB ports
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Universal serial bus used for connecting number of peripheral

devices such as printer, scanner, digital cameras, and pen drives
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etc. It is faster compared to traditional parallel and serial ports.

1.5.2 Review of Address Decoding

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The R/W memory is made of registers and each register has a group of flip flops or field-
effect transistors that store bits of information; these flip flops are called memory cells.
The number of bits stored in a register is called a memory word. In a memory chip, all
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 Instrumentation II Chapter 1: Microprocessor Based Instrumentation System

registers are arranged in a sequence and identified by binary numbers called memory
address.
To communicate with memory, the MPU should be able to:
- Select the chip
- Identify the register
- Read from or write into the register

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The address decoding circuit enables MPU to select an address within memory chip or
I/O chip and then read or write into it through the available data bus and thus avoid
contention or data collision within the data bus.

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Microprocessor is connected with memory and I/O devices via common address and data

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bus. Only one device can send data at a time and other devices can only receive that data.
If more than one device sends data at the same time, the data gets garbled. In order to
avoid this situation, ensuring that the proper device gets addressed at proper time, the

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technique called address decoding is used.

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In address decoding method, all devices like memory blocks, I/O units etc. are assigned

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with a specific address. The address of the device is determined from the way in which
the address lines are used to derive a special device selection signal known as chip select

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( ). If the microprocessor has to write or to read from a device, the
block should be enabled and the address decoding circuit must ensure that
other devices are not activated.
signal to that
signal to
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Depending upon the no. of address lines used to generate chip select signal for the device,
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the address decoding is classified as:

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a) I/O mapped I/O

In this method, a device is identified with an 8 bit address and operated by I/O related
functions IN and OUT for that IO/M’ = 1. Since only 8bit address is used, at most
256 bytes can be identified uniquely. Generally low order address bits A0-A7 are used
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and upper bits A8-A15 are considered don’t care. Usually I/O mapped I/O is used to
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map devices like 8255A, 8251A etc.

b) Memory mapped I/O

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In this method, a device is identified with 16 bit address and enabled memory related
functions such as STA, LDA for which IO/M’ = 0, here chip select signal of each
device is derived from 16 bit address lines thus total addressing capability is 64K
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bytes . Usually memory mapped I/O is used to map memories like RAM, ROM etc.
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Depending on the address that are allocated to the device the address decoding are
categorized in the following two groups.
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 Instrumentation II Chapter 1: Microprocessor Based Instrumentation System

a) Unique Address Decoding:

If all the address lines on that mapping mode are used for address decoding then that
decoding is called unique address decoding. It means all 8-lines in I/O mapped I/O and
all 16 lines in memory mapped I/O are used to derive signal. It is expensive and
complicated but fault proof in all cases.

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 If A0 is high and A1- A7 are low and if
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becomes low, the latch gets enabled.
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 The data to the LED can be transferred in only one case and hence the device has unique
address of 01H.
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Eight I/P switch interfacing at 53H. (01010011)

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 Instrumentation II Chapter 1: Microprocessor Based Instrumentation System

b) Non Unique Address decoding:

If all the address lines available on that mode are not used in address decoding then that
decoding is called non unique address decoding. Though it is cheaper there may be a
chance of address conflict.

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- If A0 is low and is low. Then latch gets enabled.
- Here A1-A7 is neglected that is any even address can enable the latch.

1.5.3 Memory Interfacing

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 A memory chip requires address lines to identify a memory register. The
number of address lines required is determined by the number of registers
in a chip (2n = number of registers where n is the number of address lines).
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 A memory chip requires a chip select ( ) signal to enable the chip. The
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remaining address lines (from above step) of the microprocessor can be

connected to the CS signal through an interfacing logic.
 Thus, all address lines are responsible to select a specific register within a
memory chip.
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Example: Design an address decoding circuit for two RAM chips each of 4K X 8 at address
2050H.
Step 1: Calculate the number of address pins
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Here both memory devices are of 4K X 8 memory which is 4KB. That means 2 n = 4KB (4X1KB
= 22X210 = 212). Therefore, 4KB memory requires 12 address lines.
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n = log (memory capacity in bytes) / log (2)

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n = log (4X1024) / log (2) = 12

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 Instrumentation II Chapter 1: Microprocessor Based Instrumentation System

Step 2: Memory Mapping

Memory Address A A A A A A A A A A A A A A A A
Block 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0
5 4 3 2 1 0

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RAM Start:2050H 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0

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End:304FH 0 0 1 1 0 0 0 0 0 1 0 0 1 1 1 1

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ROM Start:3050H 0 0 1 1 0 0 0 0 0 1 0 1 0 0 0 0

End:404FH 0 1 0 0 0 0 0 0 0 1 0 0 1 1 1 1

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Here RAM1 requires 12 address lines that is 111111111111 (FFFH). The starting address of
RAM1 is 2050H; we can calculate the end address of RAM1 by adding RAM1 addresses with its

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base address that is 2050H + FFFH = 304FH.

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Similarly RAM2 requires 12 address lines that is 111111111111 (FFFH). The next address of the
RAM1’s end address is the starting address of RAM2 that is 304FH + 01H = 3050H. Now we
can calculate the end address of RAM2 by adding RAM2 addresses with its starting address that
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is 3050H + FFFH = 404FH.
Step 3: Decide decoder pins
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Here, bit A12 in address lines for RAM1 and RAM2 referring to start address are different, so
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we require a 1X2 decoder. If we refer the end address, bits A12, A13 and A14 are different; in
this case we should use 3X8 decoder. Address lines A0 through A11 are used by RAM1 and
RAM2 as both having 12 address pins. Rest of the address lines (A15 if 3X8 decoder and A13,
A14 and A15 if 1X2 decoder) will be decoded to generate chip enable signals for decoder.
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 Instrumentation II Chapter 1: Microprocessor Based Instrumentation System

Step 4: Draw a decoding circuit

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 Instrumentation II Chapter 1: Microprocessor Based Instrumentation System

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1.5.4 Programmed I/O, Interrupt Driven I/O and Direct Memory Access
(DMA)
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Programmed I/O or Polling:

The microprocessor is kept in a loop (programmed) to check whether data are
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available. For example to read a data from an input keyboard in a single board
microcomputer, the microprocessor can keep polling the port until a key is
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pressed.

Interrupt Driven I/O:

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When a peripheral is ready to transfer data, it sends an interrupt signal to the

microprocessor. The microprocessor stops the execution of the current
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program, accepts the data from the peripheral and then returns to the program.
The processor is free to perform other tasks rather than being hold in a polling
loop.
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 Instrumentation II Chapter 1: Microprocessor Based Instrumentation System

Direct Memory Access (DMA):

This type of data transfer is employed when the peripheral is much faster than
the microprocessor. The DMA controller sends a HOLD signal to the
microprocessor, the microprocessor releases its data bus and the address bus
to the DMA controller, and data are transferred at high speed without the
intervention of the microprocessor.

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 Instrumentation II Chapter 2 : Parallel Interfacing With Microprocessor Based System

Chapter – 2
Parallel Interfacing with Microprocessor Based System
The device which can handle data at higher speed cannot support with serial interface. N bits of
data are handled simultaneously by the bus and the links to the device directly. Achieves faster
communication but becomes expensive due to need of multiple wires.

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2.1 Methods of Parallel Data Transfer: Simple Input and Output, Strobe I/O, Single
Handshake I/O, & Double Handshake I/O

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Parallel transmission of data is used for short distance where the speed of information transfer is

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critical. This form of data communication is found in newer type of computer peripheral
equipment with transfer speed of to one million characters per second. The equipment includes
printers, disk drives and various other forms of peripheral components.

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The information exchanged between a microprocessor and an I/O interface circuit consists of
input or output data and control information. The status information enable the microprocessor

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monitor the device and when it is ready then send or receive data. Control information is the
command by microprocessor to cause I/O device to take some action. If the device operates at

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different speeds, then microprocessor can be used to select a particular speed of operation of the
device. The techniques used to transfer data between different speed devices and computer is
called synchronizing. There are various ways of synchronization techniques which are involved
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in parallel data transfer such as simple input and output, simple strobe I/O, single handshaking
and double handshaking.
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Simple I/O
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To get digital data from a simple switch into a microprocessor; switch is connected on input port
line from which port can be read. The data is always present and ready so that it can be read at
any time. Similarly to output data to a simple display device like LED, the input of LED buffer
is connected on an output port pin. And output the logic level required turning on the light. The
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LED is always there and ready so that data can be sent at any time.
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This timing waveform illustrates the simple I/O where cross lines represent the time at which a
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new data byte becomes valid on the output lines of the port. Absences of other waveforms
indicate that this output operation is not directly dependent on any other signals.
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Simple Strobe I/O

In many applications, valid data is present on an external device only at a certain time and must
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be read in at that time. Here a strobe pulse is supplied to indicate the time at which data is being
transmitted. For an example, we can discuss the ASCII encoded keyboard. When a key is
pressed, circuitry on keyboard sends out ASCII code for pressed key on eight parallel data lines
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 Instrumentation II Chapter 2 : Parallel Interfacing With Microprocessor Based System

and then sends out a strobe signal on another line to indicate that valid data is present on eight
data lines

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The sending device outputs parallel data on the data lines, and then outputs STB’ signal to
represent the valid data is present.

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In this technique, microprocessors need to wait until the device is ready for the operation and
also known as simple wait I/O. Consider a simple keyboard consisting of 8 switches connected to

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a microprocessor through a parallel interface circuit (Tri-state buffer). The switch is of dip
switches. In order to use this keyboard as an input device the microprocessor should be able to

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detect that a key has been activated. This can be done by observing that all the bits are in
required order. The processor should repeatedly read the state of input port until it finds the right
order of bits i.e. at least 1 bit of 8 bits should be 0.
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Consider the tri-state A/D converter:
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 Used to convert analog to digital data which can be read by I/O unit of microprocessor.
 When SOC appears 1, I/O unit should ready for reading binary data/digital data.
 When EOC’s status is 1, then I/O unit should stop to read data.
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 Strobe signal indicates the time at which data is being activated to transmit.
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Single Handshaking
Handshaking is the method of synchronizing the actions of slow peripheral devices with that of
high speed microprocessor. It can have two transfer schemes.
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 Instrumentation II Chapter 2 : Parallel Interfacing With Microprocessor Based System

Input Handshake (Peripheral to Microprocessor):

The peripheral outputs some data and sends some strobe signal to microprocessor.
Microprocessor detects asserted strobe signal (STB’) and reads the byte of the data. Processor
then sends acknowledgement signal (ACK) to peripheral to indicate that the data has been read
and can send next byte of data.

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 The peripheral outputs some data and send signal to microprocessor to tell “Here is

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the data for you”.
 Microprocessor detects asserted
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signal, reads the data and sends an acknowledge
signal (ACK) to indicate data has been read and peripheral can send next data, “I got that
one, send me another”.
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 Microprocessor sends or receives data when peripheral is ready.
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Output Handshake (Peripheral from Microprocessor):

Microprocessor outputs data to peripheral and asserts a strobe (STB’) signal. If peripheral is
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ready it answers back with acknowledgement (ACK) signal to microprocessor.

Double Handshaking
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For data transfers where even more coordination is required between the sending system and the
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receiving system, a double handshake is used. It can have two transfer schemes.

Input Handshake (Peripheral to Microprocessor):

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Peripheral asserts strobe (STB’) line low to ask receiving device whether it is ready or not for
data reception. Receiving system raises its acknowledgement (ACK) line high to indicate it is
ready. Peripheral device then sends the byte of data and raises its strobe (STB’) line high. When
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microprocessor reads data, it drops its acknowledgement (ACK) line low and request sending
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system to send net byte of data.

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 Instrumentation II Chapter 2 : Parallel Interfacing With Microprocessor Based System

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 The peripheral asserts its line low to ask microprocessor “Are you ready?”
 The microprocessor raises its ACK line high to say “I am ready”.
 line low to say “Here is some valid data for

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Peripheral then sends data and raises its

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you.”
 Microprocessor then reads the data and drops its ACK line to say, “I have the data, thank
you, and I await your request to send the next byte of data.”

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Output Handshake (Peripheral from Microprocessor):
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Microprocessor sends a strobe (STB’) signal and data and peripheral sends acknowledgement
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(ACK) signal.

2.2 8255 as General Purpose Programmable I/O Device and its interfacing examples
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The Intel 8255 A is a general purpose programmable I/O device designed for use with Intel
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microprocessors. It has 24 I/O pins that can be grouped primarily in two 8-bit parallel ports: A
and B, with the remaining bits as port C. The 8-bits of port C can be used as individual bits or be
grouped in two 4-bits ports: C upper (Cu) and C lower (Cl). The functions of these ports are
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defined by writing a control word in the control register.

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8255 functions in two modes:


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Bit Set/Reset mode: The BSR mode is used to set or reset the bits in port C.
 I/O mode: The I/O mode is further divided into three modes: mode 0, mode 1 and mode
2. In mode 0, all ports function as simple I/O ports. Mode 1 is a handshake mode
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whereby ports A and/or B use bits from port C as handshake signals. In the handshake
mode, two types of I/O data transfer can be implemented: status check and interrupt. In
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mode 2, port A can be set up for bidirectional data transfer using handshake signals from
port C and port B can be set up either in mode 0 or mode 1.
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 Instrumentation II Chapter 2 : Parallel Interfacing With Microprocessor Based System

Block diagram of 8255:

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Fig2: Internal Block Diagram of 8255

The pin diagram and block diagram of 8255 is given above. It has the following main blocks.
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a. Data Bus Buffer

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The 3-state bidirectional 8-bit buffer is used to interface the 8255A to the system data bus.
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Data is transmitted or received by the buffer upon execution of input or output instructions
by the CPU. Control words and status information are also transferred through the data bus
buffer.
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b. Read/Write Control Logic

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The function of the block is to manage all of the internal and external transfers of both data
and control or status words. It accepts inputs from the CPU address and control buses and in
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turn, issues commands to both of the control groups.

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 Instrumentation II Chapter 2 : Parallel Interfacing With Microprocessor Based System

 Chip Select (CS’): A “low” on this pin enables the communications between the
8255A and the CPU.
 Read (RD’): A “low” on this input enables the 8255A to send the data or status
information to the CPU on the data bus. In essence, it allows the CPU to read from
the 8255A.
 Write (WR’): A “low” on this input pin enables the CPU to write data or control

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words into the 8255A.
 Reset (RESET): A “high” to this pin clears the control register and sets all ports (A, B
and C) in the input mode.

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 A0 and A1: These input signals controls the selection of one of the three ports or the
control word register. They are connected to the least significant bits of the address

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bus.

The CS’ signal is the master chip select, and A0 and A1 specify one of the I/O ports or the

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control register as given below.

CS’ A1 A0 Selected

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0 0 0 Port A
0
0
0
0
1
1
1
0
1
en Port B
Port C
Control Register
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1 X X 8255A is not
selected
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c. Group A and Group B controls

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Functional configuration of each port is programmed by the system software. In essence, the
CPU outputs a control word to the 8255A. The control word contains information such as
“mode”, “bit set’, “bit reset”, etc. that initialize the functional configuration of the 8255A.
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Each of the control blocks (Group A and Group B) accepts “commands” from the
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Read/Write control logic, receives control word from the internal data bus and issues the
proper commands to its associated ports.
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 Control Group A – Port A and Port C Upper (C7 – C4)

 Control Group B – Port B and Port C Lower (C3 – C0)
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Control Word
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When A0 and A1 pins have value 1, the mapped address addresses the control register which is
the 8-bit register to write the specific content according to the port conditions although it cannot
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be read. The content of this register is called control word which specifies an I/O function for
each port.

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 Instrumentation II Chapter 2 : Parallel Interfacing With Microprocessor Based System

The MSB (D7) of the control word tells which control word we are sending it that is it specifies
either the I/O function or the Bit Set/Reset function. If bit D7=1, bits D6-D0 determine I/O
functions in various modes as shown in figure. If bit D7=0, port C operates in the Bit Set/Reset
(BSR) mode. The BSR control word does not affect the functions of ports A and B.

np
To communicate with peripherals through 8255, following are the steps are necessary.

 Determine the Port addresses of Ports A, B and C and of the control register according to

u.
Chip Select logic and address lines A1 and A0.
 Write a control word in control register.

ed
 Write I/O instructions to communicate with peripherals through Ports A, B and C.

.
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 Instrumentation II Chapter 2 : Parallel Interfacing With Microprocessor Based System

I/O Control Word Examples

Q. Determine the Control word for the following configuration of ports of Intel 8255A
PPI chip.

a. Port A output, mode of port A mode 1, port B output, mode of port B mode 0, port C lower

np
pins as output and remaining pins of port C upper as output.

u.
D7 D6 D5 D4 D3 D2 D1 D0 = A0H
1 0 1 0 0 0 0 0

ed
b. Port A output, mode 0, port B output, mode 0, port C lower output and port C upper input.

.
es
D7 D6 D5 D4 D3 D2 D1 D0 = 88H
1 0 0 0 1 0 0 0

ot
c.
en
Port A input, mode 1, port B output, mode 1, and remaining pins of port C upper input.

= BCH [Normally don’t care (X) = 0]

io
D7 D6 D5 D4 D3 D2 D1 D0
1 0 1 1 1 1 0 X
m
fro

d. Port A input mode 1, port B output mode 0, port C lower input and port C upper output.

D7 D6 D5 D4 D3 D2 D1 D0 = B1H
d

1 0 1 1 0 0 0 1
de

e. Port A bidirectional (Mode 2), port B input mode 0, port C lower output.
oa

D7 D6 D5 D4 D3 D2 D1 D0 = C2H [Normally don’t care (X) = 0]

1 1 X X X 0 1 0
nl
ow

Operating Modes

Mode 0 (Basic Input/output)

D

This functional configuration provides simple input and output operation for each of the three
ports. No ‘handshaking” is required; data is simply written to or read from a specified port.

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 Instrumentation II Chapter 2 : Parallel Interfacing With Microprocessor Based System

Mode 0 basic functional definitions:

 Two 8-bit ports and two 4-bit ports

 Any port can be input or output
 Outputs are latched
 Inputs are not latched

np
 16 different input/output configurations are possible in this mode.

u.
BSR Mode (Bit Set/Reset)

ed
BSR mode is concerned only with eight bits of port C, which can be set or reset by writing an
appropriate control word in the control register. A control word with bit D7=0 is recognized as a
control word and it does not alter any previously transmitted control word with bit D7=1; thus the

.
es
I/O operations of ports A and B are not affected by a BSR control word. In the BSR mode
individual bits of port C can be used for applications such as On/Off switch.

ot
BSR Control Word: This control word, when written in control register, sets or resets one
bit at a time, as specified in figure.

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 Instrumentation II Chapter 2 : Parallel Interfacing With Microprocessor Based System

BSR Control Word Examples

Q. Determine the BSR Control word for the following Port C configurations.

a. Set PC7

np
To set PC7

u.
D7 D6 D5 D4 D3 D2 D1 D0 = 0FH [Normally don’t care (X) = 0]
0 X X X 1 1 1 1

ed
b. Reset PC3

.
es
D7 D6 D5 D4 D3 D2 D1 D0 = 06H [Normally don’t care (X) = 0]
0 X X X 0 1 1 0

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Mode 1 (Strobe Input/output)
en
The functional configuration provides a means for transferring I/O data to or from a specified
io
port in conjunction with strobes or handshaking signals. In mode 1, port A and port B use the
lines of port C to generate or accept these handshaking signals.
m

Mode 1 basic functional definitions:

fro

 Two groups (Group A and Group B)

 Each group contains one 8-bit data port and one 4-bit control/data port
 The 8-bit data port can be either input or output. Both inputs and outputs are latched.

d

The 4-bit port is used for control and status of the 8-bit data port.
de

Mode 2 (Strobe Bidirectional Bus I/O)

oa

The functional configuration provides a means for communicating with a peripheral device or a
structure on a single 8-bit bus for both transmitting and receiving data (bidirectional bus I/O).
“Handshaking Signals” are provided to maintain proper bus flow discipline in a similar manner
nl

to Mode 1. Interrupt generation and enable/disable functions are also available.

ow

Mode 2 basic functional definitions:

 Used in Group A only

D

 One 8-bit bidirectional bus port (Port A) and a 5-bit control port (Port C)
 Both inputs and outputs are latched

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 Instrumentation II Chapter 2 : Parallel Interfacing With Microprocessor Based System

 The 5-bit control port (Port C) is used for control and status for the 8-bit,
bidirectional bus port (Port A)

8255 Programming and Operation

np
A high on the RESET pin causes all 24 lines of the three 8-bit ports to be in the input mode. All
flip-flops are cleared and the interrupts are reset. This condition is maintained even after the

u.
RESET goes low. The ports of the 8255 can then be programmed for any other mode by sending
out a single output instruction to the control register. Also, the current mode of operation can be

ed
changed by writing a single mode word onto the control register, when required.

.
Modes for Group A and Group B can be separately defined with Port C taking on responsibilities

es
as dictated by the mode definitions or Ports A and B. If Group A is programmed for Mode 0, and
Group B is programmed for Mode 1, Port A and PC4–PC7 can be programmed for either input or
output, while Port B can be programmed for input or output with PC0–PC2 used for handshaking.

ot
en
The mode definition format and bit set-reset format are discussed in above topics. The control
words for both mode definition and Bit Set-Reset are loaded into the same control register, with
bit D7 used for specifying whether the word loaded into the control register is a mode definition
io
word or Bit Set-Reset word. If D7 is high, the word is taken as a mode definition word, and if it is
low, it is taken as a Bit Set-Reset word. The appropriate bits are set of reset depending on the
m

type of operation desired, and loaded into the control register (which is accessed when A1 and A0
both are '1'; WR and CS both are '0'. It is to be noted that Group B does not have provision for
fro

operation in Mode 2.
d

The eight possible combinations of the states of bits D1 -D3 (B2 B1 B0) in the Bit Set-Reset
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format (henceforth referred to as BSR) determine the particular bit in PC0-PC7 being set or reset
as per the status of bit D0. A BSR word is to be written for each bit that is to be set or reset. For
example, if bit PC2 is to be set and bit PC7 is to be reset, the appropriate BSR words that will
oa

have to be loaded into the control register will be, 0XXX001 and 0XXX1110, respectively,
where X can be either '0' or '1'.
nl

The BSR, word can also be used for enabling or disabling interrupt signals generated by Port C
ow

when the 8255 is programmed for Mode 1 or Mode 2 operation. This is done by setting or
resetting the associated bits of the interrupts.
D

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 Instrumentation II Chapter 2 : Parallel Interfacing With Microprocessor Based System

Programming in Mode 0 (Basic I/O Mode)

The ports A, B and C can be configured as simple input or output ports by writing the
appropriate control word in the control word register. In the control word, D7 is set to '1' (to
define a mode set operation) and D6, D5, and D2 are all set to '0' configure all the ports in Mode 0
operation. The status of bits D4, D3, D1 and D0 then determine whether the corresponding ports

np
are to be configured as Input or Output.

Example 1

u.
a) Identify the port addresses in given figure.

ed
b) Identify the Mode 0 control word to configure port A as an input port and port B as an
output port.
c) Write a program to read the Dip switches and display the reading from port A at port B.

.
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Solution
a) This is I/O mapped I/O; when A15 A14 A13 is 011, then chip select of 8255 is enabled. We
d

also know that during the execution of IN and OUT instruction, A15-A8 and AD7-AD0 carry
de

the same signals. Keeping this in mind, port addresses will be derived. Firstly, port A’s port
address will be calculated as under:
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
oa

0 1 1 X X X X X = X X X X X X 0 0
nl

To have equality, 0’s and 1’s on one side of the equation must appear on other sides. This means
that AD7 AD6 AD5 must equal 011 and A9 and A8 must equal 00 (port A) to get
ow

0 1 1 X X X 00 = 0 1 1 X X X 00
Since the remaining don’t cares can be 0’s and 1’s, there are many solutions. For instance, if all
the don’t cares are equal to zero; address of port A becomes 1110 0000 (60H). The port
D

addresses of the given figure are determined as under:

Port A = 60H

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 Instrumentation II Chapter 2 : Parallel Interfacing With Microprocessor Based System

Port B = 61H
Port C = 62H
Control Register = 63H
b) The Mode 0 control word to configure port A input and port B output is calculated as under:

np
D7 D6 D5 D4 D3 D2 D1 D0 = 90H
1 0 0 1 X 0 0 X

u.
c) Program subroutine to read DIP switches and display the reading from port A at port B is as
under:

ed
MVI A, 90H; Load ACC with the control word
OUT 63H; Write the control word in control register and initialize the ports

.
IN 60H; Reads switches at port A

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OUT 61H; Display the reading at port B
RET

ot
Programming on BSR Mode
en
Any of the eight bits of port C can be ser or reset using a single output instruction. This feature
reduces software requirements in control-based applications. When Port C is being used as Status
io
/ Control for Port A or B, these bits can be set or reset by using Bit Set/Reset. Word in the
control register when D7 = 0 is recognized as BSR control word and does not affect the I/O
m

operations of Port A and B.

fro

Example 2
Write a BSR control word to set PC7, PC6, PC5, PC4, PC3, PC2, PC1, and PC0 and reset each after
1 second.
d
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D

Fig: Example of BSR Mode

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 Instrumentation II Chapter 2 : Parallel Interfacing With Microprocessor Based System

Solution
Let us assume Port addresses same as example 1. The control word is calculated with Port C
output in this case so it is 10000 0000 (80H). BSR control word for each case is given as under:

Case D7 D6 D5 D4 D3 D2 D1 D0 BSR Control

np
Word
Set PC7 0 0 0 0 1 1 1 1 0FH

u.
Reset PC7 0 0 0 0 1 1 1 0 0EH
Set PC6 0 0 0 0 1 1 0 1 0DH

ed
Reset PC6 0 0 0 0 1 1 0 0 0CH
Set PC5 0 0 0 0 1 0 1 1 0BH

.
es
Reset PC5 0 0 0 0 1 0 1 0 0AH
Set PC4 0 0 0 0 1 0 0 1 09H
Reset PC4 0 0 0 0 1 0 0 0 08H

ot
Set PC3 0 0 0 0 0 1 1 1 07H
Reset PC3
Set PC2
0
0
0
0
0
0
0
0
0
0
1
1
1
0 en 0
1
06H
05H
io
Reset PC2 0 0 0 0 0 1 0 0 04H
Set PC1 0 0 0 0 0 0 1 1 03H
m

Reset PC1 0 0 0 0 0 0 1 0 02H

Set PC0 0 0 0 0 0 0 0 1 01H
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Reset PC0 0 0 0 0 0 0 0 0 00H

Program Subroutine
d

MVI A, 80H
de

LOOP: OUT 63H

MVI A, 0FH
oa

OUT 63H
CALL DELAY
DCR A
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ANI 0FH
ow

JMP LOOP

DELAY: MVI C, 0AH

D

LOOP: MVI D, 64H

LOOP1: MVI E, DEH

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 Instrumentation II Chapter 2 : Parallel Interfacing With Microprocessor Based System

LOOP2: DCR E
JNZ LOOP2
DCR D
JNZ LOOP1
DCR C

np
JNZ LOOP
RET

u.
Programming in Mode 1 (Strobe I/O Mode)

ed
In Mode 1, handshake signals are exchanged between the MPU and peripherals prior to data
transfer. Two ports (A and B) function as 8-bit I/O ports. They can be configured either as input
or output ports. Each port uses three lines from port C as handshake signals. The remaining two

.
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lines of port C can be used for simple I/O functions.
When Port A is to be programmed as an input port, PC3, PC4, and PC5 are used for control, PC6

ot
and PC7 can be Input or Output, as programmed by bit D3 (Cupper) of the control word. When Port
A is programmed as an output port, PC3, PC6, PC7 are used for control and PC4 and PC5 can be

en
Input or Output, as programmed by bit D3 (Cupper) of the control word. When Port B is to be
programmed as an input or output port, PC0, PC1 and PC2 are all used for control.
io
Mode 1 Input
Below figure shows Port A as input port (when it operates in Mode 1) along with the control
m

word and control signals (for handshaking with a peripheral). When the control word is loaded
into control register, Group A is configured in Mode 1 with Port A as an input port, Port A can
fro

accept parallel data from a peripheral (like a keyboard) and this data can be read by the CPU.
The peripheral first loads data into Port A by making the STBA input low. This latches the data
placed by the peripheral on the common data bus into Port A. Port A acknowledges reception of
d

data by making IBFA (Input Buffer Full) high. IBFA is set when the STBA input is made low.
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INTRA is an active output signal which can be used to interrupt the CPU so that the CPU can
suspend its current operation and read the data written into Port A by the peripheral. INTR A can
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be enabled or disabled by the INTEA flip-flop which is controlled by BIT Set-Reset operation of
PC4. INTRA is set (if enabled by setting the INTEA flip-flop) after the STBA has gone high again,
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and if IBFA is high.

On receipt of the interrupt, the CPU can be made to read Port A. The falling edge of the RD input
ow

resets IBFA and it goes low. This can be used to indicate to the peripheral that the input buffer is
empty and that data can again be loaded into it.
D

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 Instrumentation II Chapter 2 : Parallel Interfacing With Microprocessor Based System

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 Instrumentation II Chapter 2 : Parallel Interfacing With Microprocessor Based System

np
u.
. ed
es
Fig: Timing Waveforms for Strobed Input (With Handshake) – 8255 Mode 1

ot
Above figure shows Port B as an input port (when in Mode 1). The timing diagram and operation
of Port B is similar to that of Port A except that it uses different bits of Port C for control. INTEB
is controlled by Bit Set/Reset of PC2.
en
io
If the CPU is busy with other system operations, it can read data from the input port when it is
interrupted. This is often called Interrupt Controlled I/O. However, if the CPU is otherwise not
busy with other jobs, it can continuously poll (read) the status word to check for an IBF A. This is
m

often called Program Controlled I/O. The status word is accessed by reading Port C (A1 A0 must
fro

be 10, RD and CS must be low). The status word format as assumed by the bits of Port C when
Ports A and B are input ports in Mode 1, is shown in above figure.
d

Mode 1 Input Control Signals

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STB’ (Strobe Input): A low on this input loads data into the input latch. The 8255A, in
response to STB’, generates IBF and INTR.
oa

IBF (Input Buffer Full): A high on this output indicates that the data bus has been loaded into
the input latch; in essence, an acknowledgement, IBF is set by STB input being low and is reset
by the rising edge of the RD’ input.
nl

INTR (Interrupt Request): This is an output signal that may be used to interrupt the CPU. This
ow

signal is generated if STB’, IBF and INTE (Internal Flip Flop) are all at logic 1. This is reset by
the falling edge of the RD’ (Read) signal.
D

INTE: This is an internal flip-flop used to enable or disable the generation of the INTR signal.
The two flip-flops INTEA and INTEB are set/reset using the BSR mode through PC4 and PC2.

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 Instrumentation II Chapter 2 : Parallel Interfacing With Microprocessor Based System

Mode 1 Output
Figure below shows Port A configured as an output port (when in Mode 1) along with the control
word and control signals (for handshaking with a peripheral). When the control word is loaded
into the control register, Group A is configured in Mode 1 with Port A as an output port. The

np
CPU can send out data to a peripheral (like a display device) through Port A of the 8255.
The OBFA output (Output Buffer Full) goes low on the rising edge of the WR signal (when the

u.
CPU writes data into the 8255). The OBFA output from 8255 can be used as a strobe input to the
peripheral to latch the contents of Port A. The peripheral responds to the receipt of data by

ed
making the ACKA input of the 8255 low, thus acknowledging that it has received the data sent out
by the CPU through Port A. The ACKA low resets the OBFA signal, which can be polled by the

.
CPU through OBFA of the status word to load the next data when it is high again.

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INTRA is an active high output of the 8255 which is made high (if the associated INTE flip-flop
is set) when ACKA is made high again by the peripheral, and when OBFA goes high again (see

ot
timing diagram in Figure below). It can be used to interrupt the CPU whenever the output buffer
is empty. It is reset by the falling edge of WR when the CPU writes data onto Port A. It can be

en
enabled or disabled by writing a '1' or a '0' respectively to PC6 in the BSR mode.
io
Figure below shows Port B as an output port when in Mode 1. The operation of Port B is similar
to that of Port A. INTEB is controlled by writing a '1' or '0' to PC2 in the BSR mode.
The status word is accessed by issuing a Read to Port C. The format of the status word as
m

assumed by the bits of Port C when Ports A and B are Output ports in Mode 1 is shown in Figure
fro

below.
d
de
oa
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D

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 Instrumentation II Chapter 2 : Parallel Interfacing With Microprocessor Based System

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 Instrumentation II Chapter 2 : Parallel Interfacing With Microprocessor Based System

np
u.
ed
Fig: Timing Waveform for Strobed (With Handshake) Output - 8255 Mode 1

.
es
Mode 1 Output Control Signals

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OBF’ (Output Buffer Full): The OBF’ will go low to indicate that the CPU has written data out
to the specified port. The OBF’ will be set with the rising edge of the WR’ input and reset by
ACK’ input being low.
en
ACK’ (Acknowledgement Input): A low on this input informs the 8255A that the data from
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port A or port B has been accepted. In essence, a response from the peripheral device indicating
that it has received the data output by the CPU.
m

INTR (Interrupt Request): A high on this output can be used to interrupt the CPU when an
output device has accepted data transmitted by the CPU. INTR is set when OBF’, ACK’ and
fro

INTE are all 1 and reset by falling edge of WR’.

INTE: This is an internal flip-flop to a port and needs to be set to generate the INTR signal. The
two flip-flops INTEA and INTEB are set/reset using the BSR mode through PC6 and PC2.
d
de

Example 3
Below mentioned figure shows an interfacing circuit using the 8255A in Mode 1. Port A is
oa

designated as the input port for a keyboard with interrupt I/O and port B is designated as the
output port for a printer with status check I/O.
nl

a) Find port addresses by analyzing the decode logic.

b) Determine the control word to set up port A as input and port B as output in Mode 1.
ow

c) Determine the BSR word to enable INTEA.

d) Determine the masking byte to verify the OBF’ line in status check I/O.
e) Write subroutine to accept character from keyboard and send character to printer.
D

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 Instrumentation II Chapter 2 : Parallel Interfacing With Microprocessor Based System

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u.
. ed
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Solution
a) The 8255A is connected as I/O mapped I/O. When the address lines A7-A2 are all 1, the
output of NAND gate goes low and selects 8255A. The port addresses are calculated as
m

1111 11XX:
Port A = 1111 1100 (FCH)
fro

Port B = 1111 1101 (FDH)

Port C = 1111 1110 (FEH)
Control Register = 1111 1111 (FFH)
d

b) Control word to set up port A as input and port B as output Mode 1 is:
de

D7 D6 D5 D4 D3 D2 D1 D0 = B4H
oa

1 0 1 1 X 1 0 X
c) BSR word to set INTEA
nl

D7 D6 D5 D4 D3 D2 D1 D0 = 09H
ow

0 0 0 0 1 0 0 1
d) Status word to check OBFB’
D

D7 D6 D5 D4 D3 D2 D1 D0 Masking Byte = 02H

X X X X X X OBFB’ X

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 Instrumentation II Chapter 2 : Parallel Interfacing With Microprocessor Based System

e) Subroutines to accept character from keyboard and send to printer:

MVI A, B4H ; Initialize control word

OUT FFH ; Using I/O Mode
MVI A, 09H ; Set INTEA (PC4)

np
OUT FFH ; Using BSR Mode
EI ; Enable Interrupt

u.
CALL READ ; Read Character
CALL PRINT ; Display Character

ed
HLT ; Terminate Program
READ: ; Keyboard Read Subroutine
IN FEH ; Read Port C

.
es
ANI 20H ; Check IBFA (PC5)
JZ READ

ot
IN FCH ; Read ASCII code of character
MOV C, A ; Save Character

PRINT:
RET
en
io
IN FEH ; Read port C
ANI 02H ; Check OBFB’ (D1)
JZ PRINT
m

MOV A, C ; Get Character

fro

OUT FDH ; Send Character to port B

RET
d

Programming in Mode 2 (Strobe Bidirectional Bus I/O)

When the 8255 is operated in Mode 2 (by loading the appropriate control word); Port A can be
de

used as a bidirectional 8-bit I/O bus using PC3–PC7 for handshaking and Port B can be
programmed only in Mode 0 (PC0–PC2 as Input or Output), or in Mode 1 (with PC0–PC2 for
oa

handshaking).
Figure below shows the control word that would have to be loaded into the control port to
nl

configure 8255 in Mode 2. Figure below shows Port A and associated control signals when 8255
is in Mode 2. Interrupts are generated for both output and input operations on the same INTRA
ow

(PC3) line.
D

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 Instrumentation II Chapter 2 : Parallel Interfacing With Microprocessor Based System

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Fig: Timing Waveform for Mode 2 Configuration

D

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 Instrumentation II Chapter 2 : Parallel Interfacing With Microprocessor Based System

The control signal definitions for Mode 2 are:

Output Control Signals
OBF (Output Buffer Full)
This is an active low output which indicates that the CPU has written data into Port A.
ACK (Acknowledge)

np
This is an active low input signal (generated by the peripheral) which enables the tri-state output
buffer or Port A and makes Port A data available to the peripheral. In Mode 2, Port A outputs are

u.
in tri-state until enabled.
INTE 1

ed
This is the flip-flop associated with Output Buffer Full. INTE 1 can be used to enable to disable
the interrupt by setting or resetting PC6 in the BSR Mode.

.
es
Input Control Signals
STB (Strobe Input)

ot
This is an active low input signal which enables Port A to latch the data available as its input.
IBF (Input Buffer Full Flip-Flop)

en
This is an active high output which indicates that data has been loaded into the input latch of Port
A.
io
INTE 2
This is an Interrupt enable flip-flop associated with Input Buffer Full. It can be controlled by
m

setting or resetting PC4 in the BSR Mode.

fro

Status Word in Mode 2

The status word for Mode 2 (accessed by reading Port C) is shown in above figure. D 7–D3 of the
status word carry information about OBFA , INTE1, IBFA, INTE2, and INTRA. The status of the
d

bits D2 – D0 depend on the mode setting of Group B. If B is programmed in Mode 0, D2–D0 carry
de

information about the control signals for B, depending upon whether B is an Input port or Output
port respectively.
oa

Assignment 1:
 Interfacing keyboard and seven segment display
 Interfacing a microprocessor to a tape reader and lathe
nl

 Interfacing to parallel printer

ow

2.3 Parallel Interfacing with ISA and PCI bus

I/O buses are used to connect the system bus (address, data, and control buses) for example ISA
(8 or 16 bit), EISA (Extended ISA - 32 bit), VESA (Video Electronics Standards Association)
D

local bus (VL Bus), PCI (32 or 64 bit), Accelerated graphics port (AGP), PCI-X (64 bit,
133MHZ), PCI-Express etc.

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 Instrumentation II Chapter 2 : Parallel Interfacing With Microprocessor Based System

ISA Bus (Industry Standard Architecture)

 First introduced in 1982 with the first PC (IBM/PC) – [Intel 8088 8 bit microprocessor].
 Originally ISA bus was with 8-bit bus which runs at 4.77 MHz.
 16 bit version of ISA was introduced in 1984 used with Intl 80286 (16-bit
microprocessor).
 Peripheral devices such as sound cards, disk drives, network cards etc. are connected via

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ISA slots.
 ISA bus is mostly obsolete for PC nowadays, but is still used in many industrial
applications due to their low costs and existing cards.

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8-bit ISA bus Architecture

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 Has data bus width of 8 bits and address bus width of 20 bits.
 Number of pins in ISA slots/cards are 62.
 Clock frequency of 4.77 MHz.

.
es
 ISA bus connector contains:
o 20 bit address bus (A19-A0)
o 8 bit data bus

ot
o MEMR’, MEMW’. IOR’, IOW’ control signal for controlling I/O or memory on
the ISA card.
o Interrupt request lines IRQ2-IRQ7
o DMA request inputs DRQ1-DRQ3
o DMA acknowledgement O/Ps DACK0’-DACK3’
en
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o Clock signals
o Power lines and Reset
m
fro
d
de
oa
nl
ow
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 Instrumentation II Chapter 2 : Parallel Interfacing With Microprocessor Based System

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u.
. ed
es
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en
io
m
fro

Fig: 8-bit ISA Bus

16-bit ISA bus Architecture

d

 Data bus width of 16 bit and address bus width of 24 bits.

 Number of pins in ISA card/slot are 98
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 Clock frequency of 8.33 MHz

 Consists of an extra connector with 36 pins behind the 8-bit connector.
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 Compatible with both 8-bit and 16-bit ISA cards.

 16-bit card consists of two edge connectors
o One plugs into the original 8-bit connector
nl

o Other plugs into the new 16-bit connector

 Extra connector consists of
ow

o 4 additional address lines – 24 lines in total

o 8 additional data lines – 16 lines in total
o 4-bit DMA channel request and acknowledgement lines
D

o Additional Interrupt lines

o Control lines to select 8 or 16 bit transfer

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 Instrumentation II Chapter 2 : Parallel Interfacing With Microprocessor Based System

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u.
. ed
es
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en
Fig: The 16-bit ISA bus. (a) Both 8- and 16-bit connectors and (b) the pinout of the 16-bit
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connector.

Reasons for elimination of ISA Bus

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 ISA bus is slow, hard to use and bulky.

 Once each ISA slot/card uses dedicated interrupt lines, only limited number of cards can
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be used.
 Since address lines of 24 bits, a maximum of 224=16 MB of RAM can only be accessed
for DMA.
d

 Since data bus size is 16 bits only, higher bits data (32-bits) communication would reduce
system performance.
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 ISA cards do not have plug and play (PnP) technology i.e. they can’t be configures
automatically by BIOS or operating system.
 ISA cards must be controlled manually by setting the I/O addresses, interrupts and clock
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speed using jumpers and switches on the card itself.

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Improvements in ISA bus

 EISA (Extended ISA) of 32-bits, 8 MHz; now obsolete
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 ISA PnP for plug and play; now obsolete

 VL-Bus of 32-bits operated at the speed of local bus (CPU)
o Used only for graphics cards
D

o Possibility of interference with the performance of the CPU

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 Instrumentation II Chapter 2 : Parallel Interfacing With Microprocessor Based System

PCI Bus (Peripheral Component Interconnect)

 Introduced in 1990 by Intel
 Provides direct access to the CPU and system memory but uses a bridge to connect to the
system bus to eliminate the potential for interference with CPU.
 PCI bus is independent of processor type or speed
 Originally operated at 33 MHz using 32-bit data lines

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 Revised standard at 66 MHz using 64-bit data lines
 The 32-bit PCI connector has 124 pins and 64-bit PCI connector has 188 pins
 The PCI bus is able to work with so few pins because of hardware multiplexing i.e. the

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device sends more than one signal over a single pin
 Also, PCI supports devices that use 5v signalling voltage levels

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 PCI card support plug and play (PnP) feature i.e. PCI devices are automatically
recognized and configured to work in system.

.
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Advancement in PCI bus
 PCI-X (PCI extended): runs at 133 MHz, 32-bit and 1.06 GBps data rate
 PCI-E (PCI express): replaced PCI, PCI-X & AGP standards

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en
io
m
fro
d
de
oa
nl
ow
D

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 Instrumentation II Chapter 2 : Parallel Interfacing With Microprocessor Based System

np
u.
. ed
es
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en
io
m
fro
d
de
oa
nl
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Fig: The pin out of the PCI bus

D

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 Instrumentation II Chapter 2 : Parallel Interfacing With Microprocessor Based System

Tutorials:
1. Assume that your group has decided to make a PC based control system for a wine company.
After studying the system, your group found out that the following to be implemented for
controlling purpose:
 Pressure measurement (6 points)
 Temperature measurement (5 points)

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 Weight measurement (1 point)
 Volume measurement for filling (5 points)
Your group also decided to use 8255A PPI card at base address 0550H.

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a) List out collected documents and components
b) List out different signals you need to derive and or can be directly connected to your

ed
interfacing circuit.
c) Draw minimum mapping circuit for above system
d) What are the address captured by card

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es
e) Generate necessary control word
f) Write a program module for measuring the pressure of all the points and control if the
pressure is not in a range, Assume suitable data if necessary.

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Solution:

supplies (+5V, GND), gates etc. en

a) Components: 8255A card, ADC, MUX, Memory, Processor, connecting wires, power

Documents: Data sheets and technical documentation of above components

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b) Signals needed to be derived on directly connected to circuit
 A1, A2, Chip Select ( CS ) for Port selection of of 8255A, RESET signal
 Read ( RD ) and Write ( WR ) signals
m

 Start Conversion (SC) and End of Conversion (EOC)

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c) The minimum mapping circuit is as given below:

D7 PA7 D7
To 8085 PA0 D0
d

D0 8 Bit Vin
A15 ADC
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. PC7 EOC
. CS PC0 SC
.
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A2 8255A
A1 PPI
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A0

Select Line
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RD PB4 32X1
WR PB0 MUX

……
D

RESET OUT Analog

Input

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 Instrumentation II Chapter 2 : Parallel Interfacing With Microprocessor Based System

d) The base address of card is 0550H, following are address captured by card.
Port Address A A A A A A A A A A A A A A A A
1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0
5 4 3 2 1 0
A 0550H 0 0 0 0 0 1 0 1 0 1 0 1 0 0 0 0
B 0551H 0 0 0 0 0 1 0 1 0 1 0 1 0 0 0 1

np
C 0552H 0 0 0 0 0 1 0 1 0 1 0 1 0 0 1 0
CR 0553H 0 0 0 0 0 1 0 1 0 1 0 1 0 0 1 1

u.
The total numbers of monitoring points are 17. If we use 1 ADC for all of them, we need
to select any one at given time. So, we can use 32X1 MUX which would then have 25=32

ed
i.e. 5 selection lines (B0 to B4). These lines can have defined for any of the 17 lines.
In the above circuit,
Port A  Input port to read data from ADC in mode 0

.
Port B  Output port to select any one of 17 lines from MUX in mode 0

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Port C  Output port (PC0 as SC) and Input port (PC7 as EOC)

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e) Control word and BSR words:
Control word to set up port ports in above configuration:

D7
1
D6
0
D5
0
D4
1
D3
1
D2
0
D1
0
en
D0
0
= 98H
io
BSR word to set PC0
m

D7 D6 D5 D4 D3 D2 D1 D0 = 01H
0 0 0 0 0 0 0 1
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BSR word to reset PC0

D7 D6 D5 D4 D3 D2 D1 D0 = 00H
d

0 0 0 0 0 0 0 0
de

Assuming that ADC starts the conversion process only when it receives SC signal and
after conversion indicates via EOC line i.e. it has finished conversion and so ADC port
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data in its data lines which can be now be read through port A.

f) Program Module:
nl

LXI H, MEMORY
MVI A, 98H
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STA 0553H; write control word in CR

MVI C, 06H; set counter to read 6 pressure points
MVI B, 00H; selection of points for MUX
D

NEXT: MOV A, B
STA 0551H; select first pressure point
MVI A, 01H; load A with BSR word to set PC0

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 Instrumentation II Chapter 2 : Parallel Interfacing With Microprocessor Based System

STA 0553H; set SC line

CALL DELAY
MVI A, 00H; load A with BSR word to reset PC0
STA 0553H; reset SC line
READ: LDA 0552H; read port C
RAL

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JNC READ; check for PC7
LDA 0550H; read data from port A
MOV M, A; store value in memory

u.
CPI MAX_VALUE; compare with maximum value
JNC CONTROL; control value

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CPI MIN_VALUE; compare with minimum value
JC CONTROL; control value
INR B

.
INX H

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DCR C
JNZ NEXT

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2. Interfacing keyboard and seven-segment display.
(Refer Gaonkar  15.2  pages 480-487)
3. Interfacing Lathe machine and tape reader.
(Refer Hall)
en
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4. Interfacing parallel printer.
(Refer Hall)
5. Interface a temperature sensor using an A/D converter and port A of the 8255. Interface a fan
m

and a heater using optocouplers and triacs to drive the I/O devices. Write instructions to read
the temperature; if the temperature is less than 10oC, turn on the heater; and if the
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temperature is higher than 35oC, turn on the fan.

Load temperature from temperature sensor LM135 and control fan and heater.
If temperature > 35o  Fan ON
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If temperature < 10o  Heater ON

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(Refer Gaonkar  15.1.4  pages 468-472)

6. You are required to monitor the operation of pump as well as status of upper and lower tank
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in the household. Apart from that you need to control 3 lights that are to turn ON in the
evening and turn OFF in the morning time. Additionally, you also need to check the status of
smoke sensors in Room1, Room2 & Room3, and heat sensor in kitchen and ring alarm when
nl

necessary.
Your group also decided to use 8255 PPI card at base address 3000H in memory mapped I/O
ow

for controlling purpose. Make complete circuitry including relays and relay driving
transistor.
Write a program module to read status of heat sensor and generate alarm when the limit
D

exceeds.

Compiled By: Er. Hari Aryal [[email protected]] References: Gaonkar, Hall & Brey | 32
 Instrumentation II Chapter 3: Serial Interfacing With Microprocessor Based System

Chapter -3

Serial Interfacing with Microprocessor Based System

3.1 Advantages of Serial Data Transfer Over Parallel

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3.2 Synchronous and Asynchronous Data Transfer
3.3 Errors in Serial Data Transfer
3.4 Simplex, Half Duplex and Full Duplex Data Communication

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3.5 Parity and Baud Rates
3.6 Introduction Serial Standards RS232, RS423, RS422

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3.7 Universal Serial Bus
3.7.1 The Standards:- USB 1.1 and USB 2.0
3.7.2 Signals, Throughput & Protocol

.
3.7.3 Devices, Hosts and On-The-Go

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3.7.4 Interface Chips: USB Device and USB Host

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Within a microcomputer data is transferred in parallel, because that is the fastest way to do it.
For transferring data over long distances, however, parallel data transmission requires too many

en
wires. Therefore, data to be sent long distances is usually converted from parallel form to serial
form so that it can be sent on a single wire or pair of wires. Serial data received from a distant
source is converted to parallel form so that it can easily be transferred on the microcomputer
io
buses.

Advantages of Serial Data Transfer Over Parallel

m

 Longer data transmission in serial mode

o Serial; 1  -3V to -25V
fro

0  +3V to +25V
o Parallel; 1  +5V
0  0V
o Voltage loss is not much a problem in serial communication.
d

 Serial transmission requires less number of wires than parallel and so cheaper to transmit
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data.
 Crosstalk is less of an issue because there are fewer conductors’ compared to that of
parallel cables.
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 Many IC and peripherals have serial interface

 Clock skew between different cables is not an issue
 Serials can be clocked at higher data rate
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 Serial cable can be longer than parallel

 Cheaper to implement
ow

 But in serial mode of transfer, only one bit of a word is transferred at a time so that data
transfer rate is very slow; it is the one of the demerit over parallel data transfer.
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Compiled By: Er. Hari Aryal [[email protected]] References: Gaonkar, Hall & Hyde | 1
 Instrumentation II Chapter 3: Serial Interfacing With Microprocessor Based System

Serial Data Transmission

In a serial data transmission, the data are sent one bit at a time over the transmission channel.
However, since most processors process data in parallel, the transmitter needs to transform
incoming parallel data into serial data and the receiver needs to do the opposite.

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u.
ed
In case of serial transmission data is sent in a serial form i.e. bit by bit on a single line. Also, the
cost of communication hardware is considerable reduced since only a single wire or channel is

.
require for the serial bit transmission. Serial data transmission is slow as compared to parallel

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transmission. Serial data can be sent synchronously or asynchronously.

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Serial Synchronous Data Transmission
In serial synchronous data transmission, data is transmitted or received based on a clock signal.
At a specific rate of data transmission, the transmitting device sends a data bit at each clock
en
pulse. In order to interpret the data correctly, the receiving device must know the start and end of
each data unit. The transmitter must know the number of data units to be transferred and the
io
receiver must be synchronized with the data boundaries. Therefore, there must be
synchronization between the transmitter and receiver. Usually one or more SYNC characters are
used to indicate the start of each synchronous data stream or frame of data.
m

Transmitter sends a large block of data characters one after the other with no time between
characters. Transmitting device sends data continuously to the receiving device. If the data is not
fro

ready to be transmitted, the line is held in marking condition. To indicate the start of
transmission, the transmitter sends out one or more SYNC characters or a unique bit pattern
called a flag, depending on the system being used. The receiving device waits for data, when it
finds the SYNC characters or the flag then starts interpreting the data which shifts the data
d

following the SYNC characters and converts them to parallel form so they can be read in by a
de

computer.
oa
nl
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 Instrumentation II Chapter 3: Serial Interfacing With Microprocessor Based System

Synchronous transmission has the advantage that the timing information is accurately aligned to
the received data, allowing operation at much higher data rates. It also has the advantage that the
receiver tracks any clock drift which may arise (for instance due to temperature variation). The
penalty is however a more complex interfaces design, and potentially a more difficult interface to
configure (since there are many more interface options).
Data transmission takes place without any gap between two adjacent characters. However data is

np
send block by block. A block is a continuous steam of characters or data bit pattern coming at a
fixed speed. You will find a SYNC bit pattern between any two blocks of data and hence the data
transmission is synchronized. Synchronous communication is used generally when two

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computers are communicating to each other at a high speed or a buffered terminal is
communicating to the computer.

ed
Advantages and Disadvantages of Synchronous Communication
Main advantage of Synchronous data communication is the high speed. The synchronous

.
communications require high-speed peripherals/devices and a good-quality, high bandwidth

es
communication channel.
The disadvantage includes the possible in accuracy. Because when a receiver goes out of

ot
Synchronization, loosing tracks of where individual characters begin and end. Correction of
errors takes additional time.

Serial Asynchronous Data Transmission en

The receiving device does not need to be synchronized with the transmitting device. The
io
transmitting device can send one or more data units when it is ready to send data. Each data unit
must be formatted i.e. must contain start and stop bits for indicating beginning and the end of
data unit. It also includes one parity bit to identify odd or even parity of data. To send ASCII
m

character, the framing of data should contain:

 1 start bit: Beginning of data
fro

 8 bit character: Actual data transferred

 1 or 2 stop bits: End of data
When no data is being sent, the signal line is in a constant high or marking state. The beginning
of the data character is indicated by the line going low for 1 bit time and this bit is called a start
d

bit. The data bits are then sent out on the line one after the other where the least significant bit is
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sent out first. Parity bit should contain to check for errors in received data. After the data bit and
a parity bit, the signal line is returned high for at least 1 bit time to identify the end of the
character, this always high bit is referred to as a stop bit. Some older systems use 2 stop bits.
oa
nl
ow
D

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 Instrumentation II Chapter 3: Serial Interfacing With Microprocessor Based System

np
u.
. ed
In asynchronous transmission each character is transmitted separately, that is one character at a

es
time. The character (8-bits) is preceded by a start bit (1-bit), which tells the receiving end where
the character coding begins, and is followed by a stop bit (1 or 2-bits), which tells the receiver

ot
where the character coding ends. There will be intervals of ideal time on the channel shown as
gaps. Thus there can be gaps between two adjacent characters in the asynchronous

parity and stop bits) are sent at the baud rate. en

communication scheme. In this scheme, the bits within the character frame (including start,

The START bit and STOP bit including gaps allow the receiving and sending computers to
io
synchronize the data transmission. Asynchronous communication is used when slow speed
peripherals communicate with the computer. The main disadvantage of asynchronous
communication is slow speed transmission. Asynchronous communication however, does not
m

require the complex and costly hardware equipments as is required for synchronous
transmission.
fro

Synchronous versus Asynchronous serial data transmission

S.N. Parameter Asynchronous Synchronous
1. Fundamental Transmission does not Transmission based on clock
d

based on clock signal signal

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2. Data Format One character at a time Group of characters i.e. a

block of characters
3. Speed Low (< 20 kbps) High (> 20 kbps)
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4. Framing Start and stop bits are sent SYNC characters are sent
Information with each character. with each character.
5. Implementation Hardware / Software Hardware
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Serial Data Unit (SDU) & Serialization

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 SDU is a unit with 1 start bit, 8 data bits, 1 parity bit and 1 or 2 stop bits.
 Start bit always has a value of 0 & stop bits always have a value of 1.
 Following figure shows a SDU format; for asynchronous data transmission, sender and
D

receiver must be set up to the same format.

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 Instrumentation II Chapter 3: Serial Interfacing With Microprocessor Based System

Fig: SDU or frame format

np
Transmitting SDU
 The interface chip has a transmitter hold register for transmitting data which first fetches
the data bytes from CPU.

u.
 According to the selected data format, the SDU logic puts the start bit in front of data
bits; it then calculates the parity bit and appends it together with the stop bits to the data

ed
bits.
 Thus formed SDU is transferred into the transmitter shift register, which is operated by a

.
clock source determined by baud rate and thus provides the individual bits at the serial

es
output (LSB first). If no data, then the chip possesses a logical high level.

ot
Interface Control & Baud
rate Generator

Transmitter Transmitter
en
io
Bus SDU
Interfac e Hold Shift
Logic D7 D6 D5 D4 D3 D2 D1 D0
Register Register
Stop Parity Data Bits Start
m

Fig: SDU at transmitter side

Receiving SDU
fro

 Inverse reception process

 Start bit acts as trigger pulse & starts the receiver in the serial input chip.
 The SDU bits are loaded into the receiver shift register according to the phase of the
d

setup baud rate.

 The receiver SDU logic then separates the start, parity, stop bits from the received SDU
de

bits, calculates the parity of the data bits & compares it with the setup parity.
 Afterwards, the extracted data bits are transferred into the receiver buffer register from
which they may be read out as the received data byte by the CPU.
oa
nl

Interface Control & Baud

rate Generator
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Bus Receiver Receiver

SDU
Buffer Shift
D

Interfac e Logic D0 D1 D2 D3 D4 D5 D6 D7
Register Register
Start Data Bits Parity Stop

Fig: SDU at receiver Side

Compiled By: Er. Hari Aryal [[email protected]] References: Gaonkar, Hall & Hyde | 5
 Instrumentation II Chapter 3: Serial Interfacing With Microprocessor Based System

Errors in Serial Data Transfer

From the description of the transmission and reception process, it can be readily seen that
transmitter and receiver must be set to the same baud rate. Additionally, the set data formats (i.e.
number of data bits, parity, start and stop bits) must also coincide; otherwise the receiver may
resemble possibly a different byte from that which the transmitter was passed for transmitting.
Upon reception of an SDU, various errors may occur.

np
1. Framing Error
Data does not fit in frame that data format and baud rate defined i.e. non-synchronized
start / stop bit. Eg:- Change in no. of bits in receiving and transmitting end.

u.
2. Break Error
If the reception line is at logic low level for longer time than the SDU usually lasts, then

ed
the receiver assumes that the connection to the transmitter has broken. Unless the
transmitter drives the line to a logical high level, no data is transferred.
3. Overrun Error

.
If data arriving at the receiver is much faster than it can be read from the receiver buffer;

es
the latter received byte overwrites the older data in the buffer.
4. Parity Error

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The calculated parity does not coincide with the set one. It may be due to the noise or a
different set for parity at transmitter and receiver sides.
 No parity
 Even parity
 Odd parity
en
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 Mark parity
 Space parity
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Error Checks in Data Communication

During transmission, various types of errors can occur such as data bits may change because of
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noise or can be misunderstood by the receiver due to different clocks between transmitter and
receiver. These errors need to be checked; therefore, additional information for error checking is
sent during the transmission. The receiver can check the received data against the error check
d

information, and if an error is detected, the receiver can request the retransmission of that data
segment or it can correct by proper coding techniques. Three methods are generally in common
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practice; they are parity check, checksum and cyclic redundancy check.

Parity Check
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This is the simplest method of error checking which checks the characters by counting the
number of 1s. In this method, D7 of each ASCII code is used to transmit parity check
information. Parity may be the even parity (having even number of 1s in a character) or the odd
nl

parity (having odd number of 1s in a character).

In an even parity system, when a character has an odd number of 1s, the bit D7 is set to 1 and an
ow

even number of 1s is transmitted. On the other hand, in an odd parity system, when a character
has an even number of 1s, the bit D7 is set to 1 and an odd number of 1s is transmitted.
For an example, character to be sent is ‘A’ whose ASCII code is 41H (0100 0001) with two 1s. If
D

the character is transmitted in an odd parity system, the bit D7 is set to 1 and if it is transmitted in
an even parity system, the bit D7 is set to 0. Most of microprocessors are designed to detect

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 Instrumentation II Chapter 3: Serial Interfacing With Microprocessor Based System

parity using the parity flag. However, the parity check cannot detect multiple errors in any given
character.

Checksum
The checksum technique is used when blocks of data are transmitted. It involves adding all the
bytes in a block without carriers. Then, the 2’s complement of the sum (negative of the sum) is

np
transmitted as the last byte. The receiver adds all the bytes, including the 2’s complement of the
sum; thus, the result should be zero if there is no error in the block.

u.
Cyclic Redundancy Check (CRC)
This technique is based on mathematical relationships of polynomials. A stream of data can be

ed
represented as a polynomial that is divided by a constant polynomial, and the remainder, unique
to that set of bits, is generated. The remainder is sent out as a check for errors. The receiver
checks the remainder to detect an error in the transmission. This is a somewhat complex

.
technique for error checking.

es
ot
Baud Rate / Bit Rate
The difference between Bit and Baud rate is complicated and intertwining. Both are dependent
and inter-related.
en
Bit Rate is how many data bits are transmitted per second.
A baud Rate is the number of times per second a signal in a communications channel changes.
io
Bit rates measure the number of data bits (that is 0′s and 1′s) transmitted in one second in a
communication channel. A figure of 2400 bits per second means 2400 zeros or ones can be
transmitted in one second, hence the abbreviation “bps.” Individual characters (for example
m

letters or numbers) that are also referred to as bytes are composed of several bits.
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A baud rate is the number of times a signal in a communications channel changes state or varies.
For example, a 2400 baud rate means that the channel can change states up to 2400 times per
second. The term “change state” means that it can change from 0 to 1 or from 1 to 0 up to X (in
this case, 2400) times per second. It also refers to the actual state of the connection, such as
d

voltage, frequency, or phase level).

de

The main difference between the two is that one change of state can transmit one bit, or slightly
more or less than one bit, that depends on the modulation technique used. So the bit rate (bps)
and baud rate (baud per second) have this connection:
oa

If signal is changing every 10/3 ns then,

Baud rate = 1/10/3ns = 3/10*109 = 3*108
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= 300 mbd
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Note:
If 1 frame of data is coded with 1 bit then band rate and bit rate are same. Sometimes frame of
data are coded with two or more bits then baud rate and bit rate are not same.
D

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 Instrumentation II Chapter 3: Serial Interfacing With Microprocessor Based System

Simplex, Half Duplex and Full Duplex Data Communication

Simplex Mode
Simplex transmission allows data to travel only in a single, pre specified direction. An example
from everyday life is doorbell the signal can go only from the button to the chime. Two other
examples are television and radio broadcasting. The simplex standard is relatively uncommon for
most types of computer-based telecommunications applications; even devices that are designed

np
primarily to receive information, such as printers must be able to communicate
acknowledgement signals back to the sender devices.
System A System B

u.
Unidirectional
Transmitter Receiver

ed
Fig: Simplex mode

.
es
Half Duplex Mode
It is a two way communication between two ports provided that only party can communicate at a

ot
time. In half duplex transmission messages can move in either direction, but only one way at a
time. The press to talk radio phones used in police cars employs the half-duplex standard; only

en
one person can talk at a time. Often the line between a desktop workstation and a remote CPU
conforms to the half duplex patterns as well. If another computer is transmitting to a workstation,
the operator cannot send new messages until the other computer finishes its message to
io
acknowledge an interruption.

System A System B
m

Transmitter/Rec Transmitter/Rec
OR
eiver eiver
fro

Fig:Half Duplex mode

Full Duplex Mode

d

It provides simultaneous two way transmission without the intervening stop-and-wait aspect of
de

half duplex. Full duplex is widely used in applications requiring continuous channels usage. Full
duplex transmission works like traffic on a busy two way street the flow moves in two directions
at the same time. Full-duplexing is ideal for hardware units that need to pass large amounts of
oa

data between each other as in mainframe-to-mainframe communications.

System A System B
nl

Transmitter/Rec Transmitter/Rec
eiver OR/AND eiver
ow

Fig: Full Duplex mode

D

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 Instrumentation II Chapter 3: Serial Interfacing With Microprocessor Based System

Standards in Serial I/O

The serial I/O technique is commonly used to interface different peripheral terminals such as
printers, modems with microcomputers which are designed and manufactured by various
manufacturers. Therefore, a common understanding must exist, among various manufacturing
and user groups that can ensure compatibility among different equipment. The standard is
defined as the understanding which is accepted in industry and by users. A standard is normally

np
defined by a professional organizations such as IEEE (Institute of Electrical and Electronics
Engineers), EIA (Electronic Industries Association) as a de jure standard. However, a
widespread practice can become a de facto standard.

u.
In serial I/O, data can be transmitted as either current or voltage. When data are transmitted with
current signal such for teletype equipment, 20 mA (or 60 mA) current loops are used. When a

ed
teletype is marking or at logic 1, current flows; when it is at logic 0 (space), the current flow is
interrupted. The advantage of the current loop method is that signals are relatively noise-free and
are suitable for transmission over a distance.

.
When data are transmitted with voltage signal, there are various standards which are explained in

es
this section.

ot
RS-232C
Serial transmission of data is used as an efficient means for transmitting digital information

en
across long distances, the existing communication lines usually the telephone lines can be used
to transfer information which saves a lot of hardware. RS-232C is an interface developed to
standardize the interface between data terminal equipment (DTE) and data communication
io
equipment (DCE) employing serial binary data exchange. Modem and other devices used to send
serial data are called data communication equipment (DCE). The computers or terminals that are
sending or receiving the data are called data terminal equipment (DTE).
m

RS- 232C is the interface standard developed by electronic industries Association (EIA) in
fro

response to the need for the signal and handshake standards between the DTE and DCE. RS-
232C has following standardize features.

- It uses 25 pins (DB – 25P) or 9 Pins (DE – 9P) standard where 9 pins standard does not
d

use all signals i.e. data, control, timing and ground.

de

- It describes the voltage levels, impendence levels, rise and fall times, maximum bit rate
and maximum capacitance for all signal lines.
- It specifies that DTE connector should be male and DCE connector should be female.
oa

- It can send 20kBd for a distance of 50 ft.

- The voltage level for RS-232 are:
o A logic high or 1 or mark, -3V to -15V
nl

o A logic low or 0 or space, +3v to +15v

- Normally ±12V voltage levels are used
ow
D

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 Instrumentation II Chapter 3: Serial Interfacing With Microprocessor Based System

np
u.
ed
- Mc1488 line driver converts logic 1 to -9V
Logic 0 to +9v

.
es
- Mc1489 line receiver converts RS – 232 to TTL
- Signal levels of RS-232 are not compatible with that of the DTE and DCE which are TTL
signals for that line driver such as M 1488 and line receiver MC1489 are used.

ot
RS- 232 signals used in handshaking:

Signal Flow DE-9P

- 1
DB-25P
-
Signal en
Protective Ground
Description
-
io
DTE to DCE 3 2 TxD Transmitted Data
DCE to DTE 2 3 RxD Received Data
m

DTE to DCE 7 4 Request To Send

DCE to DTE 8 5 Clear To Send
fro

DCE to DTE 6 6 Data Set Ready

Common Ref 5 7 GND Signal Ground
DCE to DTE 1 8 Data Carrier Detect
d

DTE to DCE 4 20 Data Terminal Ready

de

DCE to DTE 9 22 RI Ring Indicator

DCE to DTE - 23 DSRD Data Signal Rate Detector
oa

Data Terminal Ready (DTR):

After the terminal power is turned on and terminal runs any self checks, it asserts data
terminal ready (DTR’) signal to tell the modem that it is ready.
nl

Data Set Ready (DSR):

ow

When the MODEM is powered up and ready to transmit or receive data, it will assert data
set ready (DSR’) to the terminal. Under manual control or terminal control, modem then
dials up the computer. If the computer is available, it will send back a specified tone.
D

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 Instrumentation II Chapter 3: Serial Interfacing With Microprocessor Based System

Request to send (RTS):

When a terminal has a character ready to send, it will assert a request-to-send (RTS’)
signal to the modem.

Data Carrier Detect (DCD):

The modem will then assert its data-carrier-detect (DCD’) signal to the terminal to

np
indicate that it has established connection with the computer.

Clear to send (CTS):

u.
When the modem is fully ready to receive data, it asserts the clear-to-send (CTS’) signal
back to the terminal.

ed
Ring indicator (RI):
It indicates that a ring has occurred at modem. Deactivating DTR or DSR breaks the

.
connection but RI works independently of DTR i.e. a modem may activate RI signal even

es
if DTR is not active.

ot
Transmitted Data (TxD):
The terminal then sends serial data characters to the modem.

Received Data (RxD): en

Modem will receive data from terminal through this line.
io
Data Signal Rate Detect (DSRD):
It is used for switching different baud rate.
m

Digital Data Transmission Using Modem and standard Phone Lines

fro

Standard telephone system can be used for sending serial data over long distances. However,
telephone lines are designed to handle voice, bandwidth of telephone lines ranges from 300 HZ
to 3400 HZ. Digital signal requires a bandwidth of several megahertz. Therefore, data bits should
be converted into audio tones, this is accomplished through modems.
d
de
oa
nl
ow
D

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 Instrumentation II Chapter 3: Serial Interfacing With Microprocessor Based System

- DTE asserts to tell the modem it is ready.

- Then DCE asserts signal to the terminal and dials up.
- DTE asserts signal to the modem.
- Modem then asserts signal to indicate that it has established connection with the
computer.

np
- DCE asserts signals, then DTE sends serial data.
- When sending completed, DTE asserts high, this causes modem to un assert its
signal and stop transmitting similar handshake taken between DCE and DTE other side.

u.
- To communicate from serial port of a computer to serial port of another computer without
modem, null-modem is used.

ed
Simplex, Half Duplex and Full Duplex Operation Using RS-232 port

.
es
Simplex Connection for RS-232C
There are two possibilities; data transfer from DTE to DCE or vice versa.

ot
From DTE to DCE
The DTE transfers data to the DCE via the TxD line. The RxD line is not connected. The DCE

en
does not use RTS or DTE holds RTS signal active all the time. The DCE always outputs an
inactive DCD signal as it can receive data from DTE and transfer it to destination. By means of
DTR signal, DTE can indicate DCE that it is ready for operation as usual and may activate or
io
disable DCE. RI signal has no meaning because normally transmitter calls receiver.

Form DCE to DTE

m

In this case, only the DCE transfers data to the DTE via RxD line. The TxD line is not
connected. The DCE does not either use RTS or CTS signal or holds them constantly at an active
fro

level. The DCE may output an active DCD signal as it can detect a carrier signal from an
external device and transfer data to DTE. By means of DTR, the DTE can indicate that it is ready
for operation and it can activate or disable the DCE as usual. The RI signal has a meaning as
d

external device may call DTE via DCE.

de

Half Duplex Connection for RS-232C

On a half duplex connection, both the DTE and DCE can operate as receiver and transmitter, but
only one data line is available which is alternatively used by the DTE and DCE. The TxD and
oa

RxD lines output and receive data respectively in a strictly ordered manner for assigning the
roles as receiver and transmitter between DTE and DCE; the handshake control signals RTS and
CTS are used. If a DTE device wants to act as a transmitter, then it activates the RTS signal and
nl

waits for an acknowledgement of other DCE device by means of CTS signal. Now, data can be
exchanged while DTE acting as transmitter and DCE as receiver otherwise DCE may operate as
ow

transmitter and DTE as receiver.

Full Duplex Connection for RS-232C

D

Most microcomputer modems are full duplex, and transfer data in both directions
simultaneously; thus DTE and DCE act simultaneously as receiver and transmitter. The RTS and
CTS signals are meaningless and are usually not used or are always active. Further, the DSR
Compiled By: Er. Hari Aryal [[email protected]] References: Gaonkar, Hall & Hyde | 12
 Instrumentation II Chapter 3: Serial Interfacing With Microprocessor Based System

signal is also enabled all the time on most modems but on some DCEs, DSR may be active only
if preparations for calling destination device are completed. The signal is normally activated by
DCE only if it has detected a carrier signal from the destination device. Also, in this connection,
DTR signal acts as a main switch and RI indicates that an external device wants to establish a
connection with DTE via DCE.
A full duplex connection is very comfortable, as we need not pay attention to the roles of

np
receiver and transmitter i.e. we may keep RTS signal active all time ignoring CTS and DSR
signals.

u.
Null (Zero) Modem Connection

ed
A zero modem serves for data exchange between DTEs. Since both the computers are
configured as DTEs, directly connecting them by means of the conventional serial interface cable
is impossible; not even the plug fits into the jack of the second terminal. Also the TxD meets

.
TxD and RxD meets RxD, DTR meets DTR and DSR meets DSR etc. This means that outputs

es
are connected to outputs and inputs are connected to inputs. With this convention, no data
transfer is possible.

ot
For the transmission of data, it is required to twist the TxD and RxD lines. In this way, the

en
transmitted data of one terminal (PC) becomes received data of other and vice versa. As shown
in figure, activation of RTS to begin a data transfer gives rise to an activation of CTS on same
DTE and to an activation of DCD on other DTE. Further, an activation of DTR leads to rise of
io
DSR and RI on other DTE. Hence for every DTE, it is simulated that a DCE is on the end of line,
although a connection between two DTEs is actually present. Zero modem can be operated with
standard BIOS and DOS functions.
m
fro
d
de
oa
nl
ow
D

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 Instrumentation II Chapter 3: Serial Interfacing With Microprocessor Based System

Connection to Printers
As a printer is not DCE, various control and status lines have to be connected or interchanged to
emulate behavior of a DCE. TxD data of PC becomes received data of printer. DCD and RI
signals on PC are meaningless. On PC, RTS and CTS are connected to each other so that a
transmission request from PC immediately enables the transmission. Since, printer as DTE refers
to print anything as long as no active signal is present at inputs CTS, DSR and DCD. This

np
problem is solved by connecting RTS with CTS and DTR with DCD and DSR. Thus, activating
RTS gives rise to an activation of CTS and that of DTR to an activation of DCD and DSD.
Overrun error arises in serial interface as PC can transmit data much faster than printer can print

u.
it so internal printer buffer gets full. On parallel interface, this problem is solved as printer
activates BUSY signal informing PC that it cannot accept data temporarily. In serial interface,

ed
pin 19 of printer is used to output a <<Buffer Full Signal>>. On DTE, DSR provide an input for
this signal. If printer buffer is full, printer simply disables handshake signal at pin 19 and DTE
knows that temporarily no additional data can be transferred. If enough room is available in

.
buffer again, printer enables signal once more; PC may transfer data to printer. Not all printers

es
with serial interface provide such a buffer full signal at pin 19.

ot
en
io
m
fro
d
de
oa

RS-423A
A major problem with RS-232C is that it can only transmit data reliably for about 50 ft at its
nl

maximum rate of 20Kbd. If longer lines are used the transmission rate has to be drastically
reduced due to open signal lines with a common signal ground. Another EIA standard which is
ow

improvement over RS-232C is RS-423A. The standardize features of RS-423 are:

- This standard specifies a low impendence single ended signal which can be sent over 50
coaxial cable and partially terminated at the receiving end to prevent reflection.
D

- Voltage levels
o Logic High 4V - 6V negative
o Logic Low 4V - 6V positive
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 Instrumentation II Chapter 3: Serial Interfacing With Microprocessor Based System

- It allows a maximum data rate of 100 Kbd over 40 ft line or a maximum baud rate of 1
Kbd over 4000 ft line.

np
u.
. ed
es
RS-422A
It is a newer standard for serial data transfer. It specifies that each signal will be sent

ot
differentially over two adjacent wires in a ribbon cable or a twisted pair of wires uses differential
amplifier to reject noise. The term differential in this standard means that the signal voltage is

en
developed between two signal lines rather than between signal line and ground as in RS-232C
and RS-423A. Any electrical noise induced in one signal line will be induced equally in the other
signal line. A differential line receiver MC3486 responds only to the voltage difference between
io
its two inputs so any noise voltage that is induced equally on two inputs will not have any effect
on the output of the differential receiver.
m
fro
d
de
oa

RS-422A has following standardized features:

- Logic high is transmitted by making ‘b’ line more positive than ‘a’ line.
- Logic low is transmitted by making ‘a’ line more positive than ‘b’ line.
nl

- The voltage difference between the two lines must be greater than 0.4V but less than
ow

12V.
- The MC3487 driver provides a differential voltage of about 2V.
- The center or common mode voltage on the lines must be between -7v and +7v
- Transmission rate is 10 MBd for 40 ft and 100 KBd for 4000 ft.
D

- The high data transfer is because of differential line functions as a fully terminated
transmission line.
- Mc 3486 receiver only responds to the differential voltage eliminating noise.
Compiled By: Er. Hari Aryal [[email protected]] References: Gaonkar, Hall & Hyde | 15
 Instrumentation II Chapter 3: Serial Interfacing With Microprocessor Based System

Comparison of Serial I/O Standards

S.N. Specifications RS-232C RS-423A RS-422A
1. Speed 20 Kbaud 100 Kbaud at 40 10 Mbaud at 40
ft ft
1 kbaud at 4000 100 kbaud at
ft 4000 ft

np
2. Distance 50 ft 4000 ft 4000 ft
3. Logic 0 +3 V to +25 V +4 V to +6 V B line > A line
4. Logic 1 -3 V to -25 V -4 V to –6 V A line > B line

u.
5. Receiver Input ±15V ±12V ±7V
Voltage

ed
6. Mode of Single ended Differential Differential
Operation input and output input and single input and output
ended output

.
es
7. Noise Immunity 2.0 V 3.4 V 1.8 V
8. Input Impedance 3-7 KOhm and >4 KOhm >4 KOhm
2500 pf

ot
9. Short circuit 500 mA 150 mA 150 mA
current

Universal Serial Bus (USB)


en
In the past, connecting multiple peripheral devices to computer has been a real problem.
io
There were too many different port types (serial port, parallel port, PS/2 etc.) and their
use imposes limitations such as no hot-plug ability and automatic configuration.

m

USB is designed to allow many peripherals to be connected using a single standardized

interface. It provides an expandable, fast, bi-directional, low-cost, hot-pluggable Plug and
fro

Play serial hardware interface that makes the life of the computer users easier allowing
them to plug different peripheral devices into a USB port and have them automatically
configured and ready to use. Using a single connector type, USB allows the user to
connect a wide range of peripheral devices, such as keyboards, mice, printers, scanners,
d

mass storage devices, telephones, modems, digital still-image cameras, video cameras,
audio devices to a computer. USB devices do not directly consume system resources.
de

 USB is an industry standard developed in the mid-1990s that defines the cables,
connectors and protocols used for connection, communication and power supply between
oa

computers and electronic devices.

 . It has become commonplace on other devices, such as smart phones, PDAs and video
game consoles. USB has effectively replaced a variety of earlier interfaces, such as serial
nl

and parallel ports, as well as separate power chargers for portable devices.
ow

Features of USB
 Single connector type: USB replaces all the different legacy connectors with one well-
defined, standardized USB connector for all USB peripheral devices, eliminating the need
D

for different cables and connectors and thus simplifying the design of the USB devices.
So all USB devices can be connected directly to a standard USB port on a computer.

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 Instrumentation II Chapter 3: Serial Interfacing With Microprocessor Based System

 Hot-swappable: USB devices can be safely plugged and unplugged as needed while the
computer is running. So there is no need to reboot.
 Plug and Play: Operating system software automatically identifies, configures, and loads
the appropriate device driver when a user connects a USB device.
 High performance: USB offers low speed (1.5 Mbit/s), full speed (12 Mbit/s) and high
speed (up to 480 Mbit/s) transfer rates that can support a variety of USB peripherals.

np
USB 3.0 (SuperSpeed USB) achieves the throughput up to 5.0 Gbit/s.
 Expandability: Up to 127 different peripheral devices may theoretically be connected to a
single bus at one time.

u.
 Power supplied from the bus: USB distributes the power to all connected devices
eliminating the need for external power source for low-power devices. High-power

ed
devices can still require their own local power supply. USB also supports power saving
suspend/resume modes.
 Easy to use for end user: A single standard connector type for all USB devices simplifies

.
the end user's task at figuring out which plugs go into which sockets. The operating

es
system automatically recognizes the USB device attachment and loads appropriate device
drivers.

ot
 Low-cost implementation: Most of the complexity of the USB protocol is handled by the
host, which along with low-cost connection for peripherals makes the design simple and

•
low cost.
Wide range of workloads and applications: en
– Suitable for device bandwidths ranging from a few kb/s to several Mb/s
io
– Supports isochronous as well as asynchronous transfer types over the same set of
wires
– Supports concurrent operation of many devices (multiple connections)
m

– Supports up to 127 physical devices

– Supports transfer of multiple data and message streams between the host and
fro

devices
– Allows compound devices (i.e., peripherals composed of many functions)
– Lower protocol overhead, resulting in high bus utilization
• Isochronous bandwidth
d

– Guaranteed bandwidth and low latencies appropriate for telephony, audio, etc.
de

– Isochronous workload may use entire bus bandwidth

• Robustness
– Error handling/fault recovery mechanism is built into the protocol
oa

– Dynamic insertion and removal of devices is identified in user-perceived real-time

– Supports identification of faulty devices
nl

USB Standards
USB 1.0
ow

 USB 1.0: Released in January 15, 1996.

Specified data rates of 1.5 Mbit/s (Low-Bandwidth) and 12 Mbit/s (Full-Bandwidth).
Does not allow for extension cables or pass-through monitors (due to timing and power
D

limitations). Few such devices actually made it to market.

 USB 1.1: Released in September 23, 1998.
Introduced the improved specification and was the first widely used version of USB.

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 Instrumentation II Chapter 3: Serial Interfacing With Microprocessor Based System

Fixed problems identified in 1.0, mostly relating to hubs. Earliest revision to be widely
adopted.

USB 2.0
 The USB 2.0 specification was released in April 27, 2000 and was ratified by the USB
Implementers Forum (USB-IF) at the end of 2001.

np
 The major feature of revision 2.0 was the addition of a high-speed transfer rate of 480
Mbit/s. USB 2.0 supports three speeds namely High Speed - 480Mbits/s, Full Speed -
12Mbits/s and Low Speed - 1.5Mbits/s with one host per bus (at a time).

u.
USB 3.0

ed
 The USB 3.0 specification was published on 12 November 2008.
 Brings significant performance enhancements to the USB standard while offering
backward compatibility with the peripheral devices currently in use. Legacy USB 1.1/2.0

.
es
devices continue to work while plugged into new USB 3.0 host and new USB 3.0 devices
work at USB 2.0 speed while plugged into USB 2.0 host.
 Delivering data transfer rates up to ten times faster (the raw throughput is up to 5.0

ot
Gbit/s) than Hi-Speed USB (USB 2.0), SuperSpeed USB is the next step in the continued
evolution of USB technology.

en
 Its main goals were to increase the data transfer rate (up to 5 Gbit/s), to decrease power
consumption, to increase power output, and to be backwards-compatible with USB 2.0.
USB 3.0 includes a new, higher speed bus called SuperSpeed in parallel with the USB 2.0
io
bus. For The first USB 3.0 equipped devices were presented in January 2010
 Transfer of 25 GB file in approx 70 seconds
 Extensible – Designed to scale > 25Gbps
m

 Optimized power efficiency

o No device polling (asynchronous notifications)
fro

o Lower active and idle power requirements

 Backward compatible with USB 2.0
o USB 2.0 device will work with USB 3.0 host
d

o USB 3.0 device will work with USB 2.0 host

de

Wireless USB


oa

Released in May 12, 2005 which uses UWB (Ultra Wide Band) as the radio technology.
 480 M bits/sec up to 3m
 110 m bits/sec up to 10m
nl

Signals, Throughput & Protocol

ow

USB Interconnect
• Bus Topology: Connection model between USB devices and the host.
• Inter-layer Relationships: In terms of a capability stack, the USB tasks that are performed
D

at each layer in the system.

• Data Flow Models: The manner in which data moves in the system over the USB
between producers and consumers.

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 Instrumentation II Chapter 3: Serial Interfacing With Microprocessor Based System

• USB Schedule: The USB provides a shared interconnect. Access to the interconnect is
scheduled in order to support isochronous data transfers and to eliminate arbitration
overhead.

np
u.
ed
Fig: 'A' Plug, 'B' Plug and 'Mini-B' Plug

.
es
Signals

ot
en
io
Pin Color Name Description
1 Red Vcc +5V dc
m

2 White D- Data-
fro

3 Green D+ Data+
4 Black GND Ground
d

Fig: USB electrical signals

de
oa
nl
ow
D

Fig: USB signals and states

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 Instrumentation II Chapter 3: Serial Interfacing With Microprocessor Based System

Bus State Levels

Differential '1' D+ high, D- low
Differential '0' D- high, D+ low
Single Ended Zero (SE0) D+ and D- low
Single Ended One (SE1) D+ and D- high

np
Data J State:
Low-speed Differential '0'
Full-speed Differential '1'

u.
Data K State:

ed
Low-speed Differential '1'
Full-speed Differential '0'
Idle State:

.
Low-speed D- high, D+- low

es
Full-speed D+ high, D- low
Resume State Data K state

ot
Data lines switch from idle to K
Start of Packet (SOP)
state
End of Packet (EOP)
Disconnect
en SE0 for 2 bit times followed by J
state for 1 bit time
SE0 for >= 2us
io
Connect Idle for 2.5us
Reset SE0 for >= 2.5 us
m

J, K and SEO States

fro

To make it easier to talk about the states of the data lines, some special terminology is used. The
'J State' is the same polarity as the idle state (the line with the pull-up resistor is high, and the
other line is low), but is being driven to that state by either host or device.
The K state is just the opposite polarity to the J state.
d

The Single Ended Zero (SE0) is when both lines are being pulled low.
de

The J and K terms are used because for Full Speed and Low Speed links they are actually of
opposite polarity.
oa

Single Ended One (SE1)

This is the illegal condition where both lines are high. It should never occur on a properly
functioning link.
nl

Reset
ow

When the host wants to start communicating with a device it will start by applying a 'Reset'
condition which sets the device to its default unconfigured state.
The Reset condition involves the host pulling down both data lines to low levels (SE0) for at
D

least 10 ms. The device may recognize the reset condition after 2.5 us.
This 'Reset' should not be confused with a micro-controller power-on type reset. It is a USB
protocol reset to ensure that the device USB signaling starts from a known state.
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 Instrumentation II Chapter 3: Serial Interfacing With Microprocessor Based System

EOP signal
The End of Packet (EOP) is an SE0 state for 2 bit times, followed by a J state for 1 bit time.

Suspend
One of the features of USB which is an essential part of today's emphasis of 'green' products is

np
its ability to power down an unused device. It does this by suspending the device, which is
achieved by not sending anything to the device for 3 ms.
Normally a SOF packet (at full speed) or a Keep Alive signal (at low speed) is sent by the host

u.
every 1 ms, and this is what keeps the device awake.
A suspended device may draw no more than 0.5 mA from Vbus.

ed
A suspended device must recognise the resume signal, and also the reset signal.

Resume

.
When the host wants to wake the device up after a suspend, it does so by reversing the polarity of

es
the signal on the data lines for at least 20ms. The signal is completed with a low speed end of
packet signal.

ot
It is also possible for a device with its remote wakeup feature set, to initiate a resume itself. It
must have been in the idle state for at least 5ms, and must apply the wakeup K condition for

en
between 1 and 15 ms. The host takes over the driving of the resume signal within 1 ms.

Keep Alive Signal

io
This is represented by a Low speed EOP. It is sent at least once every millisecond on a low speed
link, in order to keep the device from suspending.
m

Throughput
fro

• Throughput is the actual output of any device, USB’s actual throughput is a function of
many variables:
– Target device’s ability to source or sink data
– Bandwidth consumption by other devices in the bus
d

– Efficiency of host’s USB ports

de

– Types of data
oa
nl
ow
D

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 Instrumentation II Chapter 3: Serial Interfacing With Microprocessor Based System

Speed
A USB device must indicate its speed by pulling either the D+ or D- line high to 3.3 volts. A full
speed device, pictured below will use a pull up resistor attached to D+ to specify itself as a full
speed device. These pull up resistors at the device end will also be used by the host or hub to
detect the presence of a device connected to its port. Without a pull up resistor, USB assumes
there is nothing connected to the bus.

np
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io
m

Figure : Full Speed Device with pull up resistor connected to D+

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d
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oa
nl
ow
D

Figure : Low Speed Device with pull up resistor connected to D-

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 Instrumentation II Chapter 3: Serial Interfacing With Microprocessor Based System

USB Protocols
Unlike RS-232 and similar serial interfaces where the format of data being sent is not defined,
USB is made up of several layers of protocols. While this sounds complicated, don’t give up
now. Once you understand what is going on, you really only have to worry about the higher level
layers. In fact most USB controller I.C.s will take care of the lower layer, thus making it almost
invisible to the end designer.

np
Each USB transaction consists of a
 Token Packet (Header defining what it expects to follow), an
 Optional Data Packet, (Containing the payload) and a

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 Status Packet (Used to acknowledge transactions and to provide a means of error
correction)

ed
As we have already discussed, USB is a host centric bus. The host initiates all transactions. The
first packet, also called a token is generated by the host to describe what is to follow and whether
the data transaction will be a read or write and what the device’s address and designated endpoint

.
is. The next packet is generally a data packet carrying the payload and is followed by an

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handshaking packet, reporting if the data or token was received successfully, or if the endpoint is
stalled or not available to accept data.

ot
Common USB Packet Fields

en
Data on the USB bus is transmitted LSB first. USB packets consist of the following fields,
• Sync: All packets must start with a sync field. The sync field is 8 bits long at low and full
speed or 32 bits long for high speed and is used to synchronize the clock of the receiver
io
with that of the transmitter. The last two bits indicate where the PID fields starts.
• PID: PID stands for Packet ID. This field is used to identify the type of packet that is
being sent.
m

There are 4 bits to the PID, however to insure it is received correctly, the 4 bits are
complemented and repeated, making an 8 bit PID in total. The resulting format is shown below.
fro

PID0 PID1 PID2 PID3 nPID0 nPID1 nPID2 nPID3

• ADDR: The address field specifies which device the packet is designated for. Being 7
d

bits in length allows for 127 devices to be supported. Address 0 is not valid, as any
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device which is not yet assigned an address must respond to packets sent to address zero.
• ENDP: The endpoint field is made up of 4 bits, allowing 16 possible endpoints. Low
speed devices, however can only have 2 additional endpoints on top of the default pipe.
oa

(4 endpoints max)
• CRC: Cyclic Redundancy Checks are performed on the data within the packet payload.
All token packets have a 5 bit CRC while data packets have a 16 bit CRC.
nl

• EOP: End of packet. Signalled by a Single Ended Zero (SE0) for approximately 2 bit
times followed by a J for 1 bit time.
ow

USB Packet Types

USB has four different packet types. Token packets indicate the type of transaction to follow,
D

data packets contain the payload, handshake packets are used for acknowledging data or
reporting errors and start of frame packets indicate the start of a new frame.

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 Instrumentation II Chapter 3: Serial Interfacing With Microprocessor Based System

• Token Packets: There are three types of token packets,

o In - Informs the USB device that the host wishes to read information.
o Out - Informs the USB device that the host wishes to send information.
o Setup - Used to begin control transfers.
Token Packets must conform to the following format,

np
Sync PID ADDR ENDP CRC5 EOP

• Data Packets: There are two types of data packets each capable of transmitting up to

u.
1024 bytes of data.
o Data0

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o Data1
High Speed mode defines another two data PIDs, DATA2 and MDATA.
Data packets have the following format,

.
es
Sync PID Data CRC16 EOP
o Maximum data payload size for low-speed devices is 8 bytes.

ot
o Maximum data payload size for full-speed devices is 1023 bytes.
o Maximum data payload size for high-speed devices is 1024 bytes.

•
o
en
Data must be sent in multiples of bytes.

Status / Handshake Packets: There are three type of handshake packets which consist
io
simply of the PID
o ACK - Acknowledgment that the packet has been successfully received.
o NAK - Reports that the device temporary cannot send or received data. Also used
m

during interrupt transactions to inform the host there is no data to send.

o STALL - The device finds its in a state that it requires intervention from the host.
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Handshake Packets have the following format,

Sync PID EOP
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 Start of Frame Packets

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The SOF packet consisting of an 11-bit frame number is sent by the host every
1ms  500ns on a full speed bus or every 125 µs  0.0625 µs on a high speed bus.
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Sync PID Frame Number CRC5 EOP

nl

Transfer Model
Endpoints
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Endpoints can be described as sources or sinks of data. As the bus is host centric, endpoints
occur at the end of the communications channel at the USB function. At the software layer, your
device driver may send a packet to your devices EP1 for example. As the data is flowing out
from the host, it will end up in the EP1 OUT buffer. Your firmware will then at its leisure read
D

this data. If it wants to return data, the function cannot simply write to the bus as the bus is
controlled by the host. Therefore it writes data to EP1 IN which sits in the buffer until such time
when the host sends a IN packet to that endpoint requesting the data. Endpoints can also be seen
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 Instrumentation II Chapter 3: Serial Interfacing With Microprocessor Based System

as the interface between the hardware of the function device and the firmware running on the
function device.
All devices must support endpoint zero. This is the endpoint which receives all of the devices
control and status requests during enumeration and throughout the duration while the device is
operational on the bus.

np
Pipes
While the device sends and receives data on a series of endpoints, the client software transfers
data through pipes. A pipe is a logical connection between the host and endpoint(s). Pipes will

u.
also have a set of parameters associated with them such as how much bandwidth is allocated to
it, what transfer type (Control, Bulk, Iso or Interrupt) it uses, a direction of data flow and

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maximum packet/buffer sizes. For example the default pipe is a bi-directional pipe made up of
endpoint zero in and endpoint zero out with a control transfer type.
USB defines two types of pipes

.
 Stream Pipes have no defined USB format, that is you can send any type of data down a

es
stream pipe and can retrieve the data out the other end. Data flows sequentially and has a
pre-defined direction, either in or out. Stream pipes will support bulk, isochronous and

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interrupt transfer types. Stream pipes can either be controlled by the host or device.


en
Message Pipes have a defined USB format. They are host controlled, which are initiated
by a request sent from the host. Data is then transferred in the desired direction, dictated
by the request. Therefore message pipes allow data to flow in both directions but will
io
only support control transfers.

Data Flow Types

m

• Control Transfers:
– typically used for short, simple commands to the device, and a status response,
fro

used e.g. by the bus control pipe number 0

• Bulk Data Transfers:
– Large sporadic transfers using all remaining available bandwidth (but with no
guarantees on bandwidth or latency). A device like a printer, which receives data
d

in one big packet, uses the bulk transfer mode. A block of data is sent to the
de

printer (in 64-byte chunks) and verified to make sure it is correct.

• Interrupt Data Transfers:
– Devices that need guaranteed quick responses (bounded latency). A device like a
oa

mouse or a keyboard, which will be sending very little data, would choose the
interrupt mode.
• Isochronous Data Transfers:
nl

– At some guaranteed speed (often but not necessarily as fast as possible) but with
possible data loss A streaming device (such as speakers) uses the isochronous
ow

mode. Data streams between the device and the host in real-time, and there is no
error correction.
D

Devices (Nodes), Hosts and On-The-Go

 The USB is based on a so-called 'tiered star topology' in which there is a single host
controller and up to 127 'slave' devices. The host controller is connected to a hub,

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 Instrumentation II Chapter 3: Serial Interfacing With Microprocessor Based System

integrated within the PC, which allows a number of attachment points (often loosely
referred to as ports). A further hub may be plugged into each of these attachment points,
and so on. However there are limitations on this expansion.
 A device can be plugged into a hub, and that hub can be plugged into another hub and so
on. However the maximum number of tiers permitted is six.
 All devices have an upstream connection to the host and all hosts have a downstream

np
connection to the device.
 The length of any cable is limited to 5 metres. This limitation is expressed in the
specification in terms of cable delays etc, but 5 metres can be taken as the practical

u.
consequence of the specification. This means that a device cannot be further than 30
metres from the PC, and even to achieve that will involve 5 external hubs, of which at

ed
least 2 will need to be self-powered.
 So the USB is intended as a bus for devices near to the PC. For applications requiring

.
distance from the PC, another form of connection is needed, such as Ethernet.

es
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en
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fro

Fig: USB network protocol architecture

d

Hub
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• Hub has two major roles: power management and signal distribution.
• Hubs can be linked, potentially giving you unlimited USB ports to your computer.
• The biggest difference between types of hubs that is important to know when dealing
oa

with USB devices is between un-powered and powered hubs.

Powered Hub
• Needed when connecting multiple unpowered devices such as mice or digital cameras.
nl

• These low-powered devices derive their power source from the bus.
• If too many are connected through a hub, the computer may not be able to handle it.
ow

Un-powered Hub
• Un-powered hubs can be used with any number of high-power devices such as printers
D

and scanners that have their own power supply, thus not requiring power from the bus.
• Safe to use with low-power devices (mice, cameras, joysticks, etc.) as long as too many
aren’t connected as once.
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 Instrumentation II Chapter 3: Serial Interfacing With Microprocessor Based System

USB On The Go (OTG)

USB OTG is a new supplement to the USB 2.0 specification that arguments the capability of
existing mobile devices and USB peripherals by adding host functionality for connection to USB
peripherals. Since USB has traditionally consisted of host-peripheral topology where the PC was
the host and the peripheral was the relatively dump device, following new features were needed
to upgrade USB technology:

np
• A new standard for small form factor USB connectors and cables
• The addition of host capability to products that have traditionally been peripherals only,
to enable point-to-point connection

u.
• The ability to be either host or peripheral (dual role devices) and to dynamically switch
between the two.

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• Lowest power requirements to facilitate USB on battery powered devices.
USB On-The-Go (OTG) allows two USB devices to talk to each other without requiring the
services of a personal computer (PC). Although OTG appears to add peer-to-peer connections to

.
the USB world, it does not. Instead, USB OTG retains the standard USB host/peripheral model,

es
in which a single host talks to USB peripherals. OTG does introduce, however, the dual-role
device, or simply stated a device capable of functioning as either host or peripheral. Part of the

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magic of OTG is that a host and peripheral can exchange roles if necessary.

Interface Chips: USB device and USB host

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m
fro
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D

Fig: Logical view of device host interface

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 Instrumentation II Chapter 3: Serial Interfacing With Microprocessor Based System

• Endpoint is where data enters or leaves the USB system. An IN endpoint is data creator
and OUT endpoint is data consumer. For reliable data delivery scheme, need multiple IN
and OUT endpoints.
• The collection of endpoints is called an interface and is directly related to the real world
connection.
• An operating system will have a driver that corresponds to each interface.

np
• Some devices may have multiple interfaces such as a telephone has a keypad interface
and audio interface. Operating system will manage two separate device drivers.
• A collection of interface is called a configuration, and only one configuration can be

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active at a time.
• A configuration defines the attribute and features of a specific model.

. ed
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Fig: Interface between device and host

d
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Compiled By: Er. Hari Aryal [[email protected]] References: Gaonkar, Hall & Hyde | 28
 Instrumentation II Chapter 4: Interfacing A/D and D/A Converters

CHAPTER 4
INTERFACING A/D AND D/A CONVERTERS

4.1 Introduction
4.2 General terms involved in D/A and A/D converter
4.3 Examples of D/A and A/D Interfacing

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4.4 Selection of A/D and D/A converter based on Design Requirements

4.1 Introduction

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Even though an analog signal may represent a real physical parameter like temperature, pressure
etc, it is difficult to process or store the analog signal for later use without introducing a

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considerable error. Therefore, in microprocessor based industrial products, it is necessary to
translate an analog signal into digital signal. The electronic circuit that translates an analog signal
into digital signal is called ADC (Analog to Digital Converter). Similarly a digital signal needs to

.
be translated into an analog signal to represent a physical quantity; this translator is called DAC

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(Digital to Analog Converter).

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Analog to Digital Converter
The A/D converter is a quantizing process whereby an analog signal is represented by equivalent

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binary states. ADC can be classified into two general groups based on conversion technique.
 One technique involves comparing a given analog signal with the internally generated
equivalent signal. This includes successive approximation, counter and flash type
io
converters.
 Second technique involves a changing an analog signal into time or frequency and
comparing these new parameters to known values. This group includes integrator
m

converters and voltage to frequency converters.

The successive approximation and the flash type are faster but generally less accurate than
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integrator and voltage to frequency converters. The flash type is expensive and difficult to design
for high accuracy.

Fig. 4.1.a shows a block diagram of a 3-bit A/D converter, it has one input line for an analog
d

signal and three output lines for digital signals. Fig. 4.1.b shows the graph of the analog input
de

voltage (0-1 V) and the corresponding digital output signal. It shows 8 (23) discrete output states
from 000 to 111 each state being 1/8V apart. This is defined as the resolution of the converter.
oa

D0
nl

A/D
Analog D1
Input Converter
ow

D2

(a)
D

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 Instrumentation II Chapter 4: Interfacing A/D and D/A Converters

np
u.
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Fig. 4.1: a) A 3-bit ADC block diagram en
(b)
b) Analog input versus digital output
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Parameters (Characteristics) of ADC
 Resolution
m

In ADC, the original analog signal has essentially an infinite resolution as the signal is
continuous. The digital representation of this signal would of course reduce this
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resolution as digital quantities are discrete and vary in equal steps. The resolution of an
ADC is smallest change that can be distinguished in the analog input.
Resolution = FSR (Full Scale Range) / 2n
 Conversion Time
d

The A/D conversion another critical parameter is conversion time. This is defined as the
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total time required converting an analog signal into its digital output.
 Accuracy
It is the comparison of the actual output and the expected output.
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 Linearity
The output should be the linear function of input.
 Full scale output value
nl

The maximum bit output achieved from the respective input.

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Types of ADC
1. Successive Approximation A/D Converter
It is one of the most used ADC.
D

Conversion time is faster than Dual slope but slower than Flash.
It has fixed conversion time for any value of analog input.

Compiled By: Er. Hari Aryal [[email protected]] References: R. Gaonkar & D.V. Hall | 2
 Instrumentation II Chapter 4: Interfacing A/D and D/A Converters

Successive approximation register generates a series of bit and DAC convert it into analog value
which is compared with output. For 4-bit ADC, 1000 is generated and the analog value of 1000
is compared with the output. If it is greater, 1 is flipped to 0 otherwise retained. Then in next
clock cycle the second bit is changed to 1 and the whole cycle continues till every bit is flipped
and checked.
Comparator

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VIN +
Analog Input Start
Control Status

u.
_ Data
Ready

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CLK

VO Successive

.
4-Bit D/A
Approximation

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Converter
Register

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Analog Output
Reference Register

en
D3 D2 D1 D0
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Fig. 4.2: Block diagram of successive approximation A/D converter
It includes three major elements: the A/D converter, the successive approximation register (SAR)
and the comparator. The conversion technique involves comparing the output of the D/A
m

converter VO with the analog input signal Vin. When the DAC output matches the analog signal,
the input to the DAC is the equivalent digital signal. In the case of a 4-bit A/D converter, bit D3
fro

is turned on first and the output of the DAC is compared with an analog signal. If the comparator
changes the state, indicating that the output generated by D3 is larger than the analog signal, bit
D3 is turned off in the SAR and bit D2 is turned on. The process continues until the input reaches
bit D0.
d
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2. The Counter type ADC

The analog input is the V+ input to the comparator. As long as it is greater than V- input, the
AND gate is enabled and clock pulses are passed to the counter. The digital output of the counter
oa

is converted to an analog voltage by the DAC and that voltage is the other input to the
comparator. Thus the counter counts up until its output has a value equal to the analog input. At
that time, comparator switches low inhibiting the clock pulses and counting ceases. The count it
nl

reached is the digital output proportionate to the analog input. Control circuitry shown in fig 4.3
is used to latch the output and reset the counter. This scheme uses long time for conversion.
ow
D

Compiled By: Er. Hari Aryal [[email protected]] References: R. Gaonkar & D.V. Hall | 3
 Instrumentation II Chapter 4: Interfacing A/D and D/A Converters

Comparator

V+ + AND Gate
Analog Input
8-Bit Counter
V- _ Q7Q6Q5Q4Q3Q2Q1Q0

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Digital
Clock

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Output
DAC Output

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D7D6D5D4D3D2D1D0

.
Fig. 4.3: Block diagram of an 8-bit counter type ADC

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3. Parallel Comparator ADC (Flash Type ADC)
 The Flash Type ADC (Simultaneous ADC) is the fastest ADC that utilizes comparators

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that compares reference voltage with input analog voltage.
 A priority encoder is used to convert the output of comparator into digital output.
en
 For n-bit ADC 2n-1 comparators are required, so this is very expensive.
 It’s conversion time is less and can even digitize video signal.
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VRef = 4V
10 Ω
m

+ A3
_
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3V
10 Ω D1
Analog Input
VIN + A2 Priority Binary Code
d

_ Encoder Output
2V
10 Ω
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D0
+ A1
_
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1V
10 Ω
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Fig. 4.4: Parallel Comparator ADC

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Advantages: Very Fast, Clocks not required. Disadvantages: Expensive, Consume high power,
Complexity doubles for each additional bit.
D

Fig. 4.4 shows a circuit for 2-bit ADC using parallel comparators. A voltage divider sets
reference voltage on the inverting input’s of each of the comparator. The voltage at the top of the
divider chain represents the full scale value for the converter. The voltage to be converted is

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 Instrumentation II Chapter 4: Interfacing A/D and D/A Converters

applied to the non-inverting inputs of all the comparators in parallel. If the input voltage on a
comparator is greater than the reference voltage on the inverting input, the output of the
comparator will go high. The outputs of the comparators then give us a digital representation of
the voltage level of the input signal.
VIN A3 A2 A1 D1 D2
0 ≤ VIN ≤ 1 0 0 0 0 0

np
1 ≤ VIN ≤ 2 0 0 1 0 1
2 ≤ VIN ≤ 3 0 1 1 1 0
3 ≤ VIN ≤ 4 1 1 1 1 1

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For an example, with an input voltage of 2.6 V, the output of comparators A1 and A2 will be
high. A priority encoder produces a binary output corresponding to the input having the highest

ed
priority. In this case, the one representing the largest voltage level equal to or less than analog
input. Thus, the binary output closely represents the analog input voltage. Although it is
expensive, the conversion time is fast.

.
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4. Ramp ADC / Dual slope ramp ADC
Conversion from analog to digital form inherently involves comparator action where the value of

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the analog voltage at some point in time is compared with some standard. A common way to do
that is to apply the analog voltage to one terminal of a comparator and trigger a binary

en
counter which drives a DAC. The output of the DAC is applied to the other terminal of the
comparator. Since the output of the DAC is increasing with the counter, it will trigger the
comparator at some point when its voltage exceeds the analog input. The transition of the
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comparator stops the binary counter, which at that point holds the digital value corresponding to
the analog voltage. This has the advantage that a slow comparator cannot be disturbed by fast
input changes.
m
fro
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Fig. 4.5 (a): Ramp ADC

Dual Slope ADC is used in the Digital Voltmeter and other type of measuring instruments
because of its large resolution and low cost.
D

A ramp generator (integrator) is used to produce the dual slope characteristics.

Compiled By: Er. Hari Aryal [[email protected]] References: R. Gaonkar & D.V. Hall | 5
 Instrumentation II Chapter 4: Interfacing A/D and D/A Converters

np
u.
ed
Fig. 4.5 (b): Dual Slope Ramp ADC
Operation:

.
 First of all capacitor is reset (i.e. Vo is made zero)

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 For positive Vin we need negative Vref.
 During time T1, the capacitor is charged by the Vin for fixed time interval which is

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controlled by the control unit with a fixed current ( I = Va/R ).
 After time T1, the control unit switches the connection from Vin to –Vref through which

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the capacitor is discharged. This discharge through the fixed slope until it
 becomes zero which is sensed by the comparator. The reading of the counter is the output
for the input.
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m
fro
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5. Integrator ADC
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nl
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Fig. 4.6: Integrator ADC

The basic integrating ADC circuit consists of the op-amp integrator and a switch to select
between the voltage to be measured and the reference voltage. Depending on the
D

implementation, a switch may also be present in parallel with the integrator capacitor to allow
the integrator to be reset (by discharging the integrator capacitor). The switches will be
controlled electrically by means of the converter's controller (a microprocessor or dedicated
Compiled By: Er. Hari Aryal [[email protected]] References: R. Gaonkar & D.V. Hall | 6
 Instrumentation II Chapter 4: Interfacing A/D and D/A Converters

control logic). Inputs to the controller include a clock (used to measure time) and the output of a
comparator used to detect when the integrator's output reaches zero.
The conversion takes place in two phases: the run-up phase, where the input to the integrator is
the voltage to be measured, and the run-down phase, where the input to the integrator is a known
reference voltage. During the run-up phase, the switch selects the measured voltage as the input
to the integrator. The integrator is allowed to ramp for a fixed period of time to allow a charge to

np
build on the integrator capacitor. During the run-down phase, the switch selects the reference
voltage as the input to the integrator. The time that it takes for the integrator's output to return to
zero is measured during this phase.

u.
Q. Calculate the maximum conversion time of a successive approximation ADC and an 8-bit

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staircase ramp ADC, if the clock rate is 2MHz.
For a 8-bit successive approximation ADC, the conversion time is constant and equal to
n 8
Tc    4 106 s  4s

.
f 2 106

es
For a 8-bit staircase ramp ADC, the maximum number of count is
nc = 28 = 256

ot
Therefore, the maximum conversion time is
n 256
Tc  c   128 106 s  128s
f 2 10 6

en
It can be noted that the conversion speed of successive approximation ADC is much
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faster than the staircase ramp type.

Interfacing an 8-Bit ADC using Status Check

m
fro
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Fig: Interfacing an ADC using Status Check

D

Compiled By: Er. Hari Aryal [[email protected]] References: R. Gaonkar & D.V. Hall | 7
 Instrumentation II Chapter 4: Interfacing A/D and D/A Converters

 Above figure shows a schematic of interfacing a typical ADC using status check.
 ADC has one input line for analog signal and eight output lines for converted digital
signals.
 Typically, analog signal can range from 0 to 10V or ±5V.
 When an active low pulse is sent to the START pin, the DR goes high and the output
lines go into high impedance state.

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 The START pulse initiates conversion.
 When the conversion is complete, the DR goes low and data are made available on the

u.
output lines that can be read by the microprocessor.
 To interface A/D converter, we need one output port to and a START pulse and two

ed
input ports one to check the status of DR line and the other to read the output of the
converter.
 The subroutine instructions to initiate the conversion and to read output data, and the

.
es
flowchart are shown below.

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OUT 82H; Start conversion

Test: en
IN 80H; Read data ready status
RAR; Rotate D0 into carry
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JC TEST; If D0=1, conversion is not yet complete,

; go back and check
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IN 81 H; read output and save it in accumulator

RET
d
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Fig: Flowchart of ADC Process

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Compiled By: Er. Hari Aryal [[email protected]] References: R. Gaonkar & D.V. Hall | 8
 Instrumentation II Chapter 4: Interfacing A/D and D/A Converters

Interfacing an 8-Bit ADC using Interrupt

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Fig: Interfacing ADC 0801 using Interrupt
 In ADC interfacing using status check, we need external ports to access data and monitor
m

the data ready signal. In this configuration using Interrupt, the necessary logic is built
inside the chip.
 The converter requires a clock at CLK IN; the frequency range can be from 100 KHZ to
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800 KHZ.
 The user has two options; either to connect an external clock at CLK IN or to use the
built in internal clock by connecting a register and a capacitor externally at pins 19 & 4
d

respectively.
 The frequency is calculated by using the formula F = 1 / 1.1 RC.
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 The ADC0801 is designed to be microprocessor compatible. It has three control

signals: CS , WR and RD that are used for interfacing. To start conversion, the CS and
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WR signals are asserted low.

 When WR goes low, the internal SAR is reset and the output lines go into the high
nl

impedance state. When WR makes transition from low to high, the conversion begins.
 When the conversion is completed, the INTR is asserted low and the data are placed on
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the output lines. INTR signal can be used to interrupt the processor.
 When the processor reads the data by asserting RD , the INTR is set.
 When Vcc is +5V, the input voltage can range from 0V to 5V and the corresponding
D

output will be from 00H to FFH.

Compiled By: Er. Hari Aryal [[email protected]] References: R. Gaonkar & D.V. Hall | 9
 Instrumentation II Chapter 4: Interfacing A/D and D/A Converters

 However, the full-scale output can be restricted to the lower range of inputs by using pin
9 (Vref/2). For example, if we connect a 0.5V DC source at pin 9, we can obtain full
scale output FFH for a 1V input signal.

np
u.
. ed
es
Fig: Timing diagram for Reading Data from ADC

ot
Service Routine:
LDA 8000H; Read data
MOV M, A ; store data in memory
INX H;
DCR B;
Next memory location
Next count
en
io
STA 8000H; start next conversion
EI; Enable interrupt again
RNZ; Go back to main if counter not equal to zero
m

HLT
fro

Sample and Hold Circuit:

A Sample and Hold circuit is used before analog signal is fed to ADC, so that the value of analog
input can be kept constant and conversion can be done with constant value. Start/ EOC signals
are used for interfacing.
d

The result of sampling process is identical to multiplying the analog signal by a train of pulses of
de

unit magnitude. Sample and hold circuit is used when it is necessary to hold the sampled value of
input signal for specified period of time. Sample and hold circuit is used in order to avoid the use
of very fast and expensive A/D converters.
oa
nl
ow
D

Fig.: Sample and Hold Circuit

Compiled By: Er. Hari Aryal [[email protected]] References: R. Gaonkar & D.V. Hall | 10
 Instrumentation II Chapter 4: Interfacing A/D and D/A Converters

 When the conversion is needed the switch is opened, isolating the capacitor from the
input
 The capacitor will hold the voltage when switch is opened
 The capacitor will not discharge due to the high impedance of the voltage follower

Quantization

np
It is the process of converting an input function having continuous values to an output having
only discrete values.

u.
Binary Coding
It is the method of assigning a binary equivalent number to each discrete level.

. ed
es
ot
en
io
m
fro

Sampling Rate:
The Analog Signal is continuous in time and it is necessary to convert this to a flow of digital
values. It is therefore required to define the rate at which new digital values are sampled from the
d

analog signal. The rate of new values is called the Sampling Rate or Sampling Frequency of the
de

converter. A continuously varying band limited signal can be sampled and then the original
signal can be exactly reproduced from the discrete-time values by an interpolation formula. The
accuracy is limited by quantization error. However, this faithful reproduction is only possible if
oa

the sampling rate is higher than twice the highest frequency of the signal. This is essentially what
is embodied in the Shannon-Nyquist Sampling Theorem.
nl

Since a practical ADC cannot make an instantaneous conversion, the input value must
necessarily be held constant during the time that the converter performs a conversion (called the
ow

Conversion Time). An input circuit called a Sample and Hold performs this task in most cases by
using a capacitor to store the analog voltage at the input, and using an electronic switch or gate to
disconnect the capacitor from the input. Many ADC integrated circuits include the sample and
D

hold subsystem internally.

Compiled By: Er. Hari Aryal [[email protected]] References: R. Gaonkar & D.V. Hall | 11
 Instrumentation II Chapter 4: Interfacing A/D and D/A Converters

Aliasing:
If the digital values produced by the ADC are converted back to analog values by a DAC, it is
desirable that the output of the DAC be an exact replica of the original signal. If the input signal
is changing much faster than the sample rate, then this will not be the case, and spurious signals
(false) called aliases will be produced at the output of the DAC. For example, a 2 kHz sine wave
being sampled at 1.5 kHz would be reconstructed as a 500 Hz sine wave. This problem is called

np
aliasing. To avoid aliasing, the input to an ADC must be low-pass filtered to remove frequencies
above half the sampling rate. This filter is called an Anti-aliasing Filter, and is essential for a
practical ADC system that is applied to analog signals with higher frequency content.

u.
Dither:

ed
In ADC, performance can usually be improved using dither. This is a very small amount of
random noise (white noise), which is added to the input before conversion. The result is an
accurate representation of the signal over time. A suitable filter at the output of the system can

.
thus recover this small signal variation. An audio signal of very low level (with respect to the bit

es
depth of the ADC) sampled without dither sounds extremely distorted and unpleasant. Without
dither the low level may cause the least significant bit to "stick" at 0 or 1. With dithering, the true

ot
level of the audio may be calculated by averaging the actual quantized sample with a series of
other samples (the dither) that are recorded over time.

Sampling Theorem (Nyquist sampling theorem) en

The theorem is commonly called the Nyquist sampling theorem, is a fundamental result in the
io
field of information theory, in particular telecommunications and signal processing. Sampling is
the process of converting a signal (for example, a function of continuous time or space) into a
discrete sequence (a function of discrete time or space). Sampling theorem states: If a
m

function x(t) contains no frequencies higher than B hertz, it is completely determined by giving
its ordinates at a series of points spaced 1/(2B) seconds apart.
fro

In other way; a continuous time signal may be completely represented in its samples and
recovered back if the sampling frequency fs ≥ 2fm. Here, fs is the sampling frequency and fm is
the maximum frequency present in the signal.
d
de

A signal or function is band limited if it contains no energy at frequencies higher than some band
limit or bandwidth B. A signal that is band limited is constrained in how rapidly it changes in
time, and therefore how much detail it can convey in an interval of time. The sampling theorem
oa

asserts that the uniformly spaced discrete samples are a complete representation of the signal if
this bandwidth is less than half the sampling rate. To formalize these concepts, let x(t) represent
a continuous-time signal and X(f) be the continuous Fourier transform of that signal:
nl
ow

The signal x(t) is said to be band limited to a one-sided baseband bandwidth, B, if:
for all
D

or, equivalently, supp(X)[2] [−B, B]. Then the sufficient condition for exact
reconstructability from samples at a uniform sampling rate fs(in samples per unit time) is:

Compiled By: Er. Hari Aryal [[email protected]] References: R. Gaonkar & D.V. Hall | 12
 Instrumentation II Chapter 4: Interfacing A/D and D/A Converters

or equivalently:

2B is called the Nyquist rate and is a property of the band limited signal, while fs / 2 is
called the Nyquist frequency and is a property of this sampling system.

np
The time interval between successive samples is referred to as the sampling interval:

u.
and the samples of x(t) are denoted by:

ed
(integers).

The sampling theorem leads to a procedure for reconstructing the original x(t) from the samples

.
and states sufficient conditions for such a reconstruction to be exact.

es
What happens if we sample the signal at a frequency that is lower that the Nyquist rate? When

ot
the signal is converted back into a continuous time signal, it will exhibit a phenomenon
called aliasing. Aliasing is the presence of unwanted components in the reconstructed signal.

en
These components were not present when the original signal was sampled. In addition, some of
the frequencies in the original signal may be lost in the reconstructed signal. Aliasing occurs
because signal frequencies can overlap if the sampling frequency is too low. Frequencies "fold"
io
around half the sampling frequency - which is why this frequency is often referred to as the
folding frequency.
m

Sometimes the highest frequency components of a signal are simply noise, or do not contain
useful information. To prevent aliasing of these frequencies, we can filter out these components
fro

before sampling the signal. Because we are filtering out high frequency components and letting
lower frequency components through, this is known as low-pass filtering.
d
de
oa
nl
ow
D

Compiled By: Er. Hari Aryal [[email protected]] References: R. Gaonkar & D.V. Hall | 13
 Instrumentation II Chapter 4: Interfacing A/D and D/A Converters

Digital-to-Analog Converter (DAC)

DAC converts straight binary to analog voltage or current proportional to the digital value. DAC
can be broadly classified in three categories: Current Output, Voltage Output and Multiplying
Type.
Voltage output DAC is comparatively slower than Current output DAC because of the delay in
converting the current signal into voltage signal.

np
MSB

u.
Digital D2 D/A Analog
Input D1 Converter Output

ed
D0
LSB

.
es
(a)

FS

ot
A 7/8
n
a 3/4
l
en
io
o 5/8
g LSB
m

1/2
O
fro

u 3/8
t
p 1/4
u
d

t 1/8
de

000 001 010 011 100 101 110 111

oa

Digital Input
nl

Fig. : A 3-bit D/A converter


ow

The three input lines D2, D1 and D0 can assume 8 input combinations from 000 to 111.
 If the full scale analog voltage is 1V, the smallest unit or the LSB (Least Significat Bit)
0012 is equivalent to 1/2n of 1V. This is defined as resolution. Here, LSB (001)2 = 1/8 V.
 The MSB (Most Significat Bit) represents half of the full scale value. Here, MSB (100)2
D

= 1/2 V.

Compiled By: Er. Hari Aryal [[email protected]] References: R. Gaonkar & D.V. Hall | 14
 Instrumentation II Chapter 4: Interfacing A/D and D/A Converters

 For the maximum input signal (111)2, the output signal is equal to the value of the full
scale input signal minus the value of 1 LSB input signal. Here, maximum input signal
(111)2 represents (1 – 1 / 8) = 7 / 8 V.

Parameters (Characteristics) of DAC

 Resolution

np
It is determined by the number of bits in the input binary word. A 12-bit converter has a
resolution of 1 part in 212.

u.
 Full scale output voltage
The maximum output voltage of a converter (when all input are 1) will always have a

ed
value 1 LSB less than the named value.

 Accuracy

.
es
The actual output voltage of a DAC is different from the ideal value; the factors that
contribute to the lack of linearity also contribute to the lack of accuracy. The accuracy of
a DAC is the measure of difference between actual output voltage and the expected

ot
output voltage. For an example, a DAC with ±0.2% accuracy and full scale (maximum)
output voltage of 10V will produce a maximum error for an output voltage is of 20 mV.


[0.2/100 * 10V = 0.002*10 V = 20mV]

Linearity
en
io
An ideal DAC should be linear i.e. the output voltage should be a linear function of the
input code. All DAC depart somewhat from the ideal linearity. Typical factors
responsible for introducing non-linearity are non-exact value of resistors and non-ideal
m

electronic switches that introduce extra resistance to the circuit. The non-linearity
(linearity error) is the amount by which the actual output differs from the ideal straight
fro

line output.

 Settling time
d

When the output of DAC changes from one value to another, it typically overshoots the
new value and may oscillate briefly around that new value before it settles to a constant
de

value. It is the time interval between the instant when the analog input passes a specified
value and the time instant when the analog output enters for the last time a specified error
band about its final value.
oa

 Monotonicity
nl

A converter is said to be monotonic if its output voltage value continuous to increase with
a continuously increasing input value.
ow

 Temperature Coefficient
It is defined as the degree of inaccuracy that the temperature change can cause in any of
the parameter of the DAC.
D

Compiled By: Er. Hari Aryal [[email protected]] References: R. Gaonkar & D.V. Hall | 15
 Instrumentation II Chapter 4: Interfacing A/D and D/A Converters

Types of DAC:

1) DAC with Binary Weighted Resistor Network (WRN):

np
u.
. ed
es
Fig: DAC with Binary Weighted Resistor Network

ot
WRN DAC circuit consists of
 Reference voltage VRef
 N Binary weighted resistors R, 2R, 4R,…. 2N-1R
en
 Single Pole Double Throw (SPDT) Switches S0, S1, S2…. SN-1
 Op Amp with feedback resistance RF=R/2
io
Switches controlled N-bit digital input word
m
fro
d
de
oa

Accuracy of Binary Weighted DAC depends critically on

 Accuracy of VRef
nl

 Precision of Binary weighted resistors

 Perfection of switches
ow

Drawbacks of Binary Weighted DAC:

Large spread between smallest and largest resistance for higher no. of bits
D

Precise resistor values not available

Impractical for large number of bits.

Compiled By: Er. Hari Aryal [[email protected]] References: R. Gaonkar & D.V. Hall | 16
 Instrumentation II Chapter 4: Interfacing A/D and D/A Converters

2) R-2R Ladder Network

It uses only two resistor values R and 2R. Hence, its implementation in IC form is much easier
than the weighted resistor converted.

np
u.
. ed
es
ot
Fig: R-2R Ladder (Voltage Mode)
en
io
m
fro
d
de
oa
nl
ow
D

Compiled By: Er. Hari Aryal [[email protected]] References: R. Gaonkar & D.V. Hall | 17
 Instrumentation II Chapter 4: Interfacing A/D and D/A Converters

Interfacing 8-Bit DAC with 8085

Q. Design an output port with address FFH to interface the 1408 DAC that is calibrated for 0 to
10 V range.

np
u.
. ed
es
ot
Fig: Interfacing 1408 DAC in Unipolar Range en
io
This includes an 8-input NAND gate and a NOR gate as the address decoding logic, the
74LS373 as a latch, and a 1408 DAC. Address lines (A7-A0) are decoded using the 8-input
m

NAND gate and its output is combined with the control signal IOW . When the microprocessor
sends the address FFH, the output of the negative AND gate enables the latch, and the data bits
fro

are placed on the input lines of the converter for conversion.

The total reference current source is determined by the resistor R14 and the voltage VRef. The
resistor R15 is generally equal to R14 to match the input impedance of the reference source. The
output IO is calculated as:
d
de

IO = VRef/R14 (A1/2 + A2/4 + A3/8 + A4/16 + A5/32 + A6/64 + A7/128 + A8/256)

For full scale input,

oa

IO = 5V/2.5K (1/2 + ¼ + 1/8 + 1/16 + 1/32 + 1/64 + 1/128 + 1/256)

= 2mA (255/256)
= 1.992mA
nl

Output voltage,
ow

VO = IO * RF
= 2mA (255/256) * 5K
= 9.961V
D

Compiled By: Er. Hari Aryal [[email protected]] References: R. Gaonkar & D.V. Hall | 18
 Instrumentation II Chapter 4: Interfacing A/D and D/A Converters

np
u.
ed
This program outputs 00 to FF continuously to the DAC. Analog output of DAC starts at 0 and
increases approximately up to 10V as ramp. Slope of the ramp can be varied by changing the

.
delay.

es
Q. Explain the operation of the 1408 which is calibrated for a bipolar range ±5V. Calculate

ot
output voltage VO if the input is 100000002.

en
io
m
fro
d
de
oa

Fig: Interfacing 1408 DAC in Bipolar Range

The 1408 is calibrated for the bipolar range from -5V to +5V by adding the resistor RB (5.0K)
nl

between the reference voltage VRef and the output pin 4. RB supplies 1mA (VRef/RB) current to
the output in the opposite direction of the current generated by input signal.
ow

Here, IO’ = IO – VRef/RB

When input signal is zero,
VO = IO’ RF
D

= (IO – VRef/RB) RF
= (0 – 5V/5K) 5K
= -5V

Compiled By: Er. Hari Aryal [[email protected]] References: R. Gaonkar & D.V. Hall | 19
 Instrumentation II Chapter 4: Interfacing A/D and D/A Converters

When the input = 1000 0000, output VO is

VO = IO’ RF
= (IO – VRef/RB) RF
= (VRef/R14 * A1/2 - VRef/RB) RF [A8-A2 = 0]
= (5V/2.5K * 1/2 – 5V/5K) 5K
= (1mA-1mA) 5K

np
= 0V
Microprocessor Compatible DAC
In response to the growing need for interfacing DAC with the microprocessor, specially designed

u.
microprocessor-compatible DAC are available. These DAC generally include a latch on the chip,
thus eliminating the need for an external latch.

. ed
es
ot
en
io
m
fro

Fig: Block Diagram of Analog Device along with latch and output Op-Amp internal to the Chip
d

To interface a device with the microprocessor, two signals are required: Chip Select ( CS ) and
Chip Enable ( CE ). In the figure shown above, the address line A7 through inverter is used for
de

Chip Select, which assigns port address 80H (assuming all other address lines 0) to the DAC
port.
oa
nl
ow
D

Fig: Timing Diagram: Control Signals and Data Transfer

Compiled By: Er. Hari Aryal [[email protected]] References: R. Gaonkar & D.V. Hall | 20
 Instrumentation II Chapter 4: Interfacing A/D and D/A Converters

Figure above shows the timing of latching data in relation to the control signals. When both
signals CS and CE are at logic 0, the latch is transparent, meaning the input is transferred to the
DAC. When either CS or CE goes logic 1, input is latched in the register and held until both
control signals go to logic 0.

Interfacing 10-Bit DAC with 8085

np
In many DAC applications, 10 or 12-bit resolution is required. But microprocessor has only 8-bit
data lines. One method is to use two output ports on time shared basis; one for first eight bits and

u.
second for the remaining bits. A disadvantage of this method is that the DAC input assumes on
intermediate value between two input operations. The solution to this difficulty can be using a
double buffer DAC.

. ed
es
ot
en
io
m
fro
d
de
oa

Fig: Interfacing 10-Bit DAC with 8085

 AD7522 is a CMOS 10-bit DAC consists of an input buffer and a holding register. 10 bits
nl

are loaded into the input register in two steps using two output ports.
 The low-order 8-bits are loaded with the control line LBS and remaining 2-bits are loaded
ow

with the control line HBS. Then all 10-bits are switched into a holding register for
conversion by enabling LDAC line.
 When a data byte is sent to the port address 8000H in a memory map I/O, the WR and
D

IO/ M signals go low along with A0 and the line LBS is enabled. Similarly, the address
8001H enables lines HBS and LDAC.

Compiled By: Er. Hari Aryal [[email protected]] References: R. Gaonkar & D.V. Hall | 21
 Instrumentation II Chapter 4: Interfacing A/D and D/A Converters

np
u.
ed
Fig: Timing Diagram
 The following instructions illustrate how to load the maximum input of 10-bits all 1’s
into the DAC.

.
es
LXI B, 03FFH; Load 10-bit at logic 1 in BC register
LXI H, 8000H; Load HL with port address for lower 8-bits
MOV M, C; Load 8-bits D7-D0 in the DAC

ot
INX H; Point to port address 8001H
MOV M, B; Load two bits D9 and D8 and switch all ten bits for conversion
HLT

Interfacing 12-bit DAC to 8-bit Data Bus

en
io
m
fro
d
de
oa
nl
ow

Fig: Interfacing 12-bit DAC to 8-bit Data Bus

D

Compiled By: Er. Hari Aryal [[email protected]] References: R. Gaonkar & D.V. Hall | 22
 Instrumentation II Chapter 4: Interfacing A/D and D/A Converters

Selection of DAC or ADC (Design Requirements)

• Resolution
• Linearity
• DAC: Settling Time
• ADC: Conversion Time
• Accuracy

np
• Codes Used
• Cost

u.
Errors in ADC and DAC
1. Dynamic Errors

ed
A. Conversion Time
It is the elapsed time between the command to perform a conversion and the appearance at
the converter output of the complete digital representation of the analog input value.

.
es
B. Delay Time
It is the time interval between the instant when the digital input changes and the instant when

ot
the analog output passes a specified value that is close to its initial value.

C. Settling Time
en
When the output of DAC changes from one value to another, it typically overshoots the new
value and may oscillate briefly around that new value before it settles to a constant value. It
io
is the time interval between the instant when the analog output passes a specified value and
the instant when the analog output enters for a last time a specified error band about its final
value.
m
fro

A
n
a
d

l Error band (± ½ LSB)

o
de

O
oa

u
t
p
nl

u
t
ow

Digital Input
Settling Time (TS)
Time that digital Time of last entry
D

input changes into error band

Fig: Settling Time

Compiled By: Er. Hari Aryal [[email protected]] References: R. Gaonkar & D.V. Hall | 23
 Instrumentation II Chapter 4: Interfacing A/D and D/A Converters

2. Static Errors
A. Differential Linearity
It is a measure of the separation between adjacent levels. Differential linearity measures the
bit-to-bit deviations from ideal output steps rather than entire output range. If VS is the ideal
change and VCX is the actual change, then the differential linearity can be expressed as:
[(VCX-VS)/VS]*100%

np
Actual Output
FS Ideal Output

u.
A 7/8
n
a 3/4

ed
l
o 5/8
g
1/2

.
O

es
u 3/8
t
p 1/4

ot
u
t 1/8

000 001 010 011 100

Digital Input
101 110
en
111
io
Fig: Differential Linearity Error
m

B. Monotonicity
In a D/A converter; means that as the digital input to the converter increases over its full scale
fro

range, the analog output never exhibit a decrease between one conversion step and next.
A FS Ideal Output
n
a 7/8
d

l Actual Output
de

o
3/4
g
5/8
O
oa

u 1/2
t
p 3/8
u
nl

t
1/4
ow

1/8

000 001 010 011 100 101 110 111

D

Digital Input
Point of Non-Monotonic Output

Fig: Non-Monotonic transfer function

Compiled By: Er. Hari Aryal [[email protected]] References: R. Gaonkar & D.V. Hall | 24
 Instrumentation II Chapter 4: Interfacing A/D and D/A Converters

C. Integral Linearity
It is the maximum deviation of the output of a D/A for any given input code from a straight line
drawn from its ideal minimum to its ideal maximum.
A FS
n Actual Output

np
a 7/8
l
o Expected Output
3/4

u.
g Integral
Linearity Error
5/8

ed
O
u 1/2
t

.
es
p 3/8
u
t
1/4

ot
1/8
en
io
000 001 010 011 100 101 110 111
Digital Input
m

Fig: Integral Linearity error

fro

I. Absolute Linearity
It is measured by assuming that the output of a D/A will begin at zero and end at full scale.
The actual outputs are compared with a line drawn through these two points.
a. Zero Error
d

It is the difference between the actual output and zero when the digital word for a zero
de

output is applied.
b. Full Scale Error
It is the difference between the actual and the ideal voltage when the digital word for a
oa

full scale output is applied.

i. Gain Error (Scale Factor Non-Linearity)
It is the difference between the gains of the actual static and ideal input output
nl

characteristics.
ow
D

Compiled By: Er. Hari Aryal [[email protected]] References: R. Gaonkar & D.V. Hall | 25
 Instrumentation II Chapter 4: Interfacing A/D and D/A Converters

A FS Expected Output
n
a 7/8
l Actual Output
o
3/4
g

np
5/8
O
u 1/2
t

u.
p 3/8
u
t

ed
1/4

1/8

.
es
000 001 010 011 100 101 110 111
Digital Input

ot
Fig: Gain error

ii. Offset Error

en
Offset error adds a constant value to output.
io
Actual Output
A FS Ideal Output
n
m

a 7/8
l
fro

o
3/4
g
5/8
O
d

u 1/2
t
de

p 3/8
u
t
oa

1/4

1/8
nl

Offset Error
000 001 010 011 100 101 110 111
ow

Digital Input
D

Fig: Offset error

Compiled By: Er. Hari Aryal [[email protected]] References: R. Gaonkar & D.V. Hall | 26
 Instrumentation II Chapter 4: Interfacing A/D and D/A Converters

II. Best Straight Line Linearity

It depicts the accuracy of a D/A in terms of the deviation from the ideal output range without
regard to zero or full scale errors.

np
n
a
l u t } Gain Error

u.
o Outp
d
g
ju ste

ed
Ad ut
utp
O a lO
u Ide

.
es
t
p
u

ot
t

Offset Error
en
Digital Input
io
Fig: Best straight line error
III. End Point Linearity
m

It uses a straight line through the actual end points instead of the ideal points.
fro

A
n
a
d

l
ut
o utp
de

g lO
tua
Ac
oa

O
u
t
nl

p
u
ow

t
D

Digital Input

Fig.: End Point Linearity Error

Compiled By: Er. Hari Aryal [[email protected]] References: R. Gaonkar & D.V. Hall | 27
 Instrumentation II Chapter 4: Interfacing A/D and D/A Converters

Errors in D/A and A/D Converters

Static Dynamic

np
Integral Best Straight Differential Linearity: is Conversion Time: is

u.
Linearity: is Line Linearity: a measure of the the elapsed time
the maximum depicts the separation between between the command

ed
deviation of accuracy of a D/A adjacent levels. to perform a
the output of a in terms of the Differential linearity conversion and the
D/A for any deviation from the measures the bit-to-bit appearance at the

.
es
given input ideal output range deviations from ideal converter output of the
code from a without regard to output steps rather than complete digital
straight line zero or full scale entire output range. If VS representation of the

ot
drawn from its errors. is the ideal change and analog input value.
ideal minimum
to its ideal
maximum.
End Point
Linearity: uses a
straight line
en
VCX is the actual change,
then the differential
linearity can be expressed Delay Time: is the
io
through the actual as: [(VCX-VS)/VS]*100% time interval between
end points instead the instant when the
m

of the ideal points. digital input changes

Monotonicity: in a D/A and the instant when
fro

converter; means that as the analog output

Zero Error: is the the digital input to the passes a specified
difference between converter increases over value that is close to
Absolute
d

the actual output its full scale range, the its initial value.
Linearity: is
analog output never
de

measured by and zero when the

digital word for a exhibit a decrease
assuming that Settling Time: it is
zero output is between one conversion
the output of a the time interval
oa

applied. step and next.

D/A will begin between the instant
at zero and end Full Scale Error: when the analog
Gain Error: is the
nl

at full scale. is the difference output passes a

difference between the
The actual between the actual specified value and
ow

gains of the actual static

outputs are and the ideal the time instant when
and ideal input output
compared with voltage when the the analog output
characteristics.
a line drawn digital word for a enters for the last time
D

through these full scale output is Offset Error: it adds a a specified error band
two points. applied. constant value to output. about its final value.

Compiled By: Er. Hari Aryal [[email protected]] References: R. Gaonkar & D.V. Hall | 28
 Instrumentation II Chapter 4: Interfacing A/D and D/A Converters

Designing the embedded system with ADC, MUX, S/H circuit for transmitting data in long
distance.

Gain Adjustment
Temperature
Humidity EOC
Display

np
Pressure OP Micro 8255
…………..

MUX S/H Circuit ADC

Amp Processor PPI
Input Data Recorder
SOC

u.
Select
Parallel
to Serial

ed
Selectors Converter
RS232/RS422/RS423 or
Radio link or Optical Fibre
Display 1

.
Serial to
8255

es
Parallel Display 2
Converter PPI
Recorder

ot
 A typical system that converts signals from analog to digital and back to analog includes:
 A transducer that converts non-electrical signals into electrical signals
en
 An A/D converter that converts analog signals into digital signals
 A digital processor that processes digital data (signals)
 A D/A converter that converts digital signals into equivalent analog signals
io
 A transducer that converts electrical signals into real life non-electrical signals
(sound, pressure, and video)
m
fro
d
de
oa
nl
ow
D

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 Instrumentation II Chapter 5: Data Acquisition and Transmission

Chapter – 5
Data Acquisition and Transmission
5.1 Analog and Digital Transmission
Analog Transmission
• Analog signal transmitted without regard to content

np
• May be analog or digital data
• Attenuated over distance

u.
• Use amplifiers to boost signal
• Also amplifies noise

ed
Digital Transmission
• Concerned with content

.
• Integrity endangered by noise, attenuation etc.

es
• Repeaters used
• Repeater receives signal
• Extracts bit pattern

ot
• Retransmits
• Attenuation is overcome
• Noise is not amplified

Advantages of Digital Transmission

en
io
• Increased immunity to channel noise and external interference
• Flexible operation
m

• Low cost LSI/VLSI technology

• Easy to use
• Common Format
fro

o Data, audio, video can be transmitted through same channel

• Security & Privacy
o Encryption and coding
d

• Integration
o Can treat analog and digital data similarly
de

Disadvantages of Digital Transmission

• High bandwidth requires
oa

• Complex circuitry than analog

nl

Analog Communication System

In case of analog communication, the message signal to be transmitted is analog. This analog
ow

message can be obtained from sources such as speech, video shooting etc. The analog signal
varies smoothly and continuously with time. The message signal is then modulated on some
carrier frequency by the modulator. The amplifier then gives this signal to the transmitting
antenna. Figure below shows the basic, block diagram of analog communication system.
D

Compiled By: Er. Hari Aryal [[email protected]] References: R. Gaonkar & D.V. Hall | 1
 Instrumentation II Chapter 5: Data Acquisition and Transmission

np
Fig: Analog communication system

u.
Presently, all the AM, FM radio transmission and TV transmission is analog communication.

ed
The analog communication needs lower bandwidth compared to digital communication. But the
effect of noise interference is more in case of analog communication.

.
es
Digital Communication System

ot
en
io
m
fro

Fig: Digital communication system

• Source are converted into a sequence of binary digits which is called information
sequence Represent the source by an efficient number of binary digits
d

• Efficiently converting the source into a sequence of binary digits is a process, which is
de

called source encoding of data compression

• Channel encoder adds some redundancy into binary information sequence that can be
used for handle noise and interference effects at the receiver.
oa

• Digital modulator maps the binary information sequence into signal waveforms.
• Communication channel is used to send the signal from the transmitter to the receiver.
Physical channels: the atmosphere, wireless, optical, compact disk,….
nl

• Digital demodulator receives transmitted signal contains the information which is

corrupted by noise
ow

• Cannel decoder attempts the reconstruct the original information sequence from
knowledge of the code used by channel encoder.
• Source decoder attempts the reconstruct the original signal from the binary information
D

sequence using the knowledge of the source encoding methods.

• The difference between the original signal and the reconstructed signal is measured of the
distortion introduced by the digital communication system

Compiled By: Er. Hari Aryal [[email protected]] References: R. Gaonkar & D.V. Hall | 2
 Instrumentation II Chapter 5: Data Acquisition and Transmission

• Estimate what was send, aiming at the minimum possible probability of making mistakes

5.2 Transmission Schemes

• Guided transmission media – wire (twisted pair, cable, fibre)
• Unguided – wireless (radio wave, microwave, satellite, Bluetooth)
• Characteristics and quality determined by medium and signal

np
• For guided, the medium is more important
• For unguided, the bandwidth produced by the antenna is more important
• Key concerns are data rate and distance

u.
Design Factors

ed
• Bandwidth
o Higher bandwidth gives higher data rate
• Transmission impairments

.
o Attenuation

es
• Interference
• Number of receivers

ot
o In guided media
o More receivers (multi-point) introduce more attenuation (need more amplifies or
repeaters)

5.2.1 Fiber Optics

en
io
• Optical Fiber is a cylindrical waveguide system through which the optical wave can
propagate.
m

• An Optical Fiber consists of three main parts: Core, Cladding and Jacket (See Figure )
• An optical fiber is a dielectric (nonconductor of electricity) waveguide made of glass or
fro

plastic. As shown in Figure below, it consists of three distinct regions: a core, the
cladding, and a sheath or jacket. The sheath or jacket protects the fiber but does not
govern the transmission capability of the fiber.
d
de
oa
nl
ow
D

Compiled By: Er. Hari Aryal [[email protected]] References: R. Gaonkar & D.V. Hall | 3
 Instrumentation II Chapter 5: Data Acquisition and Transmission

np
Fig: Optical Fiber transmission block diagram

Optical fibers come in two types:

u.
1. Single-mode fibers:
It is used to transmit one signal per fiber (used in telephone and cable TV). They have small

ed
cores (9 microns in diameter) and transmit infra-red light from laser.
A Fiber having very narrow core (core diameter of the order of wavelength of light injected)
is called Single mode fiber. The light travels only along the cores without reflection and with

.
no model dispersion.

es
Because of it high performance it is used for long distance, very high speed, large bandwidth
applications.

ot
2. Multi-mode fibers:
It is used to transmit many signals per fiber (used in computer networks). They have larger

en
cores (62.5 microns in diameter) and transmit infra-red light from LED.
The multimode fiber has larger core diameter than single mode fiber. The core diameter is
about 40 um and that of cladding is 70 um. The relative refractive difference is also larger
io
than single mode fiber. They are not suitable for long distance communication due to large
dispersion and attenuation of the signal. The fabrication of multi fiber is less difficult and so
m

the fiber is not costly.

There are two types of optical fibers based on refractive index

fro

1. Step-index Optical Fiber

• In step index optical fiber, the core and cladding has their uniform refractive index, say
μ1 and μ2 respectively.
d

• These fibers have greatest range of core sizes (50-200 um).

• The light rays propagate through it are in the form of meridional rays which cross the
de

fiber axis during every reflection at the core-cladding boundary.

• Advantages - relatively easy to manufacture, cheaper than other types, larger layer NA,
they have longer life times than laser diodes
oa

• Disadvantages – lower bandwidth, high dispersion and smearing of signal pulse.

nl

2. Graded-index optical fiber

• In Graded-index Optical Fibers the refractive index of core gradually decreases from the
ow

centre towards the core-cladding interface. The cladding has a uniform refractive index
profile.
• The light lays propagate through it in the form of skew rays or helical rays. They do not
cross the fiber axis at any time and are propagating around the fiber axis in helical or
D

spiral manner.
• There is a periodic self focusing of the rays. Due to this self focusing the signal distortion
is very low.
Compiled By: Er. Hari Aryal [[email protected]] References: R. Gaonkar & D.V. Hall | 4
 Instrumentation II Chapter 5: Data Acquisition and Transmission

• Advantages – Dispersion is low, bandwidth is greater than step-index multimode fiber

and easy to couple with optical source.
• Disadvantages – Expansive and very difficult to manufacture.

np
u.
. ed
es
Advantages of Optical Fiber
• Thinner

ot
• Less Expensive
• Higher Carrying Capacity
• Less Signal Degradation& Digital Signals
• Light Signals
• Non-Flammable
en
io
• Light Weight
• Enormous capacity
m

• Low transmission loss

• Cables and equipment have small size and weight
• Immunity to interference
fro

• Electrical isolation
• Signal security
• Silica fibers have abundant raw material
d
de

Disadvantages of Optical Fiber

• Requires skilled manpower for installation
• Difficult to repair and maintenance
oa

• High equipment and manufacturing cost

• Splicing (joining two optical fibers) is difficult
nl

Applications of Optical Fiber

• In communication – Compared to a conventional system they offer better reliability, large
ow

information transmission capacity, cost effective etc.

• Fiber Optic Sensors – They are used to convert various input variable into light signals
• In Medical Science – With the advent of fiber optics the otherwise inaccessible parts of
D

the body are now visible to the surgeon without actually cutting through the body. Ex.
Endoscopy.

Compiled By: Er. Hari Aryal [[email protected]] References: R. Gaonkar & D.V. Hall | 5
 Instrumentation II Chapter 5: Data Acquisition and Transmission

• Military Applications – Optical Fiber are lighter in transportation and more reliable in
terms of secrecy as compared to conventional systems.
• Entertainment – A coherent Optical Fiber bundle offers better enlargement of the image
displayed on a TV or screen.

5.2.2 Satellite

np
• A Satellite communication system consists of ground stations for transmitting and
receiving signals and a communication satellite in the space.
• A satellite is simply a repeater

u.
• It consists of several transponders each of which listens to some portion of the spectrum,
amplifies the incoming signal and then rebroadcasts it at another frequency to avoid

ed
interference with the incoming signal.
• The range of frequencies used for transmission of signals from ground station to the
satellite is uplink frequency and those used for transmission of signals from satellites to

.
ground station is downlink frequency. Uplink and downlink frequencies are different to

es
avoid interference.
• The downlink beam can be broad, covering a substantial fraction of the earth’s surface

ot
(used in broadcasting) or narrow beam covering only a hundreds of km in diameter.

en
io
m
fro
d
de
oa
nl

Two major elements of Satellite Communications Systems are

ow

1. Space Segment
2. Ground Segment
The Space Segment includes
• Satellite
D

• Means for launching satellite

• Satellite control centre for station keeping of the satellite

Compiled By: Er. Hari Aryal [[email protected]] References: R. Gaonkar & D.V. Hall | 6
 Instrumentation II Chapter 5: Data Acquisition and Transmission

The ground segment of satellite communications system establishes the communications

links with the satellite and the user. The functions of the ground segment are to transmit the
signal to the satellite and receive the signal from the satellite.
The ground segment consists:
• Earth Stations: It consists of transmitting equipment, receiving equipments and antenna
system.

np
• Rear Ward Communication links
• User terminal and interface network

u.
. ed
es
ot
en
io
m
fro

Types of Satellite
1. Low Earth Orbit (LEO)
• LEO satellites are much closer to the earth than GEO satellites, ranging from 500 to
1,500 km above the surface.
d

• LEO satellites don’t stay in fixed position relative to the surface, and are only visible for
de

15 to 20 minutes each pass.

• A network of LEO satellites is necessary for LEO satellites to be useful.
oa

Advantages
o A LEO satellite’s proximity to earth compared to a GEO satellite gives it a better
signal strength and less of a time delay, which makes it better for point to point
nl

communication.
o A LEO satellite’s smaller area of coverage is less of a waste of bandwidth.
ow

Disadvantages
o A network of LEO satellites is needed, which can be costly
o LEO satellites have to compensate for Doppler shifts cause by their relative
D

movement.
o Atmospheric drag affects LEO satellites, causing gradual orbital deterioration.

Compiled By: Er. Hari Aryal [[email protected]] References: R. Gaonkar & D.V. Hall | 7
 Instrumentation II Chapter 5: Data Acquisition and Transmission

2. Medium Earth Orbit (MEO)

• A MEO satellite is in orbit somewhere between 8,000 km and 18,000 km above the
earth’s surface.
• MEO satellites are similar to LEO satellites in functionality.
• MEO satellites are visible for much longer periods of time than LEO satellites, usually
between 2 to 8 hours.

np
• MEO satellites have a larger coverage area than LEO satellites.
Advantage
o A MEO satellite’s longer duration of visibility and wider footprint means fewer

u.
satellites are needed in a MEO network than a LEO network.
Disadvantage

ed
o A MEO satellite’s distance gives it a longer time delay and weaker signal than a LEO
satellite, though not as bad as a GEO satellite.

.
3. Geostationary Earth Orbit (GEO)

es
• These satellites are in orbit 35,863 km above the earth’s surface along the equator.
• Objects in Geostationary orbit revolve around the earth at the same speed as the earth

ot
rotates. This means GEO satellites remain in the same position relative to the surface of
earth.
Advantages
en
o A GEO satellite’s distance from earth gives it a large coverage area, almost a
fourth of the earth’s surface.
io
o GEO satellites have a 24 hour view of a particular area.
o These factors make it ideal for satellite broadcast and other multipoint
applications.
m

Disadvantages
o A GEO satellite’s distance also cause it to have both a comparatively weak signal
fro

and a time delay in the signal, which is bad for point to point communication.
o GEO satellites, centered above the equator, have difficulty broadcasting signals to
near Polar Regions.
d

Advantages of Satellites
de

• The coverage area of a satellite greatly exceeds that of a terrestrial system.

• Multiple signals can be superimposed at a time so capacity increased
• Transmission cost of a satellite is independent of the distance from the center of the
oa

coverage area.
• Satellite to Satellite communication is very precise.
• Higher Bandwidths are available for use.
nl

Disadvantages of satellite
• Bandwidth is decreased due to gradually becoming used up
ow

• Launching satellites into orbit is costly.

• There is a larger propagation delay in satellite communication than in terrestrial
communication.
D

Compiled By: Er. Hari Aryal [[email protected]] References: R. Gaonkar & D.V. Hall | 8
 Instrumentation II Chapter 5: Data Acquisition and Transmission

Service Types (Application Area) of Satellite

• Fixed Service Satellites (FSS)
o Example: Point to Point Communication
• Broadcast Service Satellites (BSS)
o Example: Satellite Television/Radio
o Also called Direct Broadcast Service (DBS).

np
• Mobile Service Satellites (MSS)
o Example: Satellite Phones

u.
Different kinds of satellites use different frequency bands.
• L–Band: 1 to 2 GHz, used by MSS

ed
• S-Band: 2 to 4 GHz, used by MSS, NASA, deep space research
• C-Band: 4 to 8 GHz, used by FSS
• X-Band: 8 to 12.5 GHz, used by FSS and in terrestrial imaging

.
• Ku-Band: 12.5 to 18 GHz: used by FSS and BSS (DBS)

es
• K-Band: 18 to 26.5 GHz: used by FSS and BSS
• Ka-Band: 26.5 to 40 GHz: used by FSS

ot
5.2.3 Bluetooth Devices
Bluetooth
en
• Bluetooth is a global standard Radio Frequency (RF) specification for short-range, point-
to-multipoint voice and data transfer. Bluetooth can transmit through solid, non-metal
io
objects. Its nominal link range is from 10 cm to 10 m, but can be extended to 100 m by
increasing the transmit power. It is based on a low-cost, short-range radio link, and
facilitates ad hoc connections for stationary and mobile communication environments.
m

• A standard for wireless electronics communication “Open Wireless”.

• It provides agreement at the physical level -- Bluetooth is a radio-frequency standard.
fro

• It also provides agreement at the next level up, where products have to agree on when
bits are sent, how many will be sent at a time and how the parties in a conversation can be
sure that the message received is the same as the message sent.
• Bluetooth communicates on a frequency of 2.45 gigahertz, which has been set aside by
d

international agreement for the use of industrial, scientific and medical devices (ISM).
de

• Bluetooth devices avoid interfering with other systems:

• Very weak signals of 1 mill watt. (Average cell phones can transmit a signal of 3 watts.)
• Range of a Bluetooth device to about 10 meters.
oa

• Bluetooth uses a technique called spread-spectrum frequency hopping.

• In this technique, a device will use 79 individual, randomly chosen frequencies within a
designated range, changing from one to another on a regular basis. In the case of
nl

Bluetooth, the transmitters change frequencies 1,600 times every second

• Bluetooth systems create a personal-area network (PAN), or piconet,
ow

• There is frequency hopping with once the piconet is established.

• Many piconets are possible in the same room.
• Half-duplex communication or full-duplex communication.
D

• Bluetooth can send data at more than 64 kilobits per second (Kbps) in a full-duplex link -
- a rate high enough to support several human voice conversations.

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 Instrumentation II Chapter 5: Data Acquisition and Transmission

• Half-duplex link -- connecting to a computer printer, for example -- Bluetooth can

transmit up to 721 kilobits per second (Kbps) in one direction, with 57.6 Kbps in the
other. If the use calls for the same speed in both directions, a link with 432.6-Kbps
capacity in each direction can be made.

Bluetooth Connection

np
u.
. ed
es
ot
en
Bluetooth uses the concept of Master/Slave mode of data communication which is packet based.
1. Passive State
io
2. Inquiry; Search of devices
3. Paging; Synchronization
m

4. Access Point Service Discovery; Wireless link

5. Channel Creation
6. Pairing; Optional (require pin code)
fro
d
de

Bluetooth Characteristics
oa

Bluetooth characteristics:
 Operates in the 2.4 GHz Industrial-Scientific-Medical (ISM) band.
 Uses Frequency Hop (FH) spread spectrum, which divides the frequency band into a
nl

number of hop channels. During a connection, radio transceivers hop from one channel
to another in a pseudo-random fashion.
ow

 Supports up to 8 devices in a piconet (two or more Bluetooth units sharing a channel).

 Built-in security.
 Non line-of-sight transmission through walls and briefcases.
D

 Omni-directional.
 Supports both isochronous and asynchronous services; easy integration of TCP/IP for
networking.
Compiled By: Er. Hari Aryal [[email protected]] References: R. Gaonkar & D.V. Hall | 10
 Instrumentation II Chapter 5: Data Acquisition and Transmission

 Regulated by governments worldwide.

Bluetooth Network Topology

1. Piconet
• A maximum of 8 devices (7 active slaves plus 1 master) form a Piconet
• A piconet is characterized by the master: frequency hopping scheme, access code,

np
timing synchronization, bit rate allocated to each slave
• Only one master: dynamically selected, roles can be switched
• Up to 7 active slaves; up to 255 parked slaves

u.
• No central network structure: “Ad-hoc” network

. ed
es
ot
en
io
2. Scatternet
• Interconnected piconets, one master per piconet
• A few devices shared between piconets
m

• No central network structure: “Ad-hoc” network

fro
d
de
oa
nl
ow
D

Compiled By: Er. Hari Aryal [[email protected]] References: R. Gaonkar & D.V. Hall | 11
 Instrumentation II Chapter 5: Data Acquisition and Transmission

Bluetooth Protocol Stack

np
u.
. ed
es
ot
en
io
m

• Radio layer: defines the requirements for a Bluetooth transceiver operating in the 2.4
GHz ISM band
fro

• Baseband layer: describes the specification of the Bluetooth Link Controller (LC) which
carries out the baseband protocols and other low-level link routines
• Link Manager Protocol (LMP): is used by the Link Managers (on either side) for link set-
up and control
d

• Host Controller Interface (HCI): provides a command interface to the Baseband Link
de

Controller and Link Manager, and access to hardware status and control registers
• Logical Link Control and Adaptation Protocol (L2CAP): supports higher level protocol
multiplexing, packet segmentation and reassembly, and the conveying of quality of
oa

service information
• RFCOMM protocol: provides emulation of serial ports over the L2CAP protocol. The
protocol is based on the ETSI standard TS 07.10
nl

• Service Discovery Protocol (SDP): provides a means for applications to discover which
services are provided or available.
ow

How will Bluetooth communicate with other hardware?

• USB
D

o USB 2.0 compliant. The module is a USB full-speed class device (12 Mbps) and
has the full functionality of a USB slave.
• UART

Compiled By: Er. Hari Aryal [[email protected]] References: R. Gaonkar & D.V. Hall | 12
 Instrumentation II Chapter 5: Data Acquisition and Transmission

o Signals supported are Rx, Tx, RTS and CTS. The module is DCE, Data Circuit-
terminal Equipment. The maximum UART speed is 460.8 kbps
• PCM
o The PCM data can be: Linear PCM 13-16 bit, μ-law 8 bit, A-law 8 bit. The PCM
sync is 8 kHz and the PCM clock 200 kHz – 2 MHz.

np
What could be done with Bluetooth?
• Wireless package handling
• Secure and instant credit transactions

u.
• Phones headsets computers networks
• Security-selective access

ed
• Anywhere a wire is currently run

Bluetooth Applications

.
• Bluetooth profiles were written to make sure that the application level works the same

es
way across different manufacturers' products
• Bluetooth applications:

ot
 Wireless control of and communication between a cell phone and a hands free
headset or car kit.
 Wireless networking between PCs in a confined space and where little bandwidth
is required en
 Wireless communications with PC input devices such as mice and keyboards
io
 Wireless communications to PC output devices such as printers
 Built-in in modern laptops or dongles
 Wireless communications with PC input devices such as mice and keyboards
m

 Wireless communications to PC output devices such as printers

 Transfer of files between devices via OBEX
fro

 Replacement of traditional wired serial communications in test equipment, GPS

receivers and medical equipment
 Thus often a serial interface is emulated over the BT link as shown on the
d

following slides ...

 Remote controls where infrared was traditionally used
de

Advantages
 Uses low power
oa

 Can connect various type of devices

 Free of cost
nl

 Ad Hoc hardware can be established by Bluetooth connection

 Simple, Secure and Global data transfer
ow

 Less time consumption

Disadvantages
 Large data transmission is difficult
D

 Bluejack is not possible (Bluejacking problem)

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 Instrumentation II Chapter 5: Data Acquisition and Transmission

5.3 Data Acquisition System

A data acquisition system consists of many components that are integrated to:
• Sense physical variables (use of transducers)
• Condition the electrical signal to make it readable by an A/D board
• Convert the signal into a digital format acceptable by a computer
• Process, analyse, store, and display the acquired data with the help of software

np
u.
. ed
es
ot
en
io
Components Description
Data acquisition At the heart of any data acquisition system lies the data acquisition
m

hardware hardware. The main function of this hardware is to convert analog signals to
digital signals, and to convert digital signals to analog signals.
fro

Sensors and Sensors and actuators can both be transducers. A transducer is a device that
actuators converts input energy of one form into output energy of another form. For
(transducers) example, a microphone is a sensor that converts sound energy (in the form
d

of pressure) into electrical energy, while a loudspeaker is an actuator that

converts electrical energy into sound energy.
de

Signal Sensor signals are often incompatible with data acquisition hardware. To
conditioning overcome this incompatibility, the signal must be conditioned. For example,
oa

hardware you might need to condition an input signal by amplifying it or by removing

unwanted frequency components. Output signals might need conditioning as
well. However, only input signals conditioning is discussed in this chapter.
nl

Computer The computer provides a processor, a system clock, a bus to transfer data,
ow

and memory and disk space to store data.

Software Data acquisition software allows you to exchange information between the
computer and the hardware. For example, typical software allows you to
D

configure the sampling rate of your board, and acquire a predefined amount
of data.

Compiled By: Er. Hari Aryal [[email protected]] References: R. Gaonkar & D.V. Hall | 14
 Instrumentation II Chapter 5: Data Acquisition and Transmission

5.3.1 Data Loggers

• Data logger automatically makes a record of the readings of instruments located at
different parts of plant.
• Data logger measures and record data effortlessly as quickly, as often, and as accurately
as desired.
• These devices measure electrical output from transducer, give plant performance

np
computation, logic analysis of alarm conditions, passes information (reading) to computer
for further processing etc.
• So they are used in power generation plant, petro-chemical installations, real time

u.
processing plants etc.

ed
Characteristics of Data Logger
a) Modularity
b) Reliability and Raggedness

.
c) Accuracy

es
d) Management Tool
e) Easy to Use

ot
Application of Data Logger

en
a) Weather station recording e.g. wind speed, wind direction, temperature, relative humidity
b) Hydrographic recording e.g. water level, depth, water flow PH, conductivity
c) Soil moisture level
io
d) Gas pressure
e) Environmental Monitoring
m

Basic Operation of Data Logger

fro
d
de
oa
nl
ow

1) Input Signals
• May be
o Pressure, transducers
D

o Thermocouple
o AC signal

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 Instrumentation II Chapter 5: Data Acquisition and Transmission

o Signals from relay, switch

o Tachometer pulses etc.
2) Input Scanner
• It is an automatic sequence switch which selects each signal in turn. Modern
scanner have input scanner which can scan at a rate of 150 inputs per second.
Characteristics of input scanner may be:

np
o Low closed resistance
o High open circuit resistance
o Low contact potential

u.
o Negligible interaction between switch, enter going signal and input signal
o Short operating time

ed
o Negligible contact bounce
o Long operation life
3) Signal Amplifier & Conditioner

.
• Amplifier for gain adjustment i.e. low level signal amplified up to 5v output.

es
Characteristics are:
o Precise and stable DC gain

ot
o High SNR
o High CMMR
o Low DC drift
o Low output impedance
o High input impedance
en
io
o Good linearity
o Wide bandwidth
• Conditioner for scaling linear transducer or correcting curvature of non linear
m

transducer i.e. signal is changed to more linear from and suitable for digital
analysis. Characteristics are:
fro

o Linear scale
o Correcting the curvature of non linear transducer
o It may include sample and hold circuit
4) A/D Converter
d

• Converts analog sample into digital data. Characteristics are:

de

o Resolution
o Accuracy
o Conversion time
oa

o Full scale output voltage

o Linearity
5) Recorder
nl

• Output from data logger may be recorded in any of following:

o Typewriter, strip printer, digital tape recorder, punched tape, computer
ow

(hard drive), magnetic tape etc.

• Characteristics are:
o Speed
D

o Memory
o Writing technique (Serial / Parallel)

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 Instrumentation II Chapter 5: Data Acquisition and Transmission

6) Programmer
• Control all units of data conversion and operation
• Microcontroller or microprocessor based system
• Basic units: main frames, front panel assembly, power supply unit, scanner
controller, input interface etc.
• Operation performed by programmer:

np
o Set amplifier
o Set linearity factor
o Set high and low alarm value

u.
o Start A/D conversion
o Record reading channel

ed
o Identify channel and time of recording
o Display recording
o Reset logger

.
es
Compact Data Logger
• A typical data logger unit provides 60 channels of data in a 20x40x60 cm box weighing

ot
about 20 Kg. Most manufacturers offer local or remote add-on scanners to expand about
100 channels.
• Scan rates are modest (1-20) channels per second
en
• The signal processing capability is limited to simple functions such as (mx+b) scaling
time averaging of single channels, group averaging of several channels and alarm
io
signalling when preset limits are exceeded.
• Most units do allow interfacing to computers where versatile processing is possible
• This class of data logger utilise a built in microprocessor to control the interval of
m

operation and carryout calculations through a single amplifier – A/D converter, which is
automatically ranged in gain switched under program control.
fro

• Multiplexers are available in both general purpose (two wire) and low level (two original
wire plus shield) versions.
• Millivolt level signals, such as from thermocouples, generally use a shielded, twisted pair
of conductors.
d

• Electro-mechanical read switches are used frequently in such scanners since speed
de

requirements are modest but low noise is important.

• Since thermocouples are very common in data logger applications, reference function
compensation and linearization options are always available.
oa

• The microprocessor also stores the equation which curve-fit the thermocouple table for
each.
• The system amplifier and A/D converter is the crucial element for several system
nl

accuracy.
• The microprocessor sets the amplifier gains at a proper value as each channel is sampled.
ow

• The A/D converter are often of dual slope type or voltage to frequency converter type as
the speed is modest with noise rejections
• Readout obtained by means of a built in digital indicator and two colour printers whose
D

format is selected by front panel programming..

Compiled By: Er. Hari Aryal [[email protected]] References: R. Gaonkar & D.V. Hall | 17
 Instrumentation II Chapter 5: Data Acquisition and Transmission

np
u.
. ed
es
ot
5.3.2 Data Archiving and Storage
en
io
Data Archiving
• Data archiving is the process of moving data that is no longer actively used to a separate
data storage device for long-term retention, but can be readily accessed if required. Data
m

archives consist of older data that is still important and necessary for future reference, as
well as data that must be retained for regulatory compliance. Referential integrity should
fro

be maintained.
• Data archives are indexed and have search capabilities so that files and parts of files can
be easily located and retrieved.
• Data archives are often confused with data backups, which are copies of data. Data
d

backups are used to restore data in case it is corrupted or destroyed. In contrast, data
de

archives protect older information that is not needed for everyday operations but may
occasionally need to be accessed.
oa

Data Storage
Storage Factors:
• Speed with which data can be accessed
nl

• Cost per unit of data

• Reliability
ow

o data loss on power failure or system crash

o physical failure of the storage device
D

Can differentiate storage into:

o volatile storage: loses contents when power is switched off
o non-volatile storage:
Compiled By: Er. Hari Aryal [[email protected]] References: R. Gaonkar & D.V. Hall | 18
 Instrumentation II Chapter 5: Data Acquisition and Transmission

 Contents persist even when power is switched off.

 Includes secondary and tertiary storage, as well as batter-backed up main-
memory.
Physical Storage Types:
• Primary storage: Fastest media but volatile (cache, main memory – RAM and ROM).
• Secondary storage: Non-volatile, moderately fast access time

np
o also called on-line storage
o E.g. flash memory, magnetic disks
• Tertiary storage: Non-volatile, slow access time which involves a robotic mechanism

u.
that will mount and dismount removable mass storage media into a storage device
according to the system demands.

ed
o also called off-line storage
o E.g. Tape libraries, optical jukebox etc.

.
es
Data Compression
• Process of encoding information using fewer bits than an un-encoded representation
would use, through specific encoding schemes.

ot
• Reduce consumption of expensive resources such as hard drive and transmission
bandwidth.

Types:
Lossy
en
• Trade-off between compression speed, compressed data size and quality (loss)

Lossless
io
For the case if loss of fidelity is acceptable Exploit statistical redundancy in such a
e.g. 6.666666 = 7 way to represent data without error
e.g. 6.666666 = 6[6]6
m

Examples: Pictures (JPEG), Video (MPEG), Examples: zip, rar, Picture (PNG, TIFF),
Audio (MP3) etc. Video (Huff, YUV, AVI) etc.
fro

RAID: Redundant Arrays of Independent Disks

It is the way of storing the data in disk organization techniques that manage a large numbers of
disks, providing a view of a single disk of
d

o high capacity and high speed by using multiple disks in parallel, and
de

o high reliability by storing data redundantly, so that data can be recovered even if
a disk fails
• RAID Level 0: Block striping; non-redundant.
oa

• RAID Level 1: Mirrored disks with block striping

• RAID Level 2: Stripes data at the bit level, and uses code for error correction.
• RAID Level 3: Bit-Interleaved Parity
nl

o a single parity bit is enough for error correction, not just detection, since we
know which disk has failed
ow

• RAID Level 4: Block-Interleaved Parity; uses block-level striping, and keeps a parity
block on a separate disk for corresponding blocks from N other disks.
• RAID Level 5: Block-Interleaved Distributed Parity; partitions data and parity among
D

all N + 1 disks, rather than storing data in N disks and parity in 1 disk.

Compiled By: Er. Hari Aryal [[email protected]] References: R. Gaonkar & D.V. Hall | 19
 Instrumentation II Chapter 6: Grounding and Shielding

Chapter – 6
Grounding and Shielding

Grounding and Shielding

 Grounds & Shields improve safety and reduce interference from noise.
 Properly connected grounds reduce dangerous voltage differentials between instruments.

np
 Shields minimize interference from noise by reducing noise emission and noise
susceptibility.

u.
6.1 Outline for Grounding and Shielding Design


ed
Step 1: Understand the safety and noise issues for a product.
 Step 2: Know the possible mechanisms of energy coupling.
 Step 3: Define the necessary grounds and shields.

.
es
Safety
 Reduce the voltage differentials between external conductor surfaces.
 Usually the design is – conducted energy, low frequency (less than 1 MHz) and

ot
associated with power lines.
 Microwave energy is not a shock hazard but it does pose danger and demands especial
attention to shielding. en
io
Safety Ground
 Provides a path for the dangerous leakage currents and short circuits.
 Properly connected safety ground reduces voltage differential between external surfaces.
m

 Safety ground must be a permanent, continuous, low impedance conductor with adequate
capacity that runs from the power source to load.
fro

 Don’t rely on a metallic conduct to form the conductive path for the safety ground,
corrosion and breaks can open the circuit.
 Don’t rely on building steel either because circulating currents can generate large and
d

noisy ground potentials.

 A separate dedicated conductor will avoid these problems.
de

Three things to remember when to develop wiring for powering instruments:

 Consider the instrument and power mains as an integrated system.
oa

 Always draw your ground scheme to understand the possible circuit paths.
 Don’t blindly rely on building steel for a ground conductor.
nl

6.2 Noise, Noise (Energy) Coupling Mechanism and Prevention

•
ow

Noise is unwanted electrical activity coupled from one circuit into another.
– 3 components: A source, A coupling mechanism, and A receiver
D

Compiled By: Er. Hari Aryal [[email protected]] Reference: K. R. Fowler | 1

 Instrumentation II Chapter 6: Grounding and Shielding

np
Fig: Block diagram of noise disrupting a circuit

u.
Noise Sources

ed
 Noise sources generate either a periodic signal or transient pulse that disrupts other
circuits.
 There are many types of sources: Power lines, Motors, High voltage equipment (e.g.

.
es
spark plug, igniter), Dischargers and sparks (e.g. lightning, static electricity), High
current equipment (e.g. arc welder)

ot
Energy Coupling Mechanism
 Four mechanisms: Conductive, inductive, capacitive & electromagnetic
Coupling
Mechanism
Frequency Range
en
Comment
io
Conductive DC to 10 MHz Requires a complete circuit loop (really no upper
limit to frequency)
m

Inductive Usually > 3KHz Larger loop area in circuit means greater self
inductance and mutual inductance associated with
fro

heavy current (can get significant coupling from

50 Hz-60 Hz power).
Capacitive Usually > 1 KHz Greater spacing between conductors reduces
d

coupling associated with high voltage (can get

significant coupling from 50 Hz-60 Hz power).
de

Electromagnetic Usually > 15 MHz Needs antenna s greater than 1/20 of wave length
in both the source and susceptible circuit.
oa

 Conductive coupling  low frequencies, caused by incorrect grounding.

nl

 Capacitive & inductive coupling  dominate at high frequencies

o Changing magnetic flux can couple circuits.
ow

o The loop area of the circuit is the primary factor that determines the inductance
and coupling.
o Changing electric potentials can drive charge through stray capacitances.
D

o Appropriate grounding, shielding and signal separation control the amount of

capacitive coupling.

Compiled By: Er. Hari Aryal [[email protected]] Reference: K. R. Fowler | 2

 Instrumentation II Chapter 6: Grounding and Shielding

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en
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m

 Electromagnetic coupling is a high frequency phenomenon.

 It requires a transmitting antenna in the source and a receiving antenna in the susceptible
fro

circuit. These antennas must be in appropriate fraction of the signal wavelength to couple
effectively.
d
de
oa
nl

Susceptible Circuit
• Third component of noise is susceptible circuit.
ow

• E.g. susceptibility includes cross talk on inputs that leads to bit flips in digital logic, radio
interference and static discharge that destroy components.
• Susceptibility usually can be traced by proper grounding (or return paths) or long signal
D

lines that are not properly shielded.

Compiled By: Er. Hari Aryal [[email protected]] Reference: K. R. Fowler | 3

 Instrumentation II Chapter 6: Grounding and Shielding

Principle of Energy Coupling

• Current will flow in the path with low impedance, not necessarily lowest resistance.
• Consequently, charge follows the path of minimum inductive and maximum capacitive
reactance for the lowest impedance.
Z  ( R 2  [WL  (1 / WC )]2 )

np
Where, Z = Impedance, R = Resistance, WL = Inductive reactance & 1/WC = Capacitive
reactance
• For frequencies above 3 KHz, a useful diagnostic for determining the mechanism is the

u.
ratio of rate of change in voltage to the rate of change in current.
• For the special cases of sinusoidal signals or resistive loads, the ratio is impedance;

ed
otherwise, it is a pseudo impedance value.
• A Diagnostic ratio called Pseudo Impedance.
• Pseudo Impedance is defined as: γ = (dv/dt)/(di/dt)

.
o If γ = 377, @ high frequencies (> 20MHz)  Electromagnetic coupling.

es
o If γ < 377, the value of di/dt > dv/dt i.e. large change in current  inductive
coupling.
o If γ > 377, the value of dv/dt > di/dt i.e. large change in voltage  capacitive

ot
coupling.

Conductive Coupling
en
• Requires a connection between source and receiver that completes a continuous circuit.
• Conductive coupling usually occurs at lower frequencies and is often caused by incorrect
io
grounding.
m
fro
d
de
oa

Fig: Conductive coupling. If either connection A or B is removed, the conductive noise is

eliminated.
nl

• Such connections are inadvertent and difficult to find; such connections are called Sneak
ow

circuits.
• A ground loop is a complete circuit that allows unwanted current to flow into the ground.
• Substantial current in a ground path (as opposed to a return path) can produce voltage
D

differences across the ground resistance and raise the ground potential at the loads.
Conversely, significant potentials in the ground can force unwanted current to flow
between circuits.
Compiled By: Er. Hari Aryal [[email protected]] Reference: K. R. Fowler | 4
 Instrumentation II Chapter 6: Grounding and Shielding

• The use of high frequency and reduction of ground loop can reduce conductive coupling
or conductive noise.

np
u.
. ed
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en
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Inductive Coupling
m

• An Inductive coupling mechanism requires a current loop that generates changing

magnetic flux.
fro

• Generally, a current transient creates the changing magnetic flux, as follows:

 = BA =  0 nIA
Then,
d
d

dB di
v  A( )  A 0 n( )
dt dt dt
de

Where,  = Magnetic Flux

B = Magnetic field
A = Loop area
oa

 0 = Permeability of free space

n = Number of turns in the loop
nl

i = Current
v = Voltage
ow

• The induced voltage in a magnetically coupled circuit is proportional to the time rate of
change of current and loop area.
• Reducing the loop area will reduce the inductive reactance of a circuit.
• For frequencies above 3 MHz, (dv/dt) / (di/dt) << 377Ω
D

• Generally, the load impedance is large, while the source impedance is small.

Compiled By: Er. Hari Aryal [[email protected]] Reference: K. R. Fowler | 5

 Instrumentation II Chapter 6: Grounding and Shielding

np
u.
. ed
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en
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m
fro

• Current follows the path of lowest impedance, not necessarily lowest resistance.
Therefore, current will follow the path of minimum inductive reactance; this means the
d

current will minimize loop area in a circuit.

de

• A slot in the ground plane of a circuit board will increase the loop area of a circuit; below
figure shows this; so avoid such slots.
oa
nl
ow
D

Compiled By: Er. Hari Aryal [[email protected]] Reference: K. R. Fowler | 6

 Instrumentation II Chapter 6: Grounding and Shielding

np
u.
. ed
es
• The long, straight wires encompass significant loop area that provides an inductive
reactance. Twisting the pairs of signal and return lines together eliminates the loop area

ot
and the mutual inductive coupling between circuits.

en
io
m
fro
d
de
oa
nl
ow

Capacitive Coupling
• Capacitive coupling mechanism requires both proximity between circuits and a changing
D

voltage.
• It occurs when two conductors are placed at some distance apart and voltage level and
frequency are changed.
Compiled By: Er. Hari Aryal [[email protected]] Reference: K. R. Fowler | 7
 Instrumentation II Chapter 6: Grounding and Shielding

• Capacitive coupling of noise becomes a factor for frequency above 1 KHz

• Generally, the total circuit impedance is high; i.e. both the source and load impedance are
large.
• (dv/dt) / (di/dt) >> 377Ω
• Capacitive coupling can be reduced by separation of conductors and appropriate
shielding.

np
u.
. ed
es
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en
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m
fro
d
de

Electromagnetic Coupling
• Electromagnetic coupling or radiative coupling becomes a factor only when the
oa

frequency of operation exceeds 20 MHz.

• f < 200 MHz, cables are primary sources and receivers for electromagnetic coupling.
• f > 200 MHz, PCB traces begin to radiate & couple energy.
nl

• Generally, the length of conductor must be longer than 5% of the bandwidth i.e. l > ʎ/20.
• Pseudo impedance factor between 100Ω and 500Ω.
ow

(dv/dt) / (di/dt) = 377Ω

• The frequency of signal must be reduced.
• Use magnetic plate shielding.
D

Compiled By: Er. Hari Aryal [[email protected]] Reference: K. R. Fowler | 8

 Instrumentation II Chapter 6: Grounding and Shielding

6.3 Single Point Grounding and Ground Loop

Grounding
• Grounding provides safety and signal reference
• General principle is to minimize the voltage differential between your instrument and a
reference point i.e. ∆V = 0 between instruments.
• Use the return conductors as a signal reference.

np
u.
. ed
es
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en
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m
fro
d
de

• Often designers use the return conductors as a signal reference.

oa
nl
ow
D

Compiled By: Er. Hari Aryal [[email protected]] Reference: K. R. Fowler | 9

 Instrumentation II Chapter 6: Grounding and Shielding

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en
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Safety Grounding
de

• Seeks to reduce the voltage differentials between exposed conducting surfaces.

• Should have many connections between the exposed conducting surfaces.
oa

Signal Referencing
• Seeks to reduce the voltage differentials between reference points.
• Should have one connection between reference points at low frequency.
nl

• In either case, ground is not the return path for a signal. Both safety and signal grounds
ow

nominally conducts current.

D

Compiled By: Er. Hari Aryal [[email protected]] Reference: K. R. Fowler | 10

 Instrumentation II Chapter 6: Grounding and Shielding

np
u.
Single Point Grounding

ed
• The separate ground conductors isolate the noise in the return paths of the separate
circuits because the single point reference connection does not complete any ground
loops between circuits.

.
• Most appropriate low-current, low-frequency (< 1 MHz) applications.

es
• The ground conductor should be a short strap to reduce high-frequency noise and unsafe
voltages.

ot
en
io
m
fro
d
de
oa
nl
ow

Disadvantages
• Conductors longer than 5m (16 ft) are susceptible to high-frequency ground noise. (A
braided cable may reduce impedance at high frequencies by increasing the skin effect;
D

that is, current tends to flow along the surface, and braided cable has a large surface
area).

Compiled By: Er. Hari Aryal [[email protected]] Reference: K. R. Fowler | 11

 Instrumentation II Chapter 6: Grounding and Shielding

• Conductors longer than 30m (100 ft) or those conducting high fault currents are
unsafe. The inherent impedance of the conductor will cause large potential
differences exist between the instrument and ground.
• ADC is one application that needs a single point ground for signal referencing
separate references can generate noisy ground loops.

np
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. ed
es
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en
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m
fro
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Ground Plane or Grid

• A ground plane within a circuit board is better for high frequency (> 100 KHz) operation.
• Likewise, a ground grid is better for high frequency or high fault currents, because it has
oa

lower impedance than a single cable.

nl
ow
D

Compiled By: Er. Hari Aryal [[email protected]] Reference: K. R. Fowler | 12

 Instrumentation II Chapter 6: Grounding and Shielding

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Ground Loop
• A ground loop is a complete circuit that comprises a signal path and part of the ground

ot
structure.
• It arises whenever multiple connections to ground are physically separated.
• External currents in the ground structure generate potential differences between the
en
ground connections and introduce noise in the signal circuit.
io
m
fro
d
de
oa
nl

•
ow

Generally, the problem arises at low frequencies (< 10 MHz); high frequencies follow the
path of minimum impedance that can avoid higher impedance ground loops.
• Ground loops are a particular problem in systems that have low level signal circuits and
multipoint grounds separated by large distances.
D

• Either circuit balance or signal isolation can eliminate noise from ground loops.

Compiled By: Er. Hari Aryal [[email protected]] Reference: K. R. Fowler | 13

 Instrumentation II Chapter 6: Grounding and Shielding

np
u.
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es
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en
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m
fro

•
d

For safety, coordinate the routing of power and signal to reduce noise introduces by the
ground structure.
de
oa
nl
ow
D

Compiled By: Er. Hari Aryal [[email protected]] Reference: K. R. Fowler | 14

 Instrumentation II Chapter 6: Grounding and Shielding

np
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en
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6.4 Filtering and Smoothing
m

Filtering
• Only filtering reduces conductive noise coupling.
fro

• A filter can either block or pass energy by three criteria.

a) Frequency
 LPF passes low frequency energy and rejects high frequency energy
 HPF passes high frequency energy and rejects low frequency energy
d

b) Mode (Common or Differential)

de

 Common-mode noise injects current in the same direction in both the

signal and return lines. Filter diverts common mode noise current to
ground.
oa
nl
ow
D

Compiled By: Er. Hari Aryal [[email protected]] Reference: K. R. Fowler | 15

 Instrumentation II Chapter 6: Grounding and Shielding

np
u.
 Differential-mode noise injects current in opposite directions in the signal

ed
and return lines. Filter blocks common mode currents while passing
differential mode current.

.
es
ot
en
io
m
fro
d
de

c) Amplitude (Surge suppression)

 Amplitude selective filters reduce large transients or spikes e.g. surge
suppressors.
oa

• Time-average filter  Implemented in software, reduce the effect of noise on data within
a signal.
• Time-synchronous filter  Stop running at periodic disturbance e.g. periodic switching
nl

in power supply.
ow

Minimize Bandwidth
• A low-pass filter reduces high frequency emissions and susceptibility for signal
applications.
D

• Filtering input signals may improve the noise immunity of the circuit.
• Sharp edges on pulses will have large Fourier coefficient. Slowing the rise and fall times
of pulse edge will reduce the bandwidth of signals.

Compiled By: Er. Hari Aryal [[email protected]] Reference: K. R. Fowler | 16

 Instrumentation II Chapter 6: Grounding and Shielding

np
u.
. ed
es
• Filtering clock signal to reduce the high-frequency harmonics is one area where we may

ot
significantly reduce noise interference. But be careful not to violate the minimum skew
rate required by the logic circuits.
en
io
m
fro
d
de
oa
nl
ow

6.5 Decoupling Capacitors and Ferrite Beads

Ferrite Beads
D

• Ferrite beads provide one form of filtering based on frequency.

• A ferrite bead is a magnetically permeable sleeve that fits around a wire. It presents
inductive impedance to signals that attenuates high frequencies.

Compiled By: Er. Hari Aryal [[email protected]] Reference: K. R. Fowler | 17

 Instrumentation II Chapter 6: Grounding and Shielding

• Ferrite beads are best suited to filter low level signals and low current power feeds to
circuit board.
• A ferrite bead is a passive electric component used to suppress high frequency noise in
electronic circuits.
• It is a specific type of electronic choke. Ferrite beads employ the mechanism of high
dissipation of high frequency currents in a ferrite to build high frequency noise

np
suppression devices.
• The ferrite bead is effectively an inductor with a very small Q factor.
• For a simple ferrite ring, the wire is simply wrapped around the core through the center

u.
typically 5 or 7 times. Clamp-on cores are also available, which can be attached without
wrapping the wire at all.

. ed
es
ot
en
io
Decoupling and Bypass Capacitors
• They provide Filtering based on frequency
m

• They filter and smooth out the spikes in DC power of ICs

• During a logic transition, a momentary short circuit from power to return in a digital
fro

device demands a large current transient. A decoupling capacitor can supply the
momentary pulse of current and effectively decouple the switching spike from the power
supply.
• They reduce the impedance of power supply circuit.
d

• Inductance in the power supply attenuates the effect of switching current transients by
de

producing large voltage spikes.

• Decoupling capacitor provides this demand for shorter time.
• Mitigate the effect of inductance by reducing effective loop area between Power supply
oa

and the ICs.

Z 0  ( R 2  [WL  (1 / WC )]2 )
nl

• Reduce impedance of power supply

• If you arbitrarily make the decoupling capacitor too large, you will move the resonance
ow

frequency of the supply inductance and decoupling capacitor down into the range of
operation of your circuit and cause excessive ringing in the supply.
• Also, large capacitors have larger parasitic inductances than smaller decoupling
D

capacitors.

Compiled By: Er. Hari Aryal [[email protected]] Reference: K. R. Fowler | 18

 Instrumentation II Chapter 6: Grounding and Shielding

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6.6 Line Filters, Isolators and Transient Suppressors

Line filters and Isolators  Mode basis
fro

Transient Suppressor  Amplitude basis

 Common mode filters for AC power lines diverts noise to ground, but beware of
polluting the signal reference ground with noise.
 An optoisolator can eliminate common mode noise by interrupting the conductive path.
d

 A differential mode filter has to separate noise from signal by criteria other than current
de

direction; a low pass filter is an example of differential mode filter that uses frequency as
the selection criterion.
 Transient  Machinery switching on or off produces transients through inductive “kick”.
oa

The opening or closing of switches changes the load current instantaneously and
generates a sizable voltage across the line inductance that affects the other loads.
 Transient protection can take one of four approaches: filter, crowbar (thyrister), arching
nl

discharge, or voltage clamp (zener diode or metal-oxide varister i.e. MOV).

1. Filter: It removes the high frequency components of the energy associated with
ow

the sharp edge of a spike. Consequently, the peak of the spike is flattened.
2. Crowbar (thyristor): It detects an over voltage and short circuit current until the
input voltage is cycled off and on again.
D

3. Arching discharge: It occurs across gap into a gas tube. The initial breakdown of
the gas requires a fairly high voltage; but once the arc is established, the holding

Compiled By: Er. Hari Aryal [[email protected]] Reference: K. R. Fowler | 19

 Instrumentation II Chapter 6: Grounding and Shielding

voltage is much lower. It is used in telephone circuits to suppress surge caused by

lightning.
4. Voltage clamp (Zener): It shorts the excess energy to prevent an overvoltage
condition. Fast, more cost, low current capacity than MOV (Metal oxide varister).

np
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fro
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6.7 Different kinds of Shielding Mechanism

Shielding
• Shielding either prevents noise energy from coupling between circuits or suppresses it.
nl

o Magnetic flux – inductive shielding

o Electric field – capacitive shielding
ow

o Electromagnetic wave propagation – electromagnetic shielding

Inductive Shielding
D

• It is concerned with Self-inductance and Mutual inductance.

• It reduces noise coupling by reducing or rerouting magnetic flux.

Compiled By: Er. Hari Aryal [[email protected]] Reference: K. R. Fowler | 20

 Instrumentation II Chapter 6: Grounding and Shielding

• The most effective inductive shielding minimizes loop area, separating circuits and
reducing the change in current help, while metal or magnetically permeable enclosures
place a distant third in usefulness.
• Magnetic noise depends on loop area and current in the emitting and receiving circuits.
• Coaxial cable has minimal loop area and may be preferable for high frequencies (>
1MHz) because it provides both capacitive shielding and controlled impedance.

np
• Always pair signals with return, otherwise, we will not gain any inductive shielding.

u.
. ed
es
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en
io
m
fro
d
de
oa

•
nl

On circuit boards,
o Make sure that the return path is always under the signal conductor to minimize
ow

loop area.
o Avoid slots in ground plane, which increase the loop area of signal path.
• Enclosures provide magnetic shielding by allowing eddy currents to reflect or absorb
interference energy. These enclosures are heavy, expensive and frequency dependent, but
D

sometimes they are only solution.

Compiled By: Er. Hari Aryal [[email protected]] Reference: K. R. Fowler | 21

 Instrumentation II Chapter 6: Grounding and Shielding

Capacitive Shielding
• Capacitive shielding reduces noise coupling by reducing or rerouting the electrical charge
in an electric field.
• Capacitive shields shunt to ground charge that is capacitively coupled.
• Capacitive coupling provides a path for the injection of noise charges.
• At low frequencies (< 1 MHz), connect a capacitive shield at one point if the signal

np
circuit is grounded. Multiple connections can form ground loops.
• Capacitive shielding can be improved by reducing:
o Noise voltage and frequency

u.
o Signal impedance
o Floating metal surfaces

ed
• Conversely, multiple ground connections are necessary for high frequencies (> 1 MHz).
Stray capacitance at the ungrounded end of a shield can complete a ground loop.
• Therefore, we should ground both ends of a long (relative to wavelength) shield.

.
• A mutual enclosure can be an effective electrostatic shield (transformer), or faraday

es
shield to prevent capacitive coupling.

ot
en
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m
fro
d
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nl
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 Instrumentation II Chapter 6: Grounding and Shielding

Electromagnetic Shielding
• Electromagnetic shielding reduces emissions and reception.
• Emission sources: Lightning, Discharges, Radio and TV transmitters, High-frequency
circuits.
• Electromagnetic Interference (EMI) always begins as conductive (current in wires)
becomes radioactive, and ends as conductive (fields interact with circuitry).

np
• Several techniques can reduce EMI:
o Reduced bandwidth (longer wavelength)
o Good layout and signal routing

u.
o Shielded enclosures
• As shielded enclosure should ideally be a completely closed conducting surface.

ed
Effective enclosure is one that has watertight metallic seams and openings. Openings
include cooling vents, cable penetration with slots larger than a fraction of a wavelength
(> ʎ/20), push buttons, and monitor screens that can leak electromagnetic radiation.

.
• Similarly, cable shields must seal completely around each connector.

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Fig: Shielded enclosure and cable shield

nl

Some Practical Applications

Twisted Pair Cable
• Effective up to 1 MHz, lossy at higher frequencies
ow

• Cheaper and mechanically more flexible

• Single ground connection to both the shield and return line provides best attenuation of
the 50 KHz noise.
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 Instrumentation II Chapter 6: Grounding and Shielding

Coaxial Cable
• Have low loss and less variance in characteristic impedance from DC to very high
frequencies (> 200 MHz).
• A pigtail connection from the shield to ground presents a loop inductance that increases
impedance with frequency. Thus, high frequencies (> 10 MHz) demand a complete 360o
seal of the shield at both ends.

np
Ribbon cable
• Ribbon cable is ubiquitous in instrumentation.

u.
• It is suitable for low frequency operation << 1 MHz
• We should pair each signal with a return conductor or use a return plane for low-level

ed
signals or higher frequencies.

EM leakage through openings of conducting enclosure can be reduced by:

.
o Seams must be soldered, welded or overlapped

es
o Penetration such as vents and cables need appropriate filters and shields. A
honeycomb matrix invents, acts as a waveguide to filter electromagnetic radiation.

ot
6.8 Protecting Against Electrostatics Discharge
• Electrostatic discharge (ESD) is a discharge at very high voltage and very low current
that readily damages sensitive electronics. en
• ESD can range from hundreds to tens of thousands of volts. Any instrument containing
io
integrated circuits is susceptible.
• ESD transfers electrical charge in three stages: pickup, storage and discharge.
• Usually mechanical rubbing between dry, insulated materials transfers the charge from
m

source to storage. Often the storage medium is person, who then unwillingly delivers the
damaging discharge.
fro

• Proximity or physical contact discharges the charge from storage.

• Several conditions including humidity, speed of the activity, and material affect the
charge transfer.
• The discharge waveform of ESD has a fast rise time and short duration. The below figure
d

illustrates sample waveform for simulating ESD while testing products.

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Fig: Discharge waveform at 4 kv

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 Instrumentation II Chapter 6: Grounding and Shielding

• Several schemes including grounding, shielding and transient limiters can protect circuits
from ESD.
• Input gates are the most susceptible to damage, so we should use surge-limiters on input
lines as shown in below figure.

Input ESD-

np
sensors sensesative
or circuit
switches

u.
. ed
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0 en
Fig: Preventing damage by shunting high voltage transients away from circuits with zener
io
diodes or MOVs
• Generally zener diodes and MOVs are used to limit surges. Zener diodes tend to turn on
m

faster, while MOVs are cheaper and handle large peak current.
• For prevention, we need to eliminate the activities and materials that create high static
fro

charge control methods including the following.

o Grounding
o Protective handling
o Protective material
d

o Humidity
• Checklist to make work areas less prone to ESD
de

o Use a “static-free” workstation, and wear a wrist ground strap

o Discharge static before handling devices
o Keep parts in original container
oa

o Minimize handling of components

o Pickup devices by their bodies, not their leads
nl

o Never slide a semiconductor over any surface

o Use conductive or antistatic containers for storage and transport of components
ow

o Clear all plastic, vinyl, Styrofoam from work area

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 Instrumentation II Chapter 6: Grounding and Shielding

np
u.
. ed
es
ot
6.9 General Rules for design
• When design and develop product, must include grounding and shielding. Also need to
follow these general guidelines.
– System Characterization
en
io
– Standards
– Procedure (good design technique)
System Characterization
m

• Establish the following

– Grounding options
fro

– Source and load impedance

– Frequency bandwidth
• Determine possible coupling mechanism
• Diagram the topology of circuit paths and reduce the loops
d

– Ground loops
de

– Inductive loops in signal and power circuits

Standards
• Undoubtedly encounter regulations and standards whatever market, product will compete
oa

in.
• Have to meet or surpass the limits of emission or susceptibility in both conducted and
radiated environments.
nl

• Regulations types may be commercial or military

ow

Procedure
• Good design techniques for grounding and shielding have a few basic rules:
– Reduce Frequency bandwidth
D

– Balance currents
– Route signals for self shielding: a return (ground) plane, short traces, decoupling
capacitors

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 Instrumentation II Chapter 6: Grounding and Shielding

– Add shielding only when necessary

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 Instrumentation II Chapter 6: Grounding and Shielding

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Case Study
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• Enclosure Design
• Enclosure Testing
• Option Module Design
oa

• Circuit Suppression Design

• Printed Circuit board Design
• Power Supply Filtering
nl

• System Design
• Acknowledgements
ow

Be important Noted:
• Example 6.5.1, Example 6.5.2, Example 6.8.1.1, Example 6.9.1
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 Instrumentation II Chapter 7: Circuit Design

Chapter – 7
Circuit Design
From symbols to substance

np
u.
. ed
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7.1
•
•
Converting requirement into design
en
Establishing requirement is the most difficult part of the circuit design.
Experience is the best guide for setting requirements
io
• General to specific approach of establishing requirements:
– Start by defining the desired function in broad term
– Redefine the function with operational concerns
m

– Settle on exact regulations and specification

• Setting specifications is one of the most difficult parts of engineering where good
fro

judgment and experience are necessary.

• Requirements often change late in the effort and spoil the design
• Some principles bound the design problem
– E.g. use of electromagnetic spectrum
d

• Time and effort in design increases as the complexity of the function of system increases
de

• Choice of certain technology and devices are the result of good analysis and may depend
on different factors
– E.g. choice of a microprocessor for a system
oa

– Choice of A/D and D/A converters

• Technology drives the requirements. Audio frequency (~KHz)  Discrete components,
wirewrap or PCB. Radio frequency (~MHz)  PCB (transmission line effect).
nl

Microwave frequency (~GHz)  RF design (Geometric structures).

• Throughput: The average rate of successful message delivers over a communication
ow

channel.
• Knowing region of operation, we can pick option available for circuit design. Right
choice  Part count (↓), board apace (↓), Power (↓), Cost (↓), time to market (↓),
D

reliability (↑).

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 Instrumentation II Chapter 7: Circuit Design

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 Instrumentation II Chapter 7: Circuit Design

ASIC (Application Specific Integrated Circuits)

• It is an IC customized for particular use. For an example chips designed solely to run cell
phones.
• Modern ASIC includes  32 bit processor, ROM, RAM etc. Such ASIC are called
System on Chip (SOC).
• Solve signal/data processing problems optimally in terms of high throughput and low

np
power.
• Low cost but takes longer time to market.

u.
Standard Cells
• Group of transistors are interconnected structures that provides Boolean logic function or

ed
storage function.
• Simplest cells are direct representatives of adder, mux, flip-flops etc.

.
Gate Array

es
• Analogous to Cu layer of PCB.
• Transistors, standard NAND, NOR gates placed at predefined position and manufactured

ot
in wafer.
• Late manufacture process  joined to logic as desired shorter time to market.

Programmable Logic Array (PLA)

• Implement combinational logic
en
io
• Set of programmable AND gates which link to set of programmable OR gates

Programmable Logic Device (PLD)

m

• To build reconfigurable logic circuits

• E.g. ROM  store i/p logic as address; o/p logic  store in ROM
fro

Programmable Array Logic (PAL)

• Fixed OR with programmable AND
• O/P logic  registered or combinational
d
de

Electrically PLD (EPLD) or Complex PLD (CPLD)

• Non volatile configuration memory
• Can implement complex logics
oa

Field Programmable Gate Array (FPGA)

• Field  firmware can be modified in field without dissembling device or returning into
nl

manufacturer
• IC designed to configure by customer or designer after manufacture
ow

• Programmable logic components called logic blocks wired together to form complex
logic plus it has analog features  programmable slew rates
• Uses HDL (hardware descriptive language) to implement logic functions.
D

• Low non-recurrent engineering cost but high unit cost in comparison to ASIC
• Logic blocks plus embedded microprocessor to form complex system on programmable
chips.

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 Instrumentation II Chapter 7: Circuit Design

• Software processor  implemented within FPGA logic; highly configurable and flexible
than hardwire processor
• Applications: DSP, aerospace, ASIC, prototyping, medical imaging etc.
• Short time to market
• Flexibility in both hardware and software

np
Technology Performance/Cost Time to market
ASIC Very high Very long
Custom processor or DSP Medium Long

u.
FPGA Low-medium Short
Generic logic Low-medium Short

ed
Microcontrollers
• CPU, I/O devices, program memory, data memory all in single chip

.
es
Microprocessors
• Requires other parts to make workable computer.

ot
Selection of microprocessor / Microcomputer
1. Experience
en
2. Software dependent tools for particular processor
3. Performance: Architecture dependent
io
4. No. of peripheral function
5. Memory
6. Tools support to determine the appropriate processor
m

7. Low power consumption

fro

Performance is determined by
o Throughput
o Resolution
o Address space and available memory
d

o Language choice, code size, speed

de

o Predominant types of calculation: integer and floating point

No. of peripheral function

oa

o Math coprocessor
o Graphics accelerator
o Interrupt handler
nl

o Data transfer and communication: DMA, small computer system interface(SCSI),

Serial I/O Ports
ow

o Timer
o ADC and DAC
o Power drivers
D

o Watchdog timing (System reset in case of system unresponsiveness)

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 Instrumentation II Chapter 7: Circuit Design

Memory
o Require minimum size of memory
o Always plan for and specify margin in the requirements for future updates and
modifications.
o Size of RAM/ROM Depends on
 Data array

np
 Stack
 Temporary and permanent variable
 Compiler overhead

u.
 I/O buffer

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Tools support to determine the appropriate processor
o Hardware emulator: Helps to debug both circuits and code
o Software tools: supports development on the selected processor

.
o Vendor: good support, good reputation, markedly affected development tools

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Power consumption within a processor

ot
• Cooling concerns
• Battery sizing

Complexity vs. Right Technology en

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 Instrumentation II Chapter 7: Circuit Design

Design time vs. Complexity

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7.2 Reliability, fault tolerance
en
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Reliability
• How long the product will last?
• Two factors role in the reliability:-
m

o Complexity:- Fewer part better

o Design margin:- We must allow for stressing of components
fro

• Two methods to measure reliability:-

o Model prediction:- help update estimates of reliability but are limited and
cannot predict every outcome
o Prototype test:- find out many weaknesses and problems but are time
d

consuming
• Combination of both is mostly used
de

• Standard methods for modeling use formulas based on practical experience of failure
rates and physical knowledge to relate environmental factors to the reliability of
oa

electronic components.
• The failure rate for a component is a generally a base rate modified by various factors
λ = λb πe πq πa ………………………..(1)
nl

Where, λ = failure rate, λb = base failure rate

πe = environmental factor, πq = quality factor
ow

πa = acceleration factor
• Reliability of a component is a function of failure rate:
R(t) = e-λt ……………………..(2)
Where R(t) = Reliability, λ = failure rate, t = time
D

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 Instrumentation II Chapter 7: Circuit Design

• Reliability of a System is a product of all component reliabilities:

n
RSystem =  Ri
i 1
……………………..(3)

Where Rsystem = reliability of the system, Ri = reliability of component

• Most failure rates relate acceleration factors (πe, πq, and πa) to temperature, but not its
applications.

np
• We may consider the application and some of the stresses and susceptibility factors might
affect reliability
– Corrosion, Thermal cracks, Electro migration, Secondary diffusion, Ionizing

u.
radiation, Vibration, High voltage breakdown, Ageing
• These can drastically alter reliability and still not predicted by standard models.

ed
Fault tolerance
• Goes beyond the design and analysis for reliable operation and reduces the possibility of

.
es
dysfunction or damage from abnormal stresses and failures.
• Allows a measure of continued operation in the event of problem
• Three distinct area

ot
– Careful design
– Testable function
– Redundant Architecture

Careful Design
en
io
• Careful design can avoid many failures from abnormal stresses. Some design
techniques that can reduce the probability of failure:
o Reduce overstress from heat with cooling and low dissipation design.
m

o Use optoisolation or transformer coupling to stop overvoltage and leakage

current
fro

o Implement ESD protection

o Mount for shock and vibration
o Tie down wires and cables
d

o Prevent incorrect hookup; Use keyed connector

de

Testable Architecture
• The process of testing and diagnosing failures within a system.
• Two possible configurations of testable architecture:
oa

– Simple Configuration: Provides Probe points / test points for a technician

or instrument to stimulate circuits and record responses. Only the trained
nl

personnel must disassemble the system and remove the circuit for testing.
– Complex Configuration: Dedicated internal circuitry called built in test
ow

(BIT) that tests the system and diagnoses problems without disassembly of
the equipment so adds complexity and reduces reliability. The trade off for
BIT is quicker diagnoses and repair versus higher reliability.
• An appropriate calibration standard is always necessary when you measure a
D

result.

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 Instrumentation II Chapter 7: Circuit Design

Redundant Architecture
The most complex and fault tolerant architecture are redundant architectures. They use
multiple copies of circuitry and software to self check between functions. It is justified
only when downtime for repair and maintenance cannot be tolerated.
• Doubly redundant architecture: merely indicates a failure in one of the subsystems;
this allows for quick repair.

np
• Triply redundant architecture: uses voting between the outputs of three identical
modules to select the correct value. It can have failure and still operate correctly.
• Dissimilar redundancy: compares the output from modules with different software

u.
and hardware to select the correct value. It can survive failure and even indicate
errors in design if one system is coded correctly and the others are not.

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7.3 High speed design

• We should consider transmission line effect when clock of frequency exceeds 1 MHz in a
circuit or system because the harmonics generated by the edges of the clock and signal
pulses can easily be 20 or 30 times the fundamental.
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• Two conservative criteria may be used to estimate when transmission line effect begins

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 Instrumentation II Chapter 7: Circuit Design

– Circuit dimension Vs signal wavelength: If circuit dimension exceed 5% of the

minimum wavelength, then signal path approaches a transmission line i.e. l > λ/20
where, l = length of signal path, λ = maximum wavelength of the signal.
– Rise time Vs propagation delay: If the rise time of a signal is less than 4 times
the propagation delay of the signal path, then the signal path approximates a
transmission line with a characteristic impedance i.e. tr < 4tp where, tr = rise time

np
of signal, tp = propagation delay of the signal path.
• Transmission line problems:- BW, decoupling, ground debounce, crosstalk, impedance
mismatch and timing skew or delay

u.
7.3.1 Bandwidth, Decoupling, ground bounce, cross talk, Impedance matching and timing

ed
Bandwidth
• Limiting the bandwidth of the signals within a system is the most effective way to reduce

.
noise, EMI and problems with transmission lines.

es
• May limit the bandwidth either by increasing the rise or fall times of the signal edges or
by reducing the clock frequency.

ot
• Selecting the appropriate logic family will set the edge rates and the consequent limit on
transmission line concerns.
• One criterion for selecting logic according to transmission line effects is a ratio less than
en
4 between the rise time, tr and the propagation delay, tp i.e. (tr/tp <4).
• Slower edge rates allow longer interconnections between circuits.
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 Instrumentation II Chapter 7: Circuit Design

Decoupling
• Switching of digital logic causes transients of current on the voltage supply through
inductive impedance of the circuit
• Decoupling capacitor minimizes inductive loop area thus reducing impedance of power
supply circuit. Shortest possible path for decoupling capacitor is best.

np
General recommendation for Decoupling:
• Use decoupling capacitor near each chip for two sided board
• Use a large filter capacitor at the power entry point

u.
• Use a ferrite bead at the power entry point to the circuit board

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 Instrumentation II Chapter 7: Circuit Design

Ground Bounce
• Ground bounce is a voltage surge that couples through the ground leads of a chip into non
switching output and injects glitches onto signal lines.
• Asynchronous signals are more prone to ground bounce.
• Can reduce ground bounce by:
o Reducing loop inductance

np
o Reducing input gate capacitance
o Choosing logic families that either control the signal transition or have slower fall
times.

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 Instrumentation II Chapter 7: Circuit Design

Crosstalk
• Coupling electromagnetic energy from an active signal to a passive line
• Coupling mechanism:- capacitive or inductive
• Depends on line spacing, length and characteristic impedance, signal rise times
• To reduce crosstalk:
– Decrease coupling length and characteristic impedance

np
– Increase rise time of signal
– Better layout and design of circuits

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Avoiding Crosstalk
ow

– Don’t run parallel traces for long distances – particularly asynchronous signal
– Increase separation between conductors
– Shield clock lines with ground strips
– Reduce magnetic coupling by reducing the loop area of circuits
D

– Sandwich signal lines between return planes

– Isolate the clock, chip-select, chip-enable, read and write lines

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 Instrumentation II Chapter 7: Circuit Design

Impedance matching
• The reflection coefficient for a signal passing from medium 1 to medium 2 is given by:
τ = (η2 – η1) / (η2 + η1)
Where ηi is the intrinsic impedance of medium i and is given by:
ηi = i / i

np
• Reflection coefficient will be zero when η1 = η2
• Impedance matching makes the source and termination impedance equal to the
characteristic impedance of the transmission line so that it will eliminate the reflections

u.
of signals that cause ringing (oscillations), undershoot, and overshoot in the signal pulses.
• Impedance discontinuities occur in two configurations endpoint and stub.

ed
End point discontinuity: - the ends of the transmission line don’t match its characteristic
impedance of the transmission line.
– Add series resistances at the end until the total impedance equals the line

.
impedance.

es
– Terminate the other end of the signal line from driver.

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Stub discontinuities cause impedance mismatch and signal reflection by connecting multiple
circuits to a single line.
• Each Connection of a stub divides the impedance and splits the power of the signal
D

• Make them very short, even zero to reduce the effect of stub discontinuities
• Good layout and design

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 Instrumentation II Chapter 7: Circuit Design

np
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Timing

ot
• Clock frequency increases, propagation delays, timing skew, and phase jitter (change in
phase) render logic design useless.

en
• Clock signal is skewed or arrived at different propagation delays of the clock signal to
different destinations (propagation delay  different clock signal to arrive at different
time).
io
• Differences in propagation delay of rising and falling edges change the duty cycle of the
signal or shrink/expand it.
• Adequate setup and hold time is required to latch data reliably.
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 Instrumentation II Chapter 7: Circuit Design

Standard data bus and networks

• Data bus or network is required to communicate with other circuit boards or devices
– Bus Architecture
– Serial communication
– Instrumentation and I/O buses
– Back-plane buses

np
• Backbone of design
• Represents a significant portion of system architecture

u.
Bus architecture concerns:
• Drive configuration

ed
– Single ended:-
• uses one trace or signal line for transmitted signal and shares circuit
ground for return signal,

.
• used for shorter paths:- e.g. on PCBs and RS 232 serial lines

es
– Differential:-
• transmits two signals with reversed polarity on two separate lines,

ot
• greater tolerance for noise than single ended as they reject common mode
noise,
• better for long cable
• Terminations en
– Multiple outputs of transistors connected in parallel present a considerable
io
capacitive load and slows the transition time of signal
– Use Scotty diodes which has low series capacitance
• Handshakes
m

– Synchronous buses shares a common clock signal and asynchronous buses use
handshake signals.
fro

7.4 Low power design

• Design practices that reduce power consumption by at least one order of magnitude; in
practice 50% reduction is often acceptable.
d

• Mobile, TV remote controls ,digital multimeter, video cameras, laptops used low power
de

for Portability, Isolation, Battery power and low heat dissipation

• Power is function of frequency, load capacitance, and voltage reduction of any of these
reduce power consumption.
oa

Ppower (P) = f * C * V2 where f is the switching frequency, C is the load capacitance, and V
is the DC supply voltage
• Reduce power by reducing
nl

– Supply voltage
– Clock frequency
ow

– Load capacitance
• These seven guidelines in design will minimize power
1. Lower clock frequency
D

2. Lower supply voltage to digital circuit

3. Shut down unused circuits
4. Sleep mode in case of not used

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 Instrumentation II Chapter 7: Circuit Design

5. Terminate all unused inputs

6. Avoid slow signal transition
7. Make normal state use the lowest current, for instance LEDs should be off

Noise and Error Budgets

• Error 1  Production variation, tolerance of resistors, capacitors

np
• Error 2  Environmental factors e.g. temperature
• Error 3  Noise within each devise
Types of Noise and error budgets:

u.
1) Johnson or Thermal noise
– Has a flat power spectrum and is “white” Gaussian noise

ed
Vnoise (rms) = 4KTRW
Where, K = the Boltzmann constant = 1.38X10-23 J/K
T = absolute temperature (K)

.
es
R = resistance (Ω)
W = bandwidth (Hz)
2) Shot noise

ot
– Is transfer of a quantum of charge and is White and Gaussian noise
Inoise (rms) = 2qIDCW
Where, q = 1.60X10-19 C
IDC = DC current (A)
en
io
W = measurement bandwidth (Hz)
3) Flicker or Pink noise
– Flicker, 1/f or “pink” noise varies with frequency
m

Vnoise (rms) = Vf[0.392 + log10(fhigh/flow)]

Where, Vf = noise at a fixed frequency [V/(Hz)1/2]
fro

fhigh = high frequency corner of bandwidth (Hz)

flow = low frequency corner of bandwidth (Hz)
4) Interference
– Coupling of unwanted energy into a device from outside sources.
d

Vtotal = (V12+V22+ … +Vn2)1/2

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Where, Vtotal = total noise (V)

V1, V2, … , Vn = individual noise components (V)
• Quantization error
oa

SNR = 10 log10 (Vsignal2/Vnoise2)

Where SNR = signal to noise ratio
Vsignal = full scale amplitude of the signal (V)
nl

Vnoise = total noise amplitude of the signal (V)

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 Instrumentation II Chapter 7: Circuit Design

7.5 Reset and power failure detection and interface unit

• All systems should initialize to a known state whenever power is applied
• Reset circuit generates a signal that prevents the generation of unwanted conditions by
the system during power application
• Reset signal
– Forces the processor to begin execution from a fixed memory location where code

np
for initialing system operation is written.
– Sets or clears critical output signals to states that don’t cause undesirable actions
• Reset circuit senses voltage level and generate reset signal when the voltage of power

u.
supply goes below the preset values and the reset signal stays active until the voltage of
the power supply exceed the preset value.

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• E.g. RC network, watchdog timer
• Some system may turn on the battery backup after power failure and also inform the
processor through interrupt.

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• The simple reset circuit as in figure uses the time constants R, C network to set the
desired duration of the reset signal.
• The Schmitt trigger inverter transforms the exponential changing waveform on the input
D

to a signal transition appropriate for logic gates.

• The diode D allows charge to drain off the capacitor if the DC voltage fails, thereby
protecting the inverter from an input voltage higher than its supply voltage.

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 Instrumentation II Chapter 7: Circuit Design

• When pressed, the manual push button shorts the charge on the capacitor to ground to
generate a reset signal so that a user can initialize the operation of the system even while
the supply power is stable.

Interface Unit
• The input to all circuit is some sort of electrical signal

np
• Each signal comes from another circuit, a transducer or a switch.
• Most signals need some preprocessing or conversion before the system can assimilate
them

u.
• E.g. Switch generates logic transitions that bounce when pressed; there is a series of rapid
glitches at the beginning and end of signal pulse.

ed
• It is necessary to design some circuitry to suppress the glitches produced by bounce.
• Also sensors produce continuously changing analog signal that must be converted to
digital logic levels for further processing

.
• You will need to define the types of inputs that you expect the system will receive

es
• Once you know the type of input, you can decide on the necessary circuitry to manipulate
the input signals.

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 Instrumentation II Chapter 7: Circuit Layout

Chapter – 8
Circuit Layout
8.1 Circuits Boards and PCBs
• Technologies available for connecting components and circuits
• Circuit boards combine electronic components and connectors into a functional system

np
through electrical connections and mechanical support.
• Stitch weld, Wire wrap, PCB, Chip on board, Hybrid and MCM
[PCB= Printed Circuit Board, MCM= Multi Chip Module]

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Wire-Wrap
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• Easily change the connections, circuit modifications & corrections.

• Larger circuit boards, require extensive effort
• Less useful for production, suitable for prototype development
D

• Limited in operation to less than 5 or 10 MHz, above which the loop inductances in the
wired connections distort signals.

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 Instrumentation II Chapter 7: Circuit Layout

Stitch Weld
• Connects components with point-to-point wiring on circuit boards much like wire wrap
• Stitch weld ports are shorter and the wire is welded to the pins, not wrapped, results
lower loop inductance and much higher operation (100 MHz).
• Better vibration and shock resistance, more expensive, requires a special welding station.

np
PCB (Printed Circuit Board)
• Etched and plated connections
• Make automated placement and soldering of components possible

u.
• Control impedances more effectively than wire-wrap
• Cost effective, manufacturing edge and reliability

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Single Sided PCB
o Low frequency operation (< 25 KHz)

.
o Signal cross over wire jumpers are used

es
Double Sided PCB

ot
o Signal traces on both sides of the circuit board and plated through vias.
o Can support higher frequency operation if laid out very carefully.

Multilayer PCB en
o A stack of alternate layers of copper-clad laminate or core and prepreg.
io
o 20 to 30 conducting layers laminated together
o Control impedance much more tightly and are absolutely necessary for high
frequency circuits
m

o Through-hole vias penetrate all layers and can connect signals on each layer.
o Buried vias connect traces on two sides of an internal layer
fro

o Blind vias are exposed on one external layer and connect traces on the two sides of
that layer.

MCM (Multi-Chip Module)

d

• Higher level of circuit density by bonding the base die of ICs onto a substrate
de

• Compact packing improves signal speeds and reduces load capacitance

• Expensive to fabricate
oa

8.2 Component Placement

• Affects circuit operation, manufacturing edge, and the probability of design errors.
• General rules:
nl

1) Group high current circuit near the connector to isolate stray currents and near the
edge of the PCB to remove heat.
ow

2) Group high frequency circuits near the connector to reduce path length, crosstalk
and noise.
3) Group low power and low frequency circuits away from high current and high
D

frequency circuits
4) Group analog circuits separately from digital circuits.

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 Instrumentation II Chapter 7: Circuit Layout

• Grouping components and circuits appropriately will reduce crosstalk and noise and will
dissipate heat efficiently.

np
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8.3 Routing Signal Traces

• Poor layout  false triggering of logic
fro

• Due to formation of capacitive and inductive parasites with stubs, vias, IC pins, multiple
loads and traces; setup and hold time violation and transmission delay.

8.3.1 Trace Density, Common Impedance, Distribution of signals and Return,

d

Transmission Line Concerns, Trace Impedance and Matching, and Avoiding

de

Crosstalk

Trace density
oa

– Trade off between greater cost and difficulty in producing the denser circuit
board.
– As you squeeze signal traces together on a board, you can space components
nl

closer and reduce the size of the circuit boards.

– Smaller boards, allowed by higher trace densities, provide flexibility in packaging
ow

your product, reduce the cost of material and may degrade signal integrity.

Common Impedance
D

– Minimize the number of circuits that share the same return path. Voltage drops
(caused by current switching) on the ground line (return path) increase system
noise.
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 Instrumentation II Chapter 7: Circuit Layout

– Common impedance paths cause components to reside at different ground

potentials from one another.
– You can reduce the voltage drops, and hence the noise by lowering effective
impedance
– Unbroken return plane is the best way.
– Choosing the right logic family and using decoupling capacitors will help by

np
reducing the magnitude of current pulses.

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. ed
es
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fro
d
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Distribute signal and return

– Address the issues of return path early in design.
– Long return path can shift the ground potential excessively, decrease noise
oa

margins, and cause false switching.

– If the return is longer than signal, then the current has high inductance path that
cause noise spikes in the ground system.
nl

– Large loops of current have high inductance or impedance and radiated noise is
often proportional to return path impedance and loop area.
ow
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 Instrumentation II Chapter 7: Circuit Layout

np
u.
. ed
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Transmission Line Concerns

– Signal conductors are never ideal transmission lines.
– Characteristic impedance: characteristic impedance Z0 depends on frequency;
d

higher frequencies attenuate more than lower frequencies.

– Dispersion: signals at different frequencies propagate at different speeds.
de

– Propagation delay: can corrupt circuit operation; depends on interconnection

length and signal velocity
– Line resistance, skin effect and dielectric losses: degrade signals and introduce
oa

delay and error into circuit operation.

nl

Trace impedance and impedance matching

– Impedance of signal conductors directly affects circuit operation.
ow

– Low characteristic impedance (Z0) radiates less and is less susceptible to

interference than a circuit with higher impedance.
– Impedance mismatches lead to reflections that can both delay switching and
trigger logic falsely.
D

Reflection Coefficient = (ZL – Z0) / (ZL + Z0)

– Multiple loads have stubs, non-uniform impedance and mismatches that
compromise noise margins.
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 Instrumentation II Chapter 7: Circuit Layout

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 Instrumentation II Chapter 7: Circuit Layout

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 Instrumentation II Chapter 7: Circuit Layout

Avoiding Crosstalk
– Simple guidelines when routing signal to a PCB:
• Don’t run parallel traces for long distances- particularly asynchronous
signals.
• Increase separation between conductors.
• Shield clock lines with guard strips.

np
• Reduce magnetic coupling by reducing the loop area of circuits.
• Sandwich signal lines between return planes to reduce crosstalk.
• Isolate the clock, chip select, chip enable, read and write lines

u.
8.4 Ground, Returns and Shields

ed
• Proper ground and return scheme will shield and suppress most EMI in electronics and
reduce errors caused by noise.

.
• Grounding

es
– Provides reference point for signal.
– Signal reference should be a single point and is as close as possible to the power

ot
entry to the PCB.
– A ground plane connected to the single-point reference will also reduce common
impedance.
en
– Be sure to separate the analog and digital circuits so that current pulses from
digital circuits will not corrupt sensitive analog circuits. Use common ground
io
plane or different planes and connect their ground leads to the single-point
reference.
m

• Distribute power and return carefully

o Address the issues of return path early in design.
fro

o Low impedance and minimum voltage drop within the power distribution of the
PCB is desirable for optimum performance of circuits.
o Reduce the inductive loop area between the powers and return traces.
o Multilayer PCB  with power and return (or ground) planes.
d

o Keep voltage drop less than 2% in the distribution of circuits.

de

• Shielding
o A return plane is the most effective shield for any circuit.
oa

o Power and return planes provide circuit paths with the lowest impedance, which
reduces radiation, noise and crosstalk.
o Minimizing spacing between power and return will minimize impedance
nl

(radiation and susceptibility)

Z0 = (120π/ Er ) . (h/d)
ow

Where, h = separation of planes

d = smaller dimension of two-dimensional plane
Er = dielectric constant of substrate board relative to air
D

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 Instrumentation II Chapter 7: Circuit Layout

np
u.
. ed
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io
m

•
fro

Guidelines for effective shield

– Use power and return planes with minimum separation.
– Place decoupling capacitors near (or in) IC packages.
– Don’t disrupt the power and return planes with slots or traces
d

– Route digital traces over digital return.

– Route analog traces over analog return.
de

– Fill the regions between analog traces with copper foil and connect to ground.
oa
nl
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 Instrumentation II Chapter 7: Circuit Layout

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. ed
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8.5 Cables and Connectors

• Connectors are the mechanical and electrical interface between cable and a circuit board.
oa

• Shape or keying polarizes a connector so that it cannot be plugged in the wrong way.
• Reduce flexing of cables.
•
nl

Some guideline for connectors and cables:

1) Pre-assign connector ground pins
ow

2) Distribute and intersperse grounds (return paths)

3) Place clock next to a ground line
4) Minimize I/O
5) Use long rise and fall times to reduce high frequency harmonics
D

6) Keep current to less than 1 amp per connector pin; otherwise use multiple pins or
special pins or special pins with large current capacity.

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 Instrumentation II Chapter 7: Circuit Layout

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8.6 Testing and Maintenance

• Refer chapter 9
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 Instrumentation II Chapter 9: Software for instrumentation and control applications

Chapter – 9
Software for instrumentation and control applications
• Software is pervasive in electronic products such as televisions, video recorders, remote
controls, microwave ovens, sewing machines, and cloth washers all have embedded
microcontrollers.

np
• Software accounts for 50-75 percent of a microcontroller project.
• General methods to improve software are code generation, reliability, maintainability and

u.
correctness.

ed
9.1 Types of software, Selection and Purchase
Types of software
Software is found in many different types of systems such as real-time control, data processing

.
systems like payroll, and graphical systems such as games and CAD. Software can be divided

es
into following types:
• System Software
– Operating system, System drivers, Firmware etc.

ot
• Programming Software
– Compiler, Debugger, Interpreter, Linker, Text editor etc.
• Application Software
en
– Industrial / Business automation, User interface, Games / Simulating software,
Database, Image editing, Auto CAD, word processor etc.
io
Compiler versus Interpreter
m

Compiler Interpreter

Source Code  Executable Code  Source Code  Intermediate Code 

fro

Machine

Lots of time is spent in analyzing and Relatively little time than compiler
d

processing the program.

de

Result  Executable in form of machine Result  Some sort of intermediate code

specific binary code.
oa

Computer (Hardware) interprets (executes) Resulting code is interpreted by another

the resulting code. program e.g. Java Virtual machine in Java.
nl

Program execution is relatively faster. Program execution is relatively slower.

ow

Not required extra program to execute the Requires extra program to execute
code. intermediate code.

Standalone code Not standalone code

D

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 Instrumentation II Chapter 9: Software for instrumentation and control applications

Processed to develop software

1. Algorithms
• List of instructions or recipes for action
• Algorithms describe the general actions to be taken and consequently are independent of
the specific programming language.
• Algorithms have the greatest effect on the utility, success, and failure of software

np
• Data structures provide another way of designing the processing architecture.
• Make a habit of collecting algorithms for your future programming efforts; when crisis
hits, there will be no time for research.

u.
• Understand each algorithm, its limitations and its boundary conditions
• Jack Ganssle writes: “It’s ludicrous that we software people reinvent the wheel with

ed
every project… Wise programmers make an ongoing effort to built an arsenal of tools for
current and future project…. Make an investment in collecting algorithms for future use.
When a crisis hits there is no time to begin research.”

.
es
2. Languages
• Software has many applications within embedded systems such as Firmware, Peripheral

ot
interface and drivers, Operating system, User interface, Application programs etc.
• May use variety of languages
• Assembly language

Assembly Language
en
• High level language: Basic, C, C++, Java etc.
High Level Language
io
Processor Architecture dependent and Processor Architecture Independent
closer to hardware.
m

Tedious because it requires steadfast Easier due to nitty-gritty details, structure and
fro

attention to exacting detail. readability.

Best suited for small, simple projects Better for larger, more complex projects
with minimum memory, highest which require more memory and execute the
d

execution speed & precise control of code more slowly.

peripheral devices.
de

3. Methods
• Whatever language you choose, your objective will be to reduce complexity and improve
oa

understanding of the software.

• Design architecture may be Structured or Object oriented or CASE (Computer aided
nl

software engineering)
• Structured designs have strategy before starting to code; small modules with clear
ow

operational flow, easy debugging and testing.

• OOP can help by incorporating data abstractions, information hiding and modularity to
aid structured design.
• CASE tools provide blend of environment, tools and language.
D

• Tools available are compilers, disassemblers, debuggers, emulators, monitors and logic
analysers.
• Operating system and software libraries ease the task.
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 Instrumentation II Chapter 9: Software for instrumentation and control applications

4. Selection
• The selection of a particular language depends on management directives, the knowledge
and expertise of the software team, hardware and available tools.
• Function and performance depends on the speed and data path width of processor,
memory (RAM and ROM), architectural features such as coprocessors, peripherals
(ADC, timers, PWM, interrupt handlers), I/O communications, power-down modes and

np
the level of integration.
• Choice of language also depends on manufacturers having following questions
o Does the vendor provide reasonable documentation and support?

u.
o Does it provide toll-free telephone support and acknowledge application
engineers?

ed
o Does it have liability support for life-critical systems.

5. Purchase

.
• Purchase the software after you have defined your software requirements and surveyed

es
vendors for availability, reputation and experience.
• Some qualification of a vendor:

ot
o Acceptance testing
o Review of vendor’s quality assurance
o Verification testing
o Qualification report en
• Furthermore, required documentations from a vendor:
io
o Requirement specification
o Interface specification
o Test plans, procedures, results
m

o Configuration management plan

o Hazard analysis
fro

• Don’t buy cheap software tools just to save money! You will lose much more money in
the long run from wasted time forced by delays and inadequacies of cheap tools.

9.2 Software Models and Their Limitations

d

1. Traditional software lifecycle / Waterfall Model

de

• Over the years many models have been proposed to deal with the problems of defining
the critical activities and tying them together
• The first formally defined software life cycle model was the waterfall model [Royce
oa

1970]
• The waterfall model is a software development model in which the results of one activity
flowed sequentially into the next as seen as flowing steadily downwards (like a water)
nl

through different phases.

• Water cascades from one stage down to the next, in stately, lockstep, glorious order.
ow

– gravity only allows the waterfall to go downstream; it’s hard to swim upstream
• The US Department of Defense contracts prescribed this model for software deliverables
for many years, in DOD Standard 2167-A.
D

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 Instrumentation II Chapter 9: Software for instrumentation and control applications

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Quality Assurance
m

• Oversees each steps of model towards producing useful, reliable software rather than
connection of modules
fro

• Methods are necessary but not sufficient to produce useful, reliable software.
• First: Classify your system and its software according to any relevant standards.
• Second: Software development plan:
d

o Hazard and fault tree analysis for life critical functions

o Configuration management: ensures current and correct version is released.
de

o Documentation
o Traceability
oa

Concept & Analysis:

• Problem described in human language.
• Model the concept with mathematical formulas and algorithms.
nl

• Analyze the software within the framework of the system description and concept.
• Analyse on the interactions and interfaces between the software, the hardware and data
ow

inputs.
• Analyze should concentrate on where most problem occurs which include:
o technical tradeoff
D

o performance timing
o human factor
o hazard and risk analysis
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 Instrumentation II Chapter 9: Software for instrumentation and control applications

o Fault tree analysis: Graphical model of sequential and concurrent events

that leads to failure of problems

Requirements
• Reduce the abstract intentions of the customer into realizable constraints.
• Tells what the software does

np
• Includes standards that the software must adhere to, the development process, the
constraints, and reliability or fault tolerance
• Requirements may call for several, successive specifications:

u.
o General specification
o Functional performance specification

ed
o Requirements specification
o Design specification
• Needs constraints considerations such as memory, timing margin, hardware,

.
communication, I/O and execution speed;

es
• Will the selected processor and associated hardware support the requirements?
• Can the software use these resources and satisfy the requirements.

ot
Design
• Design tells how the software does its functioning.
en
• Specifies how the software will fulfill the requirements.
• Consider these software elements in preparing the design:
io
o System preparation and setup
o Operating system and procedures
o Communication and I/O
m

o Monitoring procedures
o Fault recovery and special procedures
fro

o Diagnostics features
• Interfaces demands most attention communication format:
o Polled I/O
o Interrupt I/O
d

o Synchronization between tasks

de

o Intertask signaling
o Communications of polling and queuing to avoid overrunning events
• Design can specify algorithms and techniques that optimize performance, management of
oa

memory.
• Design may reuse modules and libraries in an effort to improve productivity and
reliability.
nl

Programming
ow

• The methods of programming – assembly language, high level languages.

• CASE tools are on the horizon
• Tools, language, methods
D

Source file (Assembly language mnemonics)  assembler  object file  linker  Binary
machine code  Burn  PROM

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 Instrumentation II Chapter 9: Software for instrumentation and control applications

Testing
A) Internal reviews
• By colleagues examine the correctness of software and can figure out mistakes and error
in logic
• More than 50% of errors, can be found and correct by code inspection or audit

np
B) Black box testing:
• To ensure that input and output interfaces are functioning correctly without concerning

u.
what happens in software.
• Ensures the integrity of the information flow.

ed
C) White box testing:
• Exercises all logical decisions and functional path within a software module.

.
• Requires intimate knowledge of software module

es
• Useful for determining bugs on special case
• Exhaustive testing is impossible; may take 100 of years to test each and every possible

ot
combination

D) Alpha and Beta testing:

• Type of black box testing in actual environmenten
o Alpha testing - programmer collaborate with user
io
o Beta testing - user isolated from programmer

Verification
m

• Debuggers, logic analyzer, in circuit analyzer in circuit debugger etc.

fro

Maintenance:
• Require to control the software configurations: reports, measurement, personnel costs and
documentation
• Plans for releasing software upgrades, to achieve consistency and continuity of the
d

product.
de

• Cannot separate software maintenance from system concern

Disadvantages of Waterfall Model:

oa

• Traditional view of software development

• Develop each component sequentially
• Not iterative - difficult to climb up the waterfall
nl

• Focused on software rather than work design

• One phase is completed, documented and signed off before next phase for quality
ow

assurance
• Difficult to respond to changing customer requirement
• Software only available at late development schedule
D

• Based on hardware engineering model widely used in defense/aerospace

• Waterfall develops each component sequentially and usually does not iterate through
more than a stage. In reality software seldom develops according to that model.

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 Instrumentation II Chapter 9: Software for instrumentation and control applications

Benefits of Waterfall Model

• Managers love waterfall models
• Minimizes change, maximizes predictability
• Costs and risks are more predictable
• Highly documented
• Can be used for the projects whose requirements will not changeable

np
• Each stage has milestones and deliverables: project managers can use to gauge how close
project is to completion
• Sets up division of labor: many software shops associate different people with different

u.
stages:
– Systems analyst does analysis,

ed
– Architect does design,
– Programmers code,
– Testers validate, etc.

.
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Problems with Waterfall Model
• Offers no insight into how each activity transforms artifacts (documents) of one stage

ot
into another
• Fails to treat software a problem-solving process
– Unlike hardware, software development is not a manufacturing but a creative
process en
– Manufacturing processes really can be linear sequences, but creative processes
io
usually involve back-and-forth activities such as revisions
– Software development involves a lot of communication between various human
stakeholders
m

• Complex documentation requires highly profiled manpower

• Cannot be used for changing requirements
fro

• Nevertheless, more complex models often embellish the waterfall,

– incorporating feedback loops and additional activities

2. Prototyping Model
d

• In this model the developer and client interact to establish the requirements of the
de

software.
• Accommodates the problem of changing requirements and make a subset of the software
available early.
oa

• Essence of prototyping is a quickly designed model that can undergo immediate

evaluation.
• Define the broad set of objectives.
nl

• This is follow up by the quick design, in which the visible elements of the software, the
input and the output are designed.
ow

• The quick design stresses the client’s view of the software.

• The final product of the design is a prototype.
• The client then evaluates the prototype and provides its recommendations and suggestion
D

to the analyst.
• The process continues in an iterative manner until the all the user requirements are met.
• Accommodates problem of changing requirements

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 Instrumentation II Chapter 9: Software for instrumentation and control applications

• Helps to identify missing client requirements

• A prototype may take one of three forms
o A paper model or computer based simulation
o A program with a subset of functions
o An existing program with other features that will be modified for your product.

np
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en
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Advantages of Prototyping Model
The following are the advantages of Prototyping model:
• Due the interaction between the client and developer right from the beginning, the
m

objectives and requirements of the software is well established.

• Suitable for the projects when client has not clear idea about his requirements.
fro

• The client can provide its input during development of the prototype.
• The prototype serves as an aid for the development of the final product.

Disadvantages of Prototyping Model

d

The prototyping model has the following disadvantages.

de

• The quality of the software development is compromised in the rush to present a working
version of the software to the client.
• The clients looks at the working version of the product at the outset and expect the final
oa

version of the product to be deliver immediately. This cause additional pressure over the
developers to adopt shortcut in order to meet the final product deadline.
• It becomes difficult for the developer to convince the client as why the prototype has to
nl

be discarded.
• Sometimes prototype ends as final product which result in quality + maintenance
ow

problem
• Client may divert attention solely to interface issue
• Testing + documentation forgotten
D

• Designer tends to rush product to market without considering long term reliability,
maintenance, configuration control

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 Instrumentation II Chapter 9: Software for instrumentation and control applications

• Creeping featurism: The customer voices new desires after each evolution, and the
project effort balloons.

3. Spiral Model
• Uses incremental approach to development that provides a combination of waterfall and
prototyping model.

np
• Each cycle around the development spiral provides a successively more complete version
of the software.
• Model allows flexibility to manage requirements control changes

u.
• Used in proprietary application
• Spiral Model – risk driven rather than document driven

ed
• The "risk" inherent in an activity is a measure of the uncertainty of the outcome of that
activity
• High-risk activities cause schedule and cost overruns

.
• Risk is related to the amount and quality of available information. The less information,

es
the higher the risk

ot
en
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m
fro
d
de

Spiral Model Strengths

– Introduces risk management
– Prototyping controls costs
oa

– Evolutionary development
– Release builds for beta testing
– Marketing advantage
nl

Spiral Model Weaknesses

– Lack of risk management experience
ow

– Lack of milestones
– Management is dubious of spiral process
– Change in Management
D

– Prototype Vs Production

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 Instrumentation II Chapter 9: Software for instrumentation and control applications

Metrics
• Objective understanding of the completion of the software at each stage or of its
usefulness
• Software size, development time, personnel requirements, productivity, and number of
defects all interrelate metric can define those relationships
• Cost and schedule are very poor metrics for producing quality software

np
• To rely on your estimates, you need to track the metrics honestly and record them
carefully & consistently
• Good process model needs metrics to access performance and progress of software

u.
– Correctness, Reliability, Efficiency, Maintainability, Flexibility, Testability,
Portability, Reuse, Utility, Size etc.

ed
Process
• Process incorporate models of software development to generate useful, reliable and

.
maintainable software

es
• Good process keeps statistics for feedback & improvement of the software development
• Software tools are integral to the software process; don’t change them in midstream.

ot
• Process maturity levels defined by the software engineering institute:
1) Initial: Chaos or ad hoc process
2) Repeatable: Design & Management defined
en
3) Defined: Fully defined & enforced technical practices
4) Managed Process: Feedback that detects and prevents problems, a control process
io
5) Optimizing Process: Automating, monitoring & introducing new technologies

Software Limitations
m

• Not all problems can be solved

• Specifications cannot anticipate all possible uses and problems
fro

• Errors creep into development in a number of ways

• Software simulation can predict only known outcomes
• Human error can occur in operating the software
d

9.3 Software Reliability

de

• Reliability is a broad concept.

– It is applied whenever we expect something to behave in a certain way.
• Reliability is one of the metrics that are used to measure quality.
oa

• It is a user-oriented quality factor relating to system operation.

– Intuitively, if the users of a system rarely experience failure, the system is
considered to be more reliable than one that fails more often.
nl

• A system without faults is considered to be highly reliable.

– Constructing a correct system is a difficult task.
ow

– Even an incorrect system may be considered to be reliable if the frequency of

failure is “acceptable.”
• Key concepts in discussing reliability:
D

– Fault
– Failure
– Time

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 Instrumentation II Chapter 9: Software for instrumentation and control applications

• Reliability develops complete plan

• Understands nature of bugs, their introduction and removal.

Guidelines to write reliable software

• Make each module independent
• Reduce the complexity of each task

np
• Isolate tasks from influences, both hardware and timing
• Communicate through a single well-defined interface between tasks

u.
9.4 Fault Tolerance
• Fault tolerance concerns safety and operational uptime, not reliability.

ed
• It defines how a system prevents or responds to bugs, errors, faults or failures.
• Use
– Check sums on blocks of memory to detect bit flips

.
– Watchdog timer: h/w that monitors a system characteristic to check the control

es
flow and signals the processor with logic pulse when it detect fault.
– Roll-Back-Recovery or Roll-Forward-Recovery

ot
– Careful design
– Redundant architecture

9.5 Software Bugs and Testing

Phases of bugs
en
io
1. Intent
2. Translation
3. Execution
m

4. Operation
fro

Intent
o Wrong assumption +misunderstanding
o Correctly solving wrong problems
o Viruses
d

o Slang-limits of operation to broadly or too narrowly defined

de

Translation
o Incorrect algorithm
oa

o Incorrect analysis
o Misinterpretation
nl

Execution
o Semantic error –does not know how command works
ow

o Syntax error- rules of language

o Logic error- using wrong decision
o Range error-overflow /underflow error
D

o truncation error- incorrect rounding

o Data error –not initialing values, wrong error etc
o Language misuse-inefficient coding

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 Instrumentation II Chapter 9: Software for instrumentation and control applications

o Documentation-wrong/misleading comments

Operation
o Changing paradigm
o Interface error
o Performance

np
o Hardware error
o Human error

u.
Debugging
• Print statement

ed
• Break points and watch values
• In circuit emulators ,in circuit debugger
• Logic analyzer

.
• White box testing

es
• Black box testing
• Grey Box testing

ot
o Having knowledge of internal data structure & algorithm for purpose of designing
test case but testing is black box
o Used in reverse engineering to determine instance, boundary value

Testing Levels
en
io
• Unit test
o To test functionality of specific section of code at functional level
o Building blocks work independently of each other
m

o E.g. Class level testing in OOP

• Integration test
fro

o To verify interface between components

• System test
o To test the whole system which is to be used
d

9.6 Good Programming Practice

de

• For useful, reliable, maintainable program we must make them readable and
understandable. Good design and programming practices can make programs more
readable.
oa

A) Style and format

• program- to do something
nl

- To communicate designer’s intent to other structure of program and comment.

Design:
ow

• Documentation form begin

• Pseudocode before program
• Keep routine short
D

• Write clearly: don’t sacrifice clarity for efficiency

• Make routine right, clear, simple and correct before making it faster

Compiled By: Er. Hari Aryal [[email protected]] Reference: K. R. Fowler | 12

 Instrumentation II Chapter 9: Software for instrumentation and control applications

Comments:
• Readable and clear
• Should not be paraphrase of code
• Should be correct (incorrect comments are worse than no comment)
• Comment more than you think you need
Variables:

np
• Name properly
• Minimize use of global variables
• Don’t pass pointer

u.
• Pass intact values

ed
B) Structured Programming
• Establish framework for generating code that is more readable useful, reliable
and maintainable.

.
• Framework based on clearly defined modules or procedures, each doing one

es
task well in a variety of situations.
• Modules can isolate device dependent code for simplicity and reuse.

ot
• Large modules: divide among team for more productive and parallel effort.
• Use of libraries of modules and procedures load faster and resist inadvertent
changes
en
• Structure programming encourages the installation and testing of one module
at a time to simplify the verification of the software.
io
Points to be noted
• 90% of processor time is spent in executing 10% of code. Identify this 1%.
m

• Listen to customer while developing specification

• Prototype complex task on host computer and investigate their behavior.
fro

• Design architecture for debugging and testing.

• Code small modules so that you can test and forget
• Code single entry and exit in routine
• Document carefully
d
de

C) Coupling and Cohesion

• Define tasks and design the modules.
• Modules should have a minimum of coupling or communication. If two tasks or
oa

processes communicate heavily, they should reside in the same module.

• Cohesion means everything within a module should be closely related that is they should
stick together.
nl

Cohesion:
ow

• A cohesive module performs a single task

• Modules should have maximum cohesion
• Different levels of cohesion
D

– Coincidental, logical, temporal, procedural, communications, sequential,

functional
• Coincidental Cohesion

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 Instrumentation II Chapter 9: Software for instrumentation and control applications

– Occurs when modules are grouped together for no reason at all

• Logical Cohesion
– Modules have a logical cohesion, but no actual connection in data and control
• Temporal Cohesion
– Modules are bound together because they must be used at approximately the same
time

np
• Communication Cohesion
– Modules grouped together because they access the same Input/Output devices
• Sequential Cohesion

u.
– Elements in a module are linked together by the necessity to be activated in a
particular order

ed
• Functional Cohesion
– All elements of a module relate to the performance of a single function

.
Coupling:

es
• Coupling describes the interconnection among modules
• Modules should have minimum Communication or coupling

ot
• Data coupling
– Occurs when one module passes local data values to another as parameters
• Stamp coupling
en
– Occurs when part of a data structure is passed to another module as a parameter
• Control Coupling
io
– Occurs when control parameters are passed between modules
• Common Coupling
– Occurs when multiple modules access common data areas such as Fortran
m

Common or C extern
• Content Coupling
fro

– Occurs when a module data in another module

• Subclass Coupling
– The coupling that a class has with its parent class
d

D) Documentation and Source Control

de

• Documentation describes the overall system function.

• Documentation: first to begin and last to finish ensuring completeness and veracity.
• Back up source files: disks, CD, tape drivers
oa

• Store multiple copies in separate location

• File storage is cheap but reconstructing lost data is expensive and impossible.
nl

E) Scheduling
• Should record all efforts expended in current jobs to estimate future job
ow

• Timing of meeting, planning, designing, debugging testing should be properly planned

• Give more time than required to debugging and testing.
D

Compiled By: Er. Hari Aryal [[email protected]] Reference: K. R. Fowler | 14

 Instrumentation II Chapter 9: Software for instrumentation and control applications

9.7 User Interface

• The user interface is a major concern from a system viewpoint, and software plays a
principal role in the interface.
• Good user interfaces require extraordinary attention to detail.
• The use interface can make or break an instrument; for instance, half of all hospital
accidents are due to improper use of correctly operating equipment.

np
• Strangely, the higher the cost of the equipment, the lower the quality of the human-
interface design.
• Common design issues for a user interface include response time, error handling and help

u.
facilities.
• The response time should have a reasonable interval and consistent variation application

ed
to the task.
• Error handling should be clear and give remedial action.
• Help facilities should be on line and context sensitive.

.
• Command sequences should be useful and consistent.

es
User Interface Guidelines

ot
Action or Concern Comments
Tune dialogue to user Make it smooth and consistent. Use logical

Make error messages meaningful

Provide help facilities
en
rather than visual thinking.
Let the user know what is going on
Let the user know what is going on
io
Verify critical actions Help user understand consequences
Permit reversal of actions Forgive mistakes
Reduce memory load Don’t compromise simple operations by
m

extending them for infrequent ones

Display only relevant information Remove static or redundant information
fro

Deactivate commands Fade out or clear from screen unused

Use good layout techniques Use a modular format
d

User Interface Development

• Storyboarding and rapid prototyping are particularly suited for developing user interfaces
de

because they are informal and fast.

• Try to develop the user interface with a top-down approach prototype which can take any
of three forms
oa

o A paper prototype depicting user interaction

o A working prototype with a subset of functions
o An existing program that has all features but needs modification
nl

• Creeping featurism can sidetrack development because prototyping concentrates on short

ow

term results and can miss long term concerns that may require substantial reworking in
the future.
• Finally, you need cooperation from both customer and management.
• Management must support the goal of prototyping and effect of development schedule
D

• Customer must be committed to both evaluation and refinement of the prototype.

Compiled By: Er. Hari Aryal [[email protected]] Reference: K. R. Fowler | 15

 Instrumentation II Chapter 9: Software for instrumentation and control applications

9.8 Embedded and Real Time Software

• Most of the software that runs or controls instruments is embedded and real time
software.
• Real-time software is code that responds to current events in a timely manner.
• Embedded software is hardware specific; often a user interacts with a portion of the
software system but does not have complete control over the source code.

np
• Software design concerns with occurrence and loading.
• Occurrence is the timing of events in real-time software. Events occur either
synchronously and asynchronously.

u.
• Loading is the measure of processor capacity; two metrics are utilization (amount of
processing) and throughput (no. of I/O operations).

ed
• Real time software has two components  operating system and device driver.
• Real time operating system (RTOS) controls the flow of events in priority scheduling
mechanism.

.
• Performance, fault tolerance, and reliability are major concerns for embedded software

es
which has following metrics:
o Execution speed of the processor

ot
o Response time of the system
o Data transfer rate

•
o Memory size en
o Interrupt handling: context switching and interrupt latency

Performance can measure with time I/O bus signals with an oscilloscope, logic analyzer,
io
or performance analyzer.
• Fault tolerance defines how the software deals with misused resources and outright errors
with various degrees as:
m

o Limit on downtime of the system

o Absence of catastrophic errors
fro

o Predictableness
o Robustness
• Some types of failure that affect reliability include missed or incomplete tasks, deadlock,
spurious interrupts, and stack overflow.
d
de
oa
nl
ow
D

Compiled By: Er. Hari Aryal [[email protected]] Reference: K. R. Fowler | 16

 Instrumentation II Chapter 9: Software for instrumentation and control applications

Chapter - 10

Case Study
Examples chosen from local industrial situations with particular attention paid to the basic
measurement requirements, accuracy, and specific hardware employed environmental

np
conditions under which the instruments must operate, signal processing and transmission,
output devices:

u.
a) Instrumentation for a power station including all electrical and non-electrical parameters.

ed
b) Instrumentation for a wire and cable manufacturing and bottling plant
c) Instrumentation for a beverage manufacturing and bottling plant
d) Instrumentation for a complete textile plant; for example, a cotton foil from raw cotton

.
through to finished dyed fabric.

es
e) Instrumentation for a process; for example, an oil seed processing plant from raw seeds
through to packaged edible oil product.
f) Instruments required for a biomedical application such as a medical clinic or hospital.

ot
g) Other industries can be selected with the consent of the subject teacher.

Preliminary
en
1. All students must team up for the case study and it is recommended to form a group of four
to six students in a group. Once formed, the group cannot be reshuffled.
io
2. The group will take a request letter from the department. However, before approaching to an
organization, students need to bring the responsible person’s name and post for issuing the
letter. The letter must be addressed accordingly.
m

3. The duration for the case study is for a month from the date of presentation. You need to
submit the report. Apart from the new recommended design, you need to present the cost
fro

benefit analysis of the project.

During Visit
1. You need to understand the current process control system of the visited organization and
d

describe the same in your own word in the report. List all the variables that are included in
de

the process control system.

2. The systematic approach to understand the system must be presented with necessary block
and detailing diagrams, if it is required.
oa

3. Interview managers and the personnel who are directly involved in the current system and get
to know the merits and demerits of the system.
4. Learn more from users and consumers who are directly participating and using the product of
nl

the visited organization. Comment on the product and recommend better option for the
product in the present context, if you feel its need.
ow

5. List down all the requirements needed to go for the improvised system.
6. Mention the cost of the current system.
7. Compare it to the latest system available in the market.
D

Compiled By: Er. Hari Aryal [[email protected]] Reference: K. R. Fowler | 17

 Instrumentation II Chapter 9: Software for instrumentation and control applications

After Visit
1. Think and recommend the extra mechanism to provide a better solution the current problem.
2. Draw the block diagram of the newly recommended system. How does the current system
adjusts the demerits discussed in item no 3 of during visit.
3. Include how the cost varies and what additional benefit you get with the newly proposed

np
system in place.
4. Did you face a difficulty to go for the case study? How do you relate this with the real life
situation?

u.
5. Recommend what you feel like.
6. On the basis of above prepare a report on the case study.

ed
The final report should present the instrumentation requirements in terms of engineering
specifications, the hardware solution suggested, a listing of the particular devices chosen to satisfy

.
the requirements, appropriate system flow diagrams, wiring diagrams, etc. to show how the system

es
would be connected and operated.

ot
en
io
m
fro
d
de
oa
nl
ow
D

Compiled By: Er. Hari Aryal [[email protected]] Reference: K. R. Fowler | 18

 Instrumentation II Chapter 10 - Case Study

Chapter - 10

Case Study
Examples chosen from local industrial situations with particular attention paid to the basic
measurement requirements, accuracy, and specific hardware employed environmental
conditions under which the instruments must operate, signal processing and transmission,

p
output devices:

.n
a) Instrumentation for a power station including all electrical and non-electrical
parameters.

du
b) Instrumentation for a wire and cable manufacturing and bottling plant
c) Instrumentation for a beverage manufacturing and bottling plant
d) Instrumentation for a complete textile plant; for example, a cotton foil from raw

.e
cotton through to finished dyed fabric.
e) Instrumentation for a process; for example, an oil seed processing plant from raw

es
seeds through to packaged edible oil product.
f) Instruments required for a biomedical application such as a medical clinic or hospital.

ot
g) Other industries can be selected with the consent of the subject teacher.

Preliminary
en
1. All students must team up for the case study and it is recommended to form a group of
four to six students in a group. Once formed, the group cannot be reshuffled.
2. The group will take a request letter from the department. However, before approaching to
io
an organization, students need to bring the responsible person’s name and post for issuing
the letter. The letter must be addressed accordingly.
m

3. The duration for the case study is for a month from the date of presentation. You need to
submit the report. Apart from the new recommended design, you need to present the cost
benefit analysis of the project.
fro

During Visit
1. You need to understand the current process control system of the visited organization and
d

describe the same in your own word in the report. List all the variables that are included
in the process control system.
de

2. The systematic approach to understand the system must be presented with necessary
block and detailing diagrams, if it is required.
3. Interview managers and the personnel who are directly involved in the current system and
oa

get to know the merits and demerits of the system.

4. Learn more from users and consumers who are directly participating and using the
product of the visited organization. Comment on the product and recommend better
nl

option for the product in the present context, if you feel its need.
5. List down all the requirements needed to go for the improvised system.
ow

6. Mention the cost of the current system.

7. Compare it to the latest system available in the market.
D

1
 Instrumentation II Chapter 10 - Case Study

After Visit
1. Think and recommend the extra mechanism to provide a better solution the current
problem.
2. Draw the block diagram of the newly recommended system. How does the current system
adjusts the demerits discussed in item no 3 of during visit.
3. Include how the cost varies and what additional benefit you get with the newly proposed
system in place.
4. Did you face a difficulty to go for the case study? How do you relate this with the real life

p
situation?
5. Recommend what you feel like.

.n
6. On the basis of above prepare a report on the case study.

du
The final report should present the instrumentation requirements in terms of engineering
specifications, the hardware solution suggested, a listing of the particular devices chosen to
satisfy the requirements, appropriate system flow diagrams, wiring diagrams, etc. to show how

.e
the system would be connected and operated.

es
Below is given a sample case study.

ot
en
io
m
fro
d
de
oa
nl
ow
D

2
 Instrumentation II Chapter 10 - Case Study

Abstract

The course of Instrumentation II is essentially related to design issues an electronics engineer faces
in his/her career. The design we perform on classes and labs are not adequate as they don’t involve
the rightful applications. Thus we have been asked to conduct a case study on a production industry
related to our field and view how actual design principles are in practice.

p
.n
This report presents an overview of the practical applications of electronics in Bottler’s Nepal Pvt.
Ltd. There is nothing such as perfect in real world. Thus, we are proposing some modification in the

du
plant to improve its production capacity efficiently.

.e
We are not boasting that our proposed design is more faultless than the current one. As every coin

es
has two sides the proposed design can also have its own flaws along with the new efficiency.
However, being an Electronics Engineer we believe that our proposed design can improve the

ot
efficiency of the existing plant.
en
io
m
fro
d
de
oa
nl
ow
D

3
 Instrumentation II Chapter 10 - Case Study

Introduction

Coca-cola, imported from India, was, first introduced into Nepal in 1973, with local production of
coca-cola beginning in 1979.

Bottlers Nepal Limited (BNL) is the only bottler of Coca-cola products in Nepal, and has two bottling
plants; namely Kathmandu (Bottlers Nepal Limited- BNL) and Bharatpur (Bottlers Nepal (Terai)
Limited which is 160km from Kathmandu, its capital.

p
.n
Coca-cola sabco operates in seven southern and East African countries and five Asian countries, and
employs more than 9500 people. It operates 25 bottling plants and aims to fulfill the refreshment

du
needs of more than 240 million consumers that live in its markets. It is a proud developing markets
Anchor bottler.

.e
Objectives of case study

es
The main objective of doing case study is to get acquainted about use instrumentation in real field.
So we research about the application of different designs of electronics. We were guided to find any
problems in the existing plant and propose a design to solve the problem. So in our case we propose

ot
a design to solve problems related to operation and manufacturing of coca cola.
en
Hence the main objective of our visit can be summarized as following:

 To visit the chosen organization and learn its operation under supervision of senior
io
engineers and technicians.
 To study the existing management system and technology of company.

m

To be familiar with various engineering aspects demanded by that particular company.

 To learn the vital role of engineer in a particular company.
fro

 To learn about electronics design using microcontroller and microprocessor in commercial

field. To observe the current system carefully and detect any fault in existing system if any.
 To propose solutions to boost the efficiency of the system.
d

The processing plant of coca-cola company has been installed in Balaju industrial state several years
de

ago. All the processing plants are being closely monitored by Nepal ease technicians and engineers.
The plant has been working smoothly.
oa

Process of manufacturing:
1. Preparation of bottles and cans.
2. Chemicals
nl

3. Machinery Equipments
4. Computers
ow

1. Preparation of bottles and cans: The pre-form for preparing Bottles are imported
from India where as the pre-form for the PET bottles are manufactured in Bhutan
D

and blown in Nepal using Blow Mold machine which outputs bottle and cans. The
associated label is imported from India.

4
 Instrumentation II Chapter 10 - Case Study

2. Chemicals: The flavor used for the production of beverage is imported from South
Africa and sugar from Dubai (U.A.E). The sugar required is of the quality prescribed
by the company.
As coca-cola company is primarily a private owned company, has an obligation to fulfill
various criteria for most of its work. The effect is seen in the procurement of materials and
machines. The department, either mechanical, electrical or AC section identifies need for
necessary equipments and prepares a report bases in it and forward it to material and

p
management Department. The material management then seeks for the bidders and buys

.n
the needed materials and equipments in accordance with company rule and policy.
Generally, the bidder with equipments meeting all the required specification as produced

du
the coca-cola company and low in price obtains the tender to sell the equipments to
company. Then material management department forwards the equipments to the
departments that for material.

.e
There are various operations implemented during the production and distribution of the
products. They are

es
 Collection of bottles from every part of the country.
 Cleaning of the bottles with water jet.

ot
 Testing of bottles for unwanted materials (EBI).
 Mixing of the ingredients in a proportion prescribed by coca-cola company
(Atlanta).
en
 Automatic time controlled filling.
 Automatic capping.
io
 Automatic Date coding.
 COLLECTION OF BOTTLES:
m

Initially the empty bottles are collected from the retailers by the dealers.
Now the bottles are brought to the company’s depot from the dealers.
fro

Further these bottles are fed to the plant for the next process.

 EBI(ELECTRONIC BOTTLE INDICATOR)TEST

d

The bottles are now cleaned by keeping the bottle in various positions and striking with the
de

water jet. Then so called cleaned bottle is send to the EBI unit where the sensor senses any
alien materials present in the bottle. The test if passed sends the bottle for further
processing and if failed rejects the bottle and again the bottle is recycled. This unit also
oa

checks if there is any cracks in bottle.

nl

 MIXING OF INGREDIENTS
In this unit, first of all the given proportion of the flavor is diluted with specified ratio of
ow

water with added sugar. Additional amount of flavors are also mixed up with the solution to
give it the proper flavor. The mixture thus obtained is called syrup.
D

 AUTOMATIC TIME CONTROLLED FILLING UNIT

In this unit, the bottles passed from the EBI unit are filled the solution of the mixture on the
time basis. The bottles are clamped by a robotics arm for a certain period of time during

5
 Instrumentation II Chapter 10 - Case Study

which the mixture is filled into it. The time duration is kept different for different sizes of
bottles. Followed by the filling, the carbon dioxide gas is also introduced in the bottle with
immediate capping. The carbon dioxide gas is used to make the solution harder and give it
additional flavor. It is also used as preservative.
The capping is also done automatically. As soon as the mixture is carbonated, the caps
loaded into the machine are locked onto the bottle ensuring the proper sealing.

p
 TEMPERATURE TEST UNIT

.n
Here, the filled bottles are tested for the appropriate temperatures. The testing is
performed by the bottles into water kept at 120 degree Celsius. If there is any impurity

du
present in the mixture, certain symptoms like clotting etc may seem to occur. If such
symptoms are encountered, the whole lot of the solution is discarded.

.e
es
ot
en
io
m
fro
d
de
oa
nl
ow
D

6
 Instrumentation II Chapter 10 - Case Study

Block Diagram & Description of the Plant

PET (Polyethylenterepthalate)

p
.n
Chiller Blow Mold HP Compressor
(sipa)

du
Air

.e
Para mix Rinser+Filter+cappe

es
Blender
Chain

ot
en Conveyor
Data Code

(Video jet)
io
m

Warmer
fro

(Khs)
d
de

Lableller
oa

(Krones)
nl
ow

Cartoon Taking
D

7
 Instrumentation II Chapter 10 - Case Study

RGB (Returnable Glass)

p
Decrater (Ketlner)

.n
du
.e
Bottle Washer

es
(Crown/Bade)

ot
en
EBI
io
(Empty Bottle)
m
fro

Filling+ Crowner
d
de
oa

Data Code
nl
ow
D

Carter

8
 Instrumentation II Chapter 10 - Case Study

PRODUCTION:
The production of drinking soft drink in coca-cola company broadly involves four steps:
1. Importing spring water from various part of Kathmandu.
2. Purification of soft drink.
3. Washing and filling of bottles.
4. Storage

1. Importing spring water from various part of Kathmandu.

p
As there is no boring in coca-cola company, the company has to import spring water. It imports
spring water from various part of Kathmandu such as Balaju water supply etc.

.n
2. Purification of water

du
Purification of water is a very important process. The brand name depends on the production pure
water. The basic block diagram for purification of water is shown below:

.e
Chlorine

es
Sand filter (Removes suspended particles)
Sedimentation
AM filter (Anthracite & manganese filter)

ot
Tank (sediment for
Spring water 6-8 hours) en Carbon filter (Removes organic Residue)

+ Softener (Removes hardness of water)

Chlorination Bag filter (Removes microscopic particles

io
up to 5 microns)
m

Candle filter
fro

Pure water for

d

packing (should be Reverse

Ozone contact
de

left for at least 4

Tank
hours before Osmosis
drinking)
oa
nl
ow

Ozone
D

Generator

Fig 1.Water Purification Plant

9
 Instrumentation II Chapter 10 - Case Study

Water is obtained as spring water. The water is then collected in sedimentation Tank. The simple
process of sedimentation allows heavy suspended particles to settle down. The process of
chlorination is also performed in this tank. Chlorination is the process of adding the element to
water as a method of water purification to make it fit for human consumption as drinking water.
Water which has been treated with chlorine is effective in preventing the spread of disease.

Next, pressurized water is passed through a variety of filters as shown in the figure. First, the water

p
is passed through sand filter. A sand filter is a basic tool of water purification passing flocculated
water through a sand filter strains out the flock and the particles trapped within it. The medium of

.n
filter is sand of varying grades. As water flows through the sand, impurities such as solids,
precipitates, turbidity and in some case even bacterial particles are filtered out. After being filtered

du
through the sand filter water is then filtered for any anthracite and manganese through AM filter.

.e
Next, water is passed through carbon filter. Carbon filters are most effective at removing chlorine

es
and volatile organic compounds from water. They are not generally effective at removing minerals,
salt, and dissolved inorganic compounds. Spring water generally is exposed to variety of minerals

ot
underground. This causes the formation of hard water. Hard water is the one with high mineral
content. Hard water deposits can serve as a medium for bacterial growth and irritation. During
en
purification the mineral ions are exchanged with the ions that don’t cause hardness.

Then, water is passed through bag filter to remove suspended particles smaller than 5 microns and
io
finally through candle filter.

After completion of the purification reverse osmosis is performed. The term reverse osmosis comes
m

from the process of osmosis, the natural movement of solvent from an area of low solute
concentration, through a membrane to an area of high solute concentration if no external pressure
fro

is applied. Reverse osmosis is the process of pushing a solution through a filter that traps the solute
on one side and allows the pure solvent to be obtained from the other side. More formally, it is the
process of forcing a solvent from a region of high solute concentration through a membrane to a
d

region of low solute concentration by applying a pressure in excess of the osmotic pressure. This
de

process removes minerals in the water and is best known for it’s used in desalination.

The final stage of purification involves sterilizing water with ozone. Ozone is bubbled in ozone
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contact tank to sterilize water from any remaining contamination. Ozone is an excellent sterilizing
agent without any effects. As ozone is unstable it breaks down into oxygen molecules after some
time.
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3. Washing and filling of bottles

The PC (polycarbonate) bottles are the reusable bottles. They have a capacity of holding 19 liters of
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water. The company distributes filled bottles and collects the empty bottles from the customers.

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 Instrumentation II Chapter 10 - Case Study

The equipments used are fine at performing the corresponding job assigned to them. The
equipments are from snap co. The equipments is separated into two section for washing and filling
water respectively. The overall block diagram is shown below.

Manual input of Automatic jet washer Clean bottles

Filter and
unclean bottles capper

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(Cap snap co)

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Delivery

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trolley

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Fig 2. Washing and filling of PC jars

The reusable bottles encounter a variety of environments and thus are susceptible to contamination.

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The first process is thus cleaning of the bottles as soon as they arrive at the company. Although the
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machine cleaning is sufficient enough, the bottles are first manually cleaned by sprinkling detergent
water. Then the bottles are transported to automatic jet washer. An employee observes for any
cracks and unwanted residues that cannot be removed. S/He then mounts them in the Automatic jet
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Washer one by one. The bottles are rotated in a convey halting at certain points. When halted a jet
of detergent water with chlorine jets into the bottle. Next it is washed by recalculating water. Then
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the bottle is washed by hyper assonated water to remove any remaining infections.
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 Instrumentation II Chapter 10 - Case Study

The Automatic bottle Washer performs the first three tasks. The water is filled and the bottle sealed
at filler and capper. The filler and capper section first detects the arrival of bottle and lifts them off
the convey belt. It is then filled with soft drink. The bottle is not released until the next one arrives.
After being released the caps are placed on the mouth of the bottle and sealed. The filled bottles are
then loaded in a trolley and taken to storage facility.

4. Storage

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The assonated soft drink is not suitable for drinking. Since, ozone is unstable it breaks down into

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oxygen molecules, the soft drink has to be left aside for at least four hours. Coca-cola Company,
however stores the recently packed bottles for one whole day. They are dispatched only on the

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other day.

The purification of the water is quite perfect and employs a number of filters to remove impurities

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and infections. However, the washing and filling stations employ electro mechanics. The current
system is only based on the timing sequences. The processes repeat itself in a fixed duration of time.

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The disorder in any timing sequences can disrupt the whole system. Also, if any sequence is to be
rearranged the entire system may have to be dismantled for a small purpose.

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Here, we purpose a microprocessor based automatic washing and filling station, which has a much
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easier control structure.

The different instruments and devices we propose to add are:

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1. Bottle sensor: These can be anything from simple limit switch to IR sensors to detect the
presence of the bottle at that position. The detected signal is used as an input to
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microcontroller or the counter.

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2. Solenoid valve: Solenoid valve are valves controlled via electrical signals. The proposed
design uses four of them. Three solenoid valves are used in the Automatic Jet Washer while
the final one is fill the bottle with pure soft drink.
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3. Temperature sensors: Although sensors are already present in the previous design we
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will use the temperature sensor to maintain the temperature using heaters and coolers.

4. Load cell: Previously no weighing machine was used. The time a bottle took to fill was
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estimated to be around 10-12 seconds. Now we proposed to add a weighing machine and
weigh the amount of soft drink filled. The weight information will be used to control the
amount of soft drink.
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5. User keypad: This is a new feature allows user to make different modifications according
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to his need.

6. Electromagnetic lift: This is a magnetic lift the bottles during filling of soft drink.
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7. Press: This may be a hydraulic press or any other one seal the bottle.

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 Instrumentation II Chapter 10 - Case Study

8. LCD Display: The display shows the temperature in the automatic bottle washer and the
total number of production in the factory.

The block diagram of the proposed bottle washer is as shown in fig below. The new jet
washer incorporates the use of bottle sensors to jet the soft drink in the corresponding slot.
If the bottle is into present in a slot then the corresponding jet will not eject soft drink. This
design allows the plant to save water, detergent and hyper assonated water.

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First the jets are in the off state. As soon as the motors stall the sensors checks the

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corresponding location. If the slot is full then the solenoid valve corresponding to the slot is
activated. After 10 seconds the jet are turned off and the motor rotates for about 2 seconds

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to move the bottle to next cleaning location. Again the slots are checked and results verified
to open the equivalent solenoid valve. After the washing is complete the bottles are passed
on to the conveyer belt to pass bottle to filling and capping station.

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After the bottle is washed it is transported to the filling section by a convey line. But it

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should be remembered that convey should transported the bottles smoothly without any

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 Instrumentation II Chapter 10 - Case Study

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Fig . Block Diagram of Proposed Design
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