EE 3213

Microprocessors, Microcontrollers and Peripherals

Lecture 01: Introduction to Microprocessors

Course Teacher
Dr. Kalyan Kumar Halder
Associate Professor
Dept. of EEE, KUET
Source: https://www2.slideshare.net/saquib208/8085- microprocessor-ramesh- gaonkar?fbclid=IwAR08_WdGimDr7BLv_q31aciILlAIjyyG-
40s3CqU1p0Z15hrJb0wB4kRgFw
 MICROPROCESSOR 8085

• Reference Book:
– Ramesh S. Goankar, “Microprocessor Architecture,
Programming and Applications with 8085”, 5th Edition,
Prentice Hall
 Basic Concepts of Microprocessors
• Differences between:
– Microcomputer – a computer with a
microprocessor as its CPU. Includes memory, I/O
etc.
– Microprocessor – silicon chip which includes
ALU, register circuits & control circuits
– Microcontroller – silicon chip which includes
microprocessor, memory & I/O in a single
package.
 What is a Microprocessor?
• The word comes from the combination micro and
processor.
– Processor means a device that processes whatever. In
this context processor means a device that processes
numbers, specifically binary numbers, 0’s and 1’s.
• To process means to manipulate. It is a general term that
describes all manipulation. Again in this content, it means to
perform certain operations on the numbers that depend on the
microprocessor’s design.
 What about micro?
• Micro is a new addition.
– In the late 1960’s, processors were built using discrete
elements.
• These devices performed the required operation, but were too
large and too slow.

– In the early 1970’s the microchip was invented. All of

the components that made up the processor were now
placed on a single piece of silicon. The size became
several thousand times smaller and the speed became
several hundred times faster. The “Micro”Processor
was born.
 Was there ever a “mini”-
processor?
• No.
– It went directly from discrete elements to a
single chip. However, comparing today’s
microprocessors to the ones built in the early
1970’s you find an extreme increase in the
amount of integration.

• So, What is a microprocessor?

Definition of the Microprocessor

The microprocessor is a programmable device

that takes in numbers, performs on them
arithmetic or logical operations according to
the program stored in memory and then
produces other numbers as a result.
 Definition (Contd.)
• Lets expand each of the underlined words:
– Programmable device: The microprocessor can perform
different sets of operations on the data it receives depending
on the sequence of instructions supplied in the given
program.
By changing the program, the microprocessor manipulates
the data in different ways.

– Instructions: Each microprocessor is designed to execute a

specific group of operations. This group of operations is
called an instruction set. This instruction set defines what the
microprocessor can and cannot do.
 Definition (Contd.)
– Takes in: The data that the microprocessor
manipulates must come from somewhere.
• It comes from what is called “input devices”.
• These are devices that bring data into the system
from the outside world.
• These represent devices such as a keyboard, a
mouse, switches, and the like.
 Definition (Contd.)
– Numbers: The microprocessor has a very narrow view on life. It
only understands binary numbers.

A binary digit is called a bit (which comes from binary digit).

The microprocessor recognizes and processes a group of bits

together. This group of bits is called a “word”.

The number of bits in a Microprocessor’s word, is a measure of its

“abilities”.
 Definition (Contd.)
– Words, Bytes, etc.
• The earliest microprocessor (the Intel 8088 and Motorola’s
6800) recognized 8-bit words.
– They processed information 8-bits at a time. That’s why they are
called “8-bit processors”. They can handle large numbers, but in
order to process these numbers, they broke them into 8-bit pieces
and processed each group of 8-bits separately.

• Later microprocessors (8086 and 68000) were designed with

16-bit words.
– A group of 8-bits were referred to as a “half-word” or “byte”.
– A group of 4 bits is called a “nibble”.
– Also, 32 bit groups were given the name “long word”.

• Today, all processors manipulate at least 32 bits at a time and

there exists microprocessors that can process 64, 80, 128 bits
 Definition (Contd.)
– Arithmetic and Logic Operations:
• Every microprocessor has arithmetic operations such as add
and subtract as part of its instruction set.
– Most microprocessors will have operations such as multiply and
divide.
– Some of the newer ones will have complex operations such as
square root.

In addition, microprocessors have logic operations as well.

Such as AND, OR, XOR, shift left, shift right, etc.

• Again, the number and types of operations define the

microprocessor’s instruction set and depends on the specific
microprocessor.
 Definition (Contd.)
– Stored in memory:
• First, what is memory?
– Memory is the location where information is kept while not in
current use.
– Memory is a collection of storage devices. Usually, each storage
device holds one bit. Also, in most kinds of memory, these
storage devices are grouped into groups of 8. These 8 storage
locations can only be accessed together. So, one can only read or
write in terms of bytes to and form memory.
– Memory is usually measured by the number of bytes it can hold.
It is measured in Kilos, Megas and lately Gigas. A Kilo in
computer language is 210 =1024. So, a KB (KiloByte) is 1024
bytes. Mega is 1024 Kilos and Giga is 1024 Mega.
 Definition (Contd.)
– Stored in memory:
• When a program is entered into a computer, it is
stored in memory. Then as the microprocessor starts
to execute the instructions, it brings the instructions
from memory one at a time.

• Memory is also used to hold the data.

– The microprocessor reads (brings in) the data from
memory when it needs it and writes (stores) the results
into memory when it is done.
 Definition (Contd.)
– Produces: For the user to see the result of the
execution of the program, the results must be
presented in a human readable form.
• The results must be presented on an output device.

• This can be the monitor, a paper from the printer, a

simple LED or many other forms.
 A Microprocessor-based system
From the above description, we can draw the
following block diagram to represent a
microprocessor-based system:

Output
Input

Memory
 Inside The Microprocessor
• Internally, the microprocessor is made up of
3 main units.
– The Arithmetic/Logic Unit (ALU)
– The Control Unit.
– An array of registers for holding data while it is
being manipulated.
 Organization of a microprocessor-
based system
• Let’s expand the picture a bit.
I/O
ALU Register Input/ Output
Array
System Bus
Control
Memory
ROM RAM
 Memory
• Memory stores information such as instructions
and data in binary format (0 and 1). It provides
this information to the microprocessor whenever
it is needed.

• Usually, there is a memory “sub-system” in a

microprocessor-based system. This sub-system
includes:
– The registers inside the microprocessor
– Read Only Memory (ROM)
• used to store information that does not change.
– Random Access Memory (RAM) (also known as
Read/Write Memory).
• used to store information supplied by the user. Such as
programs and data.
 Memory Map and Addresses
• The memory map is a picture representation
of the address range and shows where the
different memory chips are located within
the address range.
0000 EPROM 0000
Address Range of EPROM Chip
3FFF
4400
RAM 1 Address Range of 1st RAM Chip
Address Range

5FFF
RAM 2 6000
Address Range of 2nd RAM Chip
8FFF
9000
RAM 3 Address Range of 3rd RAM Chip
A3FF
RAM 4 A400

Address Range of 4th RAM Chip

F7FF
FFFF
 Memory
• To execute a program:
– the user enters its instructions in binary format into the
memory.
– The microprocessor then reads these instructions and
whatever data is needed from memory, executes the
instructions and places the results either in memory or
produces it on an output device.
 The three cycle instruction
execution model
• To execute a program, the microprocessor “reads”
each instruction from memory, “interprets” it, then
“executes” it.

• To use the right names for the cycles:

– The microprocessor fetches each instruction,
– decodes it,
– Then executes it.

• This sequence is continued until all instructions

are performed.
 Machine Language
• The number of bits that form the “word” of a
microprocessor is fixed for that particular
processor.
– These bits define a maximum number of combinations.
• For example an 8-bit microprocessor can have at most 28 = 256
different combinations.

• However, in most microprocessors, not all of these

combinations are used.
– Certain patterns are chosen and assigned specific
meanings.
– Each of these patterns forms an instruction for the
microprocessor.
– The complete set of patterns makes up the
microprocessor’s machine language.
 The 8085 Machine Language
• The 8085 (from Intel) is an 8-bit microprocessor.
– The 8085 uses a total of 246 bit patterns to form its
instruction set.
– These 246 patterns represent only 74 instructions.
• The reason for the difference is that some (actually most)
instructions have multiple different formats.

– Because it is very difficult to enter the bit patterns

correctly, they are usually entered in hexadecimal
instead of binary.
• For example, the combination 0011 1100 which translates into
“increment the number in the register called the accumulator”,
is usually entered as 3C.
 Assembly Language
• Entering the instructions using hexadecimal is quite
easier than entering the binary combinations.
– However, it still is difficult to understand what a program
written in hexadecimal does.
– So, each company defines a symbolic code for the
instructions.
– These codes are called “mnemonics”.
– The mnemonic for each instruction is usually a group of
letters that suggest the operation performed.
 Assembly Language
• Using the same example from before,
– 00111100 translates to 3C in hexadecimal (OPCODE)
– Its mnemonic is: “INR A”.
– INR stands for “increment register” and A is short for
accumulator.

• Another example is: 1000 0000,

– Which translates to 80 in hexadecimal.
– Its mnemonic is “ADD B”.
– “Add register B to the accumulator and keep the result in the
accumulator”.
 Assembly Language
• It is important to remember that a machine
language and its associated assembly language are
completely machine dependent.
– In other words, they are not transferable from one
microprocessor to a different one.

• For example, Motorolla has an 8-bit

microprocessor called the 6800.
– The 8085 machine language is very different from that
of the 6800. So is the assembly language.
– A program written for the 8085 cannot be executed on
the 6800 and vice versa.
 “Assembling” The Program
• How does assembly language get translated into
machine language?
– There are two ways:
– 1st there is “hand assembly”.
• The programmer translates each assembly language instruction
into its equivalent hexadecimal code (machine language). Then
the hexadecimal code is entered into memory.
– The other possibility is a program called an
“assembler”, which does the translation automatically.
 EE 3213
Microprocessors, Microcontrollers and Peripherals

Lecture 02: 8085 Microprocessor Architecture

Course Teacher
Dr. Kalyan Kumar Halder
Associate Professor
Dept. of EEE, KUET
8085 Microprocessor Architecture

• 8-bit general purpose µp

• Capable of addressing 64 k of memory
• Has 40 pins
• Requires +5 v power supply
• Can operate with 3 MHz clock
 Pin diagram
Power
Supply: +5 V
Frequency
Generator is
connected to
those pins

Input/Output/
Memory

Read

Write

Enable
Multiplexed
Address Data
Bus

Address
Bus
• System Bus – wires connecting memory & I/O to
microprocessor
– Address Bus
• Unidirectional
• Identifying peripheral or memory location
– Data Bus
• Bidirectional
• Transferring data
– Control Bus
• Synchronization signals
• Timing signals
• Control signal
Architecture of Intel 8085 Microprocessor
 Intel 8085 Microprocessor
• Microprocessor consists of:
– Control unit: control microprocessor operations.
– ALU: performs data processing function.
– Registers: provide storage internal to CPU.
– Interrupts
– Internal data bus
 The ALU
• In addition to the arithmetic & logic circuits, the
ALU includes the accumulator, which is part of
every arithmetic & logic operation.

• Also, the ALU includes a temporary register used

for holding data temporarily during the execution
of the operation. This temporary register is not
accessible by the programmer.
• Registers
– General Purpose Registers
• B, C, D, E, H & L (8 bit registers)
• Can be used singly
• Or can be used as 16 bit register pairs
– BC, DE, HL
• H & L can be used as a data pointer (holds memory
address) Accumulator Flags

– Special Purpose Registers B

D
C
E

• Accumulator (8 bit register) H

Program Counter
L

– Store 8 bit data Stack Pointer

– Store the result of an operation

– Store 8 bit data during I/O transfer Address 16 8 Data
• Flag Register
– 8 bit register – shows the status of the microprocessor before/after an
operation
– S (sign flag), Z (zero flag), AC (auxillary carry flag), P (parity flag) &
CY (carry flag)

D7 D6 D5 D4 D3 D2 D1 D0
S Z AC P CY

– Sign Flag
• Used for indicating the sign of the data in the accumulator
• The sign flag is set if negative (1 – negative)
• The sign flag is reset if positive (0 –positive)
• Zero Flag
– Is set if result obtained after an operation is 0
– Is set following an increment or decrement operation of that register
10110011
+ 01001101
---------------
1 00000000
• Carry Flag
– Is set if there is a carry or borrow from arithmetic operation

1011 0101 1011 0101

+ 0110 1100 - 1100 1100
--------------- ---------------
Carry 1 0010 0001 Borrow 1 1110 1001
• Auxillary Carry Flag
– Is set if there is a carry out of bit 3
• Parity Flag
– Is set if parity is even
– Is cleared if parity is odd
 The Internal Architecture
• We have already discussed the general purpose
registers, the Accumulator, and the flags.

• The Program Counter (PC)

– This is a register that is used to control the sequencing
of the execution of instructions.
– This register always holds the address of the next
instruction.
– Since it holds an address, it must be 16 bits wide.
 The Internal Architecture
• The Stack pointer
– The stack pointer is also a 16-bit register that is
used to point into memory.
– The memory this register points to is a special
area called the stack.
– The stack is an area of memory used to hold
data that will be retreived soon.
– The stack is usually accessed in a Last In First
Out (LIFO) fashion.
 EE 3213
Microprocessors, Microcontrollers and Peripherals

Lecture 03: 8085 Architecture and Instructions

Course Teacher
Dr. Kalyan Kumar Halder
Associate Professor
Dept. of EEE, KUET
1
 Non Programmable Registers
• Instruction Register & Decoder
– Instruction is stored in IR after fetched by processor
– Decoder decodes instruction in IR

Internal Clock generator

– 3.125 MHz internally
– 6.25 MHz externally

2
 The Address and Data Busses
• The address bus has 8 signal lines A8 – A15
which are unidirectional.
• The other 8 address bits are multiplexed (time
shared) with the 8 data bits.
– So, the bits AD0 – AD7 are bi-directional and serve as
A0 – A7 and D0 – D7 at the same time.
• During the execution of the instruction, these lines carry the
address bits during the early part, then during the late parts of
the execution, they carry the 8 data bits.
– In order to separate the address from the data, we can
use a latch to save the value before the function of the
bits changes.
3
 Demultiplexing AD7-AD0
– From the above description, it becomes obvious
that the AD7– AD0 lines are serving a dual purpose
and that they need to be demultiplexed to get all the
information.
– The high order bits of the address remain on the bus
for three clock periods. However, the low order bits
remain for only one clock period and they would
be lost if they are not saved externally. Also, notice
that the low order bits of the address disappear
when they are needed most.
– To make sure we have the entire address for the full
three clock cycles, we will use an external latch
to save the value of AD7– AD0 when it is carrying
the address bits. We use the ALE signal to enable
this latch. 4
 Demultiplexing AD7-AD0
8085
A15-A8

ALE

AD7-AD0 Latch
A7- A 0

D7- D0

– Given that ALE operates as a pulse during T1, we will

be able to latch the address. Then when ALE goes low,
the address is saved and the AD7–AD0 lines can be
used for their purpose as the bi-directional data lines.

5
 Demultiplexing the Bus AD7 – AD0
• The high order address is placed on the address bus and hold for 3 clk
periods,
• The low order address is lost after the first clk period, this address
needs to be hold however we need to use latch
• The address AD7 – AD0 is connected as inputs to the latch 74LS373.
• The ALE signal is connected to the enable (G) pin of the latch and the
OC – Output control – of the latch is grounded

6
7
Introduction to 8085 Instructions

8
 The 8085 Instructions
– Since the 8085 is an 8-bit device it can have up to 28
(256) instructions.
• However, the 8085 only uses 246 combinations that represent a
total of 74 instructions.
– Most of the instructions have more than one format.

– These instructions can be grouped into five different

groups:
• Data Transfer Operations
• Arithmetic Operations
• Logic Operations
• Branch Operations
• Machine Control Operations
9
 Instruction and Data Formats
• Each instruction has two parts.
– The first part is the task or operation to be
performed.
• This part is called the “opcode” (operation code).

– The second part is the data to be operated on

• Called the “operand”.

10
 Data Transfer Operations
– These operations simply COPY the data from the
source to the destination.
– MOV, MVI, LDA, and STA

– They transfer:
• Data between registers.
• Data Byte to a register or memory location.
• Data between a memory location and a register.
• Data between an I\O Device and the accumulator.

– The data in the source is not changed.

11
 The LXI instruction
• The 8085 provides an instruction to place
the 16-bit data into the register pair in one
step.
• LXI Rp, <16-bit address> (Load eXtended Immediate)

– The instruction LXI B 4000H will place the

16-bit number 4000 into the register pair B, C.
• The upper two digits are placed in the 1st register of
the pair and the lower two digits in the 2nd .

LXI B 40 00H B 40 00 C

12
 The Memory “Register”
• Most of the instructions of the 8085 can use a
memory location in place of a register.
– The memory location will become the “memory” register M.
• MOV M B
– copy the data from register B into a memory location.
– Which memory location?

• The memory location is identified by the contents

of the HL register pair.
– The 16-bit contents of the HL register pair are treated
as a 16-bit address and used to identify the memory
location. 13
 Using the Other Register Pairs
– There is also an instruction for moving data from
memory to the accumulator without disturbing the
contents of the H and L register.

• LDAX Rp (LoaD Accumulator eXtended)

– Copy the 8-bit contents of the memory location identified by the

Rp register pair into the Accumulator.
– This instruction only uses the BC or DE pair.
– It does not accept the HL pair.

14
 Arithmetic Operations
– Addition (ADD, ADI):
– Any 8-bit number.
– The contents of a register.
– The contents of a memory location.
• Can be added to the contents of the accumulator and the result
is stored in the accumulator.

– Subtraction (SUB, SUI):

– Any 8-bit number
– The contents of a register
– The contents of a memory location
• Can be subtracted from the contents of the accumulator. The
result is stored in the accumulator.

15
Arithmetic Operations Related to
Memory
• These instructions perform an arithmetic operation
using the contents of a memory location while
they are still in memory.
– ADD M
• Add the contents of M to the Accumulator
– SUB M
• Sub the contents of M from the Accumulator
– INR M / DCR M
• Increment/decrement the contents of the memory location in
place.

– All of these use the contents of the HL register pair to

identify the memory location being used. 16
 Arithmetic Operations
– Increment (INR) and Decrement (DCR):
• The 8-bit contents of any memory location or any
register can be directly incremented or decremented
by 1.
• No need to disturb the contents of the accumulator.

17
 Logic Operations
• These instructions perform logic operations on the
contents of the accumulator.
– ANA, ANI, ORA, ORI, XRA and XRI
• Source: Accumulator and
– An 8-bit number
– The contents of a register
– The contents of a memory location
• Destination: Accumulator
ANA R/M AND Accumulator With Reg/Mem
ANI # AND Accumulator With an 8-bit number

ORA R/M OR Accumulator With Reg/Mem

ORI # OR Accumulator With an 8-bit number

XRA R/M XOR Accumulator With Reg/Mem XOR

XRI # Accumulator With an 8-bit number

18
 Logic Operations
– Complement:
• 1’s complement of the contents of the accumulator.
CMA No operand

19
 Additional Logic Operations
• Rotate
– Rotate the contents of the accumulator one
position to the left or right.
– RLC Rotate the accumulator left.
Bit 7 goes to bit 0 AND the Carry flag.
– RAL Rotate the accumulator left through the carry.
Bit 7 goes to the carry and carry goes to bit 0.
– RRC Rotate the accumulator right.
Bit 0 goes to bit 7 AND the Carry flag.
– RAR Rotate the accumulator right through the carry.
Bit 0 goes to the carry and carry goes to bit 7.

20
 RLC vs. RAL
Carry Flag

• RLC
7 6 5 4 3 2 1 0

Accumulator

Carry Flag

• RAL 7 6 5 4 3 2 1 0

Accumulator

21
 EE 3213
Microprocessors, Microcontrollers and Peripherals

Lecture 04: 8085 Instructions and Timing Diagram

Course Teacher
Dr. Kalyan Kumar Halder
Associate Professor
Dept. of EEE, KUET
1
 Logical Operations
• Compare
• Compare the contents of a register or memory location with the
contents of the accumulator.
– CMP R/M Compare the contents of the register
or memory location to the contents of
the accumulator.
– CPI # Compare the 8-bit number to the
contents of the accumulator.

• The compare instruction sets the flags (Z, Cy, and S).

• The compare is done using an internal subtraction that does not

change the contents of the accumulator.
A – (R / M / #)

2
 Branch Operations
• Two types:
– Unconditional branch.
• Go to a new location no matter what.
– Conditional branch.
• Go to a new location if the condition is true.

3
 Unconditional Branch
– JMP Address
• Jump to the address specified (Go to).

– CALL Address
• Jump to the address specified but treat it as a subroutine.

– RET
• Return from a subroutine.

– The addresses supplied to all branch operations must be

16-bits.
4
 Conditional Branch
– Go to new location if a specified condition is met.
• JZ Address (Jump on Zero)
– Go to address specified if the Zero flag is set.
• JNZ Address (Jump on NOT Zero)
– Go to address specified if the Zero flag is not set.
• JC Address (Jump on Carry)
– Go to the address specified if the Carry flag is set.
• JNC Address (Jump on No Carry)
– Go to the address specified if the Carry flag is not set.
• JP Address (Jump on Plus)
– Go to the address specified if the Sign flag is not set
• JM Address (Jump on Minus)
– Go to the address specified if the Sign flag is set.
5
 Machine Control
– HLT
• Stop executing the program.
– NOP
• No operation
• Exactly as it says, do nothing.
• Usually used for delay or to replace instructions
during debugging.

6
 Instruction Size
• Depending on the operand type, the instruction
may have different sizes. It will occupy a different
number of memory bytes.
– Typically, all instructions occupy one byte only.
– The exception is any instruction that contains
immediate data or a memory address.
• Instructions that include immediate data use two bytes.
– One for the opcode and the other for the 8-bit data.
• Instructions that include a memory address occupy three bytes.
– One for the opcode, and the other two for the 16-bit address.

7
Instruction with Immediate Date
• Operation: Load an 8-bit number into the
accumulator.

– MVI A, 32
• Operation: MVI A
• Operand: The number 32
• Binary Code:
0011 1110 3E 1st byte.
0011 0010 32 2nd byte.

8
Instruction with a Memory Address

• Operation: go to address 2085.

– Instruction: JMP 2085

• Opcode: JMP
• Operand: 2085
• Binary code:
1100 0011 C3 1st byte.
1000 0101 85 2nd byte
0010 0000 20 3rd byte

9
 Addressing Modes
• The microprocessor has different ways of
specifying the data for the instruction. These are
called “addressing modes”.

• The 8085 has four addressing modes:

– Implied CMA
– Immediate MVI B, 45
– Direct LDA 4000
– Indirect LDAX B
• Load the accumulator with the contents of the memory location
whose address is stored in the register pair BC.
10
 Timing Diagram
Representation of Various Control signals generated during
Execution of an Instruction.
Following Buses and Control Signals must be shown in a
Timing Diagram:
•Higher Order Address Bus.
•Lower Address/Data bus
•ALE
•RD
•WR
•IO/M
 Timing Diagram
Instruction: T1 T2 T3 T4

A000H MOV A,B A0H

A15- A8 (Higher Order Address bus)
Corresponding Coding: 00H 78H

A000H 78

ALE

RD

WR

8085 Memory IO/M

Op-code fetch Cycle
 Timing Diagram
T1 T2 T3 T4 T5 T6 T7

A0H A0H
A15- A8 (Higher Order Address bus)
00H 3EH 01H 45H
DA7-DA0 (Lower order address/data Bus)
Instruction:
A000H MVI A, 45H
ALE
Corresponding Coding:
RD
A000H 3E

A001H 45
WR

IO/M

Op-Code Fetch Cycle Memory Read Cycle

 Timing Diagram

Instruction:
LXI H, FO45H
Corresponding Coding: OFC

MEMR
A000H 21
MEMR

A001H 45
F0 8085 Memory
A002H
 Timing Diagram
Op-Code Fetch Cycle Memory Read Cycle Memory Read Cycle

T1 T2 T3 T4 T5 T6 T7 T8 T9 T10

A0H A0H A0H

A15- A8 (Higher Order Address bus)
00H 21H 01H 45H 02H F0H
DA7-DA0 (Lower order address/data Bus)

ALE

RD

WR

IO/M
 Timing Diagram

T-state: It is defined as one subdivision of the operation

performed in one clock period. The terms T-state and clock period
are often used synonymously.

Machine Cycle: It is defined as the time required to complete one

operation of accessing memory, I/O, or acknowledging an external
request. This cycle may consist of three to six T-states.

Instruction Cycle: It is defined as the time required to complete

the execution of an instruction. The 8085 instruction cycle
consists of one to six machine cycles.
 EE 3213
Microprocessors, Microcontrollers and Peripherals

Lecture 05: 8085 Timing Diagram, Counters & Time Delays

Course Teacher
Dr. Kalyan Kumar Halder
Associate Professor
Dept. of EEE, KUET 1
 Timing Diagram

T1 T2 T3 T4 T5 T6 T7
A0H Content of Reg H
A15- A8 (Higher Order Address bus)
00H 7EH L Reg Content of M
Instruction: DA7-DA0 (Lower order address/data Bus)

A000H MOV A, M
Corresponding Coding:
ALE
A000H 7E
RD

WR

IO/M

Op-Code Fetch Cycle Memory Read Cycle

 Timing Diagram
T1 T2 T3 T4 T5 T6 T7
A0H Content of Reg H
A15- A8 (Higher Order Address bus)
00H 77H L Reg Content of Reg A
Instruction: DA7-DA0 (Lower order address/data Bus)

A000H MOV M,A

Corresponding Coding:
ALE
A000H 77
RD

WR

IO/M

Op-Code Fetch Cycle Memory Write Cycle

 Counters
• A loop counter is set up by loading a register with
a certain value
• Then using the DCR (to decrement) and INR (to
increment) the contents of the register are updated.
• A loop is set up with a conditional jump
instruction that loops back or not depending on
whether the count has reached the termination
count.
 Counters
• The operation of a loop counter can be
described using the following flowchart.

Initialize

Body of loop

Update the count

No Is this
Final
Count?

Yes
Sample ALP for implementing a loop
Using DCR instruction
MVI C, 15H
LOOP DCR C
JNZ LOOP
 Using a Register Pair as a Loop Counter

• Using a single register, one can repeat a loop for a

maximum count of 255 times.

• It is possible to increase this count by using a

register pair for the loop counter instead of the
single register.
– A minor problem arises in how to test for the final
count since DCX and INX do not modify the flags.
– However, if the loop is looking for when the count
becomes zero, we can use a small trick by ORing the
two registers in the pair and then checking the zero flag.
 Using a Register Pair as a Loop Counter

• The following is an example of a loop set

up with a register pair as the loop counter.

LXI B, 1000H
LOOP DCX B
MOV A, C
ORA B
JNZ LOOP
 Delays
• Each instruction passes through different
combinations of Fetch, Memory Read, and
Memory Write cycles.
• Knowing the combinations of cycles, one can
calculate how long such an instruction would
require to complete.
 Delays
• Knowing how many T-States an instruction
requires, and keeping in mind that a T-State is one
clock cycle long, we can calculate the time using
the following formula:

Delay = No. of T-States / Frequency

• For example a “MVI” instruction uses 7 T-States.

Therefore, if the Microprocessor is running at 2
MHz, the instruction would require 3.5 Seconds
to complete.
 Delay loops
• We can use a loop to produce a certain
amount of time delay in a program.

• The following is an example of a delay

loop:
MVI C, FFH 7 T-States
LOOP DCR C 4 T-States
JNZ LOOP 10 T-States

• The first instruction initializes the loop counter and is

executed only once requiring only 7 T-States.
• The following two instructions form a loop that
requires 14 T-States to execute and is repeated 255
times until C becomes 0.
 Delay Loops (Contd.)
• We need to keep in mind though that in the last
iteration of the loop, the JNZ instruction will fail and
require only 7 T-States rather than the 10.
• Therefore, we must deduct 3 T-States from the total
delay to get an accurate delay calculation.
• To calculate the delay, we use the following formula:
Tdelay = TO + TL
– Tdelay = total delay
– TO = delay outside the loop
– TL = delay of the loop

• TO is the sum of all delays outside the loop.

 Delay Loops (Contd.)
• Using these formulas, we can calculate the
time delay for the previous example:

TO = 7 T-States
– Delay of the MVI instruction

• TL = (14 X 255) - 3 = 3567 T-States

– 14 T-States for the 2 instructions repeated 255 times
(FF16 = 25510) reduced by the 3 T-States for the final
JNZ.
 Using a Register Pair as a Loop Counter

• Using a single register, one can repeat a loop for a

maximum count of 255 times.

• It is possible to increase this count by using a

register pair for the loop counter instead of the
single register.
– A minor problem arises in how to test for the final
count since DCX and INX do not modify the flags.
– However, if the loop is looking for when the count
becomes zero, we can use a small trick by ORing the
two registers in the pair and then checking the zero flag.
 Using a Register Pair as a Loop Counter

• The following is an example of a delay loop

set up with a register pair as the loop
counter.

LXI B, 1000H 10 T-States

LOOP DCX B 6 T-States
MOV A, C 4 T-States
ORA B 4 T-States
JNZ LOOP 10 T-States
Using a Register Pair as a Loop Counter

• Using the same formula from before, we can

calculate:

TO = 10 T-States
– The delay for the LXI instruction

• TL = (24 X 4096) - 3 = 98301 T-States

– 24 T-States for the 4 instructions in the loop repeated
4096 times (100016 = 409610) reduced by the 3 T-
States for the JNZ in the last iteration.
 Nested Loops Initialize loop 2

Body of loop 2

• Nested loops can be Initialize loop 1

easily setup in Body of loop 1

assembly language by Update the count1

using two registers for

Is this
the two loop counters No
Final
Count?
and updating the right
register in the right Update the count 2

loop.
Is this
– In the figure, the body of
No
Final
Count?
loop2 can be before or
Yes
after loop1.
 Nested Loops for Delay
• Instead (or in conjunction with) Register Pairs, a
nested loop structure can be used to increase the
total delay produced.

MVI B, 10H 7 T-States

LOOP2 MVI C, FFH 7 T-States
LOOP1 DCR C 4 T-States
JNZ LOOP1 10 T-States
DCR B 4 T-States
JNZ LOOP2 10 T-States
 Delay Calculation of Nested Loops
• The calculation remains the same except
that it the formula must be applied
recursively to each loop.
– Start with the inner loop, then plug that delay in
the calculation of the outer loop.

Delay of inner loop

– TO1 = 7 T-States
• MVI C, FFH instruction
– TL1 = (255 X 14) - 3 = 3567 T-States
• 14 T-States for the DCR C and JNZ instructions repeated 255
times (FF = 255) minus 3 for the final JNZ
 Delay Calculation of Nested Loops

• Delay of outer loop

– TO2 = 7 T-States
• MVI B, 10H instruction
– TL1 = (16 X (7 + 3567 + 14)) - 3 = 57405 T-States
• 14 T-States for the DCR B and JNZ instructions and (7+3567)
T-States for loop1 repeated 16 times (1016 = 1610) minus 3 for the
final JNZ.
– TDelay = 7 + 57405 = 57412 T-States

• Total Delay
– TDelay = 57412 X 0.5 Sec = 28.706 mSec
 Increasing the delay
• The delay can be further increased by using
register pairs for each of the loop counters
in the nested loops setup.
• It can also be increased by adding dummy
instructions (like NOP) in the body of the
loop.
 EE 3213
Microprocessors, Microcontrollers and Peripherals

Lecture 06: Stack and Subroutines

Course Teacher
Dr. Kalyan Kumar Halder
Associate Professor
Dept. of EEE, KUET 1
 The Stack
• The stack is an area of memory identified by the
programmer for temporary storage of information.
• The stack is a LIFO structure.
– Last In First Out.
• The stack normally grows backwards into
Memory

memory.
– In other words, the programmer
defines the bottom of the stack The Stack
and the stack grows up into grows
backwards
Bottom
reducing address range. into memory
of the
Stack
 The Stack
• Given that the stack grows backwards into
memory, it is customary to place the bottom of the
stack at the end of memory to keep it as far away
from user programs as possible.
• In the 8085, the stack is defined by setting the SP
(Stack Pointer) register.

LXI SP, FFFFH

• This sets the Stack Pointer to location FFFFH (end

of memory for the 8085).
Saving Information on the Stack
• Information is saved on the stack by PUSHing it
on.
– It is retrieved from the stack by POPing it off.

• The 8085 provides two instructions: PUSH and

POP for storing information on the stack and
retrieving it back.
– Both PUSH and POP work with register pairs ONLY.
 The PUSH Instruction
• PUSH B
– Decrement SP
– Copy the contents of register B to the memory
location pointed to by SP
– Decrement SP
– Copy the contents of register C to the memory
location pointed to by SP
 The POP Instruction
• POP D
– Copy the contents of the memory location
pointed to by the SP to register E
– Increment SP
– Copy the contents of the memory location
pointed to by the SP to register D
– Increment SP
 Operation of the Stack
• During pushing, the stack operates in a
“decrement then store” style.
– The stack pointer is decremented first, then the
information is placed on the stack.

During poping, the stack operates in a “use then

increment” style.
– The information is retrieved from the top of the the
stack and then the pointer is incremented.
 LIFO
• The order of PUSHs and POPs must be opposite
of each other in order to retrieve information back
into its original location.

PUSH B
PUSH D
...
POP D
POP B
 The PSW Register Pair
• The 8085 recognizes one additional register pair
called the PSW (Program Status Word).
– This register pair is made up of the Accumulator and
the Flags registers.

It is possible to push the PSW onto the stack, do

whatever operations are needed, then POP it off of
the stack.
– The result is that the contents of the Accumulator and
the status of the Flags are returned to what they were
before the operations were executed.
 Subroutines
• A subroutine is a group of instructions that will be
used repeatedly in different locations of the
program.
– Rather than repeat the same instructions several times,
they can be grouped into a subroutine that is called
from the different locations.

• In Assembly language, a subroutine can exist

anywhere in the code.
– However, it is customary to place subroutines
separately from the main program.
 Subroutines
• The 8085 has two instructions for dealing
with subroutines.
– The CALL instruction is used to redirect
program execution to the subroutine.
– The RET insutruction is used to return the
execution to the calling routine.
 The CALL Instruction
• CALL 4000H
– Push the address of the instruction
immediately following the CALL onto the
stack
– Load the program counter with the 16-bit
address supplied with the CALL instruction.
 The RET Instruction
• RET
– Retrieve the return address from the top of
the stack
– Load the program counter with the return
address.
 Cautions
• The CALL instruction places the return address at
the two memory locations immediately before
where the Stack Pointer is pointing.
– You must set the SP correctly BEFORE using the
CALL instruction.

• The RET instruction takes the contents of the two

memory locations at the top of the stack and uses
these as the return address.
– Do not modify the stack pointer in a subroutine. You
will loose the return address.
 Passing Data to a Subroutine
• In Assembly Language data is passed to a
subroutine through registers.
– The data is stored in one of the registers by the calling
program and the subroutine uses the value from the
register.

• The other possibility is to use agreed upon

memory locations.
– The calling program stores the data in the memory
location and the subroutine retrieves the data from the
location and uses it.
Call by Reference and Call by Value

• If the subroutine performs operations on the

contents of the registers, then these modifications
will be transferred back to the calling program
upon returning from a subroutine.
– Call by reference

• If this is not desired, the subroutine should PUSH

all the registers it needs on the stack on entry and
POP them on return.
– The original values are restored before execution
returns to the calling program.
 Cautions with PUSH and POP
• PUSH and POP should be used in opposite order.

• There has to be as many POP’s as there are

PUSH’s.
– If not, the RET statement will pick up the wrong
information from the top of the stack and the program
will fail.

• It is not advisable to place PUSH or POP inside a

loop.
Conditional CALL and RET
Instructions
• The 8085 supports conditional CALL and
conditional RET instructions.
– The same conditions used with conditional JUMP
instructions can be used.

– CC, call subroutine if Carry flag is set.

– CNC, call subroutine if Carry flag is not set
– RC, return from subroutine if Carry flag is set
– RNC, return from subroutine if Carry flag is not set
– Etc.
 A Proper Subroutine
• According to Software Engineering practices, a
proper subroutine:
– Is only entered with a CALL and exited with an RET
– Has a single entry point
• Do not use a CALL statement to jump into different points of
the same subroutine.
– Has a single exit point
• There should be one return statement from any subroutine.

• Following these rules, there should not be any

confusion with PUSH and POP usage.
 EE 3213
Microprocessors, Microcontrollers and Peripherals

Lecture 07: 8085 Instructions and Programming

Course Teacher
Dr. Kalyan Kumar Halder
Associate Professor
Dept. of EEE, KUET 1
 How Does the Microprocessor Work?
 Assume that a program and data are already entered in the
R/W memory.
 The microprocessor fetches the first instruction from its
memory sheet, decodes it, and executes that instruction.
 The sequence of fetch, decode, and execute is continued
until the microprocessor comes across an instruction to stop.
During the entire process, the microprocessor uses the
system bus to fetch the binary instructions and data from the
memory.
 It uses registers from the register section to store data
temporarily, and it performs the computing function in the
ALU section.
 Finally, it sends out the result in binary, using the same
bus lines, to memory or an output device. 2
 How Does a Microprocessor Differentiate Between Data
and Instruction Code?

The microprocessor interprets the first byte it Mnemonics Hex Memory

Code Address
fetches as an opcode. In the example, we tell the
processor that our program begins at location MVI A, 3E 2000H
2000H. The first code it fetches is 3EH. When it 32H
decodes that code, it knows that it is a two-byte 32 2001H
instruction. Therefore, it assumes that the second MVI 06 2002H
code, 32H, is a data byte. If we forget to enter 32H B,48H
and enter the next code, 06H, instead, the 8085 will 48 2003H
load 06H in the accumulator, interpret the next ADD B 80 2004H
code, 48H, as an opcode, and continue the
execution in sequence. As a consequence, we may
encounter a totally unexpected result.

3
 DATA TRANSFER GROUP

LHLD address (Load HL pair with data from address).

Example:
LHLD 2050H.

Move the data from 2050 to register L

&
Move the data from 2051 to register H
 DATA TRANSFER GROUP

XCHG (Exchange the data from HL pair to DE pair)

Example : XCHG
After
Initially
After execution

H=20H,L=30H,
H=40H,L=70H.
D=40H,E=70H.
D=20H,E=30H.
Flags Affected :No flags affected.
 DATA TRANSFER GROUP

Example:Write a program to exchange contents of

memory location D000H to D001H

LDA D000H Load Acc with data from D000

MOV B,A Move the data to B
LDA D001H Load Acc with data from D001
STA D000H Store Acc data at D000
MOV A,B Move B’s data to A
STA D001H Store Acc data at D001

6
 ARITHMETIC GROUP
ADC R (ADD register content with Acc and carry and
result in A).
Example:
ADC C (ADD the content of C with A with carry).

Suppose the Data at C register is 10H and carry is 01H.

Initially After execution
C= 10H, A=10H A=21H,C=10H.
 ARITHMETIC GROUP
SBB R (Subtract register content from Acc with borrow and
result in A ).
Example:
SBB B. (Subtract the content of B from A with borrow).

Suppose the Data at B register is 0FH and borrow is 01H .

Initially After execution
B= 0FH,A=20H A=10H,B=0FH.
 ARITHMETIC GROUP
Example: Write a program to perform 16 bit addition of
1234H & 4321H. Store answer at H & L registers.
MVI B,21H B=21H
MVI A,34H A=34H
MVI C,43H C=43H
MVI D,12H D=12H
ADD B A=34+21H
MOV L,A L=55H
MOV A,C A=43H
ADC D A=43+12H
MOV H,A H=55H
HLT STOP.
 ARITHMETIC GROUP

Example: Subtract data of memory address C800H from

C200H. Store the result at 2C00H.
LDA C800H
MOV B,A
LDA C200H
SUB B
STA 2C00H
RST1
 ARITHMETIC GROUP

DAD Rp (Add specified register pair with HL pair)

Example:DAD D.(Add the content of E with L and that
of D with H register and result in HL pair)
Suppose the content of HL pair is H=20H ,L=40H
and DE pair is D=30H, E=10H.

Initially After execution

H=20H ,L=40H H=50H ,L=50H
D=30H, E=10H D=30H, E=10H

Flags Affected: Only carry flag is modified.

 ARITHMETIC GROUP
BCD Addition
DAA (Decimal adjust accumulator)
12 BCD
Example: +39 BCD
MVI A,12H ---------------
ADI 39H 51 BCD
DAA .
Initially After execution
12+39=4B 12+39=51 in BCD form.
 LOGICAL GROUP

Write a program to reset last 4 bits of the number 32H

Store result at C200H.
MVI A, 32H A=32H
ANI F0H 00110010 AND
1111000
=00110000=30H
C200=30H
STA C200H
RST1 Stop
 PROGRAM
Write a program to add 10 data bytes. Data is stored from
locations C200H. Store result at C300H.

LXI H,C200H
MVI C, 0AH
MVI A,00H
UP MOV B,M
ADD B
INX H
DCR C
JNZ UP
STA C300H
RST1
 EE 3213
Microprocessors, Microcontrollers and Peripherals

Lecture 08: 8086 Microprocessor Architecture

Course Teacher
Dr. Kalyan Kumar Halder
Associate Professor
Dept. of EEE, KUET
 MICROPROCESSOR 8086

• Reference Book:
– Microprocessors and Interfacing: Programming and
Hardware - Douglas V. Hall
8086 MICROPROCESSOR
Pinouts
 8086 Pins
The 8086 comes in a 40 pin package which means that some pins have
more than one use or are multiplexed. The packaging technology of time
limited the number of pin that could be used.

In particular, the address lines 0 - 15 are multiplexed with data lines 0-15,
address lines 16-19 are multiplexed with status lines. These pins are

AD0 - AD15, A16/S3 - A19/S6

The 8086 has one other pin that is multiplexed and this is BHE’/S7.
BHE stands for Bus High Enable. This is an active low signal that is
asserted when there is data on the upper half of the data bus.

The 8086 has two modes of operation that changes the function of some pins.
The SDK-86 uses the 8086 in the minimum mode with the MN/MX’ pin tied to 5
volts.This is a simple single processor mode. The IBM PC uses an 8088 in the
maximum mode with the MN/MX” pin tied to ground. This is the mode
required for a coprocessor like the 8087.
8086 Pins
In the minimum mode the following pins are available.

HOLD When this pin is high, another master is requesting control of the
local bus, e.g., a DMA controller.

HLDA HOLD Acknowledge: the 8086 signals that it is going to float

the local bus.

WR’ Write: the processor is performing a write memory or I/O operation.

M/IO’ Memory or I/O operation.

DT/R’ Data Transmit or Receive.

DEN’ Data Enable: data is on the multiplexed address/data pins.

ALE Address Latch Enable: the address is on the address/data pins.

This signal is used to capture the address in latches to establish the
address bus.

INTA’ Interrupt acknowledge: acknowledges external interrupt requests.

8086 Pins
The following are pins are available in both minimum and maximum modes.

VCC + 5 volt power supply pin.

GND Ground

RD’ READ: the processor is performing a read memory or I/O operation.

READY Acknowledgement from wait-state logic that the data transfer will
be completed.

RESET Stops processor and restarts execution from FFFF:0. Must be high
for 4 clocks. CS = 0FFFFH, IP = DS = SS = ES = Flags = 0000H, no
other registers are affected.

TEST’ The WAIT instruction waits for this pin to go low. Used with 8087.

NMI Non Maskable Interrupt: transition from low to high causes an

interrupt. Used for emergencies such as power failure.

INTR Interrupt request: masked by the IF bit in FLAG register.

CLK Clock: 33% duty cycle, i.e., high 1/3 the time.
 8086 Features
• 16-bit Arithmetic Logic Unit

• 16-bit data bus (8088 has 8-bit data bus)

• 20-bit address bus - 220 = 1,048,576 = 1 meg

The address refers to a byte in memory. In the 8088, these bytes come in on
the 8-bit data bus. In the 8086, bytes at even addresses come in on the low
half of the data bus (bits 0-7) and bytes at odd addresses come in on the upper
half of the data bus (bits 8-15).

The least significant byte of a word on an 8086 family microprocessor is at the

lower address.
 8086 Architecture
•The 8086 has two parts, the Bus Interface Unit (BIU) and the
Execution Unit (EU).

•The BIU fetches instructions, reads and writes data, and computes the
20-bit address.

• The EU decodes and executes the instructions using the 16-bit ALU.
• The BIU contains the following registers:

IP - the Instruction Pointer

CS - the Code Segment Register
DS - the Data Segment Register
SS - the Stack Segment Register
ES - the Extra Segment Register

The BIU fetches instructions using the CS and IP, written CS:IP, to contruct the
20-bit address. Data is fetched using a segment register (usually the DS) and
an effective address (EA) computed by the EU depending on the addressing
mode.
8086 Block Diagram

I-10
 8086 Architecture
The EU contains the following 16-bit registers:

AX - the Accumulator
BX - the Base Register
CX - the Count Register
DX - the Data Register
SP - the Stack Pointer \ defaults to stack segment
BP - the Base Pointer /
SI - the Source Index Register
DI - the Destination Register

These are referred to as general-purpose registers, although, as seen by

their names, they often have a special-purpose use for some instructions.

The AX, BX, CX, and DX registers can be considers as two 8-bit registers, a
High byte and a Low byte. This allows byte operations and compatibility with
the previous generation of 8-bit processors, the 8080 and 8085. 8085 source
code could be translated in 8086 code and assembled. The 8-bit registers are:

AX --> AH,AL
BX --> BH,BL
CX --> CH,CL
DX --> DH,DL
I-11
 Execution Unit (EU)

Auxiliary Carry Flag Carry Flag

Flag Register When some arithmetic operations This flag is set, when there is
generates carry after the lower half a carry out of MSB in case of
and sends it to upper half, the AC will addition or a borrow in case
be 1 of subtraction.

Sign Flag Zero Flag Parity Flag

After any operation if the
MSB is 1, then it indicates This flag is set, if the result of This is even parity flag. When
that the number is negative. the computation or comparison result has even number of 1, it
And this flag is set to 1 performed by an instruction is will be set to 1, otherwise 0 for
zero odd number of 1s

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OF DF IF TF SF ZF AF PF CF

Tarp Flag
If this flag is set, the processor
Over flow Flag enters the single step execution
mode by generating internal
The overflow flag is set to 1 when the result of a signed operation
interrupts after the execution of
is too large to fit.
each instruction
Direction Flag Interrupt Flag
This is used by string manipulation instructions. If this flag bit
is ‘0’, the string is processed beginning from the lowest Causes the 8086 to recognize
address to the highest address, i.e., auto incrementing mode. external mask interrupts; clearing IF
Otherwise, the string is processed from the highest address disables these interrupts.12
towards the lowest address, i.e., auto decrementing mode.
 EE 3213
Microprocessors, Microcontrollers and Peripherals

Lecture 09: 8086 Architecture and Addressing Modes

Course Teacher
Dr. Kalyan Kumar Halder
Associate Professor
Dept. of EEE, KUET
8086 Microprocessor
Architecture

Execution Unit (EU) Bus Interface Unit (BIU)

EU executes instructions that have BIU fetches instructions, reads data

already been fetched by the BIU. from memory and I/O ports, writes
data to memory and I/ O ports.
BIU and EU functions separately.
2
8086 Microprocessor
Architecture Bus Interface Unit (BIU)

Dedicated Adder to generate

20 bit address

Four 16-bit segment

registers

Code Segment (CS)

Data Segment (DS)
Stack Segment (SS)
Extra Segment (ES)

Segment Registers >> 3

 Memory Address Calculation

 Segment addresses must be stored Segment address 0000

in segment registers
 Offset is derived from the combination + Offset

of pointer registers, the Instruction Memory address

Pointer (IP), and immediate values

 Examples

CS 3 4 8 A 0 SS 5 0 0 0 0
IP + 4 2 1 4 SP + F F E 0
Instruction address 3 8 A B 4 Stack address 5 F F E 0

DS 1 2 3 4 0
DI + 0 0 2 2
Data address 1 2 3 6 2
8086 Microprocessor
Architecture Bus Interface Unit (BIU)

Segment
Registers

8086’s 1-megabyte The 8086 can directly Programs obtain access

memory is divided address four segments to code and data in the
into segments of up (256 K bytes within the 1 segments by changing
to 64K bytes each. M byte of memory) at a the segment register
particular time. content to point to the
desired segments.

5
8086 Microprocessor
Architecture Bus Interface Unit (BIU)

Segment Code Segment Register

Registers
16-bit

CS contains the base or start of the current code segment;

IP contains the distance or offset from this address to the
next instruction byte to be fetched.

BIU computes the 20-bit physical address by logically

shifting the contents of CS 4-bits to the left and then
adding the 16-bit contents of IP.

That is, all instructions of a program are relative to the

contents of the CS register multiplied by 16 and then offset
is added provided by the IP.

6
8086 Microprocessor
Architecture Bus Interface Unit (BIU)

Segment Data Segment Register

Registers
16-bit

Points to the current data segment; operands for most

instructions are fetched from this segment.

The 16-bit contents of the Source Index (SI) or

Destination Index (DI) or a 16-bit displacement are used
as offset for computing the 20-bit physical address.

7
8086 Microprocessor
Architecture Bus Interface Unit (BIU)

Segment Stack Segment Register

Registers
16-bit

Points to the current stack.

The 20-bit physical stack address is calculated from the

Stack Segment (SS) and the Stack Pointer (SP) for stack
instructions such as PUSH and POP.

In based addressing mode, the 20-bit physical stack

address is calculated from the Stack segment (SS) and the
Base Pointer (BP).

8
8086 Microprocessor
Architecture Bus Interface Unit (BIU)

Segment Extra Segment Register

Registers
16-bit

Points to the extra segment in which data (in excess of

64K pointed to by the DS) is stored.

String instructions use the ES and DI to determine the 20-

bit physical address for the destination.

9
8086 Microprocessor
Architecture Bus Interface Unit (BIU)

Segment Instruction Pointer

Registers
16-bit

Always points to the next instruction to be executed within

the currently executing code segment.

So, this register contains the 16-bit offset address pointing

to the next instruction code within the 64Kb of the code
segment area.

Its content is automatically incremented as the execution

of the next instruction takes place.

10
8086 Microprocessor
Architecture Bus Interface Unit (BIU)

Instruction queue

A group of First-In-First-
Out (FIFO) in which up to
6 bytes of instruction
code are pre fetched
from the memory ahead
of time.

This is done in order to

speed up the execution
by overlapping
instruction fetch with
execution.

This mechanism is known

as pipelining.

11
 8086 Microprocessor
Architecture Execution Unit (EU)

EU decodes and
executes instructions.

A decoder in the EU
control system
translates instructions.

16-bit ALU for

performing arithmetic
and logic operation

Four general purpose

registers(AX, BX, CX, DX);

Pointer registers (Stack

Pointer, Base Pointer);

and
Some of the 16 bit registers can be
Index registers (Source used as two 8 bit registers as :
Index, Destination Index)
each of 16-bits AX can be used as AH and AL
BX can be used as BH and BL
CX can be used as CH and CL 12
DX can be used as DH and DL
8086 Microprocessor
Architecture Execution Unit (EU)

EU Accumulator Register (AX)

Registers
Consists of two 8-bit registers AL and AH, which can be
combined together and used as a 16-bit register AX.

AL in this case contains the low order byte of the word,

and AH contains the high-order byte.

The I/O instructions use the AX or AL for inputting /

outputting 16 or 8 bit data to or from an I/O port.

Multiplication and Division instructions also use the AX or

AL.

13
8086 Microprocessor
Architecture Execution Unit (EU)

EU Base Register (BX)

Registers
Consists of two 8-bit registers BL and BH, which can be
combined together and used as a 16-bit register BX.

BL in this case contains the low-order byte of the word,

and BH contains the high-order byte.

This is the only general purpose register whose contents

can be used for addressing the 8086 memory.

All memory references utilizing this register content for

addressing use DS as the default segment register.

14
8086 Microprocessor
Architecture Execution Unit (EU)

EU Counter Register (CX)

Registers
Consists of two 8-bit registers CL and CH, which can be
combined together and used as a 16-bit register CX.

When combined, CL register contains the low order byte of

the word, and CH contains the high-order byte.

Instructions such as SHIFT, ROTATE and LOOP use the

contents of CX as a counter.

Example:

The instruction LOOP START automatically decrements

CX by 1 without affecting flags and will check if [CX] =
0.

If it is zero, 8086 executes the next instruction;

otherwise the 8086 branches to the label START.

15
8086 Microprocessor
Architecture Execution Unit (EU)

EU Data Register (DX)

Registers
Consists of two 8-bit registers DL and DH, which can be
combined together and used as a 16-bit register DX.

When combined, DL register contains the low order byte of

the word, and DH contains the high-order byte.

Used to hold the high 16-bit result (data) in 16 X 16

multiplication or the high 16-bit dividend (data) before a
32 ÷ 16 division and the 16-bit reminder after division.

16
8086 Microprocessor
Architecture Execution Unit (EU)

EU Stack Pointer (SP) and Base Pointer (BP)

Registers
SP and BP are used to access data in the stack segment.

SP is used as an offset from the current SS during

execution of instructions that involve the stack segment in
the external memory.

SP contents are automatically updated (incremented/

decremented) due to execution of a POP or PUSH
instruction.

BP contains an offset address in the current SS, which is

used by instructions utilizing the based addressing mode.

17
8086 Microprocessor
Architecture Execution Unit (EU)

EU Source Index (SI) and Destination Index (DI)

Registers
Used in indexed addressing.

Instructions that process data strings use the SI and DI

registers together with DS and ES respectively in order to
distinguish between the source and destination addresses.

18
8086 Microprocessor
Addressing Modes

Every instruction of a program has to operate on a data.

The different ways in which a source operand is denoted
in an instruction are known as addressing modes.

1. Register Addressing
Group I : Addressing modes for
2. Immediate Addressing register and immediate data

3. Direct Addressing

4. Register Indirect Addressing

5. Based Addressing
Group II : Addressing modes for
6. Indexed Addressing memory data
7. Based Index Addressing

8. String Addressing

9. Direct I/O port Addressing

Group III : Addressing modes for
10. Indirect I/O port Addressing I/O ports

11. Relative Addressing Group IV : Relative Addressing mode

12. Implied Addressing Group V : Implied Addressing mode

19
8086 Microprocessor Group I : Addressing modes for
Addressing Modes register and immediate data

1. Register Addressing The instruction will specify the name of the

register which holds the data to be operated by
2. Immediate Addressing the instruction.
3. Direct Addressing Example:
4. Register Indirect Addressing
MOV CL, DH
5. Based Addressing
The content of 8-bit register DH is moved to
6. Indexed Addressing another 8-bit register CL

7. Based Index Addressing (CL)  (DH)

8. String Addressing

9. Direct I/O port Addressing

10. Indirect I/O port Addressing

11. Relative Addressing

12. Implied Addressing

20
8086 Microprocessor Group I : Addressing modes for
Addressing Modes register and immediate data

1. Register Addressing
In immediate addressing mode, an 8-bit or 16-bit
2. Immediate Addressing data is specified as part of the instruction
3. Direct Addressing
Example:
4. Register Indirect Addressing
MOV DL, 08H
5. Based Addressing
The 8-bit data (08H) given in the instruction is
6. Indexed Addressing moved to DL

7. Based Index Addressing (DL)  08H

8. String Addressing
MOV AX, 0A9FH
9. Direct I/O port Addressing
The 16-bit data (0A9FH) given in the instruction is
10. Indirect I/O port Addressing
moved to AX register
11. Relative Addressing
(AX)  0A9FH
12. Implied Addressing

21
8086 Microprocessor Group II : Addressing modes
Addressing Modes for memory data

1. Register Addressing

2. Immediate Addressing

3. Direct Addressing
Here, the effective address of the memory
location at which the data operand is stored is
4. Register Indirect Addressing given in the instruction.

5. Based Addressing The effective address is just a 16-bit number

written directly in the instruction.
6. Indexed Addressing
Example:
7. Based Index Addressing
MOV BX, [1354H]
8. String Addressing MOV BL, [0400H]
9. Direct I/O port Addressing
The square brackets around the 1354H denotes
the contents of the memory location. When
10. Indirect I/O port Addressing
executed, this instruction will copy the contents of
11. Relative Addressing the memory location into BX register.

12. Implied Addressing This addressing mode is called direct because the
displacement of the operand from the segment
base is specified directly in the instruction.

22
8086 Microprocessor Group II : Addressing modes
Addressing Modes for memory data

1. Register Addressing In Register indirect addressing, name of the

register which holds the effective address (EA)
2. Immediate Addressing will be specified in the instruction.

3. Direct Addressing Registers used to hold EA are any of the following

registers:
4. Register Indirect Addressing
BX, BP, DI and SI.
5. Based Addressing
Content of the DS register is used for base
6. Indexed Addressing
address calculation.
7. Based Index Addressing
Example:
Note : Register/ memory
8. String Addressing
enclosed in brackets refer
MOV CX, [BX] to content of register/
9. Direct I/O port Addressing memory
Operations:
10. Indirect I/O port Addressing
EA = (BX)
11. Relative Addressing BA = (DS) x 1610
MA = BA + EA
12. Implied Addressing
(CX)  (MA) or,

(CL)  (MA)
(CH)  (MA +1)
23
8086 Microprocessor Group II : Addressing modes
Addressing Modes for memory data

1. Register Addressing In Based Addressing, BX or BP is used to hold the

base value for effective address and a signed 8-bit
2. Immediate Addressing or unsigned 16-bit displacement will be specified
in the instruction.
3. Direct Addressing
In case of 8-bit displacement, it is sign extended
4. Register Indirect Addressing to 16-bit before adding to the base value.

5. Based Addressing When BX holds the base value of EA, 20-bit

physical address is calculated from BX and DS.
6. Indexed Addressing
When BP holds the base value of EA, BP and SS is
7. Based Index Addressing
used.
8. String Addressing
Example:
9. Direct I/O port Addressing
MOV AX, [BX + 08H]
10. Indirect I/O port Addressing
Operations:
11. Relative Addressing
0008H  08H (Sign extended)
12. Implied Addressing EA = (BX) + 0008H
BA = (DS) x 1610
MA = BA + EA

(AX)  (MA) or,

(AL)  (MA)
24
(AH)  (MA + 1)
8086 Microprocessor Group II : Addressing modes
Addressing Modes for memory data

1. Register Addressing SI or DI register is used to hold an index value for

memory data and a signed 8-bit or unsigned 16-
2. Immediate Addressing bit displacement will be specified in the
instruction.
3. Direct Addressing
Displacement is added to the index value in SI or
4. Register Indirect Addressing DI register to obtain the EA.

5. Based Addressing In case of 8-bit displacement, it is sign extended

to 16-bit before adding to the base value.
6. Indexed Addressing

7. Based Index Addressing

Example:
8. String Addressing
MOV CX, [SI + 0A2H]
9. Direct I/O port Addressing
Operations:
10. Indirect I/O port Addressing
FFA2H  A2H (Sign extended)
11. Relative Addressing
EA = (SI) + FFA2H
12. Implied Addressing BA = (DS) x 1610
MA = BA + EA

(CX)  (MA) or,

(CL)  (MA)
(CH)  (MA + 1)
25
8086 Microprocessor Group II : Addressing modes
Addressing Modes for memory data

1. Register Addressing In Based Index Addressing, the effective address

is computed from the sum of a base register (BX
2. Immediate Addressing or BP), an index register (SI or DI) and a
displacement.
3. Direct Addressing
Example:
4. Register Indirect Addressing
MOV DX, [BX + SI + 0AH]
5. Based Addressing
Operations:
6. Indexed Addressing
000AH  0AH (Sign extended)
7. Based Index Addressing

8. String Addressing EA = (BX) + (SI) + 000AH

BA = (DS) x 1610
9. Direct I/O port Addressing MA = BA + EA

10. Indirect I/O port Addressing (DX)  (MA) or,

11. Relative Addressing (DL)  (MA)

(DH)  (MA + 1)
12. Implied Addressing

26
8086 Microprocessor Group II : Addressing modes
Addressing Modes for memory data

1. Register Addressing Employed in string operations to operate on string

data.
2. Immediate Addressing
The effective address (EA) of source data is stored
3. Direct Addressing in SI register and the EA of destination is stored in
DI register.
4. Register Indirect Addressing
Segment register for calculating base address of
5. Based Addressing source data is DS and that of the destination data
is ES
6. Indexed Addressing

7. Based Index Addressing

Example: MOVS BYTE
8. String Addressing
Operations:
9. Direct I/O port Addressing
Calculation of source memory location:
10. Indirect I/O port Addressing EA = (SI) BA = (DS) x 1610 MA = BA + EA

11. Relative Addressing Calculation of destination memory location:

EAE = (DI) BAE = (ES) x 1610 MAE = BAE + EAE
12. Implied Addressing

Note : Effective address of (MAE)  (MA)

the Extra segment register
If DF = 1, then (SI)  (SI) – 1 and (DI) = (DI) - 1
If DF = 0, then (SI)  (SI) +1 and (DI) = (DI)27+ 1
8086 Microprocessor Group III : Addressing
Addressing Modes modes for I/O ports

1. Register Addressing These addressing modes are used to access data

from standard I/O mapped devices or ports.
2. Immediate Addressing
In direct port addressing mode, an 8-bit port
3. Direct Addressing address is directly specified in the instruction.

4. Register Indirect Addressing Example: IN AL, [09H]

5. Based Addressing Operations: PORTaddr = 09H

(AL)  (PORT)
6. Indexed Addressing
Content of port with address 09H is
7. Based Index Addressing
moved to AL register
8. String Addressing
In indirect port addressing mode, the instruction
9. Direct I/O port Addressing will specify the name of the register which holds
the port address. In 8086, the 16-bit port address
10. Indirect I/O port Addressing is stored in the DX register.

11. Relative Addressing Example: OUT [DX], AX

12. Implied Addressing Operations: PORTaddr = (DX)

(PORT)  (AX)

Content of AX is moved to port

whose address is specified by DX
register. 28
8086 Microprocessor Group IV : Relative
Addressing Modes Addressing mode

1. Register Addressing

2. Immediate Addressing

3. Direct Addressing In this addressing mode, the effective address of

a program instruction is specified relative to
4. Register Indirect Addressing Instruction Pointer (IP) by an 8-bit signed
displacement.
5. Based Addressing
Example: JZ 0AH
6. Indexed Addressing
Operations:
7. Based Index Addressing

8. String Addressing 000AH  0AH (sign extend)

9. Direct I/O port Addressing If ZF = 1, then

10. Indirect I/O port Addressing EA = (IP) + 000AH

BA = (CS) x 1610
11. Relative Addressing MA = BA + EA

12. Implied Addressing If ZF = 1, then the program control jumps to

new address calculated above.

If ZF = 0, then next instruction of the

program is executed.
29
8086 Microprocessor Group IV : Implied
Addressing Modes Addressing mode

1. Register Addressing

2. Immediate Addressing

3. Direct Addressing

4. Register Indirect Addressing

5. Based Addressing

6. Indexed Addressing
Instructions using this mode have no operands.
The instruction itself will specify the data to be
7. Based Index Addressing
operated by the instruction.
8. String Addressing
Example: CLC
9. Direct I/O port Addressing
This clears the carry flag to zero.
10. Indirect I/O port Addressing

11. Relative Addressing

12. Implied Addressing

30
 EE 3213
Microprocessors, Microcontrollers and Peripherals

Lecture 10: 8086 Instruction Set

Course Teacher
Dr. Kalyan Kumar Halder
Associate Professor
Dept. of EEE, KUET
8086 Microprocessor
Instruction Set

8086 supports 6 types of instructions.

1. Data Transfer Instructions

2. Arithmetic Instructions

3. Logical Instructions

4. String manipulation Instructions

5. Process Control Instructions

6. Control Transfer Instructions

2
8086 Microprocessor
Instruction Set

1. Data Transfer Instructions

Instructions that are used to transfer data/ address in to

registers, memory locations and I/O ports.

Generally involve two operands: Source operand and

Destination operand of the same size.

Source: Register or a memory location or an immediate data

Destination : Register or a memory location.

The size should be a either a byte or a word.

A 8-bit data can only be moved to 8-bit register/ memory

and a 16-bit data can be moved to 16-bit register/ memory.

3
8086 Microprocessor
Instruction Set

1. Data Transfer Instructions

Mnemonics: MOV, XCHG, PUSH, POP, IN, OUT …

MOV reg2/ mem, reg1/ mem

MOV reg2, reg1 (reg2)  (reg1)

MOV mem, reg1 (mem)  (reg1)
MOV reg2, mem (reg2)  (mem)

MOV reg/ mem, data

MOV reg, data (reg)  data

MOV mem, data (mem)  data

XCHG reg2/ mem, reg1

XCHG reg2, reg1 (reg2)  (reg1)

XCHG mem, reg1 (mem)  (reg1)

4
8086 Microprocessor
Instruction Set

1. Data Transfer Instructions

Mnemonics: MOV, XCHG, PUSH, POP, IN, OUT …

PUSH reg16/ mem

PUSH reg16 (SP)  (SP) – 2

MA S = (SS) x 16 10 + SP
(MA S ; MA S + 1)  (reg16)

PUSH mem (SP)  (SP) – 2

MA S = (SS) x 16 10 + SP
(MA S ; MA S + 1)  (mem)

POP reg16/ mem

POP reg16 MA S = (SS) x 16 10 + SP

(reg16)  (MA S ; MA S + 1)
(SP)  (SP) + 2

POP mem MA S = (SS) x 16 10 + SP

(mem)  (MA S ; MA S + 1)
(SP)  (SP) + 2
5
8086 Microprocessor
Instruction Set

1. Data Transfer Instructions

Mnemonics: MOV, XCHG, PUSH, POP, IN, OUT …

IN A, [DX] OUT [DX], A

IN AL, [DX] PORTaddr = (DX) OUT [DX], AL PORTaddr = (DX)

(AL)  (PORT) (PORT)  (AL)

IN AX, [DX] PORTaddr = (DX) OUT [DX], AX PORTaddr = (DX)

(AX)  (PORT) (PORT)  (AX)

IN A, addr8 OUT addr8, A

IN AL, addr8 (AL)  (addr8) OUT addr8, AL (addr8)  (AL)

IN AX, addr8 (AX)  (addr8) OUT addr8, AX (addr8)  (AX)

6
8086 Microprocessor
Instruction Set

2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

ADD reg2/ mem, reg1/mem

ADD reg2, reg1 (reg2)  (reg1) + (reg2)

ADD reg2, mem (reg2)  (reg2) + (mem)
ADD mem, reg1 (mem)  (mem)+(reg1)

ADD reg/mem, data

ADD reg, data (reg)  (reg)+ data

ADD mem, data (mem)  (mem)+data

ADD A, data

ADD AL, data8 (AL)  (AL) + data8

ADD AX, data16 (AX)  (AX) +data16

7
8086 Microprocessor
Instruction Set

2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

ADC reg2/ mem, reg1/mem

ADC reg2, reg1 (reg2)  (reg1) + (reg2)+CF

ADC reg2, mem (reg2)  (reg2) + (mem)+CF
ADC mem, reg1 (mem)  (mem)+(reg1)+CF

ADC reg/mem, data

ADC reg, data (reg)  (reg)+ data+CF

ADC mem, data (mem)  (mem)+data+CF

ADDC A, data

ADD AL, data8 (AL)  (AL) + data8+CF

ADD AX, data16 (AX)  (AX) +data16+CF

8
8086 Microprocessor
Instruction Set

2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

SUB reg2/ mem, reg1/mem

SUB reg2, reg1 (reg2)  (reg1) - (reg2)

SUB reg2, mem (reg2)  (reg2) - (mem)
SUB mem, reg1 (mem)  (mem) - (reg1)

SUB reg/mem, data

SUB reg, data (reg)  (reg) - data

SUB mem, data (mem)  (mem) - data

SUB A, data

SUB AL, data8 (AL)  (AL) - data8

SUB AX, data16 (AX)  (AX) - data16

9
8086 Microprocessor
Instruction Set

2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

SBB reg2/ mem, reg1/mem

SBB reg2, reg1 (reg2)  (reg1) - (reg2) - CF

SBB reg2, mem (reg2)  (reg2) - (mem)- CF
SBB mem, reg1 (mem)  (mem) - (reg1) –CF

SBB reg/mem, data

SBB reg, data (reg)  (reg) – data - CF

SBB mem, data (mem)  (mem) - data - CF

SBB A, data

SBB AL, data8 (AL)  (AL) - data8 - CF

SBB AX, data16 (AX)  (AX) - data16 - CF

10
8086 Microprocessor
Instruction Set

2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

INC reg/ mem

INC reg8 (reg8)  (reg8) + 1

INC reg16 (reg16)  (reg16) + 1

INC mem (mem)  (mem) + 1

DEC reg/ mem

DEC reg8 (reg8)  (reg8) - 1

DEC reg16 (reg16)  (reg16) - 1

DEC mem (mem)  (mem) - 1

11
8086 Microprocessor
Instruction Set

2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

MUL reg/ mem

MUL reg For byte : (AX)  (AL) x (reg8)

For word : (DX)(AX)  (AX) x (reg16)

MUL mem For byte : (AX)  (AL) x (mem8)

For word : (DX)(AX)  (AX) x (mem16)

IMUL reg/ mem

IMUL reg For byte : (AX)  (AL) x (reg8)

For word : (DX)(AX)  (AX) x (reg16)

IMUL mem For byte : (AX)  (AX) x (mem8)

For word : (DX)(AX)  (AX) x (mem16)

12
8086 Microprocessor
Instruction Set

2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

DIV reg/ mem

DIV reg For 16-bit :- 8-bit :

(AL)  (AX) :- (reg8) Quotient
(AH)  (AX) MOD(reg8) Remainder

For 32-bit :- 16-bit :

(AX)  (DX)(AX) :- (reg16) Quotient
(DX)  (DX)(AX) MOD(reg16) Remainder

DIV mem For 16-bit :- 8-bit :

(AL)  (AX) :- (mem8) Quotient
(AH)  (AX) MOD(mem8) Remainder

For 32-bit :- 16-bit :

(AX)  (DX)(AX) :- (mem16) Quotient
(DX)  (DX)(AX) MOD(mem16) Remainder

13
8086 Microprocessor
Instruction Set

2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

IDIV reg/ mem

IDIV reg For 16-bit :- 8-bit :

(AL)  (AX) :- (reg8) Quotient
(AH)  (AX) MOD(reg8) Remainder

For 32-bit :- 16-bit :

(AX)  (DX)(AX) :- (reg16) Quotient
(DX)  (DX)(AX) MOD(reg16) Remainder

IDIV mem For 16-bit :- 8-bit :

(AL)  (AX) :- (mem8) Quotient
(AH)  (AX) MOD(mem8) Remainder

For 32-bit :- 16-bit :

(AX)  (DX)(AX) :- (mem16) Quotient
(DX)  (DX)(AX) MOD(mem16) Remainder

14
8086 Microprocessor
Instruction Set

2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

CMP reg2/mem, reg1/ mem

CMP reg2, reg1 Modify flags  (reg2) – (reg1)

If (reg2) > (reg1) then CF=0, ZF=0, SF=0

If (reg2) < (reg1) then CF=1, ZF=0, SF=1
If (reg2) = (reg1) then CF=0, ZF=1, SF=0

CMP reg2, mem Modify flags  (reg2) – (mem)

If (reg2) > (mem) then CF=0, ZF=0, SF=0

If (reg2) < (mem) then CF=1, ZF=0, SF=1
If (reg2) = (mem) then CF=0, ZF=1, SF=0

CMP mem, reg1 Modify flags  (mem) – (reg1)

If (mem) > (reg1) then CF=0, ZF=0, SF=0

If (mem) < (reg1) then CF=1, ZF=0, SF=1
If (mem) = (reg1) then CF=0, ZF=1, SF=0

15
8086 Microprocessor
Instruction Set

2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

CMP reg/mem, data

CMP reg, data Modify flags  (reg) – (data)

If (reg) > data then CF=0, ZF=0, SF=0

If (reg) < data then CF=1, ZF=0, SF=1
If (reg) = data then CF=0, ZF=1, SF=0

CMP mem, data Modify flags  (mem) – (mem)

If (mem) > data then CF=0, ZF=0, SF=0

If (mem) < data then CF=1, ZF=0, SF=1
If (mem) = data then CF=0, ZF=1, SF=0

16
8086 Microprocessor
Instruction Set

2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

CMP A, data

CMP AL, data8 Modify flags  (AL) – data8

If (AL) > data8 then CF=0, ZF=0, SF=0

If (AL) < data8 then CF=1, ZF=0, SF=1
If (AL) = data8 then CF=0, ZF=1, SF=0

CMP AX, data16 Modify flags  (AX) – data16

If (AX) > data16 then CF=0, ZF=0, SF=0

If (mem) < data16 then CF=1, ZF=0, SF=1
If (mem) = data16 then CF=0, ZF=1, SF=0

17
8086 Microprocessor
Instruction Set

3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

18
8086 Microprocessor
Instruction Set

3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

19
8086 Microprocessor
Instruction Set

3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

20
8086 Microprocessor
Instruction Set

3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

21
8086 Microprocessor
Instruction Set

3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

22
8086 Microprocessor
Instruction Set

3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

23
8086 Microprocessor
Instruction Set

3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

24
8086 Microprocessor
Instruction Set

3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

25
8086 Microprocessor
Instruction Set

4. String Manipulation Instructions

 String : Sequence of bytes or words

 8086 instruction set includes instruction for string movement, comparison,

scan, load and store.

 REP instruction prefix : used to repeat execution of string instructions

 String instructions end with S or SB or SW.

S represents string, SB string byte and SW string word.

 Offset or effective address of the source operand is stored in SI register and

that of the destination operand is stored in DI register.

 Depending on the status of DF, SI and DI registers are automatically

updated.

 DF = 0  SI and DI are incremented by 1 for byte and 2 for word.

 DF = 1  SI and DI are decremented by 1 for byte and 2 for word.

26
8086 Microprocessor
Instruction Set

4. String Manipulation Instructions

Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS

REP

REPZ/ REPE While CX  0 and ZF = 1, repeat execution of

string instruction and
(Repeat CMPS or SCAS until (CX)  (CX) – 1
ZF = 0)

REPNZ/ REPNE While CX  0 and ZF = 0, repeat execution of

string instruction and
(Repeat CMPS or SCAS until (CX)  (CX) - 1
ZF = 1)

27
8086 Microprocessor
Instruction Set

4. String Manipulation Instructions

Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS

MOVS

MOVSB MA = (DS) x 1610 + (SI)

MAE = (ES) x 1610 + (DI)

(MAE)  (MA)

If DF = 0, then (DI)  (DI) + 1; (SI)  (SI) + 1

If DF = 1, then (DI)  (DI) - 1; (SI)  (SI) - 1

MOVSW MA = (DS) x 1610 + (SI)

MAE = (ES) x 1610 + (DI)

(MAE ; MAE + 1)  (MA; MA + 1)

If DF = 0, then (DI)  (DI) + 2; (SI)  (SI) + 2

If DF = 1, then (DI)  (DI) - 2; (SI)  (SI) - 2

28
8086 Microprocessor
Instruction Set

4. String Manipulation Instructions

Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS

Compare two string byte or string word

CMPS

CMPSB MA = (DS) x 1610 + (SI)

MAE = (ES) x 1610 + (DI)

Modify flags  (MA) - (MAE)

If (MA) > (MAE), then CF = 0; ZF = 0; SF = 0

If (MA) < (MAE), then CF = 1; ZF = 0; SF = 1
CMPSW If (MA) = (MAE), then CF = 0; ZF = 1; SF = 0

For byte operation

If DF = 0, then (DI)  (DI) + 1; (SI)  (SI) + 1
If DF = 1, then (DI)  (DI) - 1; (SI)  (SI) - 1

For word operation

If DF = 0, then (DI)  (DI) + 2; (SI)  (SI) + 2
If DF = 1, then (DI)  (DI) - 2; (SI)  (SI) - 2

29
8086 Microprocessor
Instruction Set

4. String Manipulation Instructions

Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS
Scan (compare) a string byte or word with accumulator
SCAS

SCASB MAE = (ES) x 1610 + (DI)

Modify flags  (AL) - (MAE)

If (AL) > (MAE), then CF = 0; ZF = 0; SF = 0

If (AL) < (MAE), then CF = 1; ZF = 0; SF = 1
If (AL) = (MAE), then CF = 0; ZF = 1; SF = 0

If DF = 0, then (DI)  (DI) + 1

If DF = 1, then (DI)  (DI) – 1

SCASW MAE = (ES) x 1610 + (DI)

Modify flags  (AL) - (MAE)

If (AX) > (MAE ; MAE + 1), then CF = 0; ZF = 0; SF = 0

If (AX) < (MAE ; MAE + 1), then CF = 1; ZF = 0; SF = 1
If (AX) = (MAE ; MAE + 1), then CF = 0; ZF = 1; SF = 0

If DF = 0, then (DI)  (DI) + 2

30
If DF = 1, then (DI)  (DI) – 2
8086 Microprocessor
Instruction Set

4. String Manipulation Instructions

Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS

Load string byte in to AL or string word in to AX

LODS

LODSB MA = (DS) x 1610 + (SI)

(AL)  (MA)

If DF = 0, then (SI)  (SI) + 1

If DF = 1, then (SI)  (SI) – 1

LODSW MA = (DS) x 1610 + (SI)

(AX)  (MA ; MA + 1)

If DF = 0, then (SI)  (SI) + 2

If DF = 1, then (SI)  (SI) – 2

31
8086 Microprocessor
Instruction Set

4. String Manipulation Instructions

Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS

Store byte from AL or word from AX in to string

STOS

STOSB MAE = (ES) x 1610 + (DI)

(MAE)  (AL)

If DF = 0, then (DI)  (DI) + 1

If DF = 1, then (DI)  (DI) – 1

STOSW MAE = (ES) x 1610 + (DI)

(MAE ; MAE + 1 )  (AX)

If DF = 0, then (DI)  (DI) + 2

If DF = 1, then (DI)  (DI) – 2

32
8086 Microprocessor
Instruction Set

5. Processor Control Instructions

Mnemonics Explanation
STC Set CF  1

CLC Clear CF  0

CMC Complement carry CF  CF/

STD Set direction flag DF  1

CLD Clear direction flag DF  0

STI Set interrupt enable flag IF  1

CLI Clear interrupt enable flag IF  0

NOP No operation

HLT Halt after interrupt is set

WAIT Wait for TEST pin active

ESC opcode mem/ reg Used to pass instruction to a coprocessor

which shares the address and data bus
with the 8086

LOCK Lock bus during next instruction 33

8086 Microprocessor
Instruction Set

6. Control Transfer Instructions

Transfer the control to a specific destination or target instruction

Do not affect flags

 8086 Unconditional transfers

Mnemonics Explanation
CALL reg/ mem/ disp16 Call subroutine

RET Return from subroutine

JMP reg/ mem/ disp8/ disp16 Unconditional jump

34
8086 Microprocessor
Instruction Set

6. Control Transfer Instructions

 8086 signed conditional  8086 unsigned conditional

branch instructions branch instructions

Checks flags

If conditions are true, the program control is

transferred to the new memory location in the same
segment by modifying the content of IP

35
8086 Microprocessor
Instruction Set

6. Control Transfer Instructions

 8086 signed conditional  8086 unsigned conditional

branch instructions branch instructions

Name Alternate name Name Alternate name

JE disp8 JZ disp8 JE disp8 JZ disp8
Jump if equal Jump if result is 0 Jump if equal Jump if result is 0

JNE disp8 JNZ disp8 JNE disp8 JNZ disp8

Jump if not equal Jump if not zero Jump if not equal Jump if not zero
JG disp8 JNLE disp8 JA disp8 JNBE disp8
Jump if greater Jump if not less or Jump if above Jump if not below
equal or equal
JGE disp8 JNL disp8 JAE disp8 JNB disp8
Jump if greater Jump if not less Jump if above or Jump if not below
than or equal equal
JL disp8 JNGE disp8 JB disp8 JNAE disp8
Jump if less than Jump if not Jump if below Jump if not above
greater than or or equal
equal
JLE disp8 JNG disp8 JBE disp8 JNA disp8
Jump if less than Jump if not Jump if below or Jump if not above
or equal greater equal 36
8086 Microprocessor
Instruction Set

6. Control Transfer Instructions

 8086 conditional branch instructions affecting individual flags

Mnemonics Explanation

JC disp8 Jump if CF = 1

JNC disp8 Jump if CF = 0

JP disp8 Jump if PF = 1

JNP disp8 Jump if PF = 0

JO disp8 Jump if OF = 1

JNO disp8 Jump if OF = 0

JS disp8 Jump if SF = 1

JNS disp8 Jump if SF = 0

JZ disp8 Jump if result is zero, i.e, Z = 1

JNZ disp8 Jump if result is not zero, i.e, Z = 1

37
 EE 3213
Microprocessors, Microcontrollers and Peripherals

Lecture 11: 8086 Assemble Directives, 8088, 8087 Co-Processor

Course Teacher
Dr. Kalyan Kumar Halder
Associate Professor
Dept. of EEE, KUET
8086 Microprocessor
Assemble Directives

Instructions to the Assembler regarding the program being

executed.

Control the generation of machine codes and organization of

the program; but no machine codes are generated for
assembler directives.

Also called ‘pseudo instructions’

Used to :
› specify the start and end of a program
› attach value to variables
› allocate storage locations to input/ output data
› define start and end of segments, procedures, macros etc..

2
8086 Microprocessor
Assemble Directives

DB Define Byte

DW Define a byte type (8-bit) variable

SEGMENT Reserves specific amount of memory

ENDS locations to each variable

ASSUME Range : 00H – FFH for unsigned value;

00H – 7FH for positive value and
ORG 80H – FFH for negative value
END
EVEN General form : variable DB value/ values
EQU

PROC
FAR Example:
NEAR LIST DB 7FH, 42H, 35H
ENDP
Three consecutive memory locations are reserved for
SHORT the variable LIST and each data specified in the
instruction are stored as initial value in the reserved
MACRO memory location
ENDM 3
8086 Microprocessor
Assemble Directives

DB Define Word

DW Define a word type (16-bit) variable

SEGMENT Reserves two consecutive memory locations

ENDS to each variable

ASSUME Range : 0000H – FFFFH for unsigned value;

0000H – 7FFFH for positive value and
ORG 8000H – FFFFH for negative value
END
EVEN General form : variable DW value/ values
EQU

PROC
FAR Example:
NEAR ALIST DW 6512H, 0F251H, 0CDE2H
ENDP
Six consecutive memory locations are reserved for
SHORT the variable ALIST and each 16-bit data specified in
the instruction is stored in two consecutive memory
MACRO location.
ENDM 4
8086 Microprocessor
Assemble Directives

DB SEGMENT : Used to indicate the beginning of

a code/ data/ stack segment
DW
ENDS : Used to indicate the end of a code/
SEGMENT data/ stack segment
ENDS
General form:
ASSUME

ORG
END Segnam SEGMENT
EVEN
…
EQU … Program code
… or
PROC … Data Defining Statements
…
FAR …
NEAR
ENDP Segnam ENDS

SHORT

MACRO User defined name of

the segment
ENDM 5
8086 Microprocessor
Assemble Directives

DB Informs the assembler the name of the

program/ data segment that should be used
DW for a specific segment.

SEGMENT General form:

ENDS
ASSUME segreg : segnam, .. , segreg : segnam
ASSUME

ORG
User defined name of
END Segment Register
the segment
EVEN
EQU

PROC Example:
FAR
NEAR ASSUME CS: ACODE, DS:ADATA Tells the assembler that the
ENDP instructions of the program are
stored in the segment ACODE and
data are stored in the segment
SHORT ADATA

MACRO
ENDM 6
8086 Microprocessor
Assemble Directives

ORG (Origin) is used to assign the starting address

DB
(Effective address) for a program/ data segment

DW END is used to terminate a program; statements

after END will be ignored
SEGMENT
ENDS EVEN : Informs the assembler to store program/
data segment starting from an even address
ASSUME
EQU (Equate) is used to attach a value to a variable

ORG
Examples:
END
EVEN ORG 1000H Informs the assembler that the statements
EQU following ORG 1000H should be stored in
memory starting with effective address
1000H
PROC
FAR
LOOP EQU 10FEH Value of variable LOOP is 10FEH
NEAR
ENDP
_SDATA SEGMENT In this data segment, effective address of
SHORT ORG 1200H memory location assigned to A will be 1200H
A DB 4CH and that of B will be 1202H and 1203H.
EVEN
MACRO B DW 1052H
ENDM _SDATA ENDS 7
8086 Microprocessor
Assemble Directives

PROC Indicates the beginning of a procedure

DB
ENDP End of procedure
DW
FAR Intersegment call
SEGMENT
ENDS NEAR Intrasegment call

General form
ASSUME

ORG
procname PROC[NEAR/ FAR]
END
EVEN …
… Program statements of the
EQU procedure
…

PROC RET Last statement of the

procedure
ENDP
FAR procname ENDP
NEAR

SHORT User defined name of

the procedure
MACRO
ENDM 8
8086 Microprocessor
Assemble Directives

DB
Examples:
DW

SEGMENT ADD64 PROC NEAR The subroutine/ procedure named ADD64 is

ENDS declared as NEAR and so the assembler will
… code the CALL and RET instructions involved
… in this procedure as near call and return
ASSUME …

RET
ORG ADD64 ENDP
END
EVEN
EQU CONVERT PROC FAR The subroutine/ procedure named CONVERT
is declared as FAR and so the assembler will
… code the CALL and RET instructions involved
PROC … in this procedure as far call and return
ENDP …
FAR
RET
NEAR CONVERT ENDP

SHORT

MACRO
ENDM 9
8086 Microprocessor
Assemble Directives

DB Reserves one memory location for 8-bit

signed displacement in jump instructions
DW
Example:
SEGMENT
ENDS

ASSUME JMP SHORT The directive will reserve one

AHEAD memory location for 8-bit
ORG displacement named AHEAD
END
EVEN
EQU

PROC
ENDP
FAR
NEAR

SHORT

MACRO
ENDM 10
8086 Microprocessor
Assemble Directives

DB MACRO Indicate the beginning of a macro

DW ENDM End of a macro

SEGMENT General form:

ENDS

ASSUME macroname MACRO[Arg1, Arg2 ...]

Program
… statements in
ORG … the macro
END …
EVEN
EQU macroname ENDM

PROC
ENDP
FAR User defined name of
NEAR the macro

SHORT

MACRO
ENDM 11
8086 Microprocessor
8086 Programming

 Write a program to multiply two hexadecimal numbers.

CODE SEGMENT
ASSUME CS: CODE & DS: CODE
MOV AX, 1234H
MOV CX, 0034H
MUL CX
HLT
CODE ENDS
END

12
8086 Microprocessor
8086 Programming

 Write a program using 8086 SDK which multiplies the two 16-bit words
in the memory locations and save the results in the next memory
locations.
DATA SEGMENT
MULTIPLICAND DW 204AH
MULTIPLIER DW 3B2AH
PRODUCT DW 2 DUP(0)
DATA ENDS

CODE SEGMENT
ASSUME CS: CODE & DS: DATA
MOV AX, DATA
MOV DS, AX
MOV AX, MULTIPLICAND
MUL MULTIPLIER
MOV PRODUCT, AX
MOV PRODUCT+2, DX
HLT
CODE ENDS
END 13
8086 Microprocessor
8086 and 8088 comparison

8086 8088

Similar EU and Instruction set ; dissimilar BIU

16-bit Data bus lines obtained by 8-bit Data bus lines obtained by
demultiplexing AD0 – AD15 demultiplexing AD0 – AD7

20-bit address bus 20-bit address bus

Two banks of memory each of 512 Single memory bank

kb

6-byte instruction queue 4-byte instruction queue

Clock speeds: 5 / 8 / 10 MHz 5 / 8 MHz

In MIN mode, pin 28 is assigned the In MIN mode, pin 28 is assigned the
signal M / 𝐈𝐎 signal IO / 𝐌

To access higher byte, 𝐁𝐇𝐄 signal is No such signal required, since the
used data width is only 1-byte
14
8086 Microprocessor
Co-processor – Intel 8087

Multiprocessor A microprocessor system comprising of two or more

processors
system
Distributed processing: Entire task is divided in to
subtasks

Advantages Better system throughput by having more than one

processor

Each processor have a local bus to access local

memory or I/O devices so that a greater degree of
parallel processing can be achieved

System structure is more flexible.

One can easily add or remove modules to change the
system configuration without affecting the other
modules in the system

15
8086 Microprocessor
Co-processor – Intel 8087

8087 Specially designed to take care of mathematical

calculations involving integer and floating point data
coprocessor
“Math coprocessor” or “Numeric Data Processor (NDP)”

Works in parallel with a 8086 in the maximum mode

Features 1) Can operate on data of the integer, decimal and real

types with lengths ranging from 2 to 10 bytes

2) Instruction set involves square root, exponential,

tangent etc. in addition to addition, subtraction,
multiplication and division.

3) High performance numeric data processor  it can

multiply two 64-bit real numbers in about 27s and
calculate square root in about 36  s

4) Follows IEEE floating point standard

5) It is multi bus compatible

16
8086 Microprocessor
Co-processor – Intel 8087

17
8086 Microprocessor
Co-processor – Intel 8087

Converting a decimal number to short-real format

18
8086 Microprocessor
Co-processor – Intel 8087

8087 stack operation

To hold numbers being worked on,

the 8087 has a register stack of
eight 80-bit registers.

The 8087 has 3-bit stack pointer.

19
8086 Microprocessor
Co-processor – Intel 8087

𝐒𝟎- 𝐒𝟐

𝐒𝟐 𝐒𝟏 𝐒𝟎 Status
1 0 0 Unused
1 0 1 Read memory
1 1 0 Write memory
1 1 1 Passive

QS0 – QS1

QS0 QS1 Status

0 0 No operation
0 1 First byte of opcode
from queue
1 0 Queue empty
1 1 Subsequent byte of
opcode from queue

20
 8086 Microprocessor
Co-processor – Intel 8087

8086 and 8087 reads 8087 keeps track for ESC

instruction bytes and instruction by monitoring
8087 puts them in the 𝑺𝟐 - 𝑺𝟎 and AD0 – AD15 of
instructions respective queues 8086.
are inserted
in the 8086 NOP Also keeps track of QS 0 –
program QS1.
8087 instructions have
11011 as the MSB of Q status 00; does nothing
their first code byte
Q status 01; 8087
compares the five MSB
bits with 11011

If there is a match, then

the ESC instruction is
fetched and executed by
8087
Memory read/ write
Additional words : 𝑹𝑸 - If there is error during
𝑮𝑻𝟎 decoding an ESC
8087 BUSY pin high instruction, 8087 sends
𝑻𝑬𝑺𝑻 an interrupt request
WAIT
21
Ref: Microprocessor, Atul P. Godse, Deepali A. Gode, Technical publications, Chap 11
 EE 3213
Microprocessors, Microcontrollers and Peripherals

Lecture 12: 80186, 80286, 80386 Microprocessors

Course Teacher
Dr. Kalyan Kumar Halder
Associate Professor
Dept. of EEE, KUET
Intel 80186
 80186
• 80186 contains 8086 processor and
several additional functional chips:
–clock generator
–2 independent DMA channels
–PIC (Priority Interrupt Controller)
–3 programmable 16-bit timers
• more a microcontroller than a
microprocessor
• used mostly in industrial control
applications
Intel 80286
 Salient features of 80286

• High performance microprocessor with

memory management and protection
– 80286 is the first member of the family
of advanced microprocessors with built-
in/on-chip memory management and
protection abilities primarily designed for
multi-user/multitasking systems
• Available in 12.5MHz, 10MHz & 8MHz
clock frequencies
 Salient features of 80286

The 80286 CPU, with its 24-bit address bus is

able to address 16MB of physical memory.

1GB of virtual memory for each task

Microprocessor Data bus Address bus Memory size
width width
8086 16 20 1M

80186 16 20 1M

80286 16 24 16M
 Salient features of 80286 Operating Modes
Intel 80286 has 2 operating modes:
 Real Address Mode :
 80286 is just a fast 8086 --- up to 6
times faster
 All memory management and
protection mechanisms are disabled
 286 is object code compatible with
8086
 Protected Virtual Address Mode
 80286 works with all of its memory
management and protection
capabilities with the advanced
instruction set.
 it is source code compatible with 8086
Internal Block Diagram of 80286

EU EU AU

BIU IU
8085 BIU
8086 80286
 Functional Parts
1. Address unit

2. Bus unit

3. Instruction unit

4. Execution unit
 Address Unit

• Calculate the physical addresses of the

instruction and data that the CPU want to
access
• Address lines derived by this unit may be
used to address different peripherals.
• Physical address computed by the
address unit is handed over to the BUS
unit.
 Bus Unit
• Performs all memory and I/O read and write
operations.
• Take care of communication between CPU
and a coprocessor.
• Transmit the physical address over address
bus A0 – A23.
• Prefetcher module in the bus unit performs
this task of prefetching.
• Bus controller controls the prefetcher module.
• Fetched instructions are arranged in a 6 –
byte prefetch queue.
 Instruction Unit

• Receive arranged instructions from 6 byte

prefetch queue.
•

• Instruction decoder decodes up to 3

prefetched instruction and are latched
them onto a decoded instruction queue.
•

• Output of the decoding circuit drives a

control circuit in the Execution unit.
 Execution unit
• EU executes the instructions received from the
decoded instruction queue sequentially.

• Contains Register Bank.

• contains one additional special register called
Machine status word (MSW) register --- lower
4 bits are only used.

• ALU is the heart of execution unit.

• After execution ALU sends the result either over

data bus or back to the register bank.
 Register organization of 80286

The 80286 CPU contains the same set of registers, as in

8086.

1. Eight 16-bit general purpose registers.

2. Four 16 bit segment registers.

3. Status and control register.

4. Instruction pointer.
Flag Registers
Intel 80386
Architecture of 80386
 Architecture of 80386
• The Internal Architecture of 80386 is divided into 3 sections.

– Central Processing Unit

• Execution Unit

• Instruction Unit

– Memory management unit

• Segmentation

• Paging Unit

– Bus interface unit

 Register Organization

• The 80386 has eight 32 - bit general purpose registers which

may be used as either 8 bit or 16 bit registers.
• A 32 - bit register known as an extended register, is
represented by the register name with prefix E.
• Example : A 32 bit register corresponding to AX is EAX,
similarly BX is EBX etc.
• The 16 bit registers BP, SP, SI and DI in 8086 are now
available with their extended size of 32 bit and are names as
EBP,ESP,ESI and EDI.
• AX represents the lower 16 bit of the 32 bit register EAX.
• BP, SP, SI, DI represents the lower 16 bit of their 32 bit
counterparts, and can be used as independent 16 bit registers.
2
1
Register Organization
GENERAL DATA AND ADDRES S REGIS TERS
31 16 15 0
AX EAX
BX EBX
CX ECX
DX EDX
SI ES I
DI EDI
BP EBP
SP ES P

S EGMENT S ELECTOR REGIS TERS

CS CODE S EGMENT
SS S TACK S EGMENT
DS
ES DATA S EGMENT
FS
GS
INS TRUCTION POINTER AND FLAG REGIS TER
31 16 15 0
IP
EIP
FLAGS
EFLAGS
 Register Organization
• The six segment registers available in 80386 are CS, SS, DS,
ES, FS and GS.
• The CS and SS are the code and the stack segment registers
respectively, while DS, ES, FS, GS are 4 data segment
registers.
• A 16 bit instruction pointer IP is available along with 32 bit
counterpart EIP.
• Flag Register of 80386: The Flag register of 80386 is a 32 bit
register. Out of the 32 bits, Intel has reserved bits D18 to D31,
D5 and D3, while D1 is always set at 1.Two extra new flags are
added to the 80286 flag to derive the flag register of 80386.
They are VM and RF flags.
• The 80386 has three modes of operation:
1. Real Address Mode (Real Mode)
2. Protected Virtual Addressing mode (Protected Mode)
3. Virtual 8086 mode.

• The BIU also offers address pipelining, data bus sizing,

and direct Byte Enable signals for each byte of data bus.
 Real Addressing Modes of 80386
• When processor Reset or Powered up then 80386 is initialized in
REAL Mode.
• Real mode has same base architecture as that of 8086, but allows
access to the 32-bit register set of 80386.
• The addressing mechanism, memory size, interrupt handling , are
identical to Real Mode of the 80286.
• All of the 80386 instructions are available in Real Mode is 16-bits,
same as that of 8086.
• To use 32-bit registers and addressing modes, override prefixes ‘E’
must be used.
• The segment size on the 80386 in Real mode is 64KB so 32-bit
effective addresses must be less than 0000FFFFH.
• The basic Purpose of Real mode in 80386 is to set up the processor
for Protected Mode Operation.
 Memory Addressing in Real Mode of
80386
• In Real mode the max. memory size is limited to
1MB, so only address line A2-A19 are used.
• In Real addressing mode the linear addresses are
the same physical addresses as paging is not
allowed.
• Physical address is calculated in Real mode by
adding the content of segment register after
shifting it left by four bits with an effective
address and generates a physical address. Which
is compatible with 80286 Real Mode.
 Protected Virtual Address Mode
(PVAM) of 80386
• When the processor operates in protected virtual
address mode i.e. Protected Mode then the complete
capabilities of the 80386 are used.
• Protected mode is used to increase the linear address
space up to 4GB and used to execute virtual memory
programs of the size of 64TB.
• Also Protected mode of 80386 is used to run all the
existing 8086 and 80286 program with a memory
management and protection mechanism.
• Protected mode of 80386 also supports the use of
additional instructions for supporting multitasking OS.
• The linear address is then either used as the 32- bit
physical address, or the paging mechanism maps the
32- bit linear address into a 32 bit physical address if
paging is enabled.
• In protected mode the selector is used as an index for
system define table such as LDT or GDT
• The LDT or GDT table contains 32 bit base address of
given segment.
• The physical address is formed by adding the base
address obtained from the table to offset.
• Paging provides additional memory management
mechanism which operates only in Protected mode
and managing the very large segments of the 80386.
 Difference between Real and
Protected Mode
Real Mode Protected Mode (PVAM)

Memory addressing up to 1 MB physical Memory addressing up to 16 MB of

memory physical memory

No virtual memory support Supports up to 64TB of virtual memory

Memory Protection mechanism is not Memory Protection Mechanism is

available available

Does not support virtual address space Gives virtual and physical address space

Does not support LDT and GDT Supports LDT and GDT

Segment descriptor cache is not available Segment descriptor cache is available

Supports Segmentation Supports segmentation and paging.

 Segmentation
• Segmentation is memory management technique
with protection.
• The information of the segment is stored in an 8 byte
format called as descriptor.
• There are three types of descriptor table:
– LDT
– GDT
– IDT
• LDT, GDT and IDT are of variable length memory size
table which ranges between 8 bytes and 64KB.
• Each table content maximum 8K of 8byte
descriptors and the upper 13 bits of selectors
are used as an index for the descriptor table.

• These tables have registers associated with

them which hold the 32-bit linear base
address and the 16- bit limit of each table and
these registers are LDTR, GDTR and IDTR.
 Protection Levels in 80386
• The 80386 supports four protection which
isolates and protect user programs for each other
and the operating system during a multi-tasking
operating system.
• The protection level avoid the use of privileged
instructions, I/O instructions and access to
segments and segment descriptors.
• The privilege protection mechanism of 80386 is
integrated in On- chip Memory Management Unit
which also gives protection to pages, when
paging is enable.
 Virtual 8086 Mode Addressing
Mechanism
• With the release of the 386, protected mode offers what the
Intel manuals call virtual 8086 mode. Virtual 8086 mode is
designed to allow code previously written for the 8086 to run
unmodified and concurrently with other tasks, without
compromising security or system stability.
• When the processor is operating in Virtual Mode the segment
registers are used in an identical to Real Mode.
• The content of the segment register are shifted towards left
by 4 bits and added to the offset to form the segment base
linear address.
• The 80386 gives facility to the OS for specifying which
programs use 8086 style address mechanism, and which
program use Protected mode addressing on a per task basis.
 EE 3213
Microprocessors, Microcontrollers and Peripherals

Lecture 13: 80486 and Pentium Microprocessors; RISC and CISC

Processors

Course Teacher
Dr. Kalyan Kumar Halder
Associate Professor
Dept. of EEE, KUET
LIMITATIONS OF 80286 THAT LEAD TO 80386
 80286 has only a 16 bit processor.

 Maximum segment size of 80286 is 64 KB.

 80286 cannot be easily switched between real mode and

protected mode because resetting was required.

 The amount of memory addressable by the 80286 is 16M byte.

 To increase the over all system performance.

THE 80386 MICROPROCESSOR
 A 32-bit microprocessor introduced by Intel in 1985.

 The chip of 80386 contains 132 pins.

 It has total 129 instructions.

 It has 32 bit data bus 32 bit address bus.

 The execution of the instructions is highly pipelined and
the processor is designed to operate in a multiuser and
multitasking.

 Software written for the 8088,8086,80186 and 80286

will also run on 386.
 The address bus is capable of addressing over 4
gigabytes of physical memory.

 Virtual addressing pushing this over 64 terabytes of

storage.

 80387 coprocessor is used.

 The processor can operate in two modes:

 In the real mode physical address space is 1Mbytes and
maximum size of segment is 64KB.

 In the protected mode address space is 4G bytes and

maximum size of segment is upto entire physical addressing
space.
THE 80486 MICROPROCESSOR

 80486 is the next in Intel’s upward compatible 80x86

architecture.

 Only few differences between the 80486 and 80386, but

these differences created a significant performance
improvement.

 32 bit microprocessor and same register set as 80386.

 Few additional instructions were added to its instruction set.

 4 gigabyte addressing space.

IMPROVEMENTS MADE IN 80486 OVER 80386
 80486 was powered with a 8KB cache memory.

 This improved the speed of 80486 processor to great extent.

 Some new 80486 instructions are included to maintain the
cache.

 80486 also uses a co-processor similar to 80387 used with

80386.

 But this co-processor is integrated on the chip allows it to

execute instructions 3 times faster as 386/387 combination.
 486 is packed with 168 pin grid array package instead of
the 132 pin used for 386 processor.
 This additional pin’s made room for the additional
signals.

 This new design of 80486 allows the instruction to

execute with fewer clock cycles.

 These small differences made 80486 more powerful

processor.
THE PENTIUM PROCESSOR
 W HY THE NAME PENTIUM ?????

 Intel wanted to prevent their competitors from branding

their processors with similar names, as AMD had done
with their Am486.

 The name Pentium is originally derived from

the Greek word pente meaning 'five' as the series was
Intel's 5th generation microarchitecture.
THE PENTIUM PROCESSOR
 Upward compatibility has been maintained.
 It can run all programs written for any 80x86 line, but
does so at a double the speed of fastest 80486.

 Pentium is mixture of both CISC and RISC technologies.

 All the prior 80x86 processor are considered as CISC

processor.
 The addition of RISC aspects lead to additional
performance improvement.
 It uses 64 bit data bus to address memory organized in
8 banks, each bank contains 512 MB of data.
 Each bank can store a byte of data.

BE7 BE6 BE5 BE4 BE3 BE2 BE1 BE0

B7 B6 B5 B4 B3 B2 B1 B0

64 bit

Memory System of Pentium

 All these bank enable signals are active low.

IMPROVEMENTS OF PENTIUM OVER 80X486

 Separate 8KB data and instruction cache memory.

 Dual Integer pipelines are present but only single
integer pipeline is present in 80486.

 Branch Prediction Logic.

CACHE MEMORY
 The Pentium contains two 8K-byte cache.

 An 8 K-byte instruction cache, which stores the instruction.

 An 8 K-byte data cache, stores the data used by the

instructions.
 In the 80486 with unified cache, a program that was data
intensive quickly fills the cache, allowing less room for
instructions.

 In Pentium this cannot occur because of the separate

instruction cache.
PIPELINING

 It is a technique used to enable one instruction to complete with

each clock cycle.

 In Pentium there are two instruction pipelines, the U pipeline

and V pipeline.

 These pipelines are responsible for executing

instructions.

 During Execution the U and V pipelines are capable of

executing two integer instructions at the same time and one
floating point instructions.
 PIPELINING
F D E F D E F D E

I1 I1 I1 I2 I2 I2 I3 I3 I3

Clock
Cycle 1 2 3 4 5 6 7 8 9

F I1 I2 I3 I4 I5

I1 I2 I3 I4
D

I1 I2 I3
E
Clock
Cycle 1 2 3 4 5
 On a non pipelined machine 9 clock cycles are needed for the
individual fetch, decode and execute cycle.

 On a pipelined machine fetch, decode and execute operations

are performed in parallel only 5 cycles are needed to execute
the same three instructions.

 The First instructions needed 3 cycles to complete.

 Additional instructions complete at rate of 1 per cycle.

 The Instruction pipelines are five-stage pipelines and capable
of independent operations.

 The Five-Stages are,

PF – Pre-Fetch
D1 – Instruction Decode
D2 – Address Generate
EX - Execute Cache and ALU Access.
WB – Write Back

 The U pipeline can execute any processor instruction where as

V pipeline only execute Simple Instruction.
BRANCH PREDICTION LOGIC

 The purpose of branch prediction logic is to reduce the

time required for a branch caused by internal delays.

 The microprocessor begins pre-fetch instruction at the

branch address.

 The instructions are loaded into the instruction cache.

 When the branch occurs, the instruction are present and
allow the branch to execute in one clock period.

 If the branch prediction logic errs, the branch requires an

extra three clock cycles.
SPEED OF PROCESSORS
 The 80286 - 25 MHz
 The 80386 - 40MHz

 The 80486 - 60 MHz

 The Pentium -90 MHz

RISC and CISC
What is CISC?
 CISC is an acronym for Complex Instruction Set Computer and are chips
that are easy to program and which make efficient use of memory. Since the
earliest machines were programmed in assembly language and memory was
slow and expensive, the CISC philosophy made sense.
 Most common microprocessor designs such as the Intel 80x86 and
Motorola 68K series followed the CISC philosophy.
 But recent changes in software and hardware technology have forced a re-
examination of CISC and many modern CISC processors are hybrids,
implementing many RISC principles.
 CISC was developed to make compiler development simpler. It shifts most
of the burden of generating machine instructions to the processor. For
example, instead of having to make a compiler write long machine
instructions to calculate a square-root, a CISC processor would have a built-
in ability to do this.
Most CISC hardware architectures have several characteristics in
common:
 Complex instruction-decoding logic, driven by the need for a single
instruction to support multiple addressing modes.
 A small number of general purpose registers. This is the direct result
of having instructions which can operate directly on memory and the
limited amount of chip space not dedicated to instruction decoding,
execution, and microcode storage.
 Several special purpose registers. Many CISC designs set aside
special registers for the stack pointer, interrupt handling, and so on.
This can simplify the hardware design somewhat, at the expense of
making the instruction set more complex.
 A 'Condition code" register which is set as a side-effect of most
instructions. This register reflects whether the result of the last
operation is less than, equal to, or greater than zero and records if
certain error conditions occur.
What is RISC?
 RISC?
RISC, or Reduced Instruction Set Computer. is a type of microprocessor
architecture that utilizes a small, highly-optimized set of instructions, rather
than a more specialized set of instructions often found in other types of
architectures.
 History
The first RISC projects came from IBM, Stanford, and UC-Berkeley in the
late 70s and early 80s. The IBM 801, Stanford MIPS, and Berkeley RISC 1
and 2 were all designed with a similar philosophy which has become known
as RISC. Certain design features have been characteristic of most RISC
processors:
 one cycle execution time: RISC processors have a CPI (clock per instruction) of
one cycle. This is due to the optimization of each instruction on the CPU and a
technique called PIPELINING
 pipelining: a techique that allows for simultaneous execution of parts, or stages,
of instructions to more efficiently process instructions;
 large number of registers: the RISC design philosophy generally incorporates a
larger number of registers to prevent in large amounts of interactions with
memory
CISC and RISC Attributes
The main characteristics of CISC microprocessors are:
 Extensive instructions.
 Complex and efficient machine instructions.
 Micro-encoding of the machine instructions.
 Extensive addressing capabilities for memory operations.
 Relatively few registers.

In comparison, RISC processors are more or less the opposite of the above:
 Reduced instruction set.
 Less complex, simple instructions.
 Hardwired control unit and machine instructions.
 Few addressing schemes for memory operands with only two basic
instructions, LOAD and STORE
 Many symmetric registers which are organized into a register file.