DB019-B ViRGE Integrated 3D Accelerator Aug1996

ViRGE Integrated 3D Accelerator
ViRGE
Integrated
3D Accelerator
August 1996
S3 Incorporated
P.O. Box 58058
Santa Clara, CA 95052-8058
NOTATIONAL CONVENTIONS
The following notational conventions are used in this data book:
Signal names are shown in all uppercase letters. For example, XD.
A bar over a signal name indicates an active low signal. For example, OE.
n-m indicates a bit field from bit n to bit m. For example, 7-0 specifies bits 7 through 0, inclusive.
n:m indicates a signal (pin) range from n to m. For example D[7:0] specifies data lines 7 through 0, inclusive
Use of a trailing letter H indicates a hexadecimal number. For example, 7AH is a hexadecimal number.
Use of a trailing letter b indicates a binary number. For example, 010b is a binary number.
When K or M are used, they refer to binary rather than decimal form. Thus, for example, 1 KByte would be equivalent to 1024, not 1,000
bytes.
When k is used, it refers to decimal 1000.
NOTICES
© Copyright 1995, 1996 S3 Incorporated. All rights reserved. If you have received this document from S3 Incorporated in electric form,
you are permitted to make the following copies for business use related to products of S3 Incorporated: one copy onto your computer
for the purpose of on-line viewing, and one printed copy. With respect to all documents, whether received in hard copy or electronic
form, other use, copying or storage, in whole or in part, by any means electronic, mechanical, photocopying or otherwise, is permitted
without the prior written consent of S3 Incorporated, P.O. Box 58058., Santa Clara CA 95052-8058. S3 and True Acceleration are registered
trademarks of S3 Incorporated. The S3 Corporate Logo, S3 on Board, S3 on Board design, S3d design, Vision968, Trio, Trio64, Trio64V+,
Trio64UV+, Trio64V2/DX, Trio64V2/GX, ViRGE, ViRGE/VX, S3d, Scenic, Scenic/MX2, Scenic Highway, Sonic, Sonic/AD, Aurora64V+,
DuoView, Cooperative Accelerator Architecture, Streams Processor, MIC, Galileo, Native-MPEG, No Compromise Integration, No
Compromise Acceleration and Innovations in Acceleration are trademarks of S3 Incorporated. Other trademarks referenced in this
document are owned by their respective companies. The material in this document is for information only and is subject to change
without notice. S3 Incorporated reserves the right to make changes in the product design without reservation and without notice to its
users.
Additional information may be obtained from:
S3 Incorporated, Literature Department, P.O. Box 58058, Santa Clara, CA 95052-8058.
Telephone: 408-980-5400, Fax: 408-980-5444

Table of Contents
Table of Figures . . . . . . . . . . vi Section 7: Display Memory . . . . 7-1

7.1 DISPLAY MEMORY
CONFIGURATIONS . . . . . . . . . 7-1
List of Tables . . . . . . . . . . . . vii 7.2 DISPLAY MEMORY REFRESH . . . 7-1
7.3 2-Cycle EDO DRAM SUPPORT . . . 7-1
Section 1: Introduction . . . . . . 1-1 7.4 1-CYCLE EDO DRAM SUPPORT . . 7-6
1.1 OVERVIEW . . . . . . . . . . . . . 1-2 7.5 DISPLAY MEMORY ACCESS
1.2 64-bit S3d ENGINE . . . . . . . . . 1-2 CONTROL . . . . . . . . . . . . . . 7-8
1.3 Streams Processor . . . . . . . . . 1-2 7.6 DISPLAY MEMORY ADDRESS
1.4 S3 Scenic Highway . . . . . . . . . 1-2 TILING . . . . . . . . . . . . . . . . 7-8
1.5 VIDEO RESOLUTIONS SUPPORTED 1-3
Section 8: RAMDAC Functionality 8-1
Section 2: Mechanical Data . . . . 2-1 8.1 OPERATING MODES . . . . . . . . 8-1
2.1 THERMAL SPECIFICATIONS . . . . 2-1 8.2 COLOR MODES . . . . . . . . . . . 8-2
2.2 MECHANICAL DIMENSIONS . . . 2-1 8.2.1 8 Bits/Pixel - Mode 0 . . . . . . 8-2
8.2.2 Output-doubled 8 Bits/Pixel -
Mode 8 . . . . . . . . . . . . . 8-2
Section 3: Pins . . . . . . . . . . . 3-1 8.2.3 15/16-Bits/Pixel - Modes 9
3.1 PINOUT DIAGRAMS . . . . . . . . 3-1
and 10 . . . . . . . . . . . . . . 8-3
3.2 PIN DESCRIPTIONS . . . . . . . . 3-4
8.2.4 24 Bits/Pixel - Mode 13 . . . . . 8-3
3.3 PIN LISTS . . . . . . . . . . . . . . 3-12
8.3 RAMDAC REGISTER ACCESS . . . 8-3
8.4 RAMDAC SNOOPING . . . . . . . . 8-3
Section 4: Electrical Data . . . . . 4-1 8.5 SENSE GENERATION . . . . . . . 8-3
4.1 MAXIMUM RATINGS . . . . . . . 4-1 8.6 POWER CONTROL . . . . . . . . . 8-3
4.2 DC SPECIFICATIONS . . . . . . . . 4-1 8.7 RAMDAC SIGNATURE ANALYSIS . 8-3
4.3 AC SPECIFICATIONS . . . . . . . . 4-3 8.7.1 Signature Analysis Steps . . . . 8-3
4.3.1 RAMDAC AC Specifications . . 4-3 8.7.2 Signature Generation . . . . . . 8-4
4.3.2 Clock Timing . . . . . . . . . . 4-4
4.3.3 Input/Output Timing . . . . . . 4-5
Section 9: Clock Synthesis and
Control . . . . . . . . . . . . . . . 9-1
Section 5: Reset and Initialization 5-1 9.1 CLOCK SYNTHESIS . . . . . . . . . 9-1
9.2 CLOCK REPROGRAMMING . . . . 9-2
Section 6: System Bus Interfaces . 6-1 9.3 DCLK CONTROL . . . . . . . . . . 9-3
6.1 PCI BUS INTERFACE . . . . . . . . 6-1 9.4 CLOCK TESTING . . . . . . . . . . 9-3
6.1.1 PCI Configuration . . . . . . . . 6-1
6.1.2 PCI Controls . . . . . . . . . . . 6-1 Section 10: Streams Processor . 10-1
6.2 VL-BUS INTERFACE . . . . . . . . 6-1 10.1 INPUT STREAMS . . . . . . . . . 10-1
6.2.1 VL-Bus Cycles . . . . . . . . . . 6-2 10.1.1 Primary Stream Input . . . . . 10-2
6.2.2 SRDY Generation . . . . . . . . 6-2 10.1.2 Secondary Stream Input . . . 10-2
iii
10.1.3 Packed True Color . . . . . . . 10-2 13.2.1 Unlocking the S3 Registers . 13-1
10.1.4 Hardware Cursor Generation . 10-3 13.2.2 Locking the S3 Registers . . . 13-4
10.1.5 Frame Buffer Organization/ 13.3 TESTING FOR THE PRESENCE OF
Double Buffering . . . . . . . . 10-3 A ViRGE CHIP . . . . . . . . . . . 13-4
10.2 INPUT PROCESSING . . . . . . . . 10-5 13.4 GRAPHICS MODE SETUP . . . . 13-4
10.2.1 Primary Stream Processing . . 10-5
10.2.2 Secondary Stream Processing . 10-5
10.3 COMPOSITION/OUTPUT . . . . . . 10-6
Section 14: VGA Compatibility
10.3.1 Opaque Rectangular Support . . . . . . . . . . . . . 14-1
Overlaying . . . . . . . . . . . 10-7 14.1 VGA COMPATIBILITY . . . . . . . 14-1
10.3.2 Blending . . . . . . . . . . . . 10-7 14.2 VESA SUPER VGA SUPPORT . . 14-2
10.3.3 Color/Chroma Keying . . . . . 10-8
10.3.4 Window Location . . . . . . . . 10-8 Section 15: Enhanced
10.4 STREAMS FIFO CONTROL . . . . . 10-8
Programming . . . . . . . . . . . 15-1
15.1 MEMORY-MAPPED I/O . . . . . . 15-1
Section 11: Local Peripheral 15.1.1 Old MMIO . . . . . . . . . . . 15-1
Bus . . . . . . . . . . . . . . . . 11-1 15.1.2 New MMIO . . . . . . . . . . 15-2
11.1 Scenic/MX2 INTERFACE . . . . . . 11-2 15.2 DIRECT BITMAP ACCESSING—
11.1.1 Scenic/MX2 Register/Memory LINEAR ADDRESSING . . . . . . 15-3
Access . . . . . . . . . . . . . . 11-2 15.2.1 Old Linear Addressing . . . . 15-3
11.1.2 Scenic/MX2 Compressed Data 15.2.2 New Linear Addressing . . . 15-3
Transfer . . . . . . . . . . . . . 11-4 15.3 READ AND WRITE ORDERING . . 15-4
11.1.3 Scenic/MX2 Video Capture . . 11-5 15.4 S3d ENGINE PROGRAMMING . . 15-5
11.2 DIGITIZER INTERFACE . . . . . . . 11-7 15.4.1 Notational Conventions . . . 15-5
11.2.1 I2C Register Interface . . . . . . 11-7 15.4.2 Initial Setup . . . . . . . . . . 15-6
11.2.2 SAA7110 Video Input . . . . . 11-8 15.4.3 Autoexecute . . . . . . . . . . 15-6
11.3 HOST PASS-THROUGH . . . . . . 11-9 15.4.4 2D Programming Examples . 15-6
11.4 LPB-ENABLED PIN 15.4.4.1 BitBLT . . . . . . . . . . . 15-7
ASSIGNMENTS . . . . . . . . . . . 11-9 15.4.4.2 Rectangle Fill . . . . . . . 15-17
15.4.4.3 2D Line Draw . . . . . . . 15-18
15.4.4.4 2D Polygon Fill . . . . . . . 15-21
Section 12: Miscellaneous 15.4.5 3D Graphics Drawing . . . . . 15-23
Functions . . . . . . . . . . . . . 12-1 15.4.5.1 3D Line Drawing . . . . . . 15-23
12.1 VIDEO BIOS ROM INTERFACE . . . 12-1 15.4.5.2 3D Triangle Drawing . . . 15-23
12.1.1 Disabling BIOS ROM Accesses 12-1 15.4.6 Z-Buffering . . . . . . . . . . 15-25
12.1.2 BIOS ROM Hardware Interface 12-1 15.4.7 MUX Buffering . . . . . . . . 15-26
12.1.3 BIOS ROM Read Functional 15.4.8 3D Pixel Color Generation . . 15-26
Timing . . . . . . . . . . . . . . 12-2 15.4.8.1 Texture Filtering . . . . . . 15-27
12.1.4 BIOS ROM Address Mapping . 12-2 15.4.8.2 Generation . . . . . . . . . 15-29
12.2 GREEN PC SUPPORT . . . . . . . . 12-4 15.4.8.3 Lighting . . . . . . . . . . 15-29
12.3 GENERAL INPUT PORT . . . . . . 12-4 15.4.8.4 Fogging . . . . . . . . . . 15-30
12.4 GENERAL OUTPUT PORT . . . . . 12-5 15.4.8.5 Alpha Blending . . . . . . 15-30
12.5 FEATURE CONNECTOR 15.5 PROGRAMMABLE HARDWARE
INTERFACE . . . . . . . . . . . . . 12-7 CURSOR . . . . . . . . . . . . . . 15-31
12.6 SERIAL COMMUNICATIONS 15.6 BUS MASTER DMA . . . . . . . 15-33
PORT . . . . . . . . . . . . . . . . 12-9 15.6.1 Video/Graphics DMA
12.7 INTERRUPT GENERATION . . . . . 12-9 Transfers . . . . . . . . . . . 15-33
15.6.2 S3d Engine Command/
Parameter/Image Data DMA
Section 13: Basic Software Transfers . . . . . . . . . . . 15-33
Functions . . . . . . . . . . . . . 13-1
13.1 CHIP WAKEUP . . . . . . . . . . . 13-1
13.2 REGISTER ACCESS . . . . . . . . . 13-1
iv
Section 16: VGA Standard Register Appendix A: Listing of Raster

Descriptions . . . . . . . . . . . 16-1 Operations . . . . . . . . . . . . A-1
16.1 GENERAL REGISTERS . . . . . . . 16-1
16.2 SEQUENCER REGISTERS . . . . . 16-5
16.3 CRT CONTROLLER REGISTERS . 16-10
Appendix B: Register Reference B-1
B.1 VGA REGISTERS . . . . . . . . . . B-2
16.4 GRAPHICS CONTROLLER
B.2 EXTENDED SEQUENCER
REGISTERS . . . . . . . . . . . . 16-25
REGISTERS . . . . . . . . . . . . . B-9
16.5 ATTRIBUTE CONTROLLER
B.3 EXTENDED CRTC REGISTERS . . B-11
REGISTERS . . . . . . . . . . . . 16-32
B.4 S3D REGISTERS . . . . . . . . . B-18
16.6 RAMDAC REGISTERS . . . . . . 16-38
B.5 STREAMS PROCESSOR
REGISTERS . . . . . . . . . . . . B-27
Section 17: Extended Sequencer B.6 MEMORY PORT CONTROLLER
Register Descriptions . . . . . . 17-1 REGISTERS . . . . . . . . . . . . B-31
B.7 MISCELLANEOUS REGISTERS . B-33
B.8 DMA REGISTERS . . . . . . . . . B-34
Section 18: Extended CRTC B.9 LPB REGISTERS . . . . . . . . . . B-35
Register Descriptions . . . . . . 18-1 B.10 PCI CONFIGURATION SPACE
REGISTERS . . . . . . . . . . . . B-39
Section 19: S3d Engine Register
Descriptions . . . . . . . . . . . 19-1 Index . . . . . . . . . . . . . . . . I-1
19.1 REGISTER MAPPING AND
ADDRESSING . . . . . . . . . . . . 19-1
19.2 COLOR PATTERN REGISTERS . . . 19-3
19.3 2D REGISTERS . . . . . . . . . . . 19-4
19.4 3D REGISTERS . . . . . . . . . . 19-24
Section 20: Streams Processor

Register Descriptions . . . . . . 20-1
Section 21: Memory Port Controller

Section 22: Miscellaneous

Section 23: DMA Register

Descriptions . . . . . . . . . . . 23-1
23.1 VIDEO/GRAPHICS DATA
TRANSFER CHANNEL . . . . . . . 23-2
23.2 COMMAND TRANSFER CHANNEL 23-4
Section 24: Local Peripheral Bus

Section 25: PCI Register

Descriptions . . . . . . . . . . . 25-1
v
List of Figures
# Title Page # Title Page

2-1 208-pin PQFP Mechanical 11-10 Scenic/MX2 Video Input
Dimensions . . . . . . . . . . . . 2-2 (ViRGE Ready) . . . . . . . . . . 11-6
3-1 PCI Bus Pinout . . . . . . . . . . 3-2 11-11 Scenic/MX2 Video Input
3-2 VL-Bus Pinout . . . . . . . . . . . 3-3 (ViRGE Not Ready) . . . . . . . 11-6
4-1 Clock Waveform Timing . . . . . 4-4 11-12 ViRGE to SAA7110 Digitizer
4-2 Input Timing . . . . . . . . . . . 4-5 Interface . . . . . . . . . . . . . 11-7
4-3 Output Timing . . . . . . . . . . 4-7 11-13 16- to 8-bit Video Data
4-4 Reset Timing . . . . . . . . . . . 4-10 Conversion . . . . . . . . . . . 11-8
6-1 VL-Bus Read Cycle . . . . . . . . 6-3 11-14 Video 8 In or 16 Mode Input . . 11-8
6-2 1 Wait-state VL-Bus Write Cycle . 6-4 12-1 BIOS ROM PCI Configuration
7-1 Memory Configurations . . . . . 7-2 Interface . . . . . . . . . . . . . 12-1
7-2 2-cycle EDO Mode Read Cycle . . 7-3 12-2 BIOS ROM VL-Bus Configuration
7-3 2-cycle EDO Mode Write Cycle . 7-4 Interface . . . . . . . . . . . . . 12-2
7-4 EDO Mode Write Following Read 7-5 12-3 BIOS ROM Read Functional
7-5 1-Cycle EDO Mode Read/Write . 7-6 Timing - PCI . . . . . . . . . . . 12-3
7-6 1-Cycle EDO Mode Write 12-4 General Input Port Interface
Following a Read . . . . . . . . . 7-7 (VL-Bus) . . . . . . . . . . . . . 12-4
8-1 Internal RAMDAC Block Diagram 8-1 12-5 General Input Port Timing
9-1 PLL Block Diagram . . . . . . . . 9-2 (VL-Bus) . . . . . . . . . . . . . 12-5
10-1 Streams Processor . . . . . . . . 10-1 12-6 General I/O Port Timing (PCI) . 12-5
10-2 Screen Definition Parameters . . 10-5 12-7 General Output Port Interface
11-1 LPB Internal Block Diagram . . . 11-1 (VL-Bus) . . . . . . . . . . . . . 12-6
11-2 ViRGE to Scenic/MX2 Hardware 12-8 General Output Port Timing
Interface . . . . . . . . . . . . . . 11-2 (VL-Bus) . . . . . . . . . . . . . 12-6
11-3 Scenic/MX2 Write (Scenic/MX2 12-9 Pass-Through Feature Connector 12-7
Ready) . . . . . . . . . . . . . . . 11-3 12-10 VAFC Implementation . . . . . 12-8
11-4 Scenic/MX2 Write (Scenic/MX2 15-1 Internal Organization . . . . . . 15-4
Not Ready) . . . . . . . . . . . . 11-3 15-2 Overlapping BitBLT Cases . . . 15-8
11-5 Scenic/MX2 Read (Scenic/MX2 15-3 2D Line Drawing Cases . . . . . 15-18
Ready) . . . . . . . . . . . . . . . 11-3 15-4 Polyline Drawing Example . . . 15-19
11-6 Scenic/MX2 Read (Scenic/MX2 15-5 Polygon Fill Example . . . . . . 15-21
Not Ready) . . . . . . . . . . . . 11-3 15-6 3D Triangle Example . . . . . . 15-24
11-7 Compressed Data Xfer 15-7 Pixel Coloring . . . . . . . . . . 15-27
(Scenic/MX2 Ready) . . . . . . . 11-4 15-8 Texture Filtering . . . . . . . . 15-28
11-8 Scenic/MX2 Stopping a
Compressed Xfer . . . . . . . . 11-5
11-9 Scenic/MX2 VSYNC and
HSYNC Protocols . . . . . . . . . 11-5
vi
List of Tables
# Title Page # Title Page

1-1 Video Resolutions Supported . . 1-3 12-2 LPB Feature Connector
3-1 Pin Descriptions . . . . . . . . . 3-4 Configuration (VL-Bus) . . . . . 12-8
3-2 Alphabetical Pin Listing . . . . . 3-12 12-3 LPB Feature Connector
3-3 Numerical Pin Listing . . . . . . . 3-15 Configuration (PCI) . . . . . . . 12-8
4-1 Absolute Maximum Ratings . . . 4-1 14-1 Standard VGA Registers Modified
4-2 RAMDAC/Clock Synthesizer DC or Extended in ViRGE . . . . . . 14-1
Specifications . . . . . . . . . . . 4-1 15-1 New MMIO Addresses . . . . . 15-2
4-3 RAMDAC Characteristics . . . . . 4-1 15-2 Programming Parameters for
4-4 Digital DC Specifications . . . . . 4-2 Overlapping BitBLTs . . . . . . 15-8
4-5 RAMDAC AC Specifications . . . 4-3 19-1 S3d Register Memory Map . . . 19-2
4-6 RAMDAC Output Specifications . 4-3 19-2 Color Pattern Data Storage
4-7 Clock Waveform Timing . . . . . 4-4 Requirements . . . . . . . . . . 19-3
4-8 SCLK-Referenced Input Timing . 4-5
4-9 LCLK-Referenced Input Timing . 4-6
4-10 MCLK-Referenced Input Timing . 4-6
. . . . . . . . . . . . . . . . . . . 4-6
4-11 SCLK-Referenced Output Timing 4-7
4-12 LCLK-Referenced Output Timing 4-8
4-13 MCLK-Referenced Output Timing 4-8
4-14 Feature Connector Timing - Output
from ViRGE to Feature Connector 4-8
4-15 Feature Connector Timing - Output
from Feature Connector to ViRGE 4-9
4-16 Reset Timing . . . . . . . . . . . 4-10
5-1 Definition of PD[28:0] at the Rising
Edge of the Reset Signal . . . . . 5-2
4-1 VL-Bus Upper Address Decoding 6-1
7-1 Memory Size/Chip Count
Configurations . . . . . . . . . . 7-1
8-1 Color Modes . . . . . . . . . . . 8-2
9-1 PLL R Parameter Decoding . . . . 9-1
10-1 Register Fields Used For Specifying
Frame Buffer Organization and
Double Buffering . . . . . . . . . 10-3
10-2 Register Fields Used For Scaling
Up the Secondary Stream . . . . 10-6
11-1 LPB-Enabled Pin Assignments . 11-10
Section 1: Introduction
High-Performance Integrated DRAM-based • Support for Indeo, Cinepak, and soft-

2D/3D Graphics and Video Accelerator ware and hardware-accelerated MPEG-1
• High-performance 64-bit 2D/3D graphics video
engine
S3 Scenic Highway Interface
• Integrated 135 MHz RAMDAC and clock
synthesizer • Philips SAA7110/SAA7111 video digitiz-
ers
• S3 Streams Processor for accelerated
video • S3 Scenic/MX2 MPEG-1 audio/video de-
coder
• S3 Scenic Highway for direct interface to
live video and MPEG-1 peripherals High Screen Resolution (Non-interlaced)
• Pin compatible with S3 Trio64V+ Support
• 1280x1024x256 colors at 75 Hz refresh
S3d Graphics Engine Features
• 1024x768x64K colors at 85 Hz refresh
• High performance 2D Windows accelera-
tion • 800x600x16.7M colors at 85 Hz refresh
• Flat and Gouraud shading for 3D High-Performance Memory Support
• High quality/performance 3D texture • 64-bit DRAM memory interface
mapping
• 2-, and 4-MByte DRAM video memory
• Perspective correction
• Single-cycle EDO operation
• Bi-linear and tri-linear texture filtering
• MIP-Mapping Non-x86 CPU Support
• Depth cueing and fogging • Big endian/little endian byte ordering
• Alpha blending • Relocatable addressing
• Video texture mapping
Industry-Standard Local Bus Support
• Z-buffering
• Glueless PCI 2.1 bus interface
S3 Streams Processor Features • Glueless VESA VL-Bus interface
• Supports on-the-fly stretching and blend-
ing of primary RGB stream and RGB or PCI Bus Mastering for Display List Processing
YUV (video) secondary stream and Video Capture Support
• Each stream can have a different color
depth
• High-quality hardware-assisted video
playback with horizontal interpolation
INTRODUCTION 1-1
Multimedia Support Hooks video as a texture map. These features provide

• S3 Scenic Highway the most realistic user experience for interactive
3D applications.
• VESA advanced feature connector
• 8- and 16-bit bi-directional feature con- Other advanced features of the S3d Engine in-
nector clude S3 proprietary compressed texture formats
for improved performance and reduced memory
Full Software Support requirements, as well as support for S3’s MUX
• Drivers for major operating systems and buffering (pat. pend.) feature, which allows for
APIs: [Windows® 95, Windows® 3.11, Z-buffering support with no additional memory
Windows® NT, OS/2® 2.1 and 3.0 requirement.
(Warp ), ADI 4.2], Direct 3D ,
BRender , RenderWare and 1.3 Streams Processor
OpenGL
Green PC/Monitor Plug and Play Support The Streams Processor provides the stretching
and YUV color space conversion features re-
• Full hardware and BIOS support for quired for full screen video playback with both
VESA Display Power Management Sig- software CODECs and hardware MPEG-1
naling (DPMS) monitor power savings sources.
modes
• DDC monitor communications The Streams Processor allows simultaneous dis-
play of graphics and video of different color
Extensive Static/Dynamic Power Management depths. For example, it is possible to display 24
bpp-equivalent video on top of an 8-bit graphics
Industry-Standard 208-pin PQFP package background. This saves memory bandwidth and
storage capacity while permitting higher frame
rates.
1.1 OVERVIEW
The S3® ViRGE integrated 3D video/graphics 1.4 S3 Scenic Highway

accelerator enables development of compelling
interactive entertainment, education, and pres- The S3 Scenic Highway allows lowest cost
entation applications for the mainstream per- direct connection to S3’s Scenic/MX2 MPEG-1
sonal computing world. audio and video decoder as well as video digitiz-
ers such as Philips®’ SAA7110/SAA7111.
1.2 64-bit S3d ENGINE
The S3d Engine provides 2D acceleration for

excellent Windows applications performance
and a full-featured high-performance 3D render-
ing engine for games and other interactive 3D
applications.
The S3d Engine incorporates the key Windows

accelerator functions of BitBLT, line draw and
polygon fill. 3D features include flat shading,
Gouraud shading and texture mapping support.
Advanced texture mapping features include per-
spective correction, bi-linear and tri-linear filter-
ing, MIP-Mapping, and Z-buffering. The S3d
Engine also includes direct support for utilizing
1-2 INTRODUCTION
1.5 VIDEO RESOLUTIONS

SUPPORTED
Table 1-1. Video Resolutions Supported
2 MBs 4 MBs
Resolution DRAM DRAM
640x480x4 ✔ ✔
640x480x8 ✔ ✔
640x480x16 ✔ ✔
640x480x24 ✔ ✔
800x600x4* ✔ ✔
800x600x8 ✔ ✔
800x600x16 ✔ ✔
800x600x24 ✔ ✔
1024x768x4* ✔ ✔
1024x768x8 ✔ ✔
1024x768x16 ✔ ✔
1024x768x24 (IL) ✔
1152x864x8 ✔ ✔
1280x1024x4* ✔ ✔
1280x1024x8 ✔ ✔
1280x1024x16 (IL) ✔
1600x1200x4* ✔ ✔
1600x1200x8 (IL) ✔ ✔
* 4 bits/pixel modes are not accelerated and use

standard VGA/VESA drivers.
INTRODUCTION 1-3
Section 2: Mechanical Data
2.1 THERMAL SPECIFICATIONS
Parameter Min Typ Max Unit

Thermal Resistance ΘJC 5 °C/W
Thermal Resistance ΘJA (Still Air) 24 °C/W
Junction Temperature 125 °C
2.2 MECHANICAL DIMENSIONS
ViRGE comes in a 208-pin PQFP package. The mechanical dimensions are given in Figure 2-1.
MECHANICAL DATA 2-1

30.60 SQUARE (BASIC)
156 28.0 SQUARE (BASIC)
105
104
157
208
53
1
52
0.50 (BASIC) 0.22±0.05

4.10 MAX
COPLANARITY = 0.08 MAX

0.15±0.05
0.25 GAGE PLANE
LINEAR DIMENSIONS
0° - 7°
ARE IN MILLIMETERS
0.60 +0.15
0.25 MIN
-0.10
1.30 REF
MECHDIM
Figure 2-1. 208-pin PQFP Mechanical Dimensions
2-2 MECHANICAL DATA

Section 3: Pins
3.1 PINOUT DIAGRAMS
ViRGE comes in a 208-pin PQFP package. The pinout for a PCI configuration is shown in Figure 3-1.
The pinout a VL-Bus configuration is shown in Figure 3-2.
PINS 3-1
ENFEAT/GOP0
LCLK/VCLK
PD15/GA15
LD3/PA3
LD2/PA2
LD1/PA1
LD0/PA0
ROMEN
HSYNC
VSYNC
PD47
PD32
PD46
PD33
PD45
PD34
PD44
PD35
PD43
PD36
PD42
PD37
PD41
PD38
PD40
PD39
PD63
PD48
PD62
PD49
PD61
PD50
PD60
PD51
PD59
PD52
PD58
PD53
PD57
PD54
PD56
PD55
INTA
VDD
VSS
VSS
VSS
OE0
VSS
VSS
XIN
WE
XOUT PD0/GA0
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
CLKAVDD1 PD14/GA14
AVSS 159 102 PD1/GA1
CLKAVDD2 160 101 PD13/GA13
AVSS 161 100 PD2/GA2
VREF 162 99 VSS
VSS 163 98 PD12/GA12
AVDD 164 97 PD3/GA3
PDOWN 165 96 VDD
RSET 166 95 PD11/GA11
AVSS 167 94 PD4/GA4
AR 168 93 PD10/GA10
AVDD 169 92 PD5/GA5
AVDD 170 91 PD9/GA9
AG 171 90 PD6/GA6
AB 172 89 PD8/GA8
AVSS 173 88 PD7/GA7
LD4/PA4 174 87 VSS
LD5/PA5 175 86 CAS0
N/C 176 85 CAS1
N/C 177 84 RAS0
N/C 178 83 CAS2
N/C 179 82 CAS3
N/C
N/C
180
181
ViRGE (PCI) 81
80
VDD
MA8
N/C
ESYNC
182
183 TOP VIEW 79
78
MA0
MA7
LD6/PA6 184 77 MA1
LD8/PA8 185 76 MA6
LD9/PA9 186 75 MA2
LD10/PA10 187 74 MA5
LD11/PA11 188 73 MA3
LD12/PA12 189 72 MA4
STWR/GOP1 190 71 VSS
BLANK 191 70 PD31
VDD 192 69 PD16/GD0
RESET 193 68 PD30
SCLK 194 67 PD17/GD1
VSS 195 66 PD29
VCLKI 196 65 PD18/GD2
GNT 197 64 PD28
REQ 198 63 PD19/GD3
LD13/PA13 199 62 VDD
LD14/PA14 200 61 PD27
LD15/PA15 201 60 VSS
LD7/PA7 202 59 PD20/GD4
VREQ/VRDY/HS/EVIDEO 203 58 PD26
CREQ/CRDY/VS/EVCLK 204 57 PD21/GD5
SPCLK 205 56 PD25
SPD 206 55 PD22/GD6
AD31 PD24
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
3
4
5
6
7
8
9
AD30 PD23/GD7
VIRPCIPN
TRDY
RAS1/OE1
AD29
AD28
AD27
AD26
AD25
AD24
C/BE3
IDSEL
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
C/BE2
FRAME
C/BE1
AD15
AD14
AD13
AD12
AD11
AD10
C/BE0
CAS4
CAS5
CAS6
CAS7
VSS
VDD
IRDY
DEVSEL
VSS
STOP
PAR
VSS
AD9
AD8
VDD
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
VSS
Figure 3-1. PCI Bus Pinout
3-2 PINS
ENFEAT/GPIOSTR/GOP0
ROMCS/GOP1
LCLK/VCLK
LD3/PA3
LD2/PA2
LD1/PA1
LD0/PA0
HSYNC
VSYNC
SINTR
PD47
PD32
PD46
PD33
PD45
PD34
PD44
PD35
PD43
PD36
PD42
PD37
PD41
PD38
PD40
PD39
PD63
PD48
PD62
PD49
PD61
PD50
PD60
PD51
PD59
PD52
PD58
PD53
PD57
PD54
PD56
PD55
PD15
VDD
VSS
VSS
VSS
OE0
VSS
VSS
XIN
WE
XOUT
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
PD0
CLKAVDD1 PD14
AVSS 159 102 PD1
CLKAVDD2 160 101 PD13
AVSS 161 100 PD2
VREF 162 99 VSS
VSS 163 98 PD12
AVDD 164 97 PD3
PDOWN 165 96 VDD
RSET 166 95 PD11
AVSS 167 94 PD4
AR 168 93 PD10
AVDD 169 92 PD5
AVDD 170 91 PD9
AG 171 90 PD6
AB 172 89 PD8
AVSS 173 88 PD7
LD4/PA4 174 87 VSS
LD5/PA5 175 86 CAS0
SA2 176 85 CAS1
SA3 177 84 RAS0
SA4 178 83 CAS2
SA5 179 82 CAS3
SA6
SA7
180
181
ViRGE (VL-BUS) 81
80
VDD
MA8
SA8
SA9
182
183 TOP VIEW 79
78
MA0
MA7
LD6/PA6 184 77 MA1
SA10 185 76 MA6
SA11 186 75 MA2
SA12 187 74 MA5
SA13 188 73 MA3
SA14 189 72 MA4
SA15 190 71 VSS
SA16 191 70 PD31
VDD 192 69 PD16
SRESET 193 68 PD30
SCLK 194 67 PD17
VSS 195 66 PD29
SA17 196 65 PD18
SA18 197 64 PD28
SA19 198 63 PD19
SA20 199 62 VDD
SA21 200 61 PD27
SA22 201 60 VSS
LD7/PA7 202 59 PD20
VREQ/VRDY/HS/EVIDEO 203 58 PD26
CREQ/CRDY/VS/EVCLK 204 57 PD21
SPCLK/ESYNC 205 56 PD25
SPD/BLANK 206 55 PD22
SD31 PD24
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
3
4
5
6
7
8
9
SD30 PD23
VIRVLPIN
SM/IO
RDYIN
SW/R
LOCA
SD29
SD28
SD27
SD26
SD25
SD24
SBE3
SD23
SD22
VDD
SD21
SD20
SD19
SD18
SD17
SD16
SBE2
SADS
SRDY
SAUP1
SBE1
SD15
SD14
SD13
SD12
SD11
SD10
CAS4
CAS5
VDD
SBE0
SAUP2
CAS6
CAS7
VSS
VSS
VSS
SD9
SD8
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
VSS
Figure 3-2. VL-Bus Pinout
PINS 3-3
3.2 PIN DESCRIPTIONS
The following table provides a brief description of each pin on ViRGE for its PCI bus and VL-Bus
configurations. The following abbreviations are used for pin types.
I - Input signal
O - Output signal
B - Bidirectional signal
Some pins have multiple names. This either reflects the different functions performed by those pins
depending on the bus configuration selected by power-on-strapping or multiplexed pins whose
functions are selected via a register bit setting. The pin definitions and functions are given for each
possible case.
Table 3-1. Pin Descriptions
Symbol Type Pin Number(s) Description

BUS INTERFACES
Address and Data
AD[31:0] B 207-208, 1-6, (PCI) Multiplexed Address/Data Bus. A bus transaction
10-11, 13-18, (cycle) consists of an address phase followed by one
28-31, 33-36, or more data phases.
39-46
SD[31:0] B (VL) System Data Bus.

SA[22:2] I 201-196, 191- (VL) System Address Bus Lines 22:2.
185, 183-176
SAUP1 (VL) I 25 (VL) Upper Address Decode 1. In conjunction with
SAUP2 this input tells ViRGE when to respond when
its memory/register address space has been relocated
above 4 MBytes. Specifically,
SAUP1 = 0, SAUP2 = 1 - register/port address access
SAUP1 = 1, SAUP2 = 0 - video memory access
The other two combinations are ignored.
SAUP2 (VL) I 50 (VL) Upper Address Decode 2. See definition for
SAUP1.
C/BE[3:0] B 7, 19, 27, 38 (PCI) Bus Command/Data Byte Enables. These signals
carry the bus command during the address phase and
the byte enables during the data phase. These signals
are outputs during bus master DMA operation.
SBE[3:0] I (VL) Data Byte Enables.

Bus Control
SCLK I 194 (PCI) PCI System Clock.
SCLK I (VL) CPU System Clock

INTA O 152 (PCI) Interrupt Request.
SINTR (VL) Interrupt Request.
3-4 PINS

IRDY B 21 (PCI) Initiator Ready. A bus data phase is completed
when both IRDY and TRDY are asserted on the same
cycle. This signal is an output during bus master DMA
operation.
RDYIN I (VL) Local Bus Cycle End Acknowledge. ViRGE holds

read data valid on the system data bus until this input
is asserted.
TRDY B 23 (PCI) Target Ready. A bus data phase is completed
when both IRDY and TRDY are asserted on the same
cycle. This signal is an input during bus master DMA
operation.
SRDY O (VL) Local Bus Cycle End.

DEVSEL B 24 (PCI) Device Select. ViRGE drives this signal active
when it decodes its address as the target of the
current access. This signal is an input during bus
master DMA operation.
LOCA O (VL) Local Bus Access Cycle Indicator. This signal is

output during local bus cycles to allow system logic
chip sets to prevent concurrent EISA/ISA cycle
generation.
IDSEL I 8 (PCI) Initialization Device Select. This input is the chip
select for PCI configuration register reads/writes.
SM/IO I (VL) Memory/I/O Cycle Indicator. This signal is high for

a memory cycle and low for an I/O cycle.
RESET I 193 (PCI) System Reset. Asserting this signal forces the
registers and state machines to a known state.
SRESET (VL) System Reset.

FRAME B 20 (PCI) Cycle Frame. This signal is asserted by the bus
master to indicate the beginning of a bus transaction.
It is deasserted during the final data phase of a bus
transaction. This signal is an output during bus master
DMA operation.
SADS I (VL) System Address Strobe.

PAR B 26 (PCI) Parity. ViRGE asserts this signal to verify even
parity during reads. This signal is an input during bus
SW/R I (VL) Write/Read Cycle Indicator. This signal is high for

a write and low for a read.
PINS 3-5

STOP B 25 (PCI) Stop. ViRGE asserts this signal to indicate a
target disconnect. This signal is an input during bus
SAUP1 I (VL) Upper Address Decode 1. In conjunction with

SAUP2 this input tells ViRGE when to respond when
its memory/register address space has been relocated
above 4 MBytes. Specifically,
SAUP1 = 0, SAUP2 = 1 - register/port address access
SAUP1 = 1, SAUP2 = 0 - video memory access
The other two combinations are ignored.
REQ O 198 Request. ViRGE asserts this signal to request control
of the PCI bus for bus master DMA operation.
GNT I 197 Grant. When active, this signal indicates that ViRGE
has control of the PCI bus for bus master DMA
operation.
CLOCK CONTROL
XIN I 156 Reference Frequency Input. If an external crystal is
used, it is connected between XOUT and this pin. A
stable external frequency source can also be input via
this pin. If PD11 is strapped low at power-on, this
becomes the DCLK (dot clock) input, bypassing the
internal oscillator. This is normally only used for test
purposes.
XOUT O 157 Crystal Output. If an external 14.318 MHz crystal is
used, it is connected between XIN and this pin. This
pin drives the crystal via an internal oscillator.
3-6 PINS

DISPLAY MEMORY INTERFACE
Address and Data
MA[8:0] O 80, 78, 76, 74, Memory Address Bus. The video memory row and
72, 73, 75, 77, column addresses are multiplexed on these lines.
79
PD[63:0] B 122, 120, 118, Display Memory Pixel Data Bus Lines. Display
116, 113, 111, Memory Pixel Data Bus Lines 31:0. PD[28:0] are also
109, 107, 106, used as the system configuration strapping bits,
108, 110, 112, providing system configuration and setup information
115, 117, 119, upon power-on or reset. After reset, the General Data
121, 144, 142, Bus signals are multiplexed on 24 of these pins.
140, 138, 134,
132, 130, 128,
127, 129, 131,
133, 136, 139,
141, 143, 70,
68, 66, 64, 61,
58, 56, 54, 53,
55, 57, 59, 63,
65, 67, 69,
105, 103, 101,
98, 95, 93, 91,
89, 88, 90, 92,
94, 97, 100,
102, 104
Memory Control
RAS[1:0] O 50, 84 Row Address Strobes. RAS1 is output on pin 50 when
bit 6 of SRA is set to 1 for a PCI configuration. It is not
available for VL-Bus configurations, limiting memory to
2 MBytes.
CAS[7:0] O 52, 51, 49, 48, Column Address Strobe Lines.
82, 83, 85, 86
WE O 125 Write Enable.
OE[1:0] O 50, 124 Output Enable. OE1 is output on pin 50 when bit 2 of
CR36 is cleared to 0. If the feature connector is
disabled (bit 0 of SRD cleared to 0), this output is the
same as OE0. OE1 is not available for LPB VL-Bus
configurations. Memory designs requiring use of pin
50 as a memory control signal cannot be used.
PINS 3-7

VIDEO INTERFACE
PDOWN I 165 Power Down. Asserting this signal turns off the RGB
analog output from the DACs.
VREF 162 Voltage Reference. This pin is tied to VSS through a 0.1
µF capacitor.
RSET 166 Reference Resistor. This pin is tied to VSS through an
external resistor to control the full-scale current value.
AR O 168 Analog Red. Analog red output to the monitor.
AG O 171 Analog Green. Analog green output to the monitor.
AB O 172 Analog Blue. Analog blue signal to the monitor.
ENFEAT O 151 Enable Feature Connector. Setting SRD_0 to 1 drives
this signal low when SR1C_1-0 are 00b. This also
enables all feature connector operations.
BLANK B 191, 206 Video Blank. The BLANK function is on pin 191 when
LPB feature connector operation is enabled in PCI
configurations. It is on pin 206 for LPB VL-Bus
configurations. When ESYNC is high, BLANK is a
feature connector output. When ESYNC is low,
BLANK is a feature connector input that, when driven
low, turns off the video output.
ESYNC I 183, 205 External SYNC. The ESYNC function is on pin 183
when LPB feature connector operation is enabled in
PCI configurations. It is on pin 205 for LPB VL-Bus
configurations. When ESYNC is driven low, HSYNC,
VSYNC and BLANK become inputs. When ESYNC is
high, HSYNC, VSYNC and BLANK become outputs.
EVIDEO I 203 External Video. The EVIDEO function is on pin 203
when LPB feature connector operation is enabled.
When this input is asserted low, PA[15:0] are inputs
and are sampled by VCLKI. When this input is high,
PA[15:0] are outputs to the feature connector.
EVCLK I 204 External VCLK. The EVCLK function is on pin 204
when LPB feature connector operation is enabled.
When this input is asserted low, VCLK is an input to
the internal RAMDAC. When this input is high, VCLK is
output to the feature connector.
VCLK B 148 Video/Pixel Clock. The VCLK function is enabled on pin
148 when feature connector operation is enabled.
When EVCLK is high, this signal is an output to the
feature connector. When EVCLK is low, this becomes
an input used only for test purposes.
VCLKI I 106 VCLK Input. The VCLKI function is enabled when LPB
VAFC (16-bit) feature connector operation is enabled.
Setting bit 1 of SRB to 1 causes VCLKI to be used to
clock in feature connector pixel data to the internal
RAMDAC.
3-8 PINS

HSYNC B 149 Horizontal Sync. When ESYNC is high, this is the
horizontal sync output. When ESYNC is low, this is an
input from the feature connector.
VSYNC B 150 Vertical Sync. When ESYNC is high, this is the vertical
sync output. When ESYNC is low, this is an input from
the feature connector.
PA[15:0] B 201-199, 189- Pixel Address Lines [15:0]. The PA[15:0] function is
185, 202, 184, enabled on the pins indicated for PCI configurations
175, 174, 155, when LPB feature connector operation is enabled.
154, 147, 146 Only PA[7:0] are enabled for VL-Bus configurations.
When EVIDEO is high, PA signals are outputs to the
feature connector. When EVIDEO is low, PA signals
are inputs and are sampled by VCLKI if bit 1 of SRB is
set to 1.
MISCELLANEOUS FUNCTIONS
General Data, I/O and Serial Ports
GA[15:0] O 105, 103, 101, (PCI) General Address Bus. These signals provide the
98, 95, 93, 91, address for BIOS ROM reads. They are multiplexed
89, 88, 90, 92, with PD signals. Programmers must ensure that the
94, 97, 100, memory bus is inactive when reading the ROM.
102, 104
GD[7:0] I 53, 55, 57, 59, (PCI) General Data Bus. These signals carry data for
63, 65, 67, 69 BIOS ROM reads. They are multiplexed with PD
signals. Programmers must ensure that the memory
bus is inactive when reading the ROM.
ROMEN O 153 (PCI) ROM Enable. This signal provides the chip output
enable input for BIOS ROM reads.
ROMCS O 153 (VL) ROM Chip Select. This signal provides the chip
output enable for BIOS ROM reads. It is output when
bits 1-0 of SR1C are any value except 11b.
GPIOSTR O 151 (VL) General Input/Output Port Write Strobe. If
SR1C_1-0 are 01b, this is asserted whenever a
General Input Port access (CR55_2 is set to 1 and the
3C8H port is read) or a General Output Port access
(write to CR5C) is made.
GOP[1:0] O 190, 151 (PCI) General Output Port Bits 1-0. If SR1C_1 is set to
1, the value of CR5C_0 is output on pin 151 (GOP0)
and the value of CR5C_1 is output on pin 190 (GOP1).
GOP[1:0] O 153, 151 (VL) General Output Port Bits 1-0. If bit 1 of SR1C is
set to 1, the value of CR5C_0 is output on pin 151
(GOP0). If SR1C_1-0 are 11b, the value of CR5C_1 is
output on pin 153 (GOP1)
PINS 3-9

STWR O 190 (PCI) Strobe Write. If SR1C_1 is cleared to 0, this
signal is asserted whenever a write is made to CR5C.
It is used to enable a General Output Port latch.
SPCLK B 205 Serial Port Clock. This is the clock for serial data
transfer, either for I2C or DDC2 monitor data
communications. As an output, it is programmed via
MMFF20_0. As an input, its status is read via
MMFF20_2. In either case the serial port must be
enabled by setting MMFF20_4 to 1. PD[26:25] can be
strapped to allow I/O (E2H or E8H) access to MMFF20
while ViRGE is disabled.
SPD B 206 Serial Port Data. This is the data signal for serial data
transfer, either for I2C or DDC2 monitor data
communications. As an output, it is programmed via
MMFF20_1. As an input, its status is read via
MMFF20_3. In either case the serial port must be
enabled by setting MMFF20_4 to 1. PD[26:25] can be
strapped to allow I/O (E2H or E8H) access to MMFF20
while ViRGE is disabled.
LOCAL PERIPHERAL BUS
Scenic/MX2 Mode
LD[7:0] B 202, 184, 175, LPB Data. This is the Scenic Highway data bus and
174, 155, 154, carries compressed data to the Scenic/MX2 and video
147. 146 data from the Scenic/MX2.
LCLK I 148 LPB Clock. This clock controls transactions between
ViRGE and Scenic Highway peripherals
VREQ/VRDY O 203 Video Request/Ready. This signal is part of the the
Scenic Highway data transfer protocol between ViRGE
and the Scenic/MX2.
CREQ/CRDY I 204 Scenic/MX2 Request/Ready. This signal is part of the
the Scenic Highway data transfer protocol between
ViRGE and the Scenic/MX2.
3-10 PINS

Video 8 in and Video 16 (PCI only) Modes
LD[7:0] I 202, 184, 175, LPB Data Bus [7:0]. This is the Scenic Highway data
174, 155, 154, bus and carries video data input.
147. 146
LD[15:8] I 201-199, 189- (PCI) LPB Data Bus [15:8]. Scenic Highway video data
185 input for the upper data byte in Video 16 mode.
HS I 203 HSYNC. HSYNC input signaling the transition from one
line to the next.
VS I 204 VSYNC. VSYNC input signaling the transition from one
frame to the next.
POWER AND GROUND
VDD I 12, 37, 62, 81, Digital power supply
96, 137, 192
AVDD I 164, 169, 170 Analog power supply (RAMDAC)
CLKAVDD[1:2] I 158, 160 Analog power supply (clock synthesizer, CLK1 =
DCLK, CLK2 = MCLK)
VSS I 9, 22, 32, 47, Digital ground
60, 71, 87, 99,
114, 123, 126,
135, 145, 195
AVSS I 159, 161, 163, Analog ground
167, 173
PINS 3-11
3.3 PIN LISTS
Table 3-2 lists all pins alphabetically. The pin number(s) corresponding to each pin name are given in
the appropriate mode/bus interface type column. Table 3-3 lists all pins in numerical order. The
corresponding pin name/pin number is given in the appropriate mode/bus interface column.
Table 3-2. Alphabetical Pin Listing

PIN(S)
Name PCI VL
AB 172 172
AD[31:0] 207-208, 1-6, 10-11,13-18, 28-31,
33-36,39-46
AG 171 171
AR 168 168
AVDD 164, 169, 170 164, 169, 170
AVSS 159, 161, 167, 173 159, 161, 167, 173
BLANK 191 206
CAS[3:0] 82, 83, 85, 86 82, 83, 85, 86
CAS[7:4] 52, 51, 49, 48 52, 51, 49, 48
C/BE[3:0] 7, 19, 27, 38
CLKAVDD[1:2] 158, 160 158, 160
CREQ/CRDY 204 204
DEVSEL 24
ENFEAT 151 151
ESYNC 183 205
EVCLK 204 204
EVIDEO 203 203
FRAME 20
GA[15:0] 105, 103, 101, 98, 90, 92, 94, 97, 100,
102, 104
GD[7:0] 53, 55, 57, 59, 63, 65, 67, 69
GOP[1:0] 190, 151 153, 151
GNT 197
GPIOSTR 151
HSYNC 149 149
IDSEL 8
INTA 152
IRDY 21
LCLK 148 148
LD[7:0] 202, 184, 175, 174, 155, 154, 147, 146 202, 184, 175, 174, 155, 154, 147, 146
LD[15:8] 201-199, 189-185
LOCA 24
MA[8:0] 80, 78, 76, 74, 72, 73, 75, 77, 79 80, 78, 76, 74, 72, 73, 75, 77, 79
OE0 124 124
OE1 50
PA[7:0] 202, 184, 175, 174, 155, 154, 147, 146 202, 184, 175, 174, 155, 154, 147, 146
3-12 PINS
Table 3-2. Alphabetical Pin Listing (Continued)
PIN(S)
Name PCI VL
PA[15:8] 201-199, 189-185, 134, 132, 130, 128
PAR 26
PD[63:0] 122, 120, 118, 116, 113, 111, 109, 107, 122, 120, 118, 116, 113, 111, 109, 107,
106, 108, 110, 112, 115, 117, 119, 121, 106, 108, 110, 112, 115, 117, 119, 121,
144, 142, 140, 138, 134, 132, 130, 128, 144, 142, 140, 138, 134, 132, 130, 128,
134, 132, 130, 128, 127, 129, 131, 133, 134, 132, 130, 128, 127, 129, 131, 133,
136, 139, 141, 143, 70, 68, 66, 64, 61, 136, 139, 141, 143, 70, 68, 66, 64, 61,
58, 56, 54, 53, 55, 58, 56, 54, 53, 55, 58, 56, 54, 53, 55, 58, 56, 54, 53, 55,
57, 59, 63, 65, 67, 69, 105, 103, 101, 57, 59, 63, 65, 67, 69, 105, 103, 101,
98, 95, 93, 91, 89, 88, 90, 92, 94, 97, 98, 95, 93, 91, 89, 88, 90, 92, 94, 97,
100, 102, 104 100, 102, 104
PDOWN 165 165
RAS0 50 50
RAS1 84
REQ 198
RESET 193
RDYIN 21
ROMEN 153
ROMCS 153
RSET 166 166
SA[22:2] 201-196, 191-185, 183-176
SADS 20
SAUP1 25
SAUP2 50
SBE[3:0] 7, 19, 27, 38
SCLK 194 194
SD[31:0] 207-208, 1-6, 10-11, 13-18, 28-31, 33-36,
39-46
SINTR 152
SM/IO 8
SPCLK 205 205
SPD 206 206
SRDY 23
SRESET 193
STOP 25
STWR 190
SW/R 26
TRDY 23
PINS 3-13
Table 3-2. Alphabetical Pin Listing (Continued)
PIN(S)
Name PCI VL
VCLKI 106 106
VDD 12, 37, 62, 81, 96, 137, 192 12, 37, 62, 81, 96, 137, 192
VREQ/VRDY 203 203
VREF 162 162
VS 204 204
VSS 9, 22, 32, 47, 60, 71, 87, 114, 123, 9, 22, 32, 47, 60, 71, 87, 114, 123,
126, 135, 145, 163, 195 126, 135, 145, 163, 195
VSYNC 150 150
WE 125 125
XIN 156 156
XOUT 157 157
3-14 PINS
Table 3-3. Numerical Pin Listing

Name
Number PCI VL
1 AD29 SD29
2 AD28 SD28
3 AD27 SD27
4 AD26 SD26
5 AD25 SD25
6 AD24 SD24
7 C/BE3 SBE3
8 IDSEL SM/IO
9 VSS VSS
10 AD23 SD23
11 AD22 SD22
12 VDD VDD
13 AD21 SD21
14 AD20 SD20
15 AD19 SD19
16 AD18 SD18
17 AD17 SD17
18 AD16 SD16
19 C/BE2 SBE2
20 FRAME SADS
21 IRDY RDYIN
22 VSS VSS
23 TRDY SRDY
24 DEVSEL LOCA
25 STOP SAUP1
26 PAR SW/R
27 C/BE1 SBE1
28 AD15 SD15
29 AD14 SD14
30 AD13 SD13
31 AD12 SD12
32 VSS VSS
33 AD11 SD11
34 AD10 SD10
35 AD9 SD9
36 AD8 SD8
37 VDD VDD
38 C/BE0 SBE0
39 AD7 SD7
40 AD6 SD6
41 AD5 SD5
42 AD4 SD4
PINS 3-15
Table 3-3. Numerical Pin Listing (Continued)

Name
Number PCI VL
43 AD3 SD3
44 AD2 SD2
45 AD1 SD1
46 AD0 SD0
47 VSS VSS
48 CAS4 CAS4
49 CAS5 CAS5
50 RAS1/OE1 SAUP2
51 CAS6 CAS6
52 CAS7 CAS7
53 PD23/GD7 PD23
54 PD24 PD24
55 PD22/GD6 PD22
56 PD25 PD25
57 PD21/GD5 PD21
58 PD26 PD26
59 PD20/GD4 PD20
60 VSS VSS
61 PD27 PD27
62 VDD VDD
63 PD19/GD3 PD19
64 PD28 PD28
65 PD18/GD2 PD18
66 PD29 PD29
67 PD17/GD1 PD17
68 PD30 PD30
69 PD16/GD0 PD16
70 PD31 PD31
71 VSS VSS
72 MA4 MA4
73 MA3 MA3
74 MA5 MA5
75 MA2 MA2
76 MA6 MA6
77 MA1 MA1
78 MA7 MA7
79 MA0 MA0
80 MA8 MA8
81 VDD VDD
82 CAS3 CAS3
83 CAS2 CAS2
84 RAS0 RAS0
3-16 PINS

Name
Number PCI VL
85 CAS1 CAS1
86 CAS0 CAS0
87 VSS VSS
88 PD7/GA7 PD7
89 PD8/GA8 PD8
90 PD6/GA6 PD6
91 PD9/GA9 PD9
92 PD5/GA5 PD5
93 PD10/GA10 PD10
94 PD4/GA4 PD4
95 PD11/GA11 PD11
96 VDD VDD
97 PD3/GA3 PD3
98 PD12/GA12 PD12
99 VSS VSS
100 PD2/GA2 PD2
101 PD13/GA13 PD13
102 PD1/GA1 PD1
103 PD14/GA15 PD14
104 PD0/GA0 PD0
105 PD15/GA15 PD15
106 PD55 PD55/
107 PD56 PD56
108 PD54 PD54
109 PD57 PD57
110 PD53 PD53
111 PD58 PD58
112 PD52 PD52
113 PD59 PD59
114 VSS VSS
115 PD51 PD51
116 PD60 PD60
117 PD50 PD50
118 PD61 PD61
119 PD49 PD49
120 PD62 PD62
121 PD48 PD48
122 PD63 PD63
123 VSS VSS
124 OE0 OE0
125 WE WE
126 VSS VSS
PINS 3-17

Name
Number PCI VL
127 PD39 PD39
128 PD40 PD40
129 PD38 PD38
130 PD41 PD41
131 PD37 PD37
132 PD42 PD42
133 PD36 PD36
134 PD43 PD43
135 VSS VSS
136 PD35 PD35
137 VDD VDD
138 PD44 PD44
139 PD34 PD34
140 PD45 PD45
141 PD33 PD33
142 PD46 PD46
143 PD32 PD32
144 PD47 PD47
145 VSS VSS
146 LD0/PA0 LD0/PA0
147 LD1/PA1 LD1/PA1
148 LCLK/VCLK LCLK/VCLK
149 HSYNC HSYNC
150 VSYNC VSYNC
151 ENFEAT/GOP0 ENFEAT/GPIOSTR/GOP0
152 INTA SINTR
153 ROMEN ROMCS/GOP1
154 LD2/PA2 LD2/PA2
155 LD3/PA3 LD3/PA3
156 XIN XIN
157 XOUT XOUT
158 CLKAVDD1 CLKAVDD1
159 AVSS AVSS
160 CLKAVDD2 CLKAVDD2
161 AVSS AVSS
162 VREF VREF
163 VSS VSS
164 AVDD AVDD
165 PDOWN PDOWN
166 RSET RSET
167 AVSS AVSS
168 AR AR
3-18 PINS

Name
Number PCI VL
169 AVDD AVDD
170 AVDD AVDD
171 AG AG
172 AB AB
173 AVSS AVSS
174 LD4/PA4 LD4/PA4
175 LD5/PA5 LD5/PA5
176 N/C SA2
177 N/C SA3
178 N/C SA4
179 N/C SA5
180 N/C SA6
181 N/C SA7
182 N/C SA8
183 ESYNC SA9
184 LD6/PA6 LD6/PD6
185 LD8/PA8 SA10
186 LD9/PA9 SA11
187 LD10/PA10 SA12
188 LD11/PA11 SA13
189 LD12/PA12 SA14
190 STWR/GOP1 SA15
191 BLANK SA16
192 VDD VDD
193 RESET SRESET
194 SCLK SCLK
195 VSS VSS
196 VCLKI SA17
197 GNT SA18
198 REQ SA19
199 LD13/PA13 SA20
200 LD14/PA14 SA21
201 LD15/PA15 SA22
202 LD7/PA7 LD7/PA7
203 VREQ/VRDY/HS/EVIDEO VREQ/VRDY/HS/EVIDEO
204 CREQ/CRDY/VS/EVCLK CREQ/CRDY/VS/EVCLK
205 SPCLK SPCLK/ESYNC
206 SPD SPD/BLANK
207 AD31 SD31
208 AD30 SD30
PINS 3-19
Section 4: Electrical Data
4.1 MAXIMUM RATINGS
Table 4-1. Absolute Maximum Ratings
Ambient temperature 0° C to 70° C

Storage temperature -40° C to 125° C
DC Supply Voltage -0.5V to 7.0V
I/O Pin Voltage with respect to VSS -0.5V to VDD+0.5V
4.2 DC SPECIFICATIONS
Note: In all cases below, digital VDD = 5V ± 5% and the operating temperature is 0° C to 70° C.
Table 4-2. RAMDAC/Clock Synthesizer DC Specifications
Symbol Parameter Min Typical Max Unit

AVDD DAC supply voltage 4.75 5 5.25 V
AVDD (CLOCK) PLL supply voltage 4.75 5 5.25 V
VREF Internal voltage reference 1.10 1.235 1.35 V
Table 4-3. RAMDAC Characteristics
Min Typical Max Unit

Resolution Each DAC 8 bits
LSB Size 66 µA
Integral Linearity Error ±1 LSB
Differential Linearity Error ±1 LSB
Output Full-Scale Current 15.4 17.6 19.8 mA
DAC to DAC Mismatch 5%
Power Supply Rejection Ratio 0.5 %/ % AVDD
Output Compliance 0.0 1.5 V
Output Capacitance 30 pF
Glitch Impulse 75 pV-Sec
ELECTRICAL DATA 4-1

Table 4-4. Digital DC Specifications (VDD = 5V ± 5%, Operating Temperature 0° C to 70° C)
Symbol Parameter Min Max Unit

VIL Input Low Voltage -0.5 0.8 V
VIH Input High Voltage 2.4 VDD +0.5 V
VOL Output Low Voltage VSS + 0.4 V
VOH Output High Voltage 2.4 V
IOL1 Output Low Current 8 (Note 1) mA
IOH1 Output High Current -4 mA
IOZ Output Tri-state Current 1 µA
CIN Input Capacitance 5 pF
COUT Output Capacitance 5 pF
ICC Power Supply Current 500 (Note 4) mA
Notes
1. IOL1, IOH1 for pins ROMEN, INTA, STWR, HSYNC, VSYNC, VCLK, BLANK, ENFEAT,
MA[8:0], CAS[7:0], PD[63:0], AD[31:0], LD[7:0], VREQ/VRDY, SPCLK, SPD, REQ
2. IOL2, IOH2 for pins OE[1:0], WE, RAS[1:0]3
3. IOL3, IOH3 for pins PAR, STOP, DEVSEL, TRDY
4. ICC measured for a resolution of 1024x768x8 with a 75 MHz DCLK and a 50 MHz MCLK at 25°C
and 5V.
5. The pin names used in these notes are the primary ones for PCI configurations. An output
signal multiplexed on one of these pins has the same drive level, as does a VL-Bus output for
the same pin.
4-2 ELECTRICAL DATA

4.3 AC SPECIFICATIONS
4.3.1 RAMDAC AC Specifications
Table 4-5. RAMDAC AC Specifications
Parameter Typical Max Unit Notes

DAC Output Delay 5 ns 1
DAC Output Rise/Fall Time 3 ns 2
DAC Output Settling Time 15 ns
DAC-to-DAC Output Skew 2 5 ns 3
Notes
1. Measured from the 50% point of VCLK to the 50% point of full scale transition
2. Measured from 10% to 90% full scale
3 With DAC outputs equally loaded
Table 4-6. RAMDAC Output Specifications
Description IOUT (mA) VOUT (V) BLANK Input Data

White 17.6 typical 0.66 typical 1 FFH
Data Data Data 1 Data
Data (sync) Data Data 1 Data
Black 0 0 1 00H
Black (sync) 0 0 1 00H
BLANK 0 0 0 Don’t Care
Note
1. Condition for VOUT is a 75 Ohm doubly terminated load, RSET = 147 Ohms and use of internal
VREF.
ELECTRICAL DATA 4-3

4.3.2 Clock Timing
THIGH
2.4V
1.5V
0.8V
TLOW
TCYC DCLKTIME
Figure 4-1. Clock Waveform Timing
Table 4-7. Clock Waveform Timing
Symbol Parameter Min Max Units Notes

TCYC SCLK Cycle Time (VL-Bus) 20 125 ns 1
SCLK Cycle Time (PCI) 30 125 ns 1
LCLK Cycle Time 30 200 ns
MCLK Cycle Time 20 100 ns
DCLK Cycle Time (VGA Mode) 25 100 ns 1
DCLK Cycle Time (Enhanced Mode) 12.5 100 ns 1, 2
THIGH SCLK High Time (VL-Bus) 8 80 ns
SCLK High Time (PCI) 12 80 ns
LCLK High Time 12 160 ns
TLOW SCLK Low Time (VL-Bus) 8 80 ns
SCLK Low Time (PCI) 12 80 ns
LCLK Low Time 12 160 ns
SCLK Slew Rate 1 4 V/ns 3
LCLK Slew Rate 1 4 v/nS 3
Notes
1. fDCLK ≥ 1/2 fSCLK to ensure valid writes to the PLLs.

2. For DCLK rates above 80 MHz, clock doubling is used. The maximum DCLK rate with clock
doubling is 67.5 MHz.
3. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate
must be met across the minimum peak-to peak portion of the clock waveform.
4-4 ELECTRICAL DATA

4.3.3 Input/Output Timing
CLOCK 1.5 V
TSU TH
INPUT 1.5 V 1.5 V

TCLKIN
Figure 4-2. Input Timing
Table 4-8. SCLK-Referenced Input Timing
PCI Bus
Symbol Parameter Min Units
TSU AD[31:0], C/BE[3:0], FRAME, IRDY, IDSEL setup 7 ns
TH AD[31:0] hold 1 ns
TH C/BE[3:0], FRAME, IRDY, IDSEL hold 1 ns
TSU GNT setup 10 ns
TH GNT hold 0 ns
VL-Bus
TSU AD[31:2], BE[3:0], SM/IO, SW/R, SADS (address 12 ns
phase) setup
TH AD[31:2], BE[3:0], SM/IO, SW/R, SADS (address 1 ns
phase) hold
TSU AD[31:2], BE[3:0], D1, D0, SADS (data phase) 4 ns
setup
TH AD[31:2], BE[3:0], D1, D0, SADS (data phase) 1 ns
hold
TSU RDYIN setup 6 ns
TH RDYIN hold 1 ns
Miscellaneous
TSU ROM data GD[7:0] setup (PCI) 5 ns
TH ROM data GD[7:0] hold (PCI) 7 ns
TSU General Input Port GD[7:0] setup 5 ns
TH General Input Port GD[7:0] hold 7 ns
ELECTRICAL DATA 4-5

Table 4-9. LCLK-Referenced Input Timing
Scenic/MX2 Interface
TSU LD[7:0] setup 10 ns
TH LD[7:0] hold 9 ns
TSU CREQ/CRDY 6 ns
TH CREQ/CRDY 8 ns
SAA7110 Interface
TSU LD[7:0] setup (also LD[15:8] for 16-bit interface) 6 ns
TH LD[7:0] hold (also LD[15:8] for 16-bit interface) 8 ns
TSU HS setup 6 ns
TH HS hold 7 ns
TSU VS setup 6 ns
TH VS hold 7 ns
Table 4-10. MCLK-Referenced Input Timing

TSU MD[63:0] setup to MCLK high (2-cycle EDO) 0 ns
TH MD[63:0] hold from MCLK high (2-cycle EDO) 15 ns
TSU MD[63:0] setup to following CAS low (1-cycle 0 ns
EDO)
TH MD[63:0] hold from following CAS low (1-cycle 12.5 ns
EDO)
Note
1. The timing reference in each of the two cases above is to the event that causes the latching
of the read data. The MCLK used to latch 2-cycle EDO data is an internal signal that cannot be
directly observed. The CAS signals used to latch read data in 1-cycle EDO mode are derived
from the internal MCLK.
4-6 ELECTRICAL DATA

CLOCK 1.5 V
MAX
MIN
OUTPUT 1.5 V 1.5 V

TCLKOUT
Figure 4-3. Output Timing

The minimum delay is the minimum time after the clock edge that the valid signal state from the
previous cycle will begin transition to the next state (become invalid). The maximum delay is the
maximum time after the clock edge that the signal state is valid for the next cycle.
Note: All output timings are based on an 60 pF test load. For each additional 10 pF load, add 0.94 ns
to the maximum value and add 0.4 ns to the minimum value.
Table 4-11. SCLK-Referenced Output Timing
PCI Bus
Parameter Min Max Units Notes
AD[31:0] valid delay 2 16 ns 1
DEVSEL, PAR delay 2 11 ns Medium DEVSEL
timing used
STOP delay 2 11 ns
TRDY delay 2 11 ns
INTA delay 2 11 ns
REQ delay 2 10 ns
VL-Bus
AD[31:2], D1, D0 valid delay 7 16 ns
SINTR delay 5 30 ns
SRDY delay 5 11 ns
LOCA active delay 5 15 ns
LOCA inactive delay 5 20 ns
Miscellaneous
STRD delay 3 15 ns
ROMEN (PCI) delay 4 10
ROM address valid delay (PCI) 5 30 ns
AD[7:0] ROM data valid delay (PCI) 5 30 ns
Note
1. Due to the timing for TRDY for read cycles, data is not sampled on the clock edge immediately
following its becoming valid. This guarantees the PCI 2.1 specification time of 11 ns.
ELECTRICAL DATA 4-7

Table 4-12. LCLK-Referenced Output Timing
Scenic/MX2 Interface
VREQ/VRDY active delay 6 18 ns
LD[7:0] valid delay 7 19 ns
LD[7:0] tri-state from LCLK 7 15 ns
Table 4-13. MCLK-Referenced Output Timing

PD[63:0] valid delay 4 14 ns 1, 2
MA[8:0] valid delay 8 19 ns 2
CAS[7:0] active delay 8 18 ns 2
CAS[7:0] inactive delay 7 18 ns 2
RAS[1:0] active delay 8 18 ns 2
RAS[1:0] inactive delay 7 17 ns 2
OE[1:0] active delay 7 18 ns 2
OE[1:0] inactive delay 7 18 ns 2
WE active delay 7 17 ns 2
WE inactive delay 7 16 ns 2
Note
1. The maximum delay time is for 1-cycle operation.

2 These values are based on the externally observable MCLK (output on pin 147 when SR15_2 = 1.
See the Tech Note DRAMs Supported by the S3 ViRGE 3D Accelerator for more DRAM timing
information.
Table 4-14. Feature Connector Timing - Output from ViRGE to Feature Connector
Symbol Parameter Min Units Notes

TSU PA[15:0], BLANK setup to VCLK rising 5 ns
TH PA[15:0], BLANK hold from VCLK rising 5 ns
4-8 ELECTRICAL DATA

Table 4-15. Feature Connector Timing - Output from Feature Connector to ViRGE
Symbol Parameter Min Max Units Notes

TSU PA[15:0], BLANK setup to VCLK or 6 ns 1
VCLKI rising
TH PA[15:0], BLANK hold from VCLK or 6 ns 1
VCLKI rising
VCLK 25 40 ns 1
VCLKI 27 40 ns 1, 2
VCLK, VCLKI duty cycle 40 60 %
VCLK, VCLKI high time 10 25 ns
VCLK, VCLKI low time 10 25 ns
VCLK, VCLKI slew rate 1 4 V/ns
Notes
1. Pixel data is clocked into the internal RAMDAC using VCLK for a pass-through feature
connector and VCLKI for a VAFC configuration.
2. This corresponds to the VESA VAFC specification of a maximum clock of 37.5 MHz.
ELECTRICAL DATA 4-9

TLOW
SRESET, RESET
TH
SYSTEM
CONFIGURATION
DATA
RESETTM
TSU
Figure 4-4. Reset Timing
Table 4-16. Reset Timing

TLOW SRESET (VL) or RESET (PCI) active pulse width 1000 ns
TSU PD[28:0] setup to SRESET (VL) or RESET (PCI) 20 ns
inactive
TH PD[28:0] hold from SRESET (VL) or RESET (PCI) 10 ns
inactive
4-10 ELECTRICAL DATA

Section 5: Reset and Initialization
The reset signal (RESET for PCI, SRESET for VL-

Bus) resets the internal state machines in ViRGE
and places all registers in their power-on default
states. It also initiates several configuration ac-
tions, as described in this section.
The PD[28:0] pins are pulled up internally . They

can be individually pulled low through external
10 KΩ resistors. These pull-ups and pull-downs
do not affect normal operation of the pins as part
of the pixel data bus, but they do force the pins
to a definite state during reset. At the rising edge
of the reset signal, this state is sampled and the
data loaded into the CR36, CR37, CR68 and CR6F
registers. The data is used for system configura-
tion, such as system bus and memory parameter
selection. The definitions of the PD[28:0] strap-
ping bits at the rising edge of the reset signal are
shown in Table 5-1.
Strapping bits 7-5 define the display memory

size. However, the S3 BIOS determines this value
directly and writes it to CR36_7-5 after reset.
Therefore, systems using the S3 BIOS do not
need to strap the PD[7:5] pins. Other pins may
also not require strapping, depending on the
design and bus type.
RESET AND INITIALIZATION 5-1

Table 5-1. Definition of PD[28:0] at the Rising Edge of the Reset Signal
CR Bits PD Bits Value Function

System Bus Select
CR36_1-0 1-0 00 Reserved
01 VL-Bus
10 PCI local bus
11 Reserved
Memory Page Mode Select
CR36_3-2 3-2 00 1-cycle EDO mode
01 Reserved
10 2-cycle EDO mode
11 Reserved
Enable Video BIOS (VL-Bus)
CR36_4 4 0 Disable video BIOS access (system BIOS contains video BIOS)
1 Enable video BIOS access
Display Memory Size
CR36_7-5 7-5 000 4 MBytes
001 Reserved
010 Reserved
011 Reserved
100 2 MBytes
101 Reserved
110 Reserved
111 Reserved
Enable ViRGE (VL-Bus)
CR37_0 8 0 Disable ViRGE except for video BIOS accesses
1 Enable ViRGE
CR37_1 9 Reserved
Video BIOS ROM Size (VL-Bus
CR37_2 10 0 64-KByte video BIOS
1 32-KByte video BIOS
Clock Select
CR37_3 11 0 Use external DCLK on pin 156 and external MCLK on pin 151
(test purposes only)
1 Use internal DCLK, MCLK
RAMDAC Write Snooping (VL-Bus)
CR37_4 12 0 Disable LOCA/SRDY for RAMDAC writes
1 Enable LOCA/SRDY for RAMDAC writes
BIOS Field
CR37_7-5 15-13 Reserved for use by the S3 BIOS
5-2 RESET AND INITIALIZATION

Table 5-1. Definition of PD[28:0] at the Rising Edge of the Reset Signal (Continued)
CR Bits PD Bits Value Function

CAS/OE Adjust
CR68_1-0 17-16 00 approximately 6.5 ns adjustment
01 approximately 5 ns adjustment
10 approximately 3.5 ns adjustment
11 no adjustment
RAS Low Timing Select
CR68_2 18 0 4.5 MCLKs
1 3.5 MCLKs
RAS Pre-Charge Timing Select
CR68_3 19 0 3.5 MCLKs
1 2.5 MCLKs
CR68_7-4 23-20 Reserved
CR6F_0 24 Reserved = 0
Serial Port I/O Address Select
CR6F_1 25 0 Serial Port register accessed at I/O address 000E8H
1 Serial Port register accessed at I/O address 000E2H
Serial Port Address Type Select
CR6F_2 26 0 Serial Port register accessed at address defined in CR6F_1
1 Serial Port register accessed at its MMIO address only (offset
FF20H)
WE Delay
CR6F_4-3 28-27 00 3 units delay
01 2 units delay
10 1 unit delay
11 no delay
RESET AND INITIALIZATION 5-3

Section 6: System Bus Interfaces
ViRGE interfaces to either a PCI bus or a VESA via CR66_3 and CR66_7. The RAMDAC snoop
local bus (VL-Bus). This section describes the method is selected via CR34_0. PCI master abort
connections and functional characteristics of handling during RAMDAC snooping can be dis-
these interfaces. abled via CR34_1. PCI retry handling during RAM-
DAC snooping can be disabled via CR34_2. PCI
read burst cycles can be disabled via CR3A_7.
6.1 PCI BUS INTERFACE
ViRGE provides a complete bus master PCI inter- 6.2 VL-BUS INTERFACE
face. Power-on strapping bits 1-0 must be set to
10b to enable this interface. The pinout and other Power-on strapping bits 1-0 must be set to 01b to
specifications are in conformance with Revision enable VL-Bus operation. Only SA[22:2] are di-
2.1 of the the PCI specification. No glue logic is rectly decoded. Two inputs (SAUP1, SAUP2) are
required. provided to allow decoding of the upper address
lines for ViRGE address space accesses. The
meanings of SAUP1 and SAUP2 are defined by
6.1.1 PCI Configuration the following truth table.
The Vendor ID register (Index 00H) in the PCI Table 4-1. VL-Bus Upper Address Decoding
Configuration space is hardwired to 5333H to
specify S3 Incorporated as the vendor. The SAUP2 SAUP1 EFFECT
Device ID register is hardwired to 5631H. The
0 0 Ignored
Revision ID will vary by stepping.
0 1 Decode Access to
Bits 10-9 of the Status register (Index 06H) are register/port address
hardwired to 01b to specify medium DEVSEL space
timing. The Class Code register (Index 08H) is 1 0 Decode Access to linear
hardwired to 30000xxH to specify that ViRGE is a addressing address
VGA compatible device. Bits 3-0 of the Base Ad- space (video memory)
dress 0 register (Index 10H) are hardwired to 00H. 1 1 Ignored
This indicates that the "prefetchable" bit is
cleared to 0, the base register can be located There are many ways to generate these inputs,
anywhere in a 32-bit address space and the base depending on the system design. If response to
register is located in memory space. a single linear addressing window above 4 MBy-
tes is required, a PLD can be used to decode the
appropriate address space.
6.1.2 PCI Controls
ViRGE provides several methods of controlling

PCI Bus operation. PCI disconnects are enabled
SYSTEM BUS INTERFACES 6-1

6.2.1 VL-Bus Cycles
The basic VL-Bus read cycle is shown in Figure

6-1. The address is latched by ViRGE on one of
two rising SCLK edges as shown in Figure 6-1 and
explained in Note 1.
The basic VL-Bus write cycle is shown in Figure

6-2. The single wait-state is the default configu-
ration. This can be changed to 0 wait-states
(SRDY asserted one cycle earlier) by clearing bit
4 of CR40 to 0. The address is latched at the end
of T1. By default, write data is latched on the first
rising SCLK edge after the assertion of RDYIN.
6.2.2 SRDY Generation
For a VL-Bus configuration, ViRGE raises its

SRDY output early in the T1 cycle and then tri-
states it. It then asserts SRDY to signal the end of
the cycle. Some systems synchronize or other-
wise delay this signal and then assert RDY to the
processor. If this is done, this RDY signal should
also be fed to the RDYIN input of ViRGE (see Note
3 of Figure 6-2). ViRGE holds read data active
until RDYIN is asserted. If the SRDY signal is not
intercepted, it should be fed to both the processor
RDY input and ViRGE RDYIN input.
6-2 SYSTEM BUS INTERFACES

T1 T2 T3 T4 T5
SCLK
SADS
NOTE 1
SA[31:2]
M/IO
W/R
SAUP
LOCA
SD[31:0] VALID
SRDY
RDYIN NOTE 2
KVLREAD
Figure 6-1. VL-Bus Read Cycle
Notes
1. For one decode wait state (bit 4 of CR40 set to 1), the address is latched on the first clock edge in-
dicated here if bit 3 of CR58 is set to 1. If this bit is cleared to 0, the address is latched on the
second clock edge indicated. The address is always latched on the first clock edge if bit 4 of
CR40 is cleared to 0.
2. The system chip set can delay the RDYIN input by 1 or more cycles. This example assumes a 1
cycle delay, as indicated by the solid line. Note that read data is held valid an extra cycle.
SYSTEM BUS INTERFACES 6-3

T1 T2 T2 T1
SCLK
SD[31:0] VALID
SADS
NOTE 1
SA[31:2]
M/IO
W/R
SAUP
LOCA
NOTE 2
SRDY
RDYIN NOTE 3
KVLWRITE
Figure 6-2. 1 Wait-state VL-Bus Write Cycle
Notes
1. For one decode wait state (bit 4 of CR40 set to 1), the address is latched on the first clock edge in-
dicated here if bit 3 of CR58 is set to 1. If this bit is cleared to 0, the address is latched on the
second clock edge indicated. The address is always latched on the first clock edge if bit 4 of
CR40 is cleared to 0.
2. The wait-state is inserted by setting bit 4 of CR40 to 1 to delay SRDY assertion by 1 cycle from
the assertion of SADS. This is the default value.
3. Data is latched on the rising SCLK edge following assertion of RDYIN.
6-4 SYSTEM BUS INTERFACES

Section 7: Display Memory
ViRGE supports a DRAM-based video frame buff- 7.2 DISPLAY MEMORY REFRESH
er. This section describes the various configura-
tions supported, the functional timing for
ViRGE uses the standard CAS before RAS DRAM
memory accesses and the operation of various
refresh method. The functional timing for this can
register bits that affect memory timing and op-
be found in any standard DRAM data book.
eration. It also describes how access to display
memory is controlled to maximize graphics per-
The number of refresh cycles performed per hori-
formance.
zontal line is determined by bit 6 of CR11. If bit 2
of CR3A is set to 1, the number of refresh cycles
7.1 DISPLAY MEMORY per horizontal line is determined by the setting of
CONFIGURATIONS bits 1-0 of CR3A. Refreshes are performed during
the horizontal blanking period.
ViRGE uses extended data out (EDO) DRAMs for
its frame buffer, which can be either 2 or 4 MBytes 7.3 2-Cycle EDO DRAM SUPPORT
in size. DRAMs can be configured as 256Kx8 or
256Kx16. A Tech Note lists recommended Figure 7-2 shows the functional timing for a 2-cy-
DRAMs. cle EDO mode read cycle. This also shows how
certain parameters for various control signals
For loading reasons, a maximum of 8 DRAM can be adjusted to meet the access time require-
chips can be used for the frame buffer. Table 7-1 ments of a variety of DRAMs. Power-on strapping
shows the supported memory size/chip count sets CR68_1-0 to allow adjustment of the CAS
configurations. and OE signals. MM8204_7 = 0 delays the trailing
edges by the amount indicated by CR68_1-0.
Table 7-1 Memory Size/Chip Count MM8204_7 = 1 delays the entire CAS/OE active
Configurations pulses by the amount indicated in CR68_1-0.
256Kx8 256Kx16 Power-on strapping sets CR68_2 to allow selec-

2 MB 8 4 tion of the RAS low time as 3.5 or 4.5 MCLKs.
After power-up, MM8204_2 can be programmed
4 MB 8
to change this to 2.5 MCLKs. The low time can be
increased 0.5 MCLK via CR58_7. Power-on strap-
Figure 7-1 shows a 4-MByte memory configura-
ping of CR68_3 allows selection of the RAS pre-
tion for a PCI bus configuration. A 4-MByte con-
charge time as 2.5 or 3.5 MCLKs. After power-up,
figuration requires RAS1 to select the 3rd and 4th
MM8204_1 can be programmed to change this to
MByte. ViRGE outputs RAS1 on pin 50 for PCI
1.5 MCLKs. The high time can be reduced 0.5
configurations when bit 6 of SRA is set to 1. RAS1
MCLK via CR58_7. The RAS inactive time can be
is not available for VL-Bus configurations, limit-
delayed 1/2 MCLK via MM8204_10. Note that if
ing memory size to 2 MBytes.
the minimum RAS active time is specified as 3.5
DISPLAY MEMORY 7-1

7-2 DISPLAY MEMORY
PD[63:0]
256Kx16 PD[15:0] 256Kx16 PD[47:32] 256Kx16 PD[15:0] 256Kx16 PD[47:32]
OE0 OE0 OE0 OE0

RAS0 RAS0 RAS1 RAS1
CAS1 CAS4 CAS0 CAS4
CAS0 CAS5 CAS1 CAS5
WE WE WE WE
MA[8:0]
ViRGE
256Kx16 PD[31:16] 256Kx16 PD[63:48] 256Kx16 PD[31:16] 256Kx16 PD[63:48]
OE0 OE0 OE0 OE0

RAS0 RAS0 RAS1 RAS1
CAS2 CAS6 CAS2 CAS6
CAS3 CAS7 CAS3 CAS7
WE WE WE WE
RAM CONTROL 4MB
Figure 7-1. Memory Configurations

2 MBYTES 2nd 2 MBYTES
PCI CONFIGURATIONS ONLY AND SRA_6 = 1 (PIN 50 = RAS1)
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
MCLK
SEE NOTE 1 SEE NOTE 2
RAS0
CAS
SEE NOTE 3
MA[8:0] ROW COLUMN COLUMN
OE0 SEE NOTE 3
PD[63:0] DATA DATA

EDOMEMR
LATCHING
Figure 7-2. 2-cycle EDO Mode Read Cycle
Notes
1. The RAS precharge time can be adjusted via CR68_3, MM8204_1 and CR58_7.
2. The RAS low time for a single column access is adjustable via CR68_2, MM8204_2 and CR58_7.
(The dashed line shows the RAS signal if the second page mode cycle were to be eliminated.)
3. The CAS and OE edges can be adjusted via CR68_1-0 and MM8204_7. CAS and OE edges move
together, but either the trailing edges or entire pulses can be delayed.
DISPLAY MEMORY 7-3

T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
MCLK
SEE NOTE 1 SEE NOTE 2
RAS
CAS
SEE NOTE 3
WE
SEE NOTE 3
PD[63:0] DATA DATA

MMEMWR
Figure 7-3. 2-cycle EDO Mode Write Cycle
Notes
1. The minimum RAS precharge time can be adjusted from 2.5 to 3.5 MCLKs via CR68_3, to 1.5
MCLKs via MM81EC_16, and reduced by 0.5 MCLK via CR58_7.
2. This figure shows a RAS low time for a single column access of 3.5 MCLKs. (The dashed line
shows the RAS signal if the second page mode cycle were to be eliminated.) This RAS active
time can be changed to 4.5 MCLKs via CR68_2 or to 2.5 MCLKs via MM81EC_15 and increased
by 0.5 MCLK via CR58_7.
3. The CAS active (low) time can be stretched via bits 1-0 of CR68 and the WE active time delayed
via bits 4-3 of CR6F.
7-4 DISPLAY MEMORY

T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
MCLK
RAS
CAS
OE
WE
PD[63:0] READ DATA WRITE DATA

EDORMW
Figure 7-4. EDO Mode Write Following Read
MCLKs, the actual minimum for a single EDO DRAM turn-off time guarantees that valid data is
read cycle will be 4.5 MCLKs. latched.
Read data is latched on the rising edge of CAS. Figure 7-3 shows the functional timing for a 2-cy-
An internal CAS is used for this purpose. The cle EDO mode write cycle. The RAS and CAS
internal OE signal rises at the same time, but signals can be adjusted as explained for the read
because of propagation delays, the DRAM will cycle above. Power-on strapping sets CR6F_4-3
not see this edge immediately. This plus the to allow the WE signal to be delayed. MM8204_8
DISPLAY MEMORY 7-5

= 0 delays the trailing edge by the amount indi- 7.4 1-CYCLE EDO DRAM SUPPORT
cated by CR6F_4-3. MM8204_8 = 1 delays the
entire active pulse by the amount indicated by
Bits 3-2 of CR36 are cleared to 00b to indicate that
CR6F_4-3.
1-cycle EDO DRAM operation is being used. This
is the normal mode of operation for ViRGE.
Figure 7-4 shows the functional timing for an
EDO write following a read cycle. This is a 1- wait
The functional timing for 1-cycle EDO reads and
state cycle.
writes is provided by Figure 7-5. The DRAM
drives valid read data after the CAS falling edge
at T5. The chip latches the data on the next falling
CAS edge. Note that a dummy cycle is required
T1 T2 T3 T4 T5 T6 T7 T8 T9
MCLK
RAS
CAS
MA[8:0]
MB[8:0] ROW COL 1 COL 2 COL 3 DUMMY
OE
PD[63:0] RD 1 RD 2 RD 3
WE
PD[63:0] WR 1 WR 2 WR 3
SCEDORW
Figure 7-5. 1-Cycle EDO Mode Read/Write
7-6 DISPLAY MEMORY

at the end to latch the last read. Write data is CPU (i.e., linear addressing) access to memory
latched by the DRAM on the falling edge of CAS. and hardware cursor fetch are not supported with
No dummy cycle is required, so RAS rises one 1-cycle EDO. 2-cycle EDO operation will automat-
cycle earlier than shown in Figure 7-7 and the last ically be used for these functions.
CAS shown in the figure does not occur.
Figure 7-6 shows a write following a read cycle

with 1-cycle EDO operation. A dummy cycle is
added between the read and write.
T1 T2 T3 T4 T5 T6 T7 T8 T9
MCLK
RAS
CAS
MA[8:0]
MB[8:0] ROW COL RD COL WR
OE
WE
PD[63:0] R DAT W DAT

SCEDORMW
Figure 7-6. 1-Cycle EDO Mode Write Following a Read
DISPLAY MEMORY 7-7

7.5 DISPLAY MEMORY ACCESS address line order is sequential, producing the
widest page size. Other orderings may be se-
CONTROL lected to generate a narrower (and deeper) page
size. This can be used to minimize page breaks
A number of processes compete for access to when memory accesses are confined to a small
display memory. These competing processes are region of memory, such as to draw a triangle.
(in decreasing order of access priority):
• Primary Stream High

• RAM refresh
• Secondary Stream High
• Hardware cursor fetch
• LPB
• Read DMA High
• Secondary controller request/grant (S3
Shared Frame Buffer Interface)
• CPU accesses
• S3d Engine accesses
• Primary Stream Low
• Secondary Stream Low
• Read DMA Low
The three processes with high and low priorities

have associated threshold register fields. If the
current count is above the threshold level for a
process, that process is given its low priority.
Once the threshold is reached, the process is
given its high priority.
MM8204_10 = 0 enables servicing of low priority

Streams Processor requests when an S3d Engine
request goes inactive. If MM8204_10 = 1, a low
priority Streams Processor request will only be
serviced after an S3d Engine request has gone
inactive for more than 3 MCLKs.
Each of the processes (except for RAM refresh

and hardware cursor fetch) has an associated
timeout register field. These define the maxi-
mum latencies for giving up the memory bus
when another process requests control. All of
these threshold and timeout fields are described
in the MPC Register section.
7.6 DISPLAY MEMORY ADDRESS

TILING
MM8224_1-0 allow selection of several memory

address tiling schemes. Standard CPU memory
7-8 DISPLAY MEMORY

Section 8: RAMDAC Functionality
For 8 bits/pixel modes, the ViRGE internal 24-bit 8.1 OPERATING MODES
RAMDAC provides three 256 6-bit word color
look-up table (LUT) RAMs feeding three 8-bit
Depending on the setting of CR67_3-2, the follow-
DACs. A clock doubled mode is also provided for
ing operating modes are available:
8 bits/pixel modes. A 24-bit LUT bypass is pro-
vided for 15/16- and 24-bit color modes. The
• Streams Processor Off
block diagram for the internal RAMDAC is shown
in Figure 8-1. • Streams Processor On
• Streams Processor On - secondary
The method of operation depends on whether or stream overlaid on VGA Mode 13 back-
not the Streams Processor is active and the color ground
mode.
With the Streams Processor off (CR67-3-1 = 00b),
data from the video FIFO (memory) is processed
by another ViRGE module and then passed di-
rectly to the RAMDAC. (Figure 8-1 shows the data
VREF RSET
SP
OFF INTERNAL VREF DAC CONTROL
PA[15:8]
HIGH- AND TRUE-COLOR BYPASS
8 RED
24 AR
24 DAC
FIFO 8 GREEN
R LUT 6 MUX AG
DAC
8 B 256X6 8
U ADDRESS 18 BLUE
STREAMS 6 AB
F AND 8 G LUT DAC
PROCESSOR F MASK 256X6
24 8 REG'S
E B LUT 6 COMPARATOR
PA[7:0] R 256X6
INTERNAL RAMDAC BLOCK
18 SENSE
ViRGE
DACBLK
Figure 8-1. Internal RAMDAC Block Diagram
RAMDAC FUNCTIONALITY 8-1

Table 8-1 Color Modes
Color CR67 MAX MAX

Mode Bits 7-4 PA Bits DCLK Pixel Rate Description
0 0000 7:0 94.5 MHz 94.5 MHz 8-bit pseudo-color (LUT) - Default
8 0001 15:0 67.5 MHz 135 MHz Two 8-bit pseudo-color (LUT)
9 0011 15:0 94.5 MHz 94.5 MHz 15-bit high-color ( LUT Bypass)
10 0101 15:0 94.5 MHz 94.5 MHz 16-bit high-color (LUT Bypass)
13 1101 23:0 56.6 MHz 56.6 MHz 24-bit true-color (LUT Bypass)
going through the Streams Processor, but all Each of the 5 color modes is listed in Table 8-1.
Streams Processor functions are bypassed.) This The desired mode is selected by programming
mode is used for those video modes not sup- bits 7-4 of CR67.
ported by the Streams Processor. This includes
all VGA modes except modes D, E, 10, 12 and 13,
all interlaced modes and the clock-doubled 8 8.2.1 8 Bits/Pixel - Mode 0
bits/pixel mode.
Mode 0 is selected by setting bits 7-4 of CR67 to
With the Streams Processor on (CR67_3-2 = 11b), 0000b. In this mode, the low 8 internal pixel
memory data is passed directly to the Streams address bus bits are ANDed with the contents of
Processor. 8 bits/pixel (palettized) data is passed the Pixel Read Mask register (3C6H). The result
directly to the RAMDAC, where it is interpreted of the AND operation selects one of 256 LUT
by the color look-up table and returned to the locations. This results in the output of 6 bits of
Streams Processor as RGB666. This and other color information to each of the DACs.
input data types are converted to RGB888 (if
required) and then sent to the RAMDAC via the
high and true color bypass. 8.2.2 Output-doubled 8 Bits/Pixel -
Mode 8
8.2 COLOR MODES
This mode is selected by setting bits 7-4 of CR67
to 0001b. In this mode, latching of pixel data from
ViRGE internal RAMDAC provides 5 color modes the lower two bytes of the internal pixel data bus
of the following 3 primary types: is based on the pixel clock (VCLK) and output of
pixel data from the latches to the DACs is based
1. 8 bits (low byte of the internal pixel address on an internal clock running at twice the VCLK
bus) are latched each pixel clock and are rate. Either bit 4 or bit 6 of SR15 must be set to 1
used to select a LUT location. when this mode is selected and bit 7 of SR18
2. 16 bits (low two bytes of the internal pixel must also be set to 1.
address bus) are latched each pixel clock.
These select two consecutive LUT loca- This mode processes two pixels per VCLK with a
tions, the data from which is clocked out maximum VCLK rate of 67.5 MHz. This results in
to the DACs at twice the pixel clock rate. an effective pixel output clock rate of 135 MHz.
3. 15 or 16 bits (lower two bytes of the inter-
nal pixel address bus) or 24 bits (all three The internal pixel bus bits are ANDed with the
bytes of the internal address bus) are contents of the Pixel Read Mask register. The
transferred directly to the DACs each pixel result of the AND operation selects one of 256
clock. LUT locations. This results in the output of 6 bits
of color information to each of the DACs.
8-2 RAMDAC FUNCTIONALITY

8.2.3 15/16-Bits/Pixel - Modes 9 and SRDY are not generated by ViRGE for RAMDAC
write accesses. ViRGE generates write cycles to
10 the local RAMDAC and the ISA controller also
generates cycles to an off-board RAMDAC (mir-
These modes are selected by setting bits [7:4] of roring). RAMDAC reads are always from the local
CR67 to 0011b (15 bits/pixel) or 0101b (16 RAMDAC.
bits/pixel). In either case, one pixel is transferred
on the lower two bytes of the internal pixel bus If bit 7 of CR37 is set to 1, ViRGE claims all
each VCLK cycle. This data is sent directly to the RAMDAC read and write cycles (LOCA and SRDY
DACs via the LUT bypass. are generated).
8.2.4 24 Bits/Pixel - Mode 13 8.5 SENSE GENERATION

This mode is selected by setting bits [7:4] of CR67 The internal RAMDAC contains analog voltage
to 1101b. One pixel is transferred to the DACs comparators. These drive the internal SENSE
each VCLK cycle via the LUT bypass. signal active low whenever the output on any of
the AR, AG or AB pins exceeds 330 mV ± 20%.
The Streams Processor must be enabled The state of this internal signal can be read via
(CR67_3-2 = 01b or 11b) In order to display 24 bit 4 of 3C2H. This information can be used to
bits/pixel packed color. See Section 10.3.1 for detect the existence and type of monitor
further information. (color/mono) connected to the system.
8.3 RAMDAC REGISTER ACCESS 8.6 POWER CONTROL

The standard VGA RAMDAC register set (3C6H - ViRGE provides a PDOWN input pin. When a
3C9H) is used to access the internal RAMDAC logic 0 signal is driven to this pin, the RGB analog
registers. CR65_2 must be cleared to 0 to enable outputs are turned off.
MMIO access to these registers.
8.7 RAMDAC SIGNATURE

8.4 RAMDAC SNOOPING ANALYSIS
For PCI bus configurations, setting bit 5 of the
RAMDAC signature analysis is a method of test-
Command configuration space register (Index
ing that the video data pipeline is operating cor-
04H) to 1 causes ViRGE to snoop for RAMDAC
rectly.
writes. This means that ViRGE will write the data
to its local RAMDAC but will not claim the cycle
by asserting DEVSEL. This allows the ISA control- 8.7.1 Signature Analysis Steps
ler to also generate a write cycle to a secondary
RAMDAC. ViRGE always provides the data for
1. Set up the desired mode and eliminate all
RAMDAC reads.
borders (BLANK active during the entire
non-active display period). To do this, set
If bit 5 of the PCI Command register is cleared to
CR33_5 to 1. This does not quite work for
0, ViRGE claims all RAMDAC read and write cy-
the right border, so CR65_4-3 are used to
cles.
delay BLANK by DCLK to produce the de-
sired condition.
Bits 2-0 of CR34 allow handling of PCI master
aborts and retries to be individually enabled or 2. Wait until the VSYNC period. 3DAH_3 = 1 in-
disabled during RAMDAC cycles. dicates active VSYNC. Alternately, set
CR32_4 = 1 to enable interrupts. Set
If power-on strapping bit 12 (CR37, bit 4) is pulled CR11_4 = 1 and CR11_5 = 0 to enable the
low at reset for a VL-Bus configuration, LOCA and VSYNC interrupt. Then poll for 3C2H_7 =
RAMDAC FUNCTIONALITY 8-3

1. (The following two steps must take Bit 7 of each Q value is generated by the following
place during the blanking period. Using logic:
the VSYNC period is safe and this is easier
to detect. The test could also be run be- Q n e x t [ 7 ] = X N O R( XN O R ( I N [ 0 ] , Q[0]),
tween HSYNCs, but these are harder to de- XNOR(IN[3], Q[3]))
tect.)
3. Reset the signature register by toggling Signature output = NOT Q (for the final Q byte)
SR18_1 from low to high to low.
4. Set SR18_0 to 1 to enable clocking of the
signature register.
5. Generate a known and repeatable se-
quence of pixels to the RAMDAC during
the next non-blanking period. Each pixel is
logically mixed with the current signature
register contents and the result is left in
the signature register.
6. Wait for the next VSYNC active, then clear
SR18_0 to 0 to disable clocking of the sig-
nature register.
7. Toggle SR18_2 from low to high to low to
read out red signature data, then read this
data from CR6E.
read out green signature data, then read
this data from CR6E.
read out blue signature data, then read
this data from CR6E.
The expected result for a given test can be manu-

ally calculated from the logic equations used to
update the signature register. These are given
below. In addition, all tests using the same input
data stream should produce the same result.
8.7.2 Signature Generation
A byte of data (IN) is read in logically and mixed

with a byte of all 0’s. The result (Q) is stored and
then mixed with the next IN byte, resulting in a
new Q value (Qnext). This process is repeated
until all data is read in, at which time the final Q
value is inverted. This is the signature that is read
from the signature register.
Bits 0-6 of each Q value are generated by the

following logic:
Qnext[k-1) = XNOR(IN[k], Q[K]), k = 1 to 7
8-4 RAMDAC FUNCTIONALITY

Section 9: Clock Synthesis and Control
ViRGE contains two phase-locked loop (PLL) fre- On power-up, the CLK1 frequency is 44.606 MHz.
quency synthesizers. These generate the DCLK This can be reprogrammed in exactly the same
(video clock) and MCLK (memory clock) signals manner as explained above for the CLK0 frequen-
for the graphics controller block. The DCLK signal cies.
is converted to the VCLK signal by the graphics
controller block. This signal latches pixel data to The PLL M value can be programmed with any
the RAMDAC. integer value from 1 to 127. The binary equivalent
of this value is programmed in bits 6-0 of SR11
for the MCLK and in bits 6-0 of SR13 for the DCLK.
9.1 CLOCK SYNTHESIS The PLL feedback loop frequency from the volt-
age controlled oscillator stage is scaled by divid-
Each PLL scales a single reference frequency ing that frequency by (M+2).
input on the XIN pin. By placing a parallel-reso-
nant crystal between the XOUT output pin and The PLL N value can be programmed with any
the XIN pin, the reference frequency is generated integer value from 1 to 31. The binary equivalent
by an internal oscillator. Alternately, a CMOS- of this value is programmed in bits 15-11 of SR10
compatible clock input can be connected to XIN for the MCLK and in bits 15-11 of SR12 for the
to provide the reference frequency. DCLK. The reference frequency is divided by
(N+2) before being fed to the phase detector
The frequency synthesized by each PLL is deter- stage of the PLL.
mined by the following equation:
The PLL R value is a 2-bit range value that can be
(M+2) programmed with any integer value from 0 to 3.
fOUT = × fREF The R value is programmed in bits 6-5 of SR 10
(N+2)×2R
for MCLK and bits 6-5 of SR12 for DCLK. This
where R = 0, 1, 2 or 3 value codes the selection of a frequency divider
for the PLL output. This is shown Table 9-1.
Programmed PLL M and PLL N values should be
consistent with the following constraints: Table 9-1. PLL R Parameter Decoding
(M+2)fREF R-Range Code Frequency Divider

1. 135MHz ≤ ≤ 270MHz
(N+2) 00 1
01 2
2. min N ≥ 1 10 4
11 8
Note that values used for the parameters are the
integer equivalents of the programmed value. In
The entire PLL block diagram is shown in Figure
particular, the R value is the code, not the actual
9-1.
frequency divisor.
CLOCK SYNTHESIS AND CONTROL 9-1

fREF 1 PHASE CHARGE LOOP 1

(N+2) VCO fOUT
DETECT PUMP FILTER 2R
1
(M+2) KPLLBLK
Figure 9-1. PLL Block Diagram
The following sequence may be followed to ar- ways. If bit 5 of SR15 is cleared to 0, the new DCLK
rive at M and N values for any mode. frequency is loaded by setting bit 1 of SR15 to 1
and then setting bits 3-2 of 3C2H to 11 (if they are
1. Calculate an R which does not violate the not already programmed to this value). Bit 1 of
following constrains: SR15 should be left at a value of 1. Actual loading
will be delayed for a short but variable period of
135MHz < 2R×fOUT ≤ 270MHz time.
2. Start with N1 = 1 and calculate:
The alternate approach to loading the new DCLK
R
frequency is to program bits 3-2 of 3C2 to 11 (if
fOUT × (N+2) ×2 they are not already programmed to this value).
M=[ ]−2
fREF Next, program SR12 and SR13 and then toggle
3. Determine if the following constraint is met: bit 5 of SR15 by programming it to a 1 and then
a 0. This immediately loads the DCLK and MCLK
(M+2) fREF frequencies (no variable delay). For example,
0.995 fOUT < < 1.005 fOUT pseudocode to change DCLK to the frequency
(N+2) 2R specified by PLL parameter values of 34H and
4. If the constraint in step 3 is met, the M and 56H is:
N values used will generate the desired
frequency (within the specified tolerance). 3C2 ⇐ 6FH ; DCLK specified by
If the constrain is not met, repeat steps 2 ; SR12 and SR13
and 3 with N increased by 1 each time un- 3C4 ⇐ 12H ; SR12 index
til the constraint in step 3 is met. Note that 3C5 ⇐ 34H ; SR12 PLL value
multiple combinations of M and N are pos-
3C4 ⇐ 13H ; SR13 index
sible for a given output frequency.
3C5 ⇐ 56H ; SR13 PLL value
3C4 ⇐ 15H ; SR15 index
9.2 CLOCK REPROGRAMMING 3C5 ⇐ RMW ; Use read/modify/write to
; set bit 5 to 1 and leave
ViRGE powers up with a DCLK frequency of ; other bits unchanged
25.175 MHz (standard VGA) and an MCLK fre- 3C5 ⇐ RMW ; Use read/modify/write to
quency of 45 MHz. The DCLK frequency can be ; clear bit 5 to 0 and
changed to 28.322 MHz by setting bits 3-2 of 3C2H ; leave other bits
to 01b and can be changed back to 25.125 MHz ; unchanged
by setting bits 3-2 of 3C2H to 00b. The loading of
the DCLK frequency values requires that bit 1 of Either loading approach should work. The sec-
SR15 be set to 1. ond (immediate loading) approach helps with
system testing since the timing of the load is
All other DCLK frequencies must be generated by predictable. The first approach (via bit 1 of SR15)
re-programming SR12 and SR13. The new PLL has the advantage of separating the loading of
parameter values can be loaded in one of two DCLK from that of MCLK.
9-2 CLOCK SYNTHESIS AND CONTROL

After power-up, all MCLK frequency changes 1. Program SR10/SR11 (MCLK) or SR12/SR13
must be made by re-programming SR10 and (DCLK) to generate the desired frequency.
SR11. If bit 5 of SR15 is cleared to 0, the new 2. Select either MCLK or DCLK for testing via
frequency does not take effect until a 1 has been SR14_3. If DCLK is selected, also ensure
written to bit 0 of SR15. This bit must then be that 3C2_3-2 = 11b to select SR12/SR13 as
cleared to 0 to prevent repeated loading. Actual the source of the DCLK PLL parameters.
loading will be delayed for a short but variable
period of time. 3. Clear the clock synthesizer counter by tog-
gling SR14_4.
As explained above for DCLK, toggling bit 5 of 4. Set SR14_2 = 1 for some exact amount of
SR15 (0,1,0) immediately loads both the DCLK time (∆t).
values in SR12 and SR13 and the MCLK values in 5. Read SR16 (most significant byte) and
SR10 and SR11. SR17 (least significant byte). This is the bi-
nary count of the number of clock cycles
9.3 DCLK CONTROL actually executed.
6. Calculate the expected result (∆t/clock pe-
DCLK is generated by the internal clock synthe- riod) and compare it with the value read in
sizer. VCLK is the signal used to clock pixel data the previous step. The two should agree
into the internal RAMDAC. For most modes of within 2 or 3 counts.
operation, VCLK is generated directly from DCLK
and has the same frequency and phase (neglect-
ing internal gate delays). Bit 0 of CR67 provides
the option to invert DCLK before it becomes
VCLK.
In mode 8, the internal RAMDAC requires two

clocks. The normal internal DCLK frequency is
divided by two via bit 4 of SR15 to provide the
standard VCLK input. Undivided DCLK provides
the other input. This clock can be inverted via bit
6 of SR15.
The internal RAMDAC can also have pixel data

clocked in by an externally provided feature con-
nector clock. For the VESA Advanced Feature
Connector (VAFC), this clock is VCLKI, which is
selected via bit 1 of SRB. For a pass-through
connector, this clock is input on the VCLK pin and
is enabled by asserting the EVCLK signal and by
clearing bit 3 of CR33 to 0.
Certain 4 bits/pixel modes require that DCLK be

halved. This is the case for bit 6 of AR10 set to 1
and bit 4 of CR3A cleared to 0 and is enabled by
setting bit 4 or SR15 to 1 and clearing bit 3 of CR33
to 0.
9.4 CLOCK TESTING
The procedure for testing clock synthesis is:
CLOCK SYNTHESIS AND CONTROL 9-3

Section 10: Streams Processor
The S3 Streams Processor processes data from 2. Secondary Stream - RGB or YUV/YCbCr
the graphics frame buffer, composes it and out- (video) data from another region within
puts the result to the internal DACs for generation the frame buffer
of the analog RGB outputs to the monitor. The 3. Hardware Cursor - 64x64x2 cursor, either
general data flow is shown in Figure 10-1. Note Microsoft or X-11 definition
that the DAC shown in this figure is inside ViRGE.
Regardless of the input formats, the Streams
10.1 INPUT STREAMS Processor creates a composite RGB-24 (8.8.8)
output to the DACs. This means that, for exam-
ple, RGB-8 pseudo-color graphics data can be
The processor can compose data from up to 3 overlaid with true-color-equivalent (24 bits/pixel)
independent streams as shown in Figure 10-1: video data. The result is improved video quality
and/or reduced memory bandwidth require-
ments as compared with systems that require
1. Primary Stream - RGB graphics data both graphics and video to be stored in the same
frame buffer format. In certain modes, the
GRAPHICS
FRAME BUFFER
GRAPHICS BUFFER 0
B
S K
L
C E
E D
GRAPHICS BUFFER 1 A Y
N A MONITOR
L I
D C
I N
I
SPRITE/VIDEO 0 N G
N
G
G
SPRITE/VIDEO 1
STREAMS PROCESSOR
OFF SCREEN/
HARDWARE CURSOR
STREAMS
Figure 10-1. Streams Processor
STREAMS PROCESSOR 10-1

Streams Processor also saves memory band- also be RGB, YUV or YCbCr data written to the
width by eliminating the need to save and restore frame buffer by some video source (CPU, de-
the overlay background since the background coder, digitizer). The format for this data can be
(primary stream) is never overwritten in the any of the following as selected via bits 26-24 of
frame buffer. MM8190.
Streams Processor support is not available for • YCbCr-16 (4.2.2), 16 to 240 input range
clock-doubled 8 bits/pixel modes, interlaced • YUV-16 (4.2.2), -128 to 127 input range
graphics modes and standard VGA modes except
for modes D, E, 10, 12 and 13. • KRGB-16 (1.5.5.5) - The K bit is the color
key.
Bits 3-2 of CR67 specify the Streams Processor • YUV (2.1.1)
mode of operation. If they are cleared to 00b, • RGB-16 (5.6.5)
Streams Processor operation is disabled. They
are programmed to 01b when the primary stream • RGB-24 (8.8.8)
is VGA mode D, E, 10, 12 or 13 (the only sup- • XRGB-32 (X.8.8.8) - X is the ignored up-
ported modes). A secondary stream can be over- per byte.
laid on the primary stream. CR67_3-2 are set to
11b to support an Enhanced mode primary The data can be passed through unscaled or
stream and a secondary stream. scaled up horizontally and vertically by an arbi-
trary amount. YCbCr/YUV data is color space
converted and all data is converted to RGB-24
10.1.1 Primary Stream Input (8.8.8) format.
The primary stream is generated by reading the

RGB pixel data written to the frame buffer by the 10.1.3 Packed True Color
graphics controller. The format for this data can
be any of the following as selected via bits 26-24 In order to display 24 bits/pixel packed color, the
of MM8180. Streams Processor needs to be turned on. The
fo ll ow in g i s a n e xa mple for se tting up
• RGB-8 (Although not shown in Figure 1, 640x480x24 (packed true color). For other resolu-
the frame buffer data is first passed tions, modify the steam’s stride (MM81C8) and
through the internal RAMDACs color the stream width and height (MM81F4) accord-
lookup table (CLUT), where it is palet- ingly.
tized before being passed to the
Streams Processor. 1. Set up required display mode (for exam-
• KRGB-16 (1.5.5.5) - The K bit is the color ple, VESA mode 112 for 640x480x24).
key. 2. Enable the Streams Processor by setting
• RGB-16 (5.6.5) bit 3-2 of CR67 to 01b or 11b.
• RGB-24 (8.8.8) 3. Program the Streams Processor registers
as follows:
• XRGB-32 (X.8.8.8) - X is the ignored up-
per byte.
Register Value
MM8180 06000000
10.1.2 Secondary Stream Input
MM8184 00000000
MM8190 03000000
The secondary stream is generated by reading
pixel data from a separate section of the frame MM8194 00000000
buffer than that used to generate the primary MM8198 00000000
screen. This might be RGB data written by the MM81A0 01000000
graphics controller, such as a sprite used by
MM81C0 00000000
game programmers for moving objects. It could
10-2 STREAMS PROCESSOR

MM81C4 00000000 10.1.4 Hardware Cursor Generation

MM81C8 00000780 (640*3)
MM81CC 00000000 Hardware cursor generation is explained in Sec-
MM81D0 00000000 tion 15. The cursor is overlaid on the Streams
Processor image.
MM81D4 00000000
MM81D8 00000001
MM81DC 40000000 10.1.5 Frame Buffer Organization/
MM81E0 00000000 Double Buffering
MM81E4 00000000
For each stream to be used, the starting location
MM81E8 00000000
(offset) in the frame buffer and the stride (byte
MM81F0 00010001 offset between vertically adjacent pixels on the
MM81F4 027F01E0 (640x480) screen) must be specified. Both the primary and
MM81F8 07FF07FF the secondary streams can be double buffered as
MM81FC 00010001 depicted in Figure 10-1. This means that dupli-
cate frame buffer storage can be provided for
MM8200 00006088 both the primary and secondary image (or for
either one of them). With double buffering, the
The Graphics Engine is now set up for 24 programmer can rapidly switch from one pri-
bits/pixel operation. mary or secondary image to the other. In addi-
tion, having two images allows more time for
Please note that before changing the display updating one image while the other is being
mode, be sure to disable the Streams Processor displayed. Defining the frame buffer organization
by the following steps: and implementing double buffering are done via
the register fields described in Table 10-1. LPB
1. Write 0x0000C000 to MM8200. stands for Local Peripheral Bus.
2. Disable the Streams Processor by resetting
bits 3-2 of CR67 to 00b. The secondary stream can be generated from
data written to the frame buffer via the LPB when
LPB mode is enabled. In this case, the Secondary
Display Buffer Address 0 and the LPB Frame
Buffer Address 0 will normally be the same, as
will the Address 1’s for both the secondary
stream and the LPB input if double buffering is
Table 10-1. Register Fields Used For Specifying Frame Buffer Organization and Double Buffering
Register Field Description

MM81C0_21-0 Primary Display Buffer Address 0. This is the starting address (offset) in the
frame buffer for 1 primary graphics image.
MM81C4_21-0 Primary Display Buffer Address 1. This is the starting address (offset) in the
frame buffer for a second primary graphics image.
MM81C8_11-0 Primary Stream Stride. This is the byte offset in the frame buffer from a pixel in
a given primary image display line to the pixel directly below it on the next
display line. The stride must be the same for both primary buffers.
MM81CC_0 Primary Stream Buffer Select
0 = Primary frame buffer starting address 0 (MM81C0_21-0) used for primary
stream
1 = Primary frame buffer starting address 1 (MM81C4_21-0) used for primary
stream

Table 10-1. Register Fields Used For Specifying Frame Buffer Organization and Double Buffering
(continued)
MM81CC_2-1 Secondary Stream Buffer Select
00 = Secondary frame buffer starting address 0 (MM81D0_21-0) used for the
secondary stream
secondary stream
secondary stream and LPB frame buffer starting address 0 (MMFF0C_21-0)
used for the LPB input stream OR secondary frame buffer starting address
1 (MM81D4_21-0) used for the secondary stream and LPB frame buffer
starting address 1 (MMFF10_21-0) used for the LPB input stream. Which
alternative applies is determined by LPB starting address register selected
by bit 4 of this register.
secondary stream and LPB frame buffer starting address 1 (MMFF0C_21-0)
used for the LPB input stream OR secondary frame buffer starting address
1 (MM81D4_21-0) used for the secondary stream and LPB frame buffer
starting address 0 (MMFF10_21-0) used for the LPB input stream. Which
alternative applies is determined by the LPB starting address register
selected by bit 4 of this register.
MM81CC_4 LPB Input Buffer Select
0 = LPB frame buffer starting address 0 (MMFF0C_21-0) used for LPB input
1 = LPB frame buffer starting address 1 (MMFF10_21-0) used for LPB input
MM81CC_5 LPB Input Buffer Select Loading
0 = The value programmed in bit 4 of this register takes effect immediately
1 = The value programmed in bit 4 of this register takes effect at the end of the
next frame (completion of writing all the data for a frame into the frame
buffer)
MM81CC_6 LPB Input Buffer Select Toggle
0 = End of frame (completion of writing all the data fro a from into the frame
buffer) has no effect on the setting of bit 4 of this register
1 = End of frame causes the setting of bit 4 of this register to toggle
MM81D0_21-0 Secondary Display Buffer Address 0. This is the starting address (offset) in the
frame buffer for 1 secondary graphics or video image.
MM81D4_21-0 Secondary Display Buffer Address 1. This is the starting address (offset) in the
frame buffer for a second secondary graphics or video image.
MM81D8_11-0 Secondary Stream Stride. This is the byte offset in the frame buffer from a
pixel in a given secondary image display line to the pixel directly below it on
the next display line. The stride must be the same for both secondary buffers.
MMFF0C_21-0 LPB Frame Buffer Address 0. This is the starting address (offset) in the frame
buffer for one image buffer into which is written data from the LPB. The
secondary stream can be generated from this buffer.
MMFF10_21-0 LPB Frame Buffer Address 1. This is the starting address (offset) in the frame
buffer for a second image buffer into which is written data from the LPB. The
secondary stream can be generated from this buffer.
MM81CC_6 LPB Input Buffer Select Toggle
0 = End of frame (completion of writing all the data fro a from into the frame
buffer) has no effect on the setting of bit 4 of this register

used. The various LPB control bits described in and uses line replication. The 2x scaling allows a
Table 10-1 allow complete hardware control of 320x240 image (as used by many games) to be
the capture and display of video data using either displayed at a full-screen 640x480 resolution.
single or double buffering.
10.2.2 Secondary Stream Processing

10.2 INPUT PROCESSING
The secondary stream input format is converted
Different processing options are available for the (if required) to RGB-24 (8.8.8) format. F o r
primary and secondary input streams. These are YUV/YCbCr inputs, the required color space con-
explained next. version is automatically performed. Before con-
version, the data can be passed through unscaled
or scaled up horizontally and/or vertically by ar-
10.2.1 Primary Stream Processing bitrary factors. Horizontal scaling uses filtering
for interpolation. Vertical scaling uses line repli-
The primary stream input RGB format is con- cation. The register fields involved in scaling up
verted (if required) to RGB-24 (8.8.8) format. Each the secondary stream are described in Table 10-
color byte is padded as required with low order 2. Figure 10-2 graphically describes the various
zeros. After this conversion, the data can be fields.
passed through unscaled or scaled up horizon-
tally and vertically by a factor of 2 via bits 30-28 For example, assume a 10x10 window that is to
of MM8180. For MM8180_30-28 = 001, horizontal be scaled up horizontally by a factor of 2.5. The
scaling is done via replication. If these bits are filter characteristics are set for bi-linear (2x to 4x
programmed to 010, horizontal scaling is done stretch). The starting line width is 10 pixels and
using interpolation. Vertical scaling is automatic the ending line width is 25 pixels. The DDA hori-
SCREEN START X0
(MM81F0_26-16)
WINDOW START X1
(MM81F8_26-16)
WINDOW HEIGHT H0
WINDOW HEIGHT H1 AFTER

BEFORE SCALING
SCALING (MM81FC_10-0)
X1-X0
WINDOW WIDTH W0
BEFORE SCALING
WINDOW WIDTH W1 AFTER

SCALING (MM81FC_26-16)
SPWINDEF
Figure 10-2. Screen Definition Parameters

Table 10-2. Register Fields Used For Scaling Up the Secondary Stream

MM8190_30-28 Filter Characteristics
000 = Secondary stream (pass-through)
001 = Secondary stream, linear, 0-2-4-2-0, for X stretch
010 = Secondary stream, bi-linear, for 2X to 4X stretch
011 = Secondary stream, linear, 1-2-2-2-1, for 4X stretch
This selection applies only to horizontal scaling.

MM8190_11-0 DDA Horizontal Accumulator Initial Value. Value = 2 (W0-1) - (W1-1), where
W0 is the line width in pixels before scaling and W1 is the line width after
scaling. This is a signed value.
MM8198_10-0, K1 Horizontal Factor. Value = W0-1, where W0 is the line width in pixels before
scaling. This is a signed value.
MM8198_26-16 K2 Horizontal Factor. Value = W0-W1, where W0 is the line width in pixels
before scaling and W1 is the line width after scaling. This is a signed value.
MM81E0_10-0, K1 Vertical Factor. Value = [height (in lines) of the initial output window
(before scaling)] -1. The initial output window height is the vertical resolution
of the data written to the frame buffer and is shown as H0 in Figure 10-2.
MM81E4_10-0, K2 Vertical Factor. Value = 2’s complement of [height (in lines) of the initial
output window (before scaling)] - [height (in lines) of the final output window
(after scaling)]
The initial output window height is the vertical resolution of the data written
to the frame buffer and is shown as H0 in Figure 10-2. The final value is the
same height value that is programmed in MM81FC_10-0 and is shown as H1 in
Figure 10-2. This value is then the 2’s complement of (H1 - H0).
MM81E8_11-0, DDA Vertical Accumulator Initial Value. Value = 2’s complement of [height (in
lines) of the output window after scaling] -1. This is the same height value that
is programmed in MM81FC_10-0 and is shown as H1 in Figure 10-2.
zontal accumulator initial value is 2 (10-1) - (25-1) ple, for a video window overlaying the
= -6. The K1 horizontal factor is 10-1 = 9. The K2 graphics screen. Note that this mode will
horizontal factor is 10-25 = -15. Programming not work for the case where the user
these parameters with these values results in a needs to pull down a graphics window
2.5x horizontal stretch for the secondary stream over the video since the graphics window
window. is defined as being under the video win-
dow. Color keying (number 5 in this list)
must be used for this purpose.
10.3 COMPOSITION/OUTPUT
2. MM81A0_26-24 = 001b - Primary stream
overlaid on the secondary stream in an
A variety of output types can be composed from opaque rectangular window. This could
the streams described above. The compose be used, for example, to provide graphics
modes are: captions for a video window. The video is
not visible behind the rectangular graph-
1. MM81A0_26-24 = 000b - Secondary stream ics window.
overlaid on the primary stream in an
opaque rectangular window. This is the 3. MM81A0_26-24 = 010b - Secondary stream
default mode and can be used, for exam- blended with the primary stream on a
pixel by pixel basis within the secondary

stream window. This is used to provide a integer to ensure that the first pixel not fetched
dissolve between two scenes. in inside the opaque overlay window. Note that
4. MM81A0_26-24 = 011b - Secondary stream if the secondary stream is in the background,
blended with the primary stream on a then the value is (X0 - X1) x bytes per pixel/8,
pixel by pixel basis within the secondary again rounded up.
stream window. This is used to provide a
fade between two scenes. Pixel fetching must start again before or at the
last pixel position of the opaque overlay window.
5. MM81A0_26-24 = 101b - Secondary stream Using the terms in Figure 10-2, this position is (X1
overlaid on the primary stream in an ir- - X0) + W1, with W1 programmed in MM81FC_26-
regular window. This requires a color key. 16 (secondary stream is on top). Converting to
This would be used, for example, for quadwords, the value is [(X1 - X0) + W1] x bytes
game sprites. Only the graphics area be- per pixel/8. If the result is a fraction, the result is
hind the sprite shape would be covered truncated to the next lowest integer (minus 1)
up. and programmed in MM81DC_28-19. Note that if
6. MM81A0_26-24 = 110b - Primary stream the secondary stream is in the background, then
overlaid on the secondary stream in an ir- (X0 - X1) is used and W1 is the value in
regular window. This requires a MM81F4_26-16 (primary stream is on top).
color/chroma key. This case allows, for ex-
ample, graphics text to overlay video with Opaque overlay control cannot be used with key-
the video appearing around and even in- ing or blending and should never be enabled
side of the text characters. when one of these modes is being used.
10.3.1 Opaque Rectangular 10.3.2 Blending

Overlaying
These modes are items 3 and 4 in the compose
These modes are items 1 and 2 in the compose modes list. The blender accepts the primary and
modes list. When one of these modes is used, the secondary pixel streams and blends them with
programmer can invoke a feature called opaque an arithmetic weighting. The result is then over-
overlay control. This is enabled by setting laid with the cursor stream. Both blender inputs
MM81DC_31 to 1. If MM81A0_26-24 = 000b (sec- are RGB 8.8.8 from the outputs of the primary
ondary stream on top), then MM81DC_30 must stream interpolator and secondary stream color
be cleared to 0 to also specify secondary stream space converter. Note that blending makes sense
on top. Similarly, If MM81A0_26-24 = 001b (pri- only when both streams are defined. In addition,
mary stream on top), then MM81DC_30 must be when blending is selected, the concept of back-
set to 1 to also specify primary stream on top. The ground/foreground or top and bottom window
next step is to define when to stop fetching pixels has no meaning.
for a line from memory and when to restart
fetching them. The goal is to not fetch those Two types of blending are provided: dissolve and
pixels in the background window that are cov- fade.
ered up by the opaque rectangular overlay win-
dow, thus saving memory bandwidth. When dissolve is chosen, the output pixels are
generated using the following equation:
The first pixel that does not need to be fetched is
at horizontal position X1 shown in Figure 10-2. [Pp x Kp + Ps x (8 - Kp)]/8
This is programmed in MM8158_26-16. The start-
ing pixel position for the background (X0) is Pp and Ps are the primary and secondary stream
programmed in MM81F0_26-16. The difference pixel colors respectively, both RGB 8.8.8. Kp is
(X1 - X0) must be converted into quadwords and the primary stream weighting factor. It is a 3-bit
then programmed in MM81DC_12-3. The value is value programmed in MM81A0_12-10. This
(X1 - X0) x bytes per pixel/8. If the result is a weight value is applied to each of the three color
fraction, it is rounded up to the next highest values for the pixel. If Kp = 0, only the secondary

stream is displayed. As Kp is increased, more of the most significant bit of each pixel value is used
the pixel color from the primary stream is as a color key as long as MM8184_28 is cleared
blended into output. At the maximum (Kp = 7 or to 0. When the most significant pixel bit is a 0, the
111b), 7/8ths of the color will be due to the pri- other stream pixel is displayed.
mary stream and 1/8th will be due to the secon-
dary stream. Therefore, by starting with the For other RGB input types (as specified by
primary stream only, then overlaying the secon- MM8180_26-24), a color key must be defined.
dary stream with Kp values decreasing from 7 to This is done by programming MM8184_23-0 with
0, the overlay window can be dissolved gradually a specific RGB 8.8.8 color value. MM8184_28
from primary stream to secondary stream. Note must be set to 1 to enable use of this value. The
that when the Kp value is reprogrammed, its new number of bits to compare for each color is
value does not take effect until the next VSYNC, specified in MM8184_26-24. If there is a color
so it can be reprogrammed during frame display match with the keyed stream pixel, the corre-
without disruptive effects. sponding other stream pixel is displayed.
When fade is chosen, the output pixels are gen- If the secondary stream input format is YUV or
erated using the following equation: YCbCr, the chroma key is specified as a range of
color values. The lower bound value is defined in
[Pp x Kp + Ps x Ks]/8, where Kp + Ks must be ≤ 8. MM8184_23-0. The upper bound value is defined
in MM8194_23-0. If the secondary stream pixel
Ks is the secondary stream weighting factor. It is color value falls within this range (inclusive of the
a 3-bit value programmed in MM81A0_4-2. This lower and upper bounds), the Streams Processor
weight value is applied to each of the three color displays the corresponding pixel from the pri-
values for the pixel. Note that when fading is mary stream. If the secondary stream pixel color
selected, the default values for Kp and Ks (both is outside this range, the secondary stream pixel
0) result in a color value of 0. As with Kp, when is displayed.
the Ks value is reprogrammed, its new value
does not take effect until the next VSYNC.
10.3.4 Window Location
10.3.3 Color/Chroma Keying The starting X,Y coordinates and window size for
the primary stream are specified in MM81F0 and
These modes are items 5 and 6 in the compose MM81F4 respectively. The starting X,Y coordi-
modes list. Keying is a way of selecting on a pixel nates and window size for the secondary stream
by pixel basis which stream will be displayed. are specified in MM81F8 and MM81FC respec-
Color keying is used when the stream source is tively.
in RGB format (graphics). This is always the case
for the primary stream. Chroma keying is used
when the stream source is YUV or YCbCr (video). 10.4 STREAMS FIFO CONTROL
The secondary stream source can be either
graphics or video, so either color or chroma key- The streams FIFO can be reconfigured to opti-
ing might be used. If 81A0_26-24 (compose mize performance for various operating modes.
mode) = 101b and MM8184_28 = 1, the color key The FIFO is 24 8-byte slots deep. By program-
is compared with the primary stream pixel. If ming MM8200_4-0, the FIFO can be reconfigured
there is a match, the corresponding secondary to assign all 24 slots to either the primary or
stream pixel is displayed. If 81A0_26-24 = 110b secondary stream. Allocations of 16-8 and 12-12
and MM8184_28 = 1, the color or chroma key is slots between the two streams are also possible.
compared with the secondary stream pixel. If As an example, if only a primary stream is being
there is a match, the corresponding primary displayed, optimal performance is generated by
stream pixel is displayed. assigning all 24 FIFO slots to the primary stream.
If the input format is KRGB-16 (1.5.5.5), selected No matter what the allocation, FIFO thresholds
when MM8180_26-24 or MM8190_26_24 = 011b, must be specified for the primary and secondary

streams. This is done via MM8200_16-12 for the

primary stream and MM8200_10-6 for the secon-
dary stream. When the FIFO empties to the
threshold level, an internal signal is generated
requesting the memory controller to begin refill-
ing the FIFO. The programmed threshold levels
must never exceed the corresponding FIFO
depths. The optimal settings for the threshold
levels will be system and operating mode de-
pendent and will have to be determined by trial
and error.

LPB operation is enabled when bit 0 of MMFF00 • Host Video Data Pass-through. This al-
is set to 1. LPB clocking with LCLK must also be lows decimation of 32-bit CPU data be-
enabled by setting bit 24 of MMFF00 to 1. The LPB ing written to the frame buffer.)
function provides the following: • LPB Feature Connector (glueless 8-bit bi-
directional or 16-bit VAFC)
• S3 Scenic Highway interface to the
Scenic/MX2 MPEG Audio/Video Decoder • 4-bit General Input Port and 4-bit Gen-
(glueless, bi-directional) eral Output Port
• Scenic Highway interface to the Philips® The LPB mode also provides the support required
video digitizers (glue logic is required to for DDC2 monitor communications. This, the fea-
convert 16-bit output to 8-bit ViRGE in- ture connector interfaces and the General In-
put for VL-Bus configurations. However, put/Output Port are described in Section 12.
the Scenic/MX2 has a glueless SAA7100
interface which can be used to provide The internal block diagram for the LPB is shown
the 16- to 8-bit conversion). A 16-bit data in Figure 11-1.
interface is available on ViRGE for PCI
configurations.
LPB
LPB DATA/ADDRESS 8
HOST REGISTERS
32 PORT
32 8 8 (VL)
LPB 8x32 EXTERNAL
OUTPUT FIFO 16 (PCI) DEVICE
32
VIDEO FIFO 8/16
TO MEMORY 8x32
INTERFACE 32/64
8x32
DECIMATION
TO MEMORY MEMORY ADDRESS KVBLOCK

INTERFACE GENERATION
Figure 11-1. LPB Internal Block Diagram
LOCAL PERIPHERAL BUS 11-1

11.1 Scenic/MX2 INTERFACE 0 for a memory access. Bits 3-0 are bits 19-16 of
the address. The second byte is bits 15-8 of
MMFF14 and the third byte is bits 7-0. The data
The hardware interface to the Scenic/MX2 is
immediately follows in four byte writes. Data is
shown in Figure 11-2.
written in the opposite byte order to that for the
address, i.e., least significant byte (bits 7-0) first
The Scenic/MX2 interface is selected by setting
and most significant byte (bits 31-24) last. ViRGE
MMFF00_3-1 to 000b. This interface is fully bi-di-
then deasserts VREQ/VRDY. The Host repeats the
rectional. Scenic/MX2 registers can be accessed,
above sequence for another write if required.
compressed data sent and decompressed video
data received.
If the Scenic/MX2 is not ready to receive data, it
drives its CREQ/CRDY signal low during the A0-0
11.1.1 Scenic/MX2 Register/Memory byte (LSB) of the address phase. ViRGE then
delays sending the data until the Scenic/MX2
Access raises CREQ/CRDY. This is depicted in Figure
11-4.
To read/write a Scenic/MX2 register or private
memory location (other than to transfer com- Figure 11-5 shows a Scenic/MX2 register/mem-
pressed data), the LPB Direct Read/Write Address ory read when the Scenic/MX2 is ready to pro-
register (MMFF14) is written. The new regis- vide data. This is indicated by the Scenic/MX2
ter/memory data is then written to MMFF18. For holding the CREQ/CRDY high throughout the cy-
a write access, this write triggers the sequence cle. The three upper bits of the first address byte
shown in Figure 11-3 if the Scenic/MX2 is ready are 001 to define a read.
to receive the data (CREQ/CRDY remains high).
One cycle after ViRGE asserts its VREQ/VRDY If the Scenic/MX2 is not ready to provide data, it
signal, it sends the address in three byte writes. drives its CREQ/CRDY signal low during the ad-
The first byte is composed of bits 23-16 of dress phase. ViRGE then waits until the Sce-
MMFF14. The three upper bits are 000b to define
this as a write. Bit 4 is 1 for a register access and
Scenic/MX2 ViRGE
LCLK LCLK
LD[7:0] LD[7:0]
VREQ/VRDY VREQ/VRDY
CREQ/CRDY CREQ/CRDY
ENABLE ENFEAT
VVCTOK
Figure 11-2. ViRGE to Scenic/MX2 Hardware Interface
11-2 LOCAL PERIPHERAL BUS

LCLK
CREQ/CRDY
VREQ/VRDY
LD[7:0] A0-2 A0-1 A0-0 D0 D1 D2 D3

CPRWRY
Figure 11-3. Scenic/MX2 Write (Scenic/MX2 Ready)
LCLK
CREQ/CRDY
VREQ/VRDY
LD[7:0] A0-2 A0-1 A0-0 D0 D1 D2 D3

CPRWRN
Figure 11-4. Scenic/MX2 Write (Scenic/MX2 Not Ready)
LCLK
CREQ/CRDY
VREQ/VRDY
LD[7:0] A0-2 A0-1 A0-0 D0 D1 D2 D3

CPRRY
Figure 11-5. Scenic/MX2 Read (Scenic/MX2 Ready)
LCLK
CREQ/CRDY
VREQ/VRDY
LD[7:0] A0-2 A0-1 A0-0 D0 D1 D2 D3

CPRRN
Figure 11-6. Scenic/MX2 Read (Scenic/MX2 Not Ready)

nic/MX2 raises CREQ/CRDY and provides register provided for this FIFO. Writes to any of these
data. This is depicted in Figure 11-6. addresses are directed to the FIFO.
To prevent data starvation and deal with request MMFF00_17-16 are programmed to specify the
contention, the following protocol is followed. number of doublewords of data to burst to the
Scenic/MX2. A write to the output FIFO then
• No transaction can be initiated if the bus initiates a compressed data write to the Sce-
is active nic/MX2. This is depicted in Figure 11-7 for a
• There is one dead cycle on the bus fol- burst count of 2 (MMFF00_17-16 = 01b) for the
lowing all transactions case where the Scenic/MX2 is ready to receive
the data. The address and first doubleword are
• One device may not initiate a transac- transferred exactly as for a register/memory
tion until the second cycle following the write. Following doublewords in the burst are
completion of a transaction initiated by each separated by one dead cycle. The address
the other device has no meaning except for the upper three bits,
• Neither device may initiate a transaction which are forced to 110b by hardware to specify
until the third cycle following the com- a compressed data transfer. Note that burst
pletion of a transaction initiated by itself writes that end because the FIFO is empty (as
• If CREQ/CRDY and VREQ/VRDY are both opposed to the maximum burst count being
driven low on the same cycle (request reached) hold VREQ/VRDY low for one more cy-
contention), CREQ/CRDY (the Sce- cle than is shown in Figure 11-7.
nic/MX2) wins.
The Scenic/MX2 cannot accept a burst larger than
eight doublewords. If MMFF00_17-16 are pro-
11.1.2 Scenic/MX2 Compressed Data grammed to 11b (burst all) and eight double-
Transfer words are loaded into the FIFO, software must
ensure that the FIFO is empty before loading
more data into the FIFO.
ViRGE has an output FIFO for handling the trans-
fer of compressed video data from the Host to the A compressed data transfer when the Sce-
Scenic/MX2 (see Figure 11-1). The Host must first
nic/MX2 is not ready to receive data is almost the
check the number of empty slots (MMFF04_3-0), same as a register write for the same circum-
then send no more than this many doublewords stances (see Figure 11-4). The only difference is
(32 bits) of compressed data to the FIFO. An eight
that after the Scenic/MX2 returns its CRDY signal,
doubleword address range (FF40H - FF5CH) is
LCLK
CREQ/CRDY
VREQ/VRDY
LD[7:0] A0-2 A0-1 A0-0 D0-0 D0-1 D0-2 D0-3 D1-0 D1-1 D1-2 D1-3
CPDTDY
Figure 11-7. Compressed Data Xfer (Scenic/MX2 Ready)

LCLK
CREQ/CRDY
VREQ/VRDY
LD[7:0] A0-2 A0-1 A0-0 D0-0 D0-1 D0-2 D0-3

CPSTOP
Figure 11-8. Scenic/MX2 Stopping a Compressed Xfer

additional doubleword packets may be burst to • ViRGE is placed in Scenic/MX2 mode
the Scenic/MX2 as shown in Figure 11-7. (MMFF00_3-1 = 000b).
• One or two frame buffer starting ad-
The Scenic/MX2 can stop a compressed data dresses are defined (MMFF0C,
transfer by pulling CREQ/CRDY low for one (and MMFF10). One is required. The second
only one) cycle during byte three of any double- is required for double buffering.
word. This is shown in Figure 11-8.
• The horizontal and vertical decimation
An output FIFO empty interrupt can be enabled registers are programmed (MMFF2C,
by setting MMFF08_17 to 1. The status is read via MMFF30). This is optional.
bit 1 of this same register. • The line stride is programmed
(MMFF34_10-0). This is not required if
HSYNCs are not being sent.
11.1.3 Scenic/MX2 Video Capture
ViRGE signals its readiness to accept data by
The following setup is done for Scenic/MX2 driving VREQ/VRDY high. This is done automat-
video capture: ically when ViRGE does not need to drive this
LCLK
CREQ/CRDY
VSYNC HSYNC CPVSHS
Figure 11-9. Scenic/MX2 VSYNC and HSYNC Protocols

signal low such as to initiate a register access or shown in Figure 11-10. ViRGE assumes data has
to indicate an LPB video FIFO full state. The begun any time CREQ/CRDY is held low for more
Scenic/MX2 responds by sending a VSYNC than two cycles. When the Scenic/MX2 is sending
(CREQ/CRDY low for one cycle) followed by an the last byte, it drives CREQ/CRDY high. The
HSYNC (CREQ/CRDY low for two cycles). This is Scenic/MX2 must always send data in 4-byte
shown in Figure 11-9. As indicated in the figure, packets. If it has fewer to send for the last packet,
the time between VSYNC and HSYNC is variable. it must pad the transmission with dummy writes
The HSYNC sequence occurs after each line, but to create a 4-byte packet.
may not occur before the first line, depending on
how the Scenic/MX2 is programmed. Figure 11-10 shows what happens when ViRGE
is ready to receive all the data. If ViRGE cannot
After the VSYNC/HSYNC sequence, the Sce- accept more data, such as when its LPB video
nic/MX2 can pull CREQ/CRDY low at any time and FIFO is full, it drives its VREQ/VRDY signal low
begin sending data three clocks later. This is during the first byte phase of a 4-byte packet. All
LCLK
CREQ/CRDY
VREQ/VRDY
LD[7:0] D00 D01 D02 D03 D10 Dn1 Dn2 Dn3
CPVCAP
Figure 11-10. Scenic/MX2 Video Input (ViRGE Ready)
LCLK
CREQ/CRDY
VREQ/VRDY
LD[7:0] D Dn0 Dn0

CPVCAPNR
Figure 11-11. Scenic/MX2 Video Input (ViRGE Not Ready)

bytes starting with this one are rejected by ViRGE The functional timing for converting the
and must be resent by the Scenic/MX2 after SAA7110 16-bit video output to the 8-bit input
ViRGE drives its VREQ/VRDY signal high again. required by the LPB in a VL-Bus configuration is
This is depicted in Figure 11-11, where the Dn0 shown in Figure 11-13.
byte, which is the first byte of the nth 4-byte
packet, is rejected. When ViRGE can accept more In Video 16 mode (MMFF00_3-1 = 001b), which is
data, it drives VREQ/VRDY high. The Scenic/MX2 available only for PCI configurations, no data
drives CREQ/CRDY high (two cycles later) and conversion is required. Y[7:0} connects to LD[7:0]
then drives it low when it is ready to resend the and UV[7:0] connects to LD[15:8]. LLC2 connects
data. The resend of Dn0 and subsequent bytes to LCLK and LLC is not connected.
starts two cycles later.
As an alternative, the Scenic/MX2 provides a
When ViRGE receives an HSYNC from the Sce- glueless interface to the SAA7110. In this case,
nic/MX2, it adds the line offset (MMFF34_10-0) to the Scenic/MX2 handles the 16-bit to 8-bit con-
the previous line starting address and starts writ- version and also provides the I2C interface to the
ing the next data at that location. In this way, for SAA7110. ViRGE then receives the video data,
example, it can transfer 640-byte lines into a clock and controls from the Scenic/MX2. The
frame buffer configured for 1024-byte lines. If Scenic/MX2 documentation describes this inter-
HSYNCs are not sent, memory will be written in face.
a contiguous manner.
11.2.1 I2C Register Interface

11.2 DIGITIZER INTERFACE
SAA7110 registers are programmed via a serial
The hardware interface to the Philips digitizer in I2C interface. This interface is described in Sec-
Video 8 In mode (MMFF00_3-1 = 010b) is shown tion 12.
in Figure 11-12. This section describes the inter-
face to the Philips SAA7110 digitizer.
SAA7110 ViRGE
Y[7:0]
LD[7:0]
UV[7:0]
LLC2
LLC LCLK
HS HS
VS VS
SDA SPD
SCK SPCLK
VVDTOK
Figure 11-12. ViRGE to SAA7110 Digitizer Interface

LLC (27 MHZ)
LLC2 (13.5 MHZ)
Y[7:0] Y0 Y1 Y2
UV[7:0] U01 V01 U23
LD[7:0] Y0 U01 Y1 V01 Y2 U23

K2V16TO8
Figure 11-13. 16- to 8-bit Video Data Conversion
11.2.2 SAA7110 Video Input • The correct vertical and horizontal sync
polarities are specified (MMFF00_9, 10).
The following setup is done for SAA7110 video • One or two frame buffer starting ad-
input: dresses are defined (MMFF0C,
MMFF10). One is required. The second
• ViRGE is placed in Video 8 In mode is required for double buffering.
(MMFF00_3-1 = 010) or Video 16 mode • The horizontal and vertical decimation
(MMFF00_3-1 = 001b) for PCI configura- registers are programmed (MMFF2C,
tions. MMFF30). This is optional.
• Byte swapping is disabled by setting • The video input window size (height in
MMFF00_6 to 1. lines and width in pixels) is pro-
grammed in MMFF24.
LCLK
VS
HS
LD[7:0] D0 ... Dn-2 Dn-1 Dn CPV8CAP
SKIPPED LINE HO LW
Figure 11-14. Video 8 In or 16 Mode Input

• The video data horizontal and vertical 11.4 LPB-ENABLED PIN

offsets are programmed in MMFF28.
ASSIGNMENTS
• The line offset (stride) is programmed
(MMFF34_10-0). The pin assignments when the various LPB
modes are enabled are shown in Table 11-1. Note
The SAA7110 then sends video data as shown in that some functions are available only in PCI
Figure 11-14. In this figure, both VSYNC (VS) and configurations. These have (PCI) next to the pin
HSYNC (HS) have active high polarity. The verti- number.
cal offset (MMFF28_24-16) is 1, meaning the first
line is skipped. The horizontal offset HO
(MMFF28_11-0) is 1, meaning that the first data
starts one clock after the second HS goes low. HS
goes high again some time after the last byte of
the line, whose position is specified by the line
width (LW) programmed in MMFF24_11-0. The
widths of the VS and HS pulses shown may vary.
Alternate frames of the video input can be dis-

carded (not written to memory) by setting bit 5
of MMFF00 to 1.
11.3 HOST PASS-THROUGH
W h e n p a ss - t h r o u g h m o d e i s e n a bl e d
(MMFF00_3-1 = 100b), the CPU can write 32-bit
data to the output FIFO and have this data passed
directly to the decimation block (bypassing the
LPB bus). The data are sent exactly as for com-
pressed video data to an MPEG decoder. The
data will then be decimated according to the
programming of MMFF2C (horizontal) and
MMFF30 (vertical) and then passed to the video
FIFO to be written to display memory. This path
is shown in Figure 11-1.
When the Host sends an HSYNC (MMFF00_12 =

1) or VSYNC (MMFF00_11), the decimation reg-
isters are re-loaded. Therefore, the Host must
ensure that at least 5 clocks pass between the
sync and the start of data to allow time for this
reloading.
When pass-through is used in LPB mode, bit 24

of MMFF00 provides the option of using SCLK to
clock the LPB function.
Pass-through is not supported if big-endian ad-

dressing is being used.

Table 11-1. LPB-Enabled Pin Assignments
Video 16 or 8 In
Scenic/MX2 MMFF00_3-1 = 001
Pin # MMFF00_3-1 = 000 MMFF00_3-1 = 010
146 LD0 LD0
147 LD1 LD1
148 LCLK LCLK
154 LD2 LD2
155 LD3 LD3
174 LD4 LD4
175 LD5 LD5
176(PCI) NO FUNCTION NO FUNCTION
184 LD6 LD6
185 (PCI) NO FUNCTION LD8 (Video 16)
202 LD7 LD7
203 VREQ/VRDY HS
204 CREQ/CRDY VS

Section 12: Miscellaneous Functions
This section explains how ViRGE interfaces to the strapping bit 4 (CR36, bit 4) must be pulled low
video BIOS ROM and feature connector. Green to disable BIOS accesses. For this configuration,
PC support, the General I/O Ports, the serial com- ROMCS is not required. Bits 1-0 of SR1C can be
munications port and interrupt generation are set to 11, making pin 153 function as a second
also described. General Output Port bit instead of as ROMCS. For
PCI configurations, bit 0 of the BIOS ROM Base
Address register (Index 30H) is cleared to 0 to
12.1 VIDEO BIOS ROM INTERFACE disable BIOS accesses.
The video BIOS ROM contains power-on initiali-

zation, mode setup, and video data read/write 12.1.2 BIOS ROM Hardware Interface
routines. The video BIOS can be part of the sys-
tem ROM or it can be implemented separately. A separate implementation of the video BIOS for
a PCI configuration is shown in Figure 12-1. The
GD[7:0] and GA[15:0] signals are multiplexed on
12.1.1 Disabling BIOS ROM Accesses PD pins. Therefore, the BIOS ROM must be shad-
owed immediately after reset and BIOS access
If the video BIOS is integrated with the system disabled to prevent interference with graphics
BIOS in a VL-Bus configuration, then power-on operation.
ViRGE BIOS ROM
GD[7:0] D[7:0]
GA[15:0] A[15:0]
ROMEN OE
CE
VPCIROM
Figure 12-1. BIOS ROM PCI Configuration Interface
MISCELLANEOUS FUNCTIONS 12-1

VESA
LOCAL BUS
SA[31:2]
ViRGE
ADDRESS
BIOS ROMCS
ROM
D[7:0]
OE CE
OE0
74ALS244
OE1
SA[15:0] SMEMR
ISA BUS VVLROMIF
Figure 12-2. BIOS ROM VL-Bus Configuration Interface
The implementation for a VL-Bus configuration matically increments the lower address three
is shown in Figure 12-2. The ROM is accessed via times and generates the remaining three bytes of
the ISA bus. This allows a shadowed BIOS to be read data. In both cases, TRDY is delayed until all
accessed by a CPU memory read without also the required data is available on the AD bus. For
generating data directly from the physical ROM. 16-, 24- or 32- bit accesses, the ROM access time
Only 8-bit ROMs are supported. must be 10 SCLKs or less, as opposed to the 14
SCLKs shown in Figure 12.3 for an 8-bit access.
12.1.3 BIOS ROM Read Functional For a VL-Bus configuration, a BIOS ROM read is
Timing a standard ISA bus read cycle with ViRGE provid-
ing its ROMCS output as the ROM chip and buffer
Figure 12-3 depicts the PCI configuration func- enable (see Figure 12-2). ROMCS is asserted dur-
tional timing for reading one byte from the ROM. ing the time the ROM address is valid and there-
ROMEN is asserted to drive the byte of read data fore will be active when the chipset asserts the
at the address on GA[15:0] to the General Data ISA SMEMR signal.
Bus. ViRGE latches the data one clock before
deassertion of ROMEN and then drives this data
onto the AD bus.
12.1.4 BIOS ROM Address Mapping
ViRGE also supports 16- and 32-bit ROM reads, ViRGE maps the CPU memory address spaces for
as defined by the states of the byte enables. For the video BIOS ROM into physical ROM ad-
a 16-bit read, ViRGE automatically increments dresses. If implemented separately for a VL-Bus
the lower address once and generates the second system, the video BIOS normally uses the stand-
byte of read data. For a 32-bit read, ViRGE auto- ard address range C0000H–C7FFFH (32 KBytes).
12-2 MISCELLANEOUS FUNCTIONS

T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20
SCLK
FRAME
AD[31:0] ADD ROM DATA
IRDY
TRDY
DEVSEL
14 SCLKs MIN
ROMEN
GA[15:0]
Figure 12-3. BIOS ROM Read Functional Timing - PCI

GD[7:0] ROM DATA
VROMREAD

If power-on strapping bit 10 (CR37, bit 2) is 1. Disable all other LPB uses.
strapped low or if bit 2 of CR37 is cleared to 0 in 2. Enable sensing of the desired input data on
a VL-Bus system, the video BIOS address range LD[7:4].
becomes C0000H-CFFFFH (64 KBytes). PCI sys-
tems support a relocatable 64-KByte video BIOS 3. If the LPB General Output Port function is
address range via the BIOS ROM Base Address also in use, ensure that the correct output
configuration register (Index 30H). data is programmed in MMFF1C_3-0.
4. Program SR1C_1-0 to 01b.
12.2 GREEN PC SUPPORT 5. Write (anything) to CR5C. The data on
LD[7:4] are latched 2 DCLKs later into
MMFF1C_7-4. (This also drives the con-
ViRGE provides support for the VESA Display tents of MMFF1C_3-0 onto LD[3:0] and
Power Management Signaling (DPMS) protocol generates the STWR pulse on pin 190. The
by allowing independent control of the HSYNC input data is latched on the rising edge of
and VSYNC signals. To use this capability, the bit STWR. See Figure 12-6)
pattern xxxx0110b must be written to the SR8
register to unlock access to the SRD register. Bits 6. Disable sensing of input data on LD[7:4].
5-4 of SRD then control the state of HSYNC and
bits 7-6 of SRD control the state of VSYNC. ViRGE provides an 8-bit GIP for VL-Bus configu-
rations. The block diagram for this configuration
Driving pin 165 (PDOWN) low turns off the RGB is shown in Figure 12-4. The following steps
analog outputs of the internal DACs. implement the GIP function.
1. Set bit 2 of CR55 to 1 to enable the GIP

12.3 GENERAL INPUT PORT read function.
2. Program SR1C_1-0 to 01b to enable output
ViRGE provides a 4-bit General Input Port (GIP) of GPIOSTR on pin 151.
for PCI configurations as part of its LPB function. 3. The data is read from an external buffer by
The following steps are required to implement it. a read of port 3C8H (the same as the DAC
Write Index off-chip register).
VESA
LOCAL BUS
SD[31:0]
SD[7:0]
ViRGE
Q[7:0]
GENERAL
INPUT OE
PORT
BUFFER GPIOSTR
D[7:0]
OEM
DEFINABLE
DATA VVLGIP
Figure 12-4. General Input Port Interface (VL-Bus)

T1 T2 T3 T4 T5 T6 T7
SCLK
GPIOSTR
SD[7:0]
VGIPVL
Figure 12-5. General Input Port Timing (VL-Bus)
When GPIOSTR is asserted, the data is immedi- 1. Disable all other LPB uses.
ately placed on SD[7:0]. The functional timing for 2. Program the desired output in MMFF1C_3-0.
this operation is shown in Figure 12-5. The entire
cycle from assertion of SADS to data being avail- 4. Program SR1C_1-0 to 01b to enable output
able on SD[7:0] takes approximately 18-20 of STWR on pin 190.
SCLKs. 5. Write (anything) to CR5C. The data in
MMFF1C_3-0 are immediately driven onto
LD[3:0] and the STWR pulse is generated.
12.4 GENERAL OUTPUT PORT The rising edge of STWR (2 DCLKs after it
is asserted) can be used to latch the data
ViRGE provides a 4-bit General Output Port (GOP) into an external device. The data is held
for PCI configurations as part of its LPB function. valid for 1/2 DCLK after this edge. See Fig-
To implement this: ure 12-6.
T1 T2 T3
DCLK
STWR LATCH
LD[3:0]
VLPBGOP
Figure 12-6. General I/O Port Timing (PCI)

ViRGE also provides a 2-bit GOP on dedicated ViRGE provides an 8-bit GOP for VL-Bus configu-
pins for PCI configurations. To implement this: rations. The block diagram for this configuration
is shown in Figure 12-7. Whatever is pro-
1. Set SR1C_1 to 1. grammed to CR5C_7-0 is immediately provided
2. Program the desired output in CR5C_1-0. to the latch via SD[15:8]. The functional timing for
This statically drives the state of CR5C_0 this is shown in Figure 12-8. Note that the data
onto pin 151 and the state of CR5C_1 onto can be latched on either the rising or falling edge
pin 190. These pin will continue to reflect of GPIOSTR. The entire cycle from assertion of
the register bit states as long as SR1C_1 SADS to latching of data in the GOP buffer takes
=1. The values in CR5C_1-0 can be repro- approximately 6-8 SCLKs.
grammed at any time.
VESA
LOCAL BUS
SD[31:0]
SD[15:8]
ViRGE
D[7:0]
GENERAL
OUTPUT G
PORT
LATCH GPIOSTR
Q[7:0]
VVLGOP
Figure 12-7. General Output Port Interface (VL-Bus)
T1 T2 T3 T4 T5
DCLK
STWR
SD[7:0]
VGOPVL
Figure 12-8. General Output Port Timing (VL-Bus)

If both an 8-bit GIP and an 8-bit GOP are required, When a VL-Bus configuration powers up with a
the GPIOSTR enable input must be qualified with default value of 00b for bits 1-0, both pin 151 and
the SR/W signal. Additional discrete logic is re- pin 153 will be driven high (logic 1). Pins 151 and
quired to ensure that only the GOP latch is en- 190 are driven high on power-up for PCI configu-
abled for writes and only the GIP buffer is rations. Thus, external devices with active low
enabled for reads. enables will not be enabled when connected to
these pins.
ViRGE also provides a 2-bit GOP on dedicated
pins for VL-Bus configurations. To implement
this: 12.5 FEATURE CONNECTOR
INTERFACE
1. Set SR1C_1-0 to 11b.
2. Program the desired output in CR5C_1-0. Setting SRD_1 to 1 selects LPB feature connector
This statically drives the state of CR5C_0 operation. This configuration provides an inter-
onto pin 151 and the state of CR5C_1 onto face to either a baseline VESA Advanced Feature
pin 153. These pin will continue to reflect Connector (VAFC) or pass-through bidirectional
the register bit states as long as SR1C_1-0 feature connector. In all cases, SRD_0 must be set
=11b. The values in CR5C_1-0 can be re- to 1 to enable feature connector operation and
programmed at any time. SR1C_1-0 must be 00b to enable ENFEAT on pin
151. In addition, LPB operation must be disabled,
The 2-bit GOP is only useful for cases where the (MMFF00_0 = 0) and Streams Processor opera-
video BIOS is part of the system BIOS (mother- tion must be disabled (CR67_3-2 = 00b) before
board implementations) and the ROMCS signal feature connector operation is enabled.
is not needed. If ROMCS is required, a 1-bit GOP
is available by programming SR1C_1-0 to 10b. LPB feature connector operation provides an 8-
Whatever is programmed to CR5C_0 is reflected bit bi-directional feature connector for VL-Bus
on pin 151. configurations. The pins used to provide this type
of operation are listed in Table 12-2. The interface
ViRGE PASS-
THROUGH
PA[7:0] PA[7:0]
ENFEAT N/C
VCLK VCLK
HSYNC HSYNC
VSYNC VSYNC
BLANK BLANK
EVIDEO EVIDEO
ESYNC ESYNC
EVCLK EVCLK
VPASCON1
Figure 12-9. Pass-Through Feature Connector

Table 12-2 LPB Feature Connector Configura- Table 12-3 LPB Feature Connector Configura-
tion (VL-Bus) tion (PCI)
Pin(s) Signals Pin(s) Signals

202, 184, 175, 174, 155, 154, PA[7:0] 201-199, 189-185, 202, 184, PA[15:0]
147, 146 175, 174, 155, 154, 147, 146
151 ENFEAT 151 ENFEAT
206 BLANK 206 BLANK
148 VCLK 148 VCLK
183 ESYNC 196 VCLKI
203 EVIDEO 183 ESYNC
204 EVCLK 203 EVIDEO
149 HSYNC 204 EVCLK
150 VSYNC 149 HSYNC
150 VSYNC
LPB feature connector operation provides a 16-
bit bi-directional feature connector for PCI con- 8-bit feature connector operation is also available
figurations. The pins used to provide this type of for PCI configurations.
operation are listed in Table 12-3. The interface
ViRGE VAFC
PA[15:0] PA[15:0]
ENFEAT N/C
VCLKI VCLK
VCLK DCLK
HSYNC HSYNC
VSYNC VSYNC
BLANK BLANK
EVIDEO EVIDEO
ESYNC GRDY
EVCLK
+5V
+5V +5V
+5V VVAFC1
Figure 12-10. VAFC Implementation

12.6 SERIAL COMMUNICATIONS For PCI LPB configurations, SPCLK and SPD are
not multiplexed. This reduces the isolation re-
PORT quirements.
A serial communications port is implemented in If PD26 is strapped low at reset, strapping of PD25
the MMFF20 register. Bit 4 is set to 1 to enable selects either E2H (PD25 pulled high) or E8H
the interface. The clock is written to bit 0 (= 0) and (PD25 pulled low) as the I/O port address for the
data to bit 1 (= 0), driving the SPCLK and SPD pins serial port register MMFF20. This allows the ports
low respectively. The state of the SPCLK pin can to be used for serial communications, typically
be read via bit 2 and the state of the SPD pin can I2C, when ViRGE is not enabled. If analog
be read via bit 3. The SPCLK and SPD pins are switches are used for isolation as explained in the
tri-stated when their corresponding control bits previous paragraph, designers must ensure that
are reset to 0, allowing other devices to drive the the I2C function is enabled by default on reset. If
serial bus. I/O access is desired after ViRGE has been en-
abled and then disabled, programmers must en-
Typical uses for the serial port are for DDC moni- sure that the I2C function is selected before ViRGE
tor communications and I2C interfacing. When is disabled because the General Output Port may
SPCLK and SPD are tri-stated, ViRGE can detect not be available to change the selection.
an I2C start condition (SPD driven low while
SPCLK is not driven low). This condition is gen-
erated by another I2C master that wants control 12.7 INTERRUPT GENERATION
of the I2C bus. If bit 19 of MMFF08 is set to 1,
detection of a start condition generates an inter- For a PCI configuration, pin 152 is pulled low to
rupt and sets bit 3 of MMFF08 to 1. If bit 24 of signal an interrupt (INTA). For a VL-Bus configu-
MMFF08 is set to 1, ViRGE drives SPCLK low to ration, pin 152 is pulled high to signal an interrupt
generate I2C wait states until the Host can clear (SINTR).
the interrupt and service the I2C bus.
Whatever the mode of operation (VGA or En-
The SPCLK and SPD signals are multiplexed with hanced), bit 4 of CR32 must be set to 1 to enable
the ESYNC and BLANK feature connector signals interrupt generation.
on pins 205 and 206 for VL-Bus configurations. If
DDC, I2C and/or feature connector operation are When ViRGE is being operated in VGA mode
required, the lines from pins 205 and 206 must (CR66_0 = 0), only a vertical retrace can generate
be multiplexed to separate pairs of lines for each an interrupt. This is enabled when bit 5 of CR11
operation to provide the necessary signal isola- is cleared to 0 and a 1 has been programmed into
tion. The ENFEAT signal should be used to en- bit 4 of CR11. When an interrupt occurs, it is
able ESYNC and BLANK onto one pair of lines to cleared by writing a 0 to bit 4 of CR11. The
the feature connector. When ENFEAT is high, one interrupt must then be re-enabled by writing a 1
bit of the General Output Port can be used to to the same bit. Note that the BIOS clears both bit
select between I2C and DDC operation, with a 1 4 and bit 5 of CR11 to 0 during power-on, a mode
enabling output on one pair of lines and a 0 set or a reset. Thus, interrupt generation is dis-
enabling output on another. abled until bit 4 is set to 1.
The National Semiconductor CD4052B Dual 4- When ViRGE is being operated in Enhanced
Channel Analog Multiplexer/Demultiplexer pro- mode (CR66_0 = 1), interrupts can be generated
vides the capability to channel two lines to one by a vertical retrace, S3D Engine busy, S3D En-
of four pairs of lines based on two select signals. gine done, Host DMA done, Command DMA
Each side can act as either an input or output. A done, S3D FIFO empty, command FIFO overflow
set of schematics showing the use of this part is and command FIFO empty. These interrupts are
available. enabled and cleared and their status reported via
MM8504.

Multiple interrupts can be enabled at the same

time in Enhanced mode. The interrupt pin will
remain asserted until all interrupt status bits are
cleared.

Section 13: Basic Software Functions
This section describes the basic operations required for ViRGE.
13.1 CHIP WAKEUP
The following code segment wakes up ViRGE.
mov dx,3c3h ; Video Subsystem Enable register address

mov al,01h ; bit 0 = 1, enable graphics display
out dx,al ; write new bit values to 3c3h
mov dx,3cch ; Miscellaneous Output Read register
in al,dx ; Read 3cch
[load CRTCs] ; program CRTC registers
mov dx,3C6h ; DAC Mask register address
mov al,FFh ; DAC Mask register initialization value
out dx,al ; Initialize DAC mask and release BLANK signal
.
.
.
13.2 REGISTER ACCESS
S3 has added a number of graphics registers to the standard VGA set. These can be locked when not
in use to prevent accidental access and unlocked when access is requires. This section explains how
this is done.
13.2.1 Unlocking the S3 Registers
The S3 registers (CR30 and higher plus the Enhanced Commands registers) must be unlocked before
they can be accessed by the CPU. The code to do this is:
Note: Byte operations are used in the following examples for clarity. Word operations, e.g..,
mov ax, 4838h

out dx,ax
should be used for efficiency instead of the operations used in the first example below.
BASIC SOFTWARE FUNCTIONS 13-1

; Write code to SR8 to provide access to the S3 extended Sequencer registers

(SR9-SRFF)
;
mov dx,3c4h ; copy index register address into dx
mov al,08h ; copy index for SR8 register into al
out dx,al ; write index to index register
inc dx ; increment dx to 3c5h (data register address)
mov al,06h ; copy unlocking code (xxxx0110b, x=don’t care) to al
out dx,al ; write the unlocking code to the data register
dec dx ; restore the index register address to dx
;
; Write code to CR38 to provide access to extended CRTC registers CR2D-CR3F
;
mov dx,3d4h ; copy index register address into dx
mov al,38h ; copy index for CR38 register into al
inc dx ; increment dx to 3D5h (data register address)
mov al,48h ; copy unlocking code (01xx10xxb, x=don’t care) to al
;
; Write code to CR39 to provide access to extended CRTC registers CR40-CRFF
;
; dx is already loaded with 3D4h because of the previous instruction
;
mov al,0a5h ; copy unlocking code to al (the code a5H also unlocks
; access to configuration registers CR36, CR37 and CR68
;
; Set bit 0 in CR40 to enable access to the Enhanced Programming registers.
;
; dx is already loaded with 3D4h because of previous instruction
in al,dx ; read register data for read/modify/write operation
or al,1 ; set bit 0 to 1
13-2 BASIC SOFTWARE FUNCTIONS

13.2.2 Locking the S3 Registers
Relocking the S3 registers is done by repeating the code used to unlock the registers except:
1. The values written to the SR8, CR38 and CR39 registers must change at least one of the signifi-
cant bits in the valid code pattern. For example, 00h will always accomplish this.
2. After first verifying that the S3D Engine is not busy (bit 9 of 9AE8H is 0), bit 0 of CR40 must be
cleared to 0. A read-modify-write cycle must be used instead of the code used above to prevent
overwriting of any changes made to bits 7-1 in CR40 since reset.

in al,dx ; read content of CR40 into al
and al,0feh ; clear bit 0 to 0
out dx,al ; write to CR40 to lock the Enhanced Commands registers
13.3 TESTING FOR THE PRESENCE OF A ViRGE CHIP
After unlocking, a ViRGE chip can be identified via CR2E.

mov al,2eh ; copy index for CR2E register into al
in al,dx ; read content of CR2E into al
cmp al,31h : compare chip ID to the desired chip ID (31h)
jne not_ViRGE ; jump to not_ViRGE if device ID for ViRGE is not found
. ; ViRGE chip found - continue
.
.
13.4 GRAPHICS MODE SETUP
Some programs may require a graphics mode other than that provided by standard operation. For
example, a DOS game may require a resolution of 640x400x8 (VESA mode 100) instead of the standard
DOS mode, e.g., mode 03. The following code fragment shows how this is done.
mov ax,4f02h ; VESA super VGA mode function call

mov bx,100h ; mode 100
int 10h ; call video BIOS
BASIC SOFTWARE FUNCTIONS 13-3

13-4 BASIC SOFTWARE FUNCTIONS

Section 14: VGA Compatibility Support
This section describes ViRGE support for standard VGA and VESA Super VGA graphics standards.
14.1 VGA COMPATIBILITY
ViRGE is compatible with the VGA standard. These modes are not accelerated using the S3D Engine.
However, other design features provide excellent VGA performance.
Several of the standard VGA registers have been modified or extended in ViRGE. Table 14-1 describes
these changes.
Table 14-1. Standard VGA Registers Modified or Extended in ViRGE
Register Change to Standard VGA Definition

CR0 Extension bit 8 is bit 0 of CR5D. Bit 5 of CR35 controls access to this register. Bit
7 of CR43 doubles the parameter size.
CR3 The length of the blanking pulse defined in this register can be extended by 64
DCLKs via bit 3 of CR5D. Bit 5 of CR35 controls access to this register. Bit 7 of
CR43 doubles the parameter size.
CR5 The length of the HSYNC pulse defined in this register can be extended by 32
DCLKs via bit 5 of CR5D. Bit 5 of CR35 controls access to this register. Bit 7 of
CR43 doubles the parameter size.
CR6 In addition to the standard VGA extensions (bit 8 is bit 0 of CR7, bit 9 is bit 5 of
CR47), bit 10 is bit 0 of CR5E. Bit 4 of CR35 controls access to this register.
CR7 Bit 4 of CR35 controls access to bits 0, 2, 3, 5 and 7 of this register.
CR9 Bit 4 of CR35 controls access to bit 5 of this register.
CRC The display start address is a 20-bit value for ViRGE. The extension bits (19-16)
are bits 3-0 of CR69.
CRE The cursor location address is a 20-bit value for ViRGE. The extension bits (19-16)
are bits 3-0 of CR69.
VGA COMPATIBILITY SUPPORT 14-1

CR11 Bit 4 of CR35 controls access to bits 3-0 of this register. Bit 6 (3/5 refresh cycles
per line) can be overridden by CR3A_2-0. Setting bit 1 of CR33 to 1 disables the
write protect effect of bit 7 of this register on bits 1 and 6 of CR7.
CR7), bit 10 is bit 1 of CR5E.
CR13 Bit 2 of CR43 is the old extension bit (bit 8) of this register. Bits 5-4 of CR51 are
the new extension bits (bits 9-8) of this register.
CR16 Bit 4 of CR35 controls access to this register.
CR17 Bit 5 of CR35 controls access to bit 2 of this register.
CR9), bit 10 is bit 6 of CR5E.
AR00-AR0F Bit 6 of CR33 controls access to these registers.
3C6H-3C9H Bit 4 of CR33 controls writes to these registers.
For a detailed discussion of VGA programming, see Programmer’s Guide to the EGA, VGA and Super
VGA Cards, 3rd Edition by Richard F. Ferraro (Addison-Wesley Publishing Company, Inc).
14.2 VESA SUPER VGA SUPPORT
ViRGE supports the extended (Super) VGA modes defined by VESA. All modes are accelerated by the
S3d Engine except for the planar (4 bits/pixel) ones.
14-2 VGA COMPATIBILITY SUPPORT

Section 15: Enhanced Programming
Enhanced mode provides a level of performance far beyond what is possible with the VGA architecture.
Hardware BitBLTs (with 256 ROPs), 2D and 3D line drawing, 2D polygon fills and 3D triangle drawing
are implemented. Hardware cursor support and clipping are also supported. While in Enhanced mode,
the display memory bit map can be updated in two ways. One is to have the CPU issue commands
and send data to the S3d Engine, which then controls pixel updating. The other is to have the CPU
write directly to memory. (This is also possible in non-Enhanced modes via paging.) This section
explains these two methods and provides a set of Enhanced mode 2D programming examples and
explains the basic elements of 3D drawing.
15.1 MEMORY-MAPPED I/O
ViRGE provides two memory-mapped I/O (MMIO) methods. For the "old" method, the base address is
A000H (or B800H), allowing use during DOS and real mode operation. This is available for both VL-Bus
and PCI configurations. For the "new" method, the base address is the linear addressing (or PCI) base
address and requires protected mode. In addition, address space is provided for linear addressing and
big endian addressing. The new method can only be used with PCI configurations. Each of these MMIO
methods is described below.
15.1.1 Old MMIO
Setting bits 4-3 of CR53 to 10b enables the old MMIO function. A setting of 11b enables both the old
and new MMIO methods simultaneously. When the old MMIO is enabled, CR53_5 selects the base
address. CR53_5 = 0 places the MMIO window at A0000H - AFFFFH. CR53_5 =1 places the MMIO window
at B8000H - BFFFFH. The latter setting leaves A0000H - B7FFFH free for VGA memory and other uses.
In either case, all the ViRGE registers are accessible via either window at the variable offsets shown in
Table 15-1. For example, the PCI configuration space registers are found starting at A8000H (or B8000H,
depending on the setting of CR53_5).
With old MMIO enabled and CR53_5 =0, image writes are made by accessing any memory location in
the 32-KByte address space from A0000H to A7FFFH. This allows efficient use of the MOVSW and
MOVSD assembly language commands. Accesses must be to doubleword addresses. Software must
not make image writes beyond the A7FFFH range. If CR53_5 = 1, image writes cannot be made as the
A0000H - A7FFFH range is reserved.
When MMIO is enabled (old or new), clearing bit 7 of SR9 to 0 allows both programmed I/O (IN, OUT)
access and MMIO (MOV) access. Setting this bit to 1 disables programmed I/O access, allowing only
MMIO access. The latter is required for plug and play operation.
ENHANCED PROGRAMMING 15-1

15.1.2 New MMIO
The new MMIO method for ViRGE provides a 64-MByte addressing window starting at the base address
specified in CR59-5A or the PCI base address register. This space is divided into a 32-MByte space for
little endian (Intel-style) addressing and a 32-MByte space for big endian (Power PC-style) addressing.
All registers and data transfer locations are mapped into this area as shown in Table 7-1.
The new MMIO (only) is enabled by setting bits 4-3 of CR53 to 01b. This is the default for a PCI bus
configuration, allowing PCI software immediate access to all registers and the ability to relocate the
address space. The new MMIO is also enabled in conjunction with the old MMIO method when bits
4-3 of CR53 are set to 11b. VL-Bus configurations power up with bits 4-3 of CR53 cleared to 00b, disabling
both old and new MMIO operation.
When MMIO is enabled (old or new), clearing bit 7 of SR9 to 0 allows both programmed I/O (IN, OUT)
access and MMIO (MOV) access. Setting this bit to 1 disables programmed I/O access, allowing only
MMIO access. The latter is required for plug and play operation.
Table 15-1. New MMIO Addresses
Lower 32 MBytes - Little Endian Addressing

Description Offset From Base (Hex)
Linear Addressing (16M) 000 0000 - 0FF FFFF
Image Data Transfer (32K) 100 0000 - 100 7FFF
PCI Configuration Space Registers 100 8000 - 100 8043
Streams Processor Registers 100 8180 - 100 81FF
Memory Port Controller 100 8200 - 100 8224
CRT VGA 3B? Registers 100 83B0 - 100 83Bx
CRT VGA 3C? Registers 100 83C0 - 100 83Cx
CRT VGA 3D? Registers 100 83D0 - 100 83Dx
Subsystem Status Enhanced Register 100 8504
Advanced Function Control Register 100 850C
DMA Controller Registers 100 8580 - 100 85FF
Color Pattern Registers 100 A000 - 100 A1FF
BitBLT/Rectangle Fill Registers 100 A400 - 100 A5FF
2D Line Draw Registers 100 A800 - 100 A9FF
2D Polygon Fill Registers 100 AC00 - 100 ADFF
3D Line Draw Registers 100 B000 - 100 B1FF
3D Triangle Registers 100 B400 - 100 B5FF
Local Peripheral Bus Registers 100 FF00 - 100 FF5C
Values in the gaps between the memory ranges shown in Table 15-1 are reserved.
For big endian addressing, add 2 to the most significant hex digit shown in Table 15-1, i.e.,
0xx xxxx becomes 2xx xxxx and 1xx xxxx becomes 3xx xxxx. Thus, the total address space decoded
by ViRGE is 64 MBytes.
15-2 ENHANCED PROGRAMMING

15.2 DIRECT BITMAP ACCESSING—LINEAR ADDRESSING
Linear addressing is useful when software requires direct access to display memory. ViRGE provides
two linear addressing schemes. The old method can be used when MMIO is disabled or with the old
MMIO method. The second is used in conjunction with the new MMIO method.
15.2.1 Old Linear Addressing
Enhanced mode operation must be enabled before linear addressing is enabled. This means that bit
0 of CR66 is set to 1 to enable Enhanced mode functions and bit 3 of CR31 is set to 1 to specify Enhanced
mode memory mapping.
ViRGE provides linear addressing of up to 4 MBytes of display memory. Linear addressing of more
than 64 KBytes requires that the CPU be operated in protected mode.
The S3d Engine busy flag, bit 13 of MM8504 (read), should be verified to be 0 (not busy) before linear
addressing is enabled by setting bit 4 of CR58 to 1. The size of the linear address window is set via bits
1-0 of CR58. The base address for the linear addressing window is set via CR59 and CR5A (or via the
Base Address 0 (Index 10H) PCI configuration register for PCI systems).
For operation in real mode, the linear addressing window size can be set to 64 KBytes. The base address
for the window is set to A0000H by programming bits 31-16 of the window position in CR59-CR5A to
000AH. If bit 0 of CR31 is set to 1, the memory page offset (64K bank) specified in bits 5-0 of CR6A is
added to the linear addressing window position base address, allowing access to up to 4 MBytes of
display memory through a 64-KByte window.
15.2.2 New Linear Addressing
With the new MMIO enabled (CR53_4-3 = 01b or 11b), the first 16 MBytes of each 32M address space
(big and little endian) are dedicated to linear addressing. A maximum of 4 MBytes of each address
space (starting at the lowest address of the space) is usable with ViRGE. The base address is taken
from bits 31-26 of the linear address window position (bits 7-2 of CR59 or the high order 6 bits of the
the PCI Base Address 0). This is concatenated with the display memory address specified by the
programmer.
In addition to enabling the new MMIO, the programmer must also enable linear addressing and specify
the window size exactly as required for the old linear addressing. Note that since only bits 31-26 are
used to specify the base address, A0000H cannot be specified and the 64K banking scheme possible
with the old linear addressing cannot be used with the new linear addressing.
When big endian addressing is used, the required byte swapping for linear addressing is specified by
bits 2-1 of CR53. This applies to both reads and writes.

15.3 READ AND WRITE ORDERING
An overview of the ViRGE internal organization is shown in Figure 15-1. Note that there are three
independent and concurrent paths for communications between the CPU and ViRGE registers and
memory. The time required for any given read or write to complete (latency) varies by path. This can
have important implications for the programmer.
First is the issue of write ordering. For example, a linear addressing write to memory uses the command
FIFO path, while an image write to memory uses the S3d FIFO path. If the programmer issues a linear
addressing command and then an image write command before the linear address command
completes (or vise versa), there is no guarantee which will complete first. For total safety from
prematurely overwriting memory data, the programmer must check that the S3d FIFO is empty before
doing linear addressing updating or for command FIFO empty before doing an image transfer.
Similarly, if correct operation of any command is dependent on operation using another FIFO path
(such as a VGA register update before an S3d command), the programmer must ensure that the relevant
FIFO is empty before issuing the dependent command.
Reads through the LPB and VGA paths bypass the respective FIFOs. However, they will be held until
the relevant FIFO is empty before completing. For PCI systems, this will generate a disconnect (if bit
3 of CR66 is set to 1). This hold guarantees that a read of a register following a write will yield the
correct data. Reads of S3d registers go through the S3d FIFO. However, any read with the S3d FIFO
not empty or with the S3d Engine busy will yield undefined results.
SYSTEM BUS INTERFACE (PCI/VL)
BIU (BIU, STATUS AND DMA REGS)
RAMDAC REGISTER READ/WRITE
READ LPB S3D COMMAND

READ
BYPASS FIFO FIFO FIFO
BYPASS
8x32 16x40 8x64
STREAMS PROCESSOR
REGISTER READ/WRITE
LPB & S3D & VGA & STREAMS RAMDAC &

EXTERNAL LPB
REGS REGS REGS PROCESSOR REGS
& REGS
MIU & REGS

PRIMARY/
SECONDARY
STREAM
FIFO
VIDEO 24x65
MEMORY ORDERING
Figure 15-1. Internal Organization

15.4 S3d ENGINE PROGRAMMING
All Enhanced mode programming should be done using memory-mapped I/O.
MMIO Format:
Enable MMIO
Point ES to A000H (old MMIO) or base address (new MMIO)
Load the x and y values into EAX (y value in the low word and x value in the high word), I.e.,
EAX ⇐ x,y
MOV ES:[REGMNEMONIC], EAX
The MMIO scheme is the most efficient and is used where appropriate in the programming examples
provided later in this section. All assume that the ES register points to A000H is the old MMIO is being
used or the base address if the new MMIO is being used.
15.4.1 Notational Conventions
The following provides examples of the conventions used in the programming examples. Text
following a ‘;’ is a comment.
ES:[MMXXXX] ⇐ BN1 (bh-bl), BN2 (bh-bl)
MMXXXX identifies the memory-mapped register, with XXXX being the variable part of the address
offset. Thus MMA504 identifies the register at offset 100 A504H. BN1 (bh-bl) represents a bit mne-
monic followed by the bit location(s). Thus, SRC_X (26-16) indicates that the Source X value is pro-
grammed into bits 26-16.
The complete binary programming of the Command Set register is provided. For example,
ES:[MM????] ⇐ XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX Where:
???? = appropriate variable offset value for the Command Set register, e.g., A500 for BitBLTs.
X = 0; bit value = 0
X = 1; bit value = 1
X = S; this bit value must be specified, but can vary for this command
Image transfers (CPU pixel data writes to the frame buffer) are notated as follows:
COUNT
IMAGEDATA ⇐ RECT_DATA
The COUNT is the number of CPU writes. IMAGEDATA means the 32K Image Data Transfer mem-
ory space at the memory-mapped location shown in Table 15-1.

15.4.2 Initial Setup
All examples assume the desired mode is selected.
If bit 1 of the Command Set register is set to 1, all bitmap updates are affected by the settings in the
clipping registers (MMxxDC, MMxxE0).
15.4.3 Autoexecute
When bit 0 of the Command Set register is cleared to 0, the command is executed when the Command
Set register is written. If this bit is set to 1, the command is not executed until the register with the
highest address for that command type (BitBLT, Line Draw, etc.) is written. This allows multiple
executions of a given command using different parameters without re-programming the Command
Set register. Full programming examples for autoexecute on are provided for each command type.
15.4.4 2D Programming Examples
This section provides programming examples for the following Enhanced mode 2D drawing opera-
tions:
• BitBLT
• Rectangle Fill
• 2D Line Draw
• 2D Polygon Fill

15.4.4.1 BitBLT
The BitBLT function provides a full implementation of the 256 raster operations as defined by Microsoft
for Windows. A listing and explanation of these is provided in Appendix A.
Each raster op has three operands: Source, Pattern and Destination. The Source pixel can be from the
screen (current bitmap) or from the CPU (image transfer). When the source is the screen, the pixel
depth is always the same for both the source and destination (8, 16, 24 bits/pixel). When the source is
the CPU, the pixel can be either color (same source and destination pixel depth) or mono (1 bit/pixel).
The Pattern is an 8x8 array of pixels. A mono pattern is specified in the Mono Pattern 0 and 1 registers.
The Pattern Foreground and Background Color registers define the pixel colors. A color pattern is
specified in a set of registers starting at offset 100 A100H. The number of registers required depends
on the color depth.
The Destination pixel is always the screen (current bitmap) and is always color (multi bits/pixel). This
is the pixel that will be overwritten or left unchanged by the result of the operation.
Based on the above definitions, there are 6 valid BitBLT cases:
Color Pattern
• Source = Screen, Color Pixels

• Source = CPU, Color Pixels
• Source = CPU, Mono Pixels
Mono Pattern
• Source = Screen, Color Pixels

• Source = CPU, Color Pixels
• Source = CPU, Mono Pixels
When the source and destination are overlapping rectangles on the screen , care must be taken so that
the source data is not overwritten before it is moved. This issue is explained next, followed by
programming examples for each of these above cases.
Overlapping Rectangles Case
Figure 15-2 shows the 4 cases for overlapping rectangles. Table 15-2 gives the proper programming
parameters for each case. The direction indicates the order in which the pixels are moved, from left to
right (X+) or right to left (X-) and top to bottom (Y+) or bottom to top (Y-). These are specified via bits
25 and 26 of the Command Set register. The source and destination coordinates are specified via the
Rectangle Source XY and Rectangle Destination XY registers. x1,Y1 is the pixel position of the upper
left hand corner of the source rectangle. x2,Y2 is the pixel position of the upper left hand corner of the
destination rectangle. The width of the rectangle is W (in pixels) and the height is H (in lines). As
indicated in the figure, you always start with the source corner inside the overlap and move that pixel
to the corresponding corner for the destination pixel.

Table 15-2 Programming Parameters for Overlapping BitBLTs
Case Direction SRC_X SRC_Y DEST_X DEST_Y

1 X+, Y+ x1 y1 x2 y2
2 X-, Y- x1 + W - 1 y1 + H -1 x2 + W - 1 y2 + H -1
3 X-, Y+ x1 + W - 1 y1 x2 + W - 1 y2
4 X+, Y- x1 y1 + H -1 x2 y2 + H -1
The basic algorithm is if the drawing direction is negative, add [rectangle dimension -1] in that direction
to the normal source/destination location. If the drawing direction is positive, use the original
source/destination location.
The parameters for Case 1 are appropriate for non-overlapping rectangles.
CASE 1 CASE 2 CASE 3 CASE 4

x1 ≥ x2 x2 ≥ x1 x2 ≥ x1 x1 ≥ x2
y1 ≥ y2 y2 ≥ y1 y1 ≥ y2 y2 ≥ y1
x2, y2 x1, y1 x2, y2 x1, y1
x1, y1 x2, y2 x1, y1 x2, y2

D S D S
S D S D BLTCASES
Figure 15-2. Overlapping BitBLT Cases

Color Pattern Case 1 (Source = Screen, Color Pixels)
This command copies a source rectangular area in display memory to another location in display
memory. The 8x8 pixel pattern is programmed in the color pattern registers. For this example, assume
x1,y1 is the top left corner of the source rectangle in display memory and x2,y2 is the top left corner
of the destination rectangle. The rectangles can be overlapping or disjoint. See Table 15-2 for the source
and destination coordinate parameter values for overlapping cases. The height and width (in pixels)
of the rectangle being copied are H and W. The color depth is assumed to be 8 bits/pixel.
Autoexecute Off:
ES:[MMA100] ⇐ P3 (31-24), P2 (23-16), P1 (15-8), P0 (7-0) ; Pixels 3-0 of the color pattern
.
.
.
ES:[MMA13C] ⇐ P63 (31-24), P62 (23-16), P61 (15-8), P60 (7-0) ; pixels 63-60 of the color pattern
ES:[MMA504] ⇐ W-1 (26-16), H (10-0) ; rectangle width and height
ES:[MMA508] ⇐ SRC_X (26-16), SRC_Y (10-0) ; source x and y start coordinates
ES:[MMA50C] ⇐ DEST_X (26-16), DEST_Y (10-0) ; destination x and y start coord.
ES:[MMA500] ⇐ 0000 0SSS SSSS SSS0 0000 0000 0010 00S0 ; Command Set register
The following must be specified: Y direction (bit 26), X direction (bit 25), ROP (bits 24-17), clipping
enable (bit 1). Bits 4-2 will be different for other color depths.
Autoexecute On:
ES:[MMA100] ⇐ P3 (31-24), P2 (23-16), P1 (15-8), P0 (7-0) ; pixels 3-0 of the color pattern
.
.
.
ES:[MMA500] ⇐ 0000 0SSS SSSS SSS0 0000 0000 0010 00S1 ; bit 0 = 1 for autoexecute
The command is executed when MMA50C is programmed. The order of programming the other
registers is not important. With autoexecute on, additional BitBLTs can be performed by reprogram-
ming only the parameter registers (not the Command Set register), always ending with the Rectangle
Destination XY register (MMA50C).

Color Pattern Case 2 (Source = CPU, Color Pixels)
This command transfers a rectangular color image provided by the CPU to a location in display
memory. The 8x8 pixel pattern is programmed in the color pattern registers. For this example, assume
the height and width (in pixels) of the rectangle being copied are H and W. The color depth is assumed
to be 8 bits/pixel.
Autoexecute Off:
.
.
.
ES:[MMA500] ⇐ 0000 000S SSSS SSS0 00SS SS00 1010 00S0 ; Command Set register
The following must be specified: ROP (bits 24-17), first dword offset (bits 13-12), image transfer
alignment (bits 11-10), clipping enable (bit 1). Bits 4-2 will be different for other color depths.
COUNT (of image pixel data to transfer) = (See Note)

IMAGEDATA ⇐ RECT_DATA ; Output data to Image Transfer addresses for COUNT dwords
Autoexecute On:
Writing to the Destination XY register (MMA50C) executes the command.
Note
If the CPU obtains the image data from a source bitmap written to system memory by the application,
the application passes the origin of this bitmap, its width, height and color depth. Some or all of this
bitmap can then be blitted to display memory (screen). The method of transfer varies depending on
whether or not the entire bitmap or a partial bitmap is transferred.
For source bitmaps from an application, each line is required by specification to be word aligned, i.e.,
data for a new line begins with the next word after the last word containing valid data for the previous
line. Therefore, to transfer a complete source bitmap, the driver does the following:
1. All image transfers must be doubleword aligned. Therefore, bits 13-12 of the Command Set
register must be programmed to properly reflect the alignment of the first pixel of the source
bitmap. For example, if the first pixel of the source bitmap starts with the third byte of the first
doubleword-aligned read, bits 13-12 of the Command Set register must be programmed to
10b to tell the Engine to ignore the first two bytes.
2. Word alignment must be specified by programming bits 11-10 of the Command Set register to
01b. This tells the Engine that the data for the next line starts at the next word after the data
ending the line. In some cases, doubleword alignment is appropriate (bits 11-10 of the Com-
mand set register = 10b). This is more efficient, but is a special case. Word alignment always
works.
3. To determine the number of doublewords to transfer, calculate (for the source bitmap):
int [(width x height x bits/pixel) + 31]/32.

4. The image transfer area in memory is 32K (offset 100 0000H - 100 7FFFH). The driver must moni-
tor the addresses for image writes and reset the address pointer back to the start before any
writes are made beyond the 32K area.
If the application requests that only a rectangular subsection of the source bitmap be transferred to
display memory, the driver has multiple choices of how to do this.
1. The driver can transfer the entire source bitmap and use the clipping registers to eliminate the
unwanted pixels.
2. The driver can transfer only the requested pixels, but it must do this one line at time. If the start
of each line is not doubleword aligned, the driver must determine the doubleword address
containing the first data for the first line and the number of doublewords required to send the
whole line. It must then issue the command to blit this line, with bits 13-12 of the Command
Set register set to ignore the appropriate number of bytes at the start of the line. The driver
must then change the address to the start of the next line and repeat the above process, in-
cluding specification of a new destination start address. The result is that one command is
executed for each line.
Note that if the lines for the requested pixels happen to start at doubleword addresses, the en-
tire rectangle can be blitted with a single command because no data needs to be ignored at
the start of each line. The driver still needs to keep track of the line length and increment the
address by the stride at the end of each line.
3. The driver can transfer the requested pixels as described in 2 above and use the clipping
registers to eliminate any extra pixels at the start of each line.

Color Pattern Case 3 (Source = CPU, Mono Pixels)
This command transfers a rectangular mono image provided by the CPU to a location in display
memory. The mono image is converted to the screen color depth based on the the pattern color
(potentially) mixed with the screen (destination) color. The 8x8 pixel pattern is programmed in the
color pattern registers. For this example, assume the height and width (in pixels) of the rectangle being
copied are H and W. The screen color depth is assumed to be 8 bits/pixel.
Autoexecute Off:
.
.
.
ES:[MMA500] ⇐ 0000 000S SSSS SSS0 00SS SS00 1110 00S0 ; Command Set register

Autoexecute On:
Note
If the source bitmap is provided by the application, then the entire Note for the previous color pixels
case also applies to this mono pixel case because each line is required to be word aligned. If the
source bitmap is provided by the driver, e.g., font data, the driver should byte align the data and
program bits 11-10 of the Command Set register to 00b to specify byte alignment to the Engine.

Mono Pattern Case 1 (Source = Screen, Color Pixels)
This command copies a source rectangular area in display memory to another location in display
memory. It is identical to the Color Pattern Case 1 except that the 8x8 pixel pattern is programmed in
the mono pattern registers and the pattern color is taken from the pattern foreground and background
registers. For this example, assume x1,y1 is the top left corner of the source rectangle in display
memory and x2,y2 is the top left corner of the destination rectangle. The rectangles can be overlapping
or disjoint. See Table 15-2 for the source and destination coordinate parameter values for overlapping
cases. The height and width (in pixels) of the rectangle being copied are H and W. The screen color
depth is assumed to be 8 bits/pixel.
Autoexecute Off:
ES:[MMACE8] ⇐ MONO PATTERN 0 ; 1st 32 bits of mono pattern

ES:[MMACEC] ⇐ MONO PATTERN 0 ; 2nd 32 bits of mono pattern
ES:[MMACF0] ⇐ DATA1 (7-0) ; 8-bit pattern backgnd color index
ES:[MMACF4] ⇐ DATA1 (7-0) ; 8-bit pattern foregnd color index
ES:[MMA500] ⇐ 0000 0SSS SSSS SSS0 0000 0001 0010 00S0 ; Command Set register
The following must be specified: Y direction (bit 26), X direction (bit 25), ROP (bits 24-17), clipping
enable (bit 1). Bits 4-2 and the fields programmed for the background and foreground colors will be
different for other color depths.
Autoexecute On:

Mono Pattern Case 2 (Source = CPU, Color Pixels)
This command transfers a rectangular color image provided by the CPU to a location in display
memory. It is identical to the Color Pattern Case 1 described earlier except that the 8x8 pixel pattern
is programmed in the mono pattern registers and the pattern color is taken from the pattern fore-
ground and background registers. For this example, assume the height and width (in pixels) of the
rectangle being copied are H and W. The screen color depth is assumed to be 8 bits/pixel.
Autoexecute Off:

ES:[MMA500] ⇐ 0000 000S SSSS SSS0 0001 1001 0010 00S0 ; Command Set register
Autoexecute On:

Autoexecute On:
Note
If the CPU obtains the image data from a source bitmap written to system memory by the application,
the application passes the origin of this bitmap, its width, height and color depth. Some or all of this
bitmap can then be blitted to display memory (screen). The method of transfer varies depending on
whether or not the entire bitmap or a partial bitmap is transferred.
For source bitmaps from an application, each line is required by specification to be word aligned, i.e.,
data for a new line begins with the next word after the last word containing valid data for the previous
line. Therefore, to transfer a complete source bitmap, the driver does the following:
1. All image transfers must be doubleword aligned. Therefore, bits 13-12 of the Command Set
register must be programmed to properly reflect the alignment of the first pixel of the source
bitmap. For example, if the first pixel of the source bitmap starts with the third byte of the first
doubleword-aligned read, bits 13-12 of the Command Set register must be programmed to
10b to tell the Engine to ignore the first two bytes.
2. Word alignment must be specified by programming bits 11-10 of the Command Set register to
01b. This tells the Engine that the data for the next line starts at the next word after the data
ending the line. In some cases, doubleword alignment is appropriate (bits 11-10 of the Com-
mand set register = 10b). This is more efficient, but is a special case. Word alignment always
works.

3. To determine the number of doublewords to transfer, calculate (for the source bitmap):
int [(width x height x bits/pixel) + 31]/32.

4. The image transfer area in memory is 32K (offset 100 0000H - 100 7FFFH). The driver must moni-
tor the addresses for image writes and reset the address pointer back to the start before any
writes are made beyond the 32K area.
If the application requests that only a rectangular subsection of the source bitmap be transferred to
display memory, the driver has multiple choices of how to do this.
1. The driver can transfer the entire source bitmap and use the clipping registers to eliminate the
unwanted pixels.
2. The driver can transfer only the requested pixels, but it must do this one line at time. If the start
of each line is not doubleword aligned, the driver must determine the doubleword address
containing the first data for the first line and the number of doublewords required to send the
whole line. It must then issue the command to blit this line, with bits 13-12 of the Command
Set register set to ignore the appropriate number of bytes at the start of the line. The driver
must then change the address to the start of the next line and repeat the above process, in-
cluding specification of a new destination start address. The result is that one command is
executed for each line.
Note that if the lines for the requested pixels happen to start at doubleword addresses, the en-
tire rectangle can be blitted with a single command because no data needs to be ignored at
the start of each line. The driver still needs to keep track of the line length and increment the
address by the stride at the end of each line.
3. The driver can transfer the requested pixels as described in 2 above and use the clipping
registers to eliminate any extra pixels at the start of each line.

Mono Pattern Case 3 (Source = CPU, Mono Pixels)
This command transfers a rectangular mono image provided by the CPU to a location in display
memory. The mono image is converted to the screen color depth based on the the pattern color
(potentially) mixed with the screen (destination) color. It is identical to the Color Pattern Case 3
described earlier except that the 8x8 pixel pattern is programmed in the mono pattern registers and
the pattern color is taken from the pattern foreground and background registers. For this example,
assume the height and width (in pixels) of the rectangle being copied are H and W. The screen color
depth is assumed to be 8 bits/pixel.
Autoexecute Off:


Autoexecute On:
Note
If the source bitmap is provided by the application, then the entire Note for the previous color pixels
case also applies to this mono pixel case because each line is required to be word aligned. If the source
bitmap is provided by the driver, e.g., font data, the driver should byte align the data and program bits
11-10 of the Command Set register to 00b to specify byte alignment to the Engine.

15.4.4.2 Rectangle Fill
This command draws a filled rectangle on the screen. Only ROPs that do not contain a source can be
used. If the ROP contains a pattern, the pattern specification will be ignored. Instead, the pattern value
is forced to a 1 by the hardware, selecting the pattern foreground color. ROPs specifying only the
destination (screen) and optionally a logical operation (e.g., NOT D) can be used. In this case, the
rectangle color will depend only on the current screen color. For this example, assume the height and
width (in pixels) of the rectangle being drawn are H and W. The screen color depth is assumed to be
8 bits/pixel.
Autoexecute Off:
ES:[MMA4F4] ⇐ DATA1 (7-0) ; 8-bit pattern foregnd color index

The following must be specified: ROP (bits 24-17), clipping enable (bit 1). Bits 4-2 will be different
for other color depths. Bit 8 must be set to 1 to specify a mono pattern.
Autoexecute On:

15.4.4.3 2D Line Draw
This command draws a two-dimensional line on the screen. Only ROPs that do not contain a source
can be used. If the ROP contains a pattern, the pattern specification will be ignored. Instead, the pattern
value is forced to a 1 by the hardware, selecting the pattern foreground color. ROPs specifying only
the destination (screen) and optionally a logical operation (e.g., NOT D) can be used. In this case, the
line color will depend only on the current screen color. Assume x1,y1 are the starting coordinates of
the requested line and x2,y2 are the ending coordinates. x1 and x2 are pixel coordinates, with 0 being
the x coordinate of the first (leftmost) pixel on each line. y1 and y2 are line coordinates, with 0 being
the coordinate of the first (topmost) line.
The S3d Engine draws 2D lines from the bottom up, regardless of the requested drawing direction.
Figure 15-3 shows four cases of requested lines (shown by the arrows on the grids). In Case 1, the
requested drawing direction is the same as is used by the S3d Engine, so the x1,y1 coordinates are
used to determine the starting coordinates (XSTART, YSTART). In Case 2, the line will be drawn by the
S3d Engine exactly reversed from that requested, so x2,y2 are used to determine the starting
coordinates. In these and the other two cases, the small arrows outside the grid point to the starting
coordinates used by the S3d Engine. The programmer must always use the end with the largest y value
as the starting point.
Another complexity is illustrated by Case 1. If the line is X MAJOR (i.e., for a given movement along
the line, the x value increases faster than the y value), the starting x value must be adjusted to the point
indicated by the intersection of the dashed lines. This is a 1/2 pixel (x direction) extension from the first
pixel to be drawn. For Y MAJOR lines (Case 4), this adjustment is not required.
The parameters required to draw a line must be calculated by software and programmed into the
appropriate registers. The first values that must be calculated are:
∆X = x2 - x1 or x1 - x2
∆Y = y2 - y1 or y1 - y2
The important point is that if x2 - x1 is used for ∆X, then y2 - y1 must be used for ∆Y and vice versa.
The parameters required are:
CASE 1 X+ CASE 2 X+ CASE 3 X+ CASE 4 X+

0,0 0,0 0,0 0,0
Y+ Y+ Y+ Y+
2DLINE
Figure 15-3. 2D Line Drawing Cases

X DELTA = - (∆X << 20)/∆Y (integer divide)
This is value is programmed in MMA970 with bit 31 as the sign bit (0 = positive)
X START = (xSTART << 20) + (X DELTA/2) for X MAJOR lines and positive X DELTA
X START = (xSTART << 20) + (X DELTA/2) + ((1 << 20) - 1) for X MAJOR lines and negative X DELTA
X START = (xSTART << 20) for Y MAJOR lines
This value is programmed in MMA974 with bits 31 and 30 as sign bits. The preceding discussion
describes how to determine xSTART.
Y START = ySTART
This value is programmed in MMA978_10-0. It is the y value of the first scan line and is always the
largest requested y.
Y COUNT = [abs (y2 -y1)] + 1
This value is programmed in MMA97C_10-0. It is the number of scanlines to draw.
The horizontal drawing direction is specified in MMA97C_31 (0 = right to left; 1 = left to right)
The final parameters to be specified are used primarily for the case where the programmer is drawing
a polyline (connected line segments) and specifies "last pixel not drawn" for one segment. This is done
so that the last pixel of one segment is not drawn a second time as the first pixel of the next segment.
The parameters are:
END1 = x coordinate for the last pixel to be drawn for the line (MMA96C_15-0)
END0 = x coordinate for the first pixel to be drawn for the line (MMA96C_31-0)
The both cases, the 5 most significant bits are sign bits and must be 0’s to indicate a positive value.
The complication here is again that the S3d Engine drawing direction may not be the same as the
requested direction. In Case 1 of Figure 15-3, the two directions are the same. If "last pixel off" is
specified, then END0 is programmed with the x1 (requested starting x) value and END1 with x2 -1 (one
X+
0,0
Y+ POLYLINE
Figure 15-4. Polyline Drawing Example

less than the requested ending x value to stop the line one pixel short). In Case 2, the directions are
opposite. END0 is programmed with x2 +1 and END1 with x1. Thus, the S3d Engine (which starts at
the requested ending x position so it can draw upward) skips the first pixel and draws the last to
accommodate the reversed drawing direction. In a similar fashion, is is easy to see that for Case 3,
END0 is x2 - 1 and END1 is x1. For Case 4, END0 is x1 and END1 is x2 +1.
If "last pixel off" is not requested, the END0 and END1 values are the same as described above except
that 1 is not added or subtracted as appropriate. Thus, the full x values of both ends of the line are
specified. This allows a horizontal line to be drawn. Normally, the X DELTA value for a horizontal line
would be infinity (∆Y = 0). For this case, the programmer can specify an X DELTA of 0 and the S3d
engine will use the endpoint parameters to draw the correct line.
The following programming example is for a polyline as shown in Figure 15-4. The first requested
segment goes up to the right with the last pixel not drawn. The second segment goes down to the right
with all pixels drawn. This first segment must be drawn first since it has the largest y value. It is drawn
as described for Case 1 in Figure 15-3 except the line is X MAJOR. The second line segment is drawn
as described for Case 3. This line is neither X MAJOR or Y MAJOR, so the Y MAJOR assumption should
be used because it is simpler to calculate X START. Autoexecute is used so that the Command Set
register does not need to be re-programmed.
; 1st line segment

ES:[MMA96C] ⇐ END0 (31-16), END1 (15-0) ; last pixel off for END1
ES:[MMA970] ⇐ X DELTA ; x direction gradient
ES:[MMA974] ⇐ X START ; starting x coord. for S3d Engine
ES:[MMA978] ⇐ Y START (10-0) ; starting y coord. for S3d Engine
ES:[MMA900] ⇐ 0001 100S SSSS SSS0 0000 0000 0010 00S1 ; Command Set (autoexecute)
ES:[MMA97C] ⇐ DIR (31), Y COUNT (10-0) ; draw dir and # of scanlines
; 2nd line segment
ES:[MMA96C] ⇐ END0 (31-16), END1 (15-0) ; all pixels drawn
ES:[MMA970] ⇐ X DELTA ; x direction gradient
ES:[MMA974] ⇐ X START ; starting x coord. for S3d Engine
ES:[MMA978] ⇐ Y START (10-0) ; starting y coord. for S3d Engine
ES:[MMA97C] ⇐ DIR (31), Y COUNT (10-0) ; draw dir and # of scanlines
Note that with autoexecute on (bit 0 of the Command Set register set to 1), a line is drawn every time
MMA97C is programmed. Also note that the Command Set register has a unique address for each
command type, e.g., it is at offset A900 for 2D lines while it is at A500 for BitBLTs and rectangle fills.
Only the ROP (bits 24-17) and clipping (bit 1) are optionally specified for line draws.
To draw a disconnected line after drawing a polyline, autoexecute must first be turned off. This is done
by writing to the Command Set register with bit 0 cleared to 0 and the command (bits 30-27) specified
as 1111b (NOP).

15.4.4.4 2D Polygon Fill
This command is used to generate a filled polygon. Any number of edges can be drawn, but the shape
must be such that any horizontal line must intersect the polygon edges in no more than two places.
The exception is that any edge can be horizontal. Only ROPs that do not contain a source can be used.
If the ROP contains a pattern, the pattern specification will be taken from the appropriate color or mono
pattern registers. ROPs specifying only the destination (screen) and optionally a logical operation (e.g.,
NOT D) can be used. In this case, the pixel color will depend only on the current screen color for the
destination pixel.
For polygon fills, the end points of each edge segment are not explicitly specified and cannot be
optionally drawn or not drawn. Drawing of the overlapping pixels is handled automatically. Also,
instead of specifying the direction of line drawing, the edge or edges to be updated are specified via
bits 28 and 29 of MMAD7C. Otherwise, the parameters for each line are calculated exactly as for 2D
lines.
∆X = x2 - x1 or x1 - x2
∆Y = y2 - y1 or y1 - y2
The important point is that if x2 - x1 is used for ∆X, then y2 - y1 must be used for ∆Y and vice versa.
The parameters required are:
X DELTA = - (∆X << 20)/∆Y (integer divide) - right and left edges
These values are programmed in MMAD68 and MMAD70 with bit 31 as the sign bit (0 = positive)
X START = (xSTART << 20) + (X DELTA/2) + (1 << 19) for X MAJOR lines - right and left edges
X START = (xSTART << 20) + (1 << 19) for Y MAJOR lines - right and left edges
These values are programmed in MMAD6C and MMAD74 with bits 31 and 30 as sign bits. The line
draw discussion describes how to determine xSTART.
Y START = ySTART
POLYFILL
Figure 15-5. Polygon Fill Example

This value is programmed in MMA978_10-0. It is the y value of the first scan line and is always the
largest requested y.
Y COUNT = [abs (y2 -y1)] + 1
This value is programmed in MMAD78_10-0. It is the number of scanlines to draw for each edge
segment.
The S3d Engine draws polygons from the bottom up as shown in the example in Figure 15-5. In the
first iteration, the programmer specifies line parameters for the left and right edges and specifies that
they both be updated. The first iteration also specifies the number of scan lines up to the first vertex,
which is on the left edge in this example. This results in the trapezoid shown in the leftmost example.
The second iteration only specifies the second segment of the left edge, resulting in the middle
example. Since the right edge does not change slope, it should not be re-specified or updated
(MMAD7C_28 = 0). This speeds the drawing by eliminating the need for a recalculation for that edge.
The third iteration draws the third segment of the left edge, which joins the right edge to complete the
polygon as shown by the right hand example. Again, the right edge should not be re-specified or
updated.
As with the bottom edge shown in the example, if the top edge is a horizontal line, that line does not
have to be drawn to close the polygon.
; 1st iteration
ES:[MMAD68] ⇐ RIGHT EDGE X DELTA ; right edge x direction gradient
ES:[MMAD6C] ⇐ RIGHT EDGE X START ; right edge starting x coord.
ES:[MMAD70] ⇐ LEFT EDGE X DELTA ; left edge x direction gradient
ES:[MMAD74] ⇐ LEFT EDGE X START ; left edge starting x coord.
ES:[MMAD78] ⇐ Y START (10-0) ; bottommost y value
ES:[MMAD00] ⇐ 0010 100S SSSS SSS0 0000 0000 0010 00S1 ; Command Set (autoexecute)
ES:[MMAD7C] ⇐ Update Lft (29), Update Rgt (28), Y COUNT (10-0) ; update edge and # of scanlines
; 2nd iteration
ES:[MMAD7C] ⇐ Update Lft (29), Update Rgt (28), Y COUNT (10-0) ; update edge(s) and # of scanli-
nes
; 3rd iteration
ES:[MMAD7C] ⇐ Update Lft (29), Update Rgt (28), Y COUNT (10-0) ; update edge and # of scanlines
Note that with autoexecute on (bit 0 of the Command Set register set to 1), a trapezoid fill is executed
every time MMAD7C is programmed. Also note that the Command Set register has a unique address
for each command type, e.g., it is at offset AD00 for 2D polygon fills while it is at A500 for BitBLTs and
rectangle fills and A900 for 2D lines. Only the ROP (bits 24-17) and clipping (bit 1) are optionally specified
for polygon fills.

15.4.5 3D Graphics Drawing
The S3d Engine accelerates the drawing of 3D lines and triangles. Texturing of 3D triangles and fogging
and alpha blending of both 3D lines and 3D triangles is also supported. This section describes the basic
3D drawing capabilities and the register values required to generate the desired image. Programming
code is quite complex for 3D operations and will be provided by S3 to customers desiring to create
custom drivers.
15.4.5.1 3D Line Drawing
3D line drawing is very similar to 2D line drawing except:
• There is a third (Z) dimension, with increasing values going away from the viewer (into the
screen). Like the X value, this is specified in fractional coordinates. (The Y value is always an
integer number of scan lines.) The registers associated with this dimension are 3dZ and
3ZStart and are used only when Z-buffering is desired.
• There are 4 color coordinates for the start of the line and associated color deltas. The color
values are Alpha (transparency/opacity factor), Red, Green and Blue. These are all expressed
as fractional values. The registers associated with these colors are 3dGdY_dBdY and
3dAdY_dRdY (deltas) and 3GS_BS and 3AS_RS (starts).
15.4.5.2 3D Triangle Drawing
Figure 15-6 represents a typical triangle drawn into the frame buffer. The grid represents pixel
coordinates, i.e., each intersection is the location of one pixel. The origin of the grid is at the top left
(0,0), with the X dimension increasing to the right and the Y dimension increasing downward. The
specified triangle does not have to start or end on a pixel coordinate, as illustrated in the figure.
Vertices 0 through 2 of the triangle to be drawn are numbered by decreasing Y value, i.e., from bottom
to top. The triangle is always rendered from bottom to top, starting at the first scan line at or above
the starting (bottom) vertex and ending at the last scan line at or below the ending (top) vertex. The
location of the 02 side (largest Y dimension) determines the horizontal rendering direction. For a
triangle as shown in Figure 15-6, with the 02 side on the left, rendering must be done from left to right.
This is specified by setting bit 31 of MMB517C to 1. If the triangle in Figure 15-6 is flipped horizontally
so the 02 side is on the right, the rendering direction must be specified as from right to left. This is
done by clearing bit 31 of MMB51C to 0.
As many as 43 registers may be required to completely specify the rendering of one 3D triangle with
texturing applied. These registers are described in Section 19. Figure 15-6 helps to explain the relevance
of most of these registers.
The following registers are associated with point A.
Spatial Dimensions (Point A) Color Dimensions (Point A) Texture Dimensions (Point A)

TXStart02 TGS_BS TDS
TYStart TAS_RS TUS
TZS02 TVS
TWS

X
0,0
Y
2
Y12
E
B
1
A Y01
3DTRGLE
C D
Figure 15-6. 3D Triangle Example
The following registers are associated with the Y axis and side 02. Note that the Y component of side
02 (B in Figure 15-6), always determines the number of scan lines required to render the triangle.
Spatial Dimensions (Y axis) Color Dimensions (Y axis) Texture Dimensions (Y axis)

TdXdY02 TdGdY_dBdY TdDdY
TdZdY TdAdY_dRdY TdUdY
TY01_Y12 TdVdY
TdWdY
The TXEnd01 register is associated with point C in Figure 15-6.

The following registers are associated with the X axis and side 01. Note that the X component of side
01 (D in Figure 15-6), is always the maximum width of the rendered triangle.
Spatial Dimensions (X axis) Color Dimensions (X axis) Texture Dimensions (X axis)

TdXdY01 TdGdX_dBdX TdDdX
TdZdX TdAdX_dRdX TdUdX
TdVdX
TdWdX
The TXEnd12 register is associated with point E in Figure 15-6.
The TdXdY12 register is associated with side 12 (F in Figure 15-6).
The TbU and TbV registers contain the common offset values for the U and V texture dimensions, i.e.,
these values are added to all U and V specifications.
Triangles can be drawn with perspective correction (bits 30-27 of the Command Set register = 0101 or
0110). Perspective correction uses the W parameters. In addition, the U and V parameters have different
bit codings when perspective correction is specified than when it is not. These are explained in the
register descriptions. Using automatic perspective correction will normally cause some decrease in
performance, but can in some circumstances provide dramatic increases in picture quality.
15.4.6 Z-Buffering
Z-buffering allows the programmer to eliminate rendering of hidden lines and surfaces. It is enabled
when bits 25-24 of the Command Set register are 00b and bits 22-20 of the Command Set register are
not 000b. Use of z-buffering requires that space be allocated in video memory for the z-buffer. The
starting location is specified in the Z_BASE register. For each graphics pixel, the z-buffer contains a
corresponding 16 bits of depth information. Bits 22-20 of the Command Set register specify the
relational operator used to compare the z value of the source pixel with its corresponding z-buffer
value, as follow:
000 = Z compare never passes

001 = Pass if Zs > Zzb
010 = Pass if Zs = Zzb
011 = Pass if Zs ≥ Zzb
100 = Pass if Zs < Zzb
101 = Pass if Zs ≠ Zzb
110 = Pass if Zs ≤ Zzb
111 = Z compare always passes
For example, a setting of 110 means that the source pixel will replace the current pixel in video memory
only if its source z value is less than the corresponding z-buffer value. This is the normal comparison,
as it allows the pixel closer to the viewer to be drawn. If bit 23 of the Command Set register is set to
1, the source pixel z value will replace the current z-buffer value. If bit 23 of the Command Set register
is cleared to 0, the z-buffer value remains unchanged.
The z-buffer comparison occurs before any of the pixel coloring operations described below. If the z
comparison fails, no further coloring operations will be done on that pixel. Similarly, if the operator is
set to never pass, z-buffering is effectively disabled. This can improve performance.

15.4.7 MUX Buffering
Z-buffering requires 16 bits of video memory storage for each displayable pixel. If insufficient memory
is available, MUX buffering may allow z-buffering to be performed. With MUX buffering, the active
frame buffer area (draw buffer) is alternately programmed with z-buffer values and pixel colors. This
requires that all the primitives (lines and triangles) of the scene be rendered twice, which decreases
performance. Otherwise, MUX buffering produces the effects as normal z-buffering.
MUX buffering can only be used when the destination format is 16 bits/pixel and no alpha blending is
to be performed (bit 19 of the Command Set register = 0). When the destination format is 16 bits/pixel,
bit 15 = 1 indicates the word contains a z value and bit 15 = 0 indicates the word contains an RGB555
value.
With MUX buffering, double buffering should be used so that the z-buffering can be done in the inactive
(back) buffer. See the Streams Processor section for an explanation of double buffering. Z-buffering is
enabled as explained in the previous section except that bit 23 of the Command Set register must be
set to 1 so that the source pixel z value will replace the current z-buffer value. As a final setup step, the
entire buffer must be written with either a solid color or a prerendered bitmap. This sets the z bit of
each word to 0, indicating that colors are stored.
On the first pass, bits 25-24 of the Command Set register are programmed to 01b to specify the z-buffer
pass. The S3d Engine interpolates only the z values of the the source primitive (line or triangle). For
each source pixel, if the corresponding destination pixel is a color (bit 15 = 0), the source z value replaces
the destination color. For the first primitive to be drawn for the scene, the source pixels (z values) will
replace all the corresponding destination pixels (colors) because of the initialization to colors. For
subsequent primitives for the scene, the source pixel may or may not replace the destination pixel. It
will always replace it if the destination is a color, but if the destination is a z-value, it will only replace
it if the z comparison passes. At the end of this pass, all pixels corresponding to primitives are set to
z values. All other pixels retain the initialization color values.
For the second pass, bits 25-24 of the Command Set register are programmed to 10b to specify the
draw buffer pass. The S3d Engine again interpolates the z values for all source primitives. If the
destination pixel is a color, that pixel color is left unchanged. If the destination pixel is a z value, the
source z value is compared with the destination z value. If they are equal, the source color is computed
and that color value replaces the destination z value. At the end of this pass, all pixels in the buffer
contain color values. The buffer is then switched to the front (active) and is used for the next screen
refresh.
15.4.8 3D Pixel Color Generation
Pixel color generation for 3D drawing occurs in a series of steps as depicted in Figure 15-7. The first of
these, calculate the source pixel color, has been explained in the 3D line and triangle drawing sections
above. The remaining steps are:
1. Filter - If texturing is enabled for a 3D triangle, two, four or eight texels (texture pixel) from the
texture map can be filtered (interpolated) to generate a texture color to be mixed with the
source color in step 3 or a code to be used in the next step.
2. Generate - For certain applications, textures can be stored in a compact colorless mode (Blend4).
This step generates a texture color based on the compact coding, which may or may not be
the output of filtering from the previous step. This color is used in the next step.

3. Light - If a lit texture triangle is specified, the source pixel color is mixed with the texel color to
generate a color which can optionally be fogged or alpha blended.
4. Fog - Also called depth cueing. As shown in Figure 15-7, the input can either be the source pixel
color or the result of the filter/generate steps.
5. Alpha Blend - The source pixel color or the output of the fogging step (which may be disabled)
is blended with the destination pixel color in video memory. This can produce a transparency
effect.
Each of these steps is explained in more detail in the following sections.
15.4.8.1 Texture Filtering
Textures are stored in off-screen video memory at a location specified in MMB4EC. The integer
components of the U and V parameters generate the memory addresses for each texture element,
which is called a texel. The fractional part of the U and V parameters are used in the filter stage for
interpolation between texel colors. The texture color format is specified in bits 7-5 of the Command
Set register and can be one of the following:
000 = 32 bits/pixel (ARGB8888)

011 = 8 bits/pixel (Alpha4, Blend4)
100 = 4 bits/pixel (Blend4, low nibble)
101 = 4 bits/pixel (Blend4, high nibble)
110 = 8 bits/pixel (palettized)
111 = YU/YV (16 bits/pixel equivalent)
DRAW DRAW DRAW LIT TRIANGLE DRAW DRAW

LINE LIT TRIANGLE USING BLEND4 UNLIT TRIANGLE GOURAUD TRIANGLE
FILTER TEXTURE FILTER
GENERATE
LIGHT
FOG
ALPHA
BLEND
DRAW
PIXCOLOR
BUFFER
Figure 15-7. Pixel Coloring

The texture can be a single rectangular pattern or a mipmap. A mipmap contains multiple versions of
the same texture, each at successively lower resolutions (1/2, 1/4, 1/8, etc.). The size of the largest
mipmap level (level 0) must be specified via bits 11-8 of the Command Set register. The integer part
of the D parameter points to the mipmap level to be used for the texture. The fractional part of the D
parameter is used for filtering of colors between mipmap levels.
A variety of filter modes are provided via bits 14-12 of the Command Set register, as follows:
000 = M1TPP (MIP_NEAREST)

001 = M2TPP (LINEAR_MIP_NEAREST)
010 = M4TPP (MIP_LINEAR)
011 = M8TPP (LINEAR_MIP_LINEAR)
100 = 1TPP (NEAREST)
101 = V2TPP (used for YU/YV video format)
110 = 4TPP (LINEAR)
110 = Reserved
Modes starting with M are mipmapped. Those without have a single texture level. XTPP means X texels
are interpolated per source pixel. Figure 15-8 demonstrates the effect of the 011 setting (M8TPP). The
U,V and D parameters point to the texture map location indicated by the black dot at F. To generate
the color for this location, the four nearest pixels in mipmap level D (1 - 4) are interpolated to generate
the color indicated by the top medium gray dot (I1). The four nearest pixels in mipmap level D + 1 (5 -
8) are interpolated to generate the color indicated by the bottom medium gray dot (I2). The colors at
I1 and I2 are then interpolated to produce the final color at F.
If M1TPP or 1TPP is selected, the texel nearest to the programmed texture location is chosen to provide
the texture color. For M2TPP, the color is interpolated between the nearest texels from 2 mipmap levels
(e.g., texels 1 and 5 in Figure 15-8). For M4TPP or 4TPP, texels 1, 2 , 3 and 4 are interpolated. For V2TPP,
which is used only for YUV data, texels 1 and 3 are interpolated.
V MIPMAP LEVEL D
1 2
I1
3 4
U F
6
5
I2
PTEX
7 8
MIPMAP LEVEL D + 1
Figure 15-8. Texture Filtering

Filtering of 8 bits/pixel palettized data produces uncertain results. Palettized texel colors can be used
if the filter mode is M1TPP or 1TPP (only one texel is used to generate the color) and the texture blending
mode (lighting) is specified as decal. This means the texel color replaces the source pixel color (no
mixing). Because the color is now palettized, it cannot be texture lit, fogged or alpha blended.
15.4.8.2 Generation
ViRGE provides several compact texture storage modes, called Blend4 (high and low nibble) and
Alpha4/Blend4. Blend4 uses 4 bits to define the color for each texel. These bits can be in either the high
or low nibble of each byte, allowing the programmer to locate texels from two different textures in a
single byte. Alpha4/Blend4 has 4 bits of Alpha coding and 4 bits of RGB color coding in each byte.
Blend4 is useful for textures with a narrow range of colors, such as grass. The 4-bit value is an
interpolation factor between two RGB colors defined in the Color 0 (MMB4F8) and Color1 (MMB4FC)
registers.
Alpha4/Blend4 is useful for textures with a limited range of colors and transparency, such as a cloudy
sky. In this case, there are a few shades of blue-white, with whiter clouds being more opaque than
bluer sky. Alpha blending is explained below.
Generation of colors for Blend4 modes occurs after the filter phase. Therefore it is possible to filter
multiple Blend4 texels to produce a composite color interpolation factor to be used in the generate
phase. The results of this might be hard to predict. The filter phase can be bypassed by selecting a
1TPP filter mode.
15.4.8.3 Lighting
Lighting is the blending of the texel color with the source pixel color. As seen in Figure 15-7, it is used
only when a lit triangle is specified in bits 30-27 of the Command Set register. Bits 16-15 of the
Command Set register specify the blending modes as follows:
00 = Complex reflection
01 = Modulate
10 = Decal
11 = Reserved
Complex reflection adds the (normalized, 0 = black and 1 = white) texel and pixel colors, with a
maximum value of 1. This lightens the pixel.
Modulate multiplies the normalized color values. This results in a smaller value (darker pixel). The
programmer may need to compensate for this darkening effect.
Decal replaces the source pixel color with the texel color, essentially overlaying the texture on the
scene. This is the only mode that can be used with palettized data.
If the texture map is smaller than the area to be textured, texture wrapping can be turned on via bit 26
of the Command Set register. This allows the texture to be tiled across the scene. If texture wrapping
is disabled and and the texture map is smaller than the area to be textured, the texel color is taken
from the Texture Border Color register (MMB4F0) for all pixels beyond the texture.

15.4.8.4 Fogging
Fogging is enabled via bit 17 of the Command Set register. This operation uses the pixel’s alpha value
to interpolate between the pixel color at this stage of the coloring process (see Figure 15-7) and a fog
color specified in MMB(0/4)F4. If the alpha value corresponds to the distance from the viewer, this is
called depth cueing. If fogging is being done, source alpha cannot be specified for alpha blending (i.e.,
bits 19-18 of the Command set register cannot be 11b).
15.4.8.5 Alpha Blending
Alpha blending blends the pixel color at this stage of coloring (see Figure 15-7) with the color of the
corresponding pixel in the draw buffer. It is enabled via bits 19-18 of the Command Set register. If these
bits are 10b, the texture alpha is used for the interpolation factor. The texture alpha is actually the alpha
for the pixel at this stage of the coloring and not a texel alpha. If bits 19-18 are 11b, the source alpha
is used for the interpolation factor. This is the original pixel alpha before texturing.
Alpha blending is used for transparency effects. The smaller the value of alpha, the more the destination
color will dominate the final color (or higher transparency). To be effective with Z-buffering enabled,
all opaque objects must be drawn first. Then all transparent objects are drawn with z-update disabled
(MMB500_23 = 0). To be effective with Z-buffering disabled, objects must be drawn back to front.

15.5 PROGRAMMABLE HARDWARE CURSOR
A programmable cursor is supported which is compatible with the Microsoft Windows (bit 4 of CR55
= 0) and X11 (bit 4 of CR55 = 1) cursor definitions. The cursor size is 64 pixels wide by 64 pixels high,
with the cursor pattern stored in an off-screen area of display memory. Two monochrome images 64
bits wide by 64 bits high (512 bytes per image) define the cursor shape. The first bit image is an AND
mask and the second bit image is an XOR mask. The following is the truth table for the cursor display
logic.
AND Bit XOR Bit Displayed (Microsoft Windows) Displayed (X11)

0 0 Cursor Background Color Current Screen Pixel
0 1 Cursor Foreground Color Current Screen Pixel
1 0 Current Screen Pixel Cursor Background Color
1 1 NOT Current Screen Pixel Cursor Foreground Color
The hardware cursor color is taken from the Hardware Graphics Cursor Foreground Stack (CR4A) and
the Hardware Graphics Cursor Background Stack (CR4B) registers. Each of these is a stack of three 8-bit
registers. The stack pointers are reset to 0 by reading the Hardware Graphics Cursor Mode register
(CR45). The color value is then programmed by consecutive writes (low byte, second byte, third byte)
to the appropriate (foreground or background) register.
Enabling/Disabling the Cursor
The hardware cursor is disabled when a VGA-compatible mode is in use. It can be enabled or disabled
when in Enhanced mode (bit 0 of MM8508 = 1), as follows.
CR39 ⇐ A0H ; Unlock System Control registers

CR45_0 ⇐ 1 ; Enable hardware cursor
CR45_0 ⇐ 0 ; Disable hardware cursor
CR39 ⇐ 00H ; Lock System Control registers
Positioning the Cursor
The cursor can be positioned at any point on the display, with the X,Y coordinates ranging from 0 to
2047. This enables the full cursor images to be displayed on the screen and partial cursor images to
be displayed at the right edge and the bottom edge of the screen. The cursor offset OX,OY has to be
set to 0,0 for a 1024x768 resolution. If X is > (1024 – 64) or Y is > (768 – 64), then a partial cursor is
visible at the right edge or top edge of the screen respectively. Note that if Y ≥ 768 then the cursor is
not visible; it is residing in the off-screen area.
A partial cursor image can be displayed at the left edge or the top edge of the screen. To enable partial
cursor display at the top edge of the screen, Y is set to 0 and the Y offset register is set to OY (range
from 0 to 63). This displays the bottom 64–OY rows of the cursor image at the currently set X position
and the top edge of the screen. Similarly, a partial cursor can be displayed at the left edge of the screen
by setting X to 0 and the X offset register to OX (range from 0 to 63). This displays the right 64–OX
columns of the cursor image at the currently set X and the left edge of the screen. The following
pseudocode illustrates cursor positioning.

CR46_10-8 ⇐ MS 3 bits of X cursor position
CR47_7-0 ⇐ LS 8 bits of X cursor position

CR48_10-8 ⇐ MS 3 bits of Y cursor position

CR49_7-0 ⇐ LS 8 bits of Y cursor position
CR4E_5-0 ⇐ Cursor Offset X position
CR4F_5-0 ⇐ Cursor Offset Y position
CR39 ⇐ 00H ; Lock System Control registers
The cursor position is updated by the hardware once each frame. Therefore, the programmer should
ensure that the position is re-programmed no more than once for each vertical sync period.
Programming the Cursor Shape
The AND and the XOR cursor image bitmaps are 512 bytes each. These bitmaps are word interleaved
in a contiguous area of display memory, i.e., AND word 0, XOR word 0, AND word 1, XOR word 1 ...
AND word 255, XOR word 255. The starting location must be on a 1024-byte boundary. This location
is programmed into the Hardware Graphics Cursor Start Address registers (CR4C and CR4D) as follows:

CR4C_5-8 ⇐ MS 4 bits of the cursor storage start 1024-byte segment.
CR4D ⇐ LS 8 bits of the cursor storage start 1024-byte segment
CR39 ⇐ 0 ; Lock System Control registers
The value programmed is the 1024-byte segment of display memory at which the beginning of the
hardware cursor bit pattern is located. For example, for an 800x600x8 mode on a 1 MByte system,
there are 1024 1K segments. Programming CR4C_11-8 with 3H and CR4D with FEH specifies the starting
location as the 1022nd (0-based) 1K segment. The cursor pattern is programmed (using linear
addressing) at FF800H offset from the base address of the frame buffer.
Note
If the cursor is not 64 bits by 64 bits, the given images should be padded to make the cursor image 64
bits by 64 bits. The padded area should be made transparent by padding the extra AND mask bits with
‘1’s and the extra XOR bits by ‘0’s.

15.6 BUS MASTER DMA
For PCI systems, ViRGE provides bus master DMA capabilities. There are two independent DMA
channels. One handles transfers of video data to video memory or an MPEG decoder and from video
memory to system memory. The other is used to transfer command and parameter or image data to
the S3d Engine.
15.6.1 Video/Graphics DMA Transfers
These transfers are enabled by setting MM8588_0 to 1. If MM8580_1 = 1, data is transferred from system
memory to the LPB output FIFO. This can be compressed video data for transfer to an MPEG decoder
or de-compressed software MPEG data to be written to video memory with optional decimation. See
the LPB section for the appropriate register settings for each type of transfer. For either case, the starting
address in system memory for the data to be transferred is programmed in MM8580_31-2 (doubleword
aligned). The number of doublewords to transfer -1 is programmed in MM8584_23-2.
If MM8580_1 = 0, data is transferred from video memory to system memory. The starting address in
video memory is programmed in MM8220_21-3 (quadword aligned). The line width in quadwords is
programmed in MM8224_27-19 and the line stride in quadwords is programmed in MM8224_11-3. The
destination starting address in system memory is programmed in MM8580_31-2 (doubleword aligned).
The number of doublewords to transfer -1 is programmed in MM8584_23-2.
15.6.2 S3d Engine Command/Parameter/Image Data DMA Transfers
The type of transfer requires establishment of a locked circular buffer in system memory. MM8590_1
defines this buffer as being 4 or 64 KBytes. The base address for the buffer is programmed in
MM8590_31-12 (4K) or 31-16 (64K). S3d Engine DMAs are enabled by setting MM859C_0 to 1.
The DMA write and read pointer registers (MM8594 and MM8598) are initialized to all 0’s. The transfer
sequence begins with the CPU writing some amount of data to the buffer. This data is derived from
the parameter blocks passed to the driver by the application via the programming interface. In general,
the transfer should include one or more complete command/parameter/data blocks. After this data is
written to the buffer, the next offset address in the frame buffer is programmed into the DMA write
pointer field (MM8594_15-0) and MM8594_16 is set to 1 to indicate that the write pointer has been
updated. When the write pointer is ahead of the read pointer (MM8598_15-0), DMA transfers to the
S3d Engine begin. The read pointer field is automatically updated as each doubleword transfer to the
S3d Engine is made. DMA transfers will continue as long as the write pointer is ahead of the read
pointer. They stop when the read pointer equals the write pointer.
Additional data can be written to the buffer at any time, starting at the current write pointer address.
Wrapping of the writes when the end of the buffer is reached is handled by the programmer. Before
writing additional data to the buffer, the programmer must first read the read pointer to determine
how much space is available in the buffer. If this is not done, the write data could wrap and overwrite
good data before it is read from the buffer.

Each update of the circular buffer must start with a doubleword header that defines what is to follow.
The format of this header is:
Bit(s) Description
15-0 Number of doublewords to transfer
29-16 Most significant 14 bits of the least significant 16 bits of the offset of the first S3d register
to be programmed
30 Reserved
31 Data type (0 = register data, 1 = image data)
If image data is being transferred (a BitBLT with the CPU as the source), only bit 31 (=1) and bits 15-0
need be programmed.
This capability allows updating of multiple S3d registers in one DMA operation. For example, defining
a color pattern with an 8 bits/pixel color depth requires that all registers from A100H to A13CH be
programmed. Thus, bits 15-0 would be programmed with 16 (decimal). The most significant 14 bits of
A100H (dropping the two low-order 0’s) are programmed into bits 29-16. Bit 31 is cleared to 0.
The parameter register address ranges for some of the commands contain "holes" (no register). The
programmer can either send a new header for each contiguous register sequence or program garbage
in the doublewords corresponding to the holes. For example, there is a single doubleword gap between
the 3AS_RS parameter register for a 3D line and the 3dZ parameter register. This is probably best
handled by the "garbage" technique.

Section 16: VGA Standard Register Descriptions
In the following register descriptions, ‘U’ stands for undefined or unused and ‘R’ stands for reserved
(write = 0, read = U). A question mark in an address stands for a hexadecimal value of either ‘B’ or ‘D’.
If bit 0 of the Miscellaneous Output Register (3C2H, Write) is set to 1, the address is based at 3DxH for
color emulation. If this bit is reset to 0, the address is based at 3BxH for monochrome emulation.
See Appendix A for a table listing each register in this section and its page number.
16.1 GENERAL REGISTERS
This section describes general input status and output control registers.
Miscellaneous Output Register (MISC)
Write Only Address: 3C2H

Read Only Address: 3CCH
Power-On Default: 00H
This register controls miscellaneous output signals. A hardware reset sets all bits to zero.
7 6 5 4 3 2 1 0
CLK SEL ENB IOA
VSP HSP PGSL =0 1 0 RAM SEL
Bit 0 IOA SEL - I/O Address Select

0 = Monochrome emulation. Address based at 3Bx
1 = Color emulation. Address based at 3Dx
Bit 1 ENB RAM - Enable CPU Display Memory Access

0 = Disable access of the display memory from the CPU
1 = Enable access of the display memory from the CPU
VGA REGISTER DESCRIPTIONS 16-1

Bits 3–2 Clock Select - Select the Video Clock Frequency

00 = Selects 25.175 MHz DCLK for 640 horizontal pixels
01 = Selects 28.322 MHz DCLK for 720 horizontal pixels
10 = Reserved
11 = Enables loading of DCLK PLL parameters in SR12 and SR13.
A setting of either 00b or 01b causes the appropriate values to be programmed into
the DCLK PLL registers if bit 1 of SR15 is set to 1.
Bit 4 Reserved = 0
Bit 5 PGSL -Select High 64K Page

0 = Select the low 64K page of memory
1 = Select the high 64K page of memory
Bit 6 HSP - Select Negative Horizontal Sync Pulse

0 = Select a positive horizontal retrace sync pulse
1 = Select a negative horizontal retrace sync pulse
Bit 7 VSP - Select Negative Vertical Sync Pulse

0 = Select a positive vertical retrace sync pulse
1 = Select a negative vertical retrace sync pulse
Feature Control Register (FCR_WT, FCR_AD)
Write Only Address: 3?AH

Read Only Address: 3CAH
7 6 5 4 3 2 1 0
=0 =0 =0 =0 VSSL =0 =0 =0
Bits 2–0 Reserved = 0
Bit 3 VSSL - Vertical Sync Type Select

0 = Enable normal vertical sync output to the monitor
1 = The ‘vertical sync’ output is the logical OR of ‘vertical sync’ and ‘vertical active
display enable’ (an internal signal)
16-2 VGA REGISTER DESCRIPTIONS

Input Status 0 Register (STATUS_0)
Read Only Address: 3C2H

Power-On Default: Undefined
This register indicates the status of the VGA adapter.
7 6 5 4 3 2 1 0
CRT MON
INTPE =0 =0 SENS =0 =0 =0 =0
Bit 4 MON SENS - Monitor Sense Status

0 = The internal SENSE signal is a logical 0
1 = The internal SENSE signal is a logical 1
Bit 7 CRT INTPE - CRT Interrupt Status

0 = Vertical retrace interrupt cleared
1 = Vertical retrace interrupt pending
See Section 12.7 for an explanation of interrupt generation.
Input Status 1 Register (STATUS_1)
Read Only Address: 3?AH

This register indicates video sync timing and video wraparound.
7 6 5 4 3 2 1 0
TST-VDT
=0 =0 1 0 VSY =1 LPF DTM
Bit 0 DTM - Display Mode Inactive

0 = The display is in the display mode.
1 = The display is not in the display mode. Either the horizontal or vertical retrace
period is active
Bit 1 Reserved = 0
Bit 2 Reserved = 1
Bit 3 VSY - Vertical Sync Active

0 = Display is in the display mode
1 = Display is in the vertical retrace mode

Bits 5–4 TST-VDT - Video Signal Test

Video Data Feedback 1,0. These bits are feedback video signals to do read back tests.
These bits are selectively connected to two of the eight color outputs of the attribute
controller. Bits 5 and 4 of the color plane enable register (AR12) control the multi-
plexer for this video output observation.
Video Subsystem Enable Register
Read/Write Address: 3C3H

7 6 5 4 3 2 1 0
VGA
R R R R R R R ENB
Bit 0 VGA ENB - VGA Enable

0 = VGA display disabled
1 = VGA display enabled
Bits 7–1 Reserved

16.2 SEQUENCER REGISTERS
The sequencer registers are located at two-byte address spaces. These registers are accessed by first
writing the data to the index register of the sequencer at I/O address 3C4H and then writing to or reading
from the data register at 3C5H.
Sequencer Index Register (SEQX)

This register is loaded with a binary value that indexes the sequencer register for read/write data. This
value is referred to as the “Index Number” of the SR register in this document.
7 6 5 4 3 2 1 0
R R R SEQ ADDRESS
Bits 4–0 SEQ ADDRESS - Sequencer Register Index

A binary value indexing the register where data is to be accessed.
Bits 7–5 Reserved
Sequencer Data Register (SEQ_DATA)

This register is the data port for the sequencer register indexed by the Sequencer Index register (3C4H).
7 6 5 4 3 2 1 0
SEQ DATA
Bit 7–0 SEQ DATA - Sequencer Register Data

Data to the sequencer register indexed by the sequencer address index.

Reset Register (RST_SYNC) (SR0)
Read/Write Address: 3C5H, Index 00H

7 6 5 4 3 2 1 0
SYN ASY
=0 =0 =0 =0 =0 =0 RST RST
Bit 0 ASY RST - Asynchronous Reset
This bit is for VGA software compatibility only. It has no function for ViRGE.
Bit 1 SYN RST - Synchronous Reset
This bit is for VGA software compatibility only. It has no function for ViRGE.
Clocking Mode Register (CLK_MODE) (SR1)

This register controls the operation mode of dot clock and character clock.
7 6 5 4 3 2 1 0
SCRN SHF DCK SHF
=0 =0 OFF 4 1/2 LD =0 8DC
Bit 0 8DC - 8 Dot Clock Select

0 = Character clocks 9 dots wide are generated
1 = Character clocks 8 dots wide are generated
Bit 1 Reserved = 0
Bit 2 SHF LD - Load Serializers Every Second Character Clock

0 = Load the video serializer every character clock
1 = Load the video serializers every other character clock
Bit 3 DCK 1/2 - Internal Dot Clock = 1/2 DCLK

0 = Set the internal dot clock to the same frequency as DCLK
1 = Set the internal dot clock to 1/2 the frequency of DCLK
This bit is used for horizontal pixel doubling.

Bit 4 SHF 4 - Load Serializers Every Fourth Character Clock

0 = Load the serializers every character clock cycle
1 = Load the serializers every fourth character clock cycle
Bit 5 SCRN OFF - Screen Off

0 = Screen is turned on.
1 = Screen is turned off
Bit 7–6 Reserved = 0
Enable Write Plane Register (EN_WT_PL) (SR2)

This register selects write protection or write permission for CPU write access into video memory.
7 6 5 4 3 2 1 0
=0 =0 =0 =0 EN.WT.PL.
Bits 3–0 EN.WT.PL - Enable Write to a Plane

0 = Disables writing into the corresponding plane
1 = Enables the CPU to write to the corresponding color plane

Character Font Select Register (CH_FONT_SL) (SR3)

7 6 5 4 3 2 1 0
SLA SLB SLA SLB
=0 =0 2 2 1 0 1 0
In text modes, bit 3 of the attribute byte normally turns the foreground intensity on or off. This bit can
be redefined to be a switch between two character sets. The switch is enabled when there is a difference
between the value of character font select A and character font select B bits. Memory Mode (SR4)
register bit 1 = 1 (extended memory) enables all bits of this function; otherwise character fonts 0 and
4 are available. 256 KBytes of video memory support 8 character sets. This register is reset to 0
asynchronously during a system reset.
Bits 4, 1–0 SLB - Select Font B

This value selects the portion of plane 2 used to generate text character fonts when
bit 3 of the attribute byte is a logical 1, according to the following table:
Bits Font Table Location Bits Font Table Location

4,1,0 4, 1,0
000 First 8K of plane 2 100 Second 8K of plane 2
001 Third 8K of plane 2 101 Fourth 8K of plane 2
010 Fifth 8K of plane 2 110 Sixth 8K of plane 2
011 Seventh 8K of plane 2 111 Eighth 8K of plane 2
Bits 5, 3–2 SLA - Select Font A

This value selects the portion of plane 2 used to generate text character fonts when
bit 3 of attribute byte is a logical 0, according to the same table as the character font
select A.

Memory Mode Control Register (MEM_MODE) (SR4)

This register controls CPU memory addressing mode.
7 6 5 4 3 2 1 0
CHN SEQ EXT
=0 =0 =0 =0 4M MODE MEM =0
Bit 0 Reserved = 0
Bit 1 EXT MEM - Extended Memory Access

0 = Memory access restricted to 16/32 KBytes
1 = Allows complete memory access to 256 KBytes. Required for VGA
Bit 2 SEQ MODE - Sequential Addressing Mode

This bit affects only CPU write data accesses into video memory. Bit 3 of this register
must be 0 for this bit to be effective.
0 = Enables the odd/even addressing mode. Even addresses access planes 0 and 2.
Odd addresses access planes 1 and 3
1 = Directs the system to use a sequential addressing mode
Bit 3 CHN 4M - Select Chain 4 Mode

0 = Enables odd/even mode.
1 = Chain 4 Mode. This bit selects modulo 4 addressing for CPU access to display
memory. A logical 1 directs the two lower order bits of the CPU address used to
select the plane in video memory to be accessed as follows:
A1 A0 Plane Selected
0 0 0
0 1 1
1 0 2
1 1 3

16.3 CRT CONTROLLER REGISTERS
The CRT controller registers are located at two locations in I/O address space. These registers are
accessed by first writing to the index register of the CRT controller and then accessing the data register.
The index register is located at I/O address 3?4H and the CRT Controller Data register is at 3?5H. Which
address is used (3BX or 3DX) depends on bit 0 of the Miscellaneous Output register at 3C2H.
CRT Controller Index Register (CRTC_ADR) (CRX)
Read/Write Address: 3?4H

This register is loaded with a binary value that indexes the CRT controller register where data is to be
accessed. This value is referred to as the “Index Number” of the CR register (CR00–18). This register
is also used as an index to the S3 VGA registers, the System Control Registers and the System Extension
registers.
7 6 5 4 3 2 1 0
CRTC ADDRESS
Bits 7–0 CRTC ADDRESS - CRTC Register Index

CRT Controller Data Register (CRTC_DATA) (CRT)
Read/Write Address: 3?5H

This register is the data port for the CRT controller register indexed by the CRT Controller Address
register.
7 6 5 4 3 2 1 0
CRTC DATA
Bits 7–0 CRTC DATA - CRTC Register Data

Data to the CRT controller register indexed by the CRT controller address index.

Horizontal Total Register (H_TOTAL) (CR0)
Read/Write Address: 3?5H, Index 00H

This register defines the number of character clocks from HSYNC going active to the next HSYNC going
active. In other words, it is the total time required for both the displayed and non-displayed portions
of a single scan line. Bit 8 of this value is bit 0 of CR5D.
7 6 5 4 3 2 1 0
HORIZONTAL TOTAL
Bits 7–0 HORIZONTAL TOTAL.

9-bit Value = (number of character clocks in one scan line) - 5. This register contains
the least significant 8 bits of this value.
Horizontal Display End Register (H_D_END) (CR1)

This register defines the number of character clocks for one line of the active display. Bit 8 of this value
is bit 1 of CR5D.
7 6 5 4 3 2 1 0
HORIZONTAL DISPLAY END
Bits 7–0 HORIZONTAL DISPLAY END

9-bit Value = (number of character clocks of active display) - 1. This register contains
the least significant 8 bits of this value.

Start Horizontal Blank Register (S_H_BLNK) (CR2)

This register specifies the value of the character clock counter at which the BLANK signal is asserted.
Bit 8 of this value is bit 2 of CR5D.
7 6 5 4 3 2 1 0
START HORIZONTAL BLANK
Bits 7–0 START HORIZONTAL BLANK

9-bit Value = character clock value at which horizontal blanking begins. This register
contains the least significant 8 bits of this value.
End Horizontal Blank Register (E_H_BLNK) (CR3)

This register determines the pulse width of the BLANK signal and the display enable skew.
7 6 5 4 3 2 1 0
DSP-SKW
R 1 0 END HORIZONTAL BLANK
Bits 4–0 END HORIZONTAL BLANK

7-bit Value = least significant 7 bits of the character clock counter value at which time
horizontal blanking ends. To obtain this value, add the desired BLANK pulse width in
character clocks to the Start Horizontal Blank value, which is also in character clocks.
The 5 least significant bits of this sum are programmed into this field. The sixth bit is
programmed into bit 7 of CR5. The seventh bit is programmed into bit 3 of CR5D.
Bits 6–5 DSP-SKW - Display Skew

These two bits determine the amount of display enable skew. Display enable skew
control provides sufficient time for the CRT Controller to access the display buffer to
obtain a character and attribute code, access the character generator font, and then
go through the Horizontal Pixel Panning register in the Attribute Controller. Each ac-
cess requires the display enable signal to be skewed one character clock unit so the
video output is synchronous with the HSYNC and VSYNC signals. The bit values and
amount of skew are shown in the following table:
00 = Zero character clock skew
01 = One character clock skew
10 = Two character clock skew
11 = Three character clock skew
Bit 7 Reserved

Start Horizontal Sync Position Register (S_H_SY_P) (CR4)

This register is used to adjust the screen center horizontally and to specify the character position at
which HSYNC becomes active. Bit 8 of this value is bit 4 of CR5D.
7 6 5 4 3 2 1 0
START HORIZONTAL SYNC POSITION
Bits 7–0 START HORIZONTAL SYNC POSITION.

9-bit Value = character clock counter value at which HSYNC becomes active. This reg-
ister contains the least significant 8 bits of this value.
End Horizontal Sync Position Register (E_H_SY_P) (CR5)

This register specifies when the HSYNC signal becomes inactive and the horizontal skew. The HSYNC
pulse defined by this register can be extended by 32 DCLKs via bit 5 of CR5D.
7 6 5 4 3 2 1 0
EHB HOR-SKW
b5 1 0 END HORIZONTAL SYNC POS
Bits 4–0 END HORIZONTAL SYNC POS

6-bit Value = 6 least significant bits of the character clock counter value at which time
HSYNC becomes inactive. To obtain this value, add the desired HSYNC pulse width in
character clocks to the Start Horizontal Sync Position value, also in character clocks.
The 5 least significant bits of this sum are programmed into this field. The sixth bit is
programmed into bit 5 of CR5D.
Bits 6–5 HOR-SKW - Horizontal Skew

These bits control the skew of the HSYNC signal. A binary 00 equals no HSYNC delay.
For some modes, it is necessary to provide an HSYNC signal that takes up the entire
blanking interval. Some internal timings are generated by the falling edge of the
HSYNC signal. To guarantee the signals are latched properly, HSYNC is asserted be-
fore the end of the display enable signal, and then skewed several character clock
times to provide the proper screen centering.
Bit 7 EHB b5
End Horizontal Blanking bit 5.

Vertical Total Register (V_TOTAL) (CR6)

This register specifies the number of scan lines from one VSYNC active to the next VSYNC active.
The scan line counter resets to 0 at this point. Bit 8 is bit 0 of CR7. Bit 9 is bit 5 of CR7. Bit 10 is bit 0
of CR5E.
7 6 5 4 3 2 1 0
VERTICAL TOTAL
Bits 7–0 VERTICAL TOTAL

11-bit Value = (number of scan lines from VSYNC active to the next VSYNC active) - 2.
This register contains the least significant 8 bits of this value.
CRTC Overflow Register (OVFL_REG) (CR7)

7 6 5 4 3 2 1 0
VRS VDE VT LCM SVB VRS VDE VT
9 9 9 8 8 8 8 8
This register provides extension bits for fields in other registers.
Bit 0 Bit 8 of the Vertical Total register (CR6)
Bit 1 Bit 8 of the Vertical Display End register (CR12)
Bit 2 Bit 8 of the Vertical Retrace Start register (CR10)
Bit 3 Bit 8 of the Start Vertical Blank register (CR15)
Bit 4 Bit 8 of the Line Compare register (CR18)
Bit 5 Bit 9 of the Vertical Total register (CR6)
Bit 6 Bit 9 of the Vertical Display End register (CR12)
Bit 7 Bit 9 of the Vertical Retrace Start register (CR10)

Preset Row Scan Register (P_R_SCAN) (CR8)

This register is used for the pixel scrolling and panning, and text formatting and vertical scrolling.
7 6 5 4 3 2 1 0
BYTE-PAN
=0 1 0 PRE-SET ROW SCAN COUNT
Bits 4–0 PRE-SET ROW SCAN COUNT

Value = starting row within a character cell for the first character row displayed after
vertical retrace. This allows a partial character row to be displayed at the top of the
display and is used for scrolling.
Bits 6–5 BYTE-PAN

Value = number of bytes to pan. The number of pixels to pan is specified in AR13.
Bit 7 Reserved = 0
Maximum Scan Line Register (MAX_S_LN) (CR9)

This register specifies the number of scan lines per character row and provides one scanning control
bit and two overflow bits.
7 6 5 4 3 2 1 0
DBL LCM SVB
SCN 9 9 MAX SCAN LINE
Bits 4–0 MAX SCAN LINE

Value = (number of scan lines per character row) - 1
Bit 5 SVB 9
Bit 9 of the Start Vertical Blank Register (CR15)
Bit 6 LCM 9
Bit 9 of the Line Compare Register (CR18)
Bit 7 DBL SCN

0 = Normal operation
1 = Enables double scanning operation. Each line is displayed twice by repeating the
row scan counter and video memory address. Vertical parameters in the CRT
controller are not affected.

Cursor Start Scan Line Register (CSSL) (CRA)
Read/Write Address: 3?5H, Index 0AH

The cursor start register defines the row scan of a character line where the cursor begins.
7 6 5 4 3 2 1 0
CSR
=0 =0 OFF CSR CURSOR START SCAN LINE
Bits 4–0 CSR CURSOR START SCAN LINE

Value = (starting cursor row within the character cell) - 1. When the cursor start regis-
ter is programmed with a value greater than the cursor end register, no cursor is gen-
erated.
Bit 5 CSR OFF

0 = Turns on the text cursor
1 = Turns off the text cursor
Cursor End Scan Line Register (CESL) (CRB)
Read/Write Address: 3?5H, Index 0BH

This register defines the row scan of a character line where the cursor ends.
7 6 5 4 3 2 1 0
CSR-SKW
=0 1 0 CURSOR END SCAN LINE
Bits 4–0 CURSOR END SCAN LINE

Value = ending scan line number within the character cell for the text cursor. If the
value of the cursor start scan line is greater than the value of cursor end line, then no
cursor is generated.
Bits 6–5 CSR-SKW - Cursor Skew

These bits control the delay skew of the cursor signal. Cursor skew delays the text cur-
sor by the selected number of clocks. For example, a skew of 1 moves the cursor
right one character position on the screen.
Bit 7 Reserved = 0

Start Address High Register (STA(H)) (CRC)
Read/Write Address: 3?5H, Index 0CH

15 14 13 12 11 10 9 8
DISPLAY START ADDRESS (HIGH)
20-bit Value = the first address after a vertical retrace at which the display on the screen begins on each
screen refresh. These along with bits 3-0 of CR69 are the high order start address bits.
Start Address Low Register (STA(L)) (CRD)
Read/Write Address: 3?5H, Index 0DH

7 6 5 4 3 2 1 0
DISPLAY START ADDRESS (LOW)
Start address (low) contains the 8 low order bits of the address.
Cursor Location Address High Register (CLA(H)) (CRE)
Read/Write Address: 3?5H, Index 0EH

15 14 13 12 11 10 9 8
CURSOR LOCATION ADDRESS (HIGH)
20-bit Value = the cursor location address of the video memory where the text cursor is active. This
register along with bits 3-0 of CR69 are the high order bits of the address.
Cursor Location Address Low Register (CLA(L)) (CRF)
Read/Write Address: 3?5H, Index 0FH

7 6 5 4 3 2 1 0
CURSOR LOCATION ADDRESS (LOW)
Cursor location address (low) contains the 8 low order bits of the address.

Vertical Retrace Start Register (VRS) (CR10)

7 6 5 4 3 2 1 0
VERTICAL RETRACE START
Bits 7–0 VERTICAL RETRACE START.

11-bit Value = scan line counter value at which VSYNC becomes active. These are the
low-order 8 bits. Bit 8 is bit 2 of CR7. Bit 9 is bit 7 of CR7. Bit 10 is bit 4 of CR5E.
Vertical Retrace End Register (VRE) (CR11)

Power-On Default: 0xH
This register controls the vertical interrupt and CR0-7
7 6 5 4 3 2 1 0
LOCK REF DIS CLR
R0-7 3/5 VINT VINT VERTICAL RETRACE END
Bits 3–0 VERTICAL RETRACE END

Value = least significant 4 bits of the scan line counter value at which VSYNC goes in-
active. To obtain this value, add the desired VSYNC pulse width in scan line units to
the CR10 value, also in scan line units. The 4 least significant bits of this sum are pro-
grammed into this field. This allows a maximum VSYNC pulse width of 15 scan line
units.
Bit 4 CLR VINT - Clear Vertical Retrace Interrupt

0 = Vertical retrace interrupt cleared
1 = The flip-flop is able to catch the next interrupt request
At the end of active vertical display time, a flip-flop is set for a vertical interrupt. The
output of this flip-flop goes to the system interrupt controller. The CPU has to reset
this flip-flop by writing a logical 0 to this bit while in the interrupt process, then set
the bit to 1 to allow the flip-flop to catch the next interrupt request. Do not change the
other bits in this register. This bit is cleared to 0 by the BIOS during a mode set, a re-
set, or power-on.
Bit 5 DIS VINT - Disable Vertical Interrupt

0 = Vertical retrace interrupt enabled if CR32_4 = 1
1 = Vertical interrupt disabled. This bit is cleared to 0 by the BIOS during a mode set,
a reset, or power-on

Bit 6 REF 3/5 - Refresh Cycle Select

0 = Three DRAM refresh cycles generated per horizontal line
1 = Five DRAM refresh cycles generated per horizontal line. Selecting five refresh
cycles allows use of the VGA chip with slow sweep rate displays (15.75 KHz).
This bit is cleared to 0 by the BIOS during a mode set, a reset, or power-on. This
setting can be overridden via bits 1-0 of CR3A
Bit 7 LOCK R0-7 - Lock Writes to CRT Controller Registers

0 = Writing to all CRT Controller registers enabled
1 = Writing to all bits of the CRT Controller registers CR0–CR7 except bit 4 of CR7
(LCM8) disabled. This bit is set to 1 by the BIOS during a mode set, a reset or
power-on
Vertical Display End Register (VDE) (CR12)

The vertical display enable end register defines 8 bits of the 10-bit address of the scan line where the
display on the screen ends. Bit 8 and Bit 9 are bits 1 and 6 of CR7. Bit 10 is bit 1 of CR5E.
7 6 5 4 3 2 1 0
VERTICAL DISPLAY END
Bit 7–0 VERTICAL DISPLAY END

11-bit Value = (number of scan lines of active display) - 1. This register contains the
least significant 8 bits of this value.

Offset Register (SCREEN-OFFSET) (CR13)

This register specifies the logical line width of the screen and is sometimes called the screen pitch. The
starting memory address for the next display row is larger than the current row by two, four or eight
times this amount. Bits 5-4 of CR51 are extension bits 9-8 of this register. If these bits are 00b, bit 2 of
CR43 is extension bit 8 of this register.
7 6 5 4 3 2 1 0
LOGICAL SCREEN WIDTH
Bits 7–0 LOGICAL SCREEN WIDTH

10-bit Value = quantity that is multiplied by 2 (word mode), 4 (doubleword mode) or 8
(quadword mode) to specify the difference between the starting byte addresses of
two consecutive scan lines. This register contains the least significant 8 bits of this
value. The addressing mode is specified by bit 6 of CR14 and bit 3 of CR17. Setting bit
3 of CR31 to 1 forces doubleword mode.
Underline Location Register (ULL) (CR14)

This register specifies the horizontal row scan position of underline and display buffer addressing
modes.
7 6 5 4 3 2 1 0
DBWD CNT
=0 MODE BY4 UNDER LINE LOCATION
Bits 4–0 UNDER LINE LOCATION

5-bit Value = (scan line count of a character row on which an underline occurs) -1
Bit 5 CNT BY4 - Select Count by 4 Mode

0 = The memory address counter depends on bit 3 of CR17 (count by 2)
1 = The memory address counter is incremented every four character clocks
The CNT BY4 bit is used when double word addresses are used.
Bit 6 DBLWD MODE - Select Doubleword Mode

0 = The memory addresses are byte or word addresses
1 = The memory addresses are doubleword addresses
Bit 7 Reserved = 0

Start Vertical Blank Register (SVB) (CR15)

This register specifies the scan line at which the vertical blanking period begins. Bit 8 is bit 3 of CR7.
Bit 9 is bit 5 of CR9. Bit 10 is bit 2 of CR5E.
7 6 5 4 3 2 1 0
START VERTICAL BLANK
Bits 7–0 START VERTICAL BLANK.

11-bit value = (scan line count at which BLANK becomes active) - 1. This register con-
tains the least significant 8 bits of this value.
End Vertical Blank Register (EVB) (CR16)

This register specifies the scan line count value when the vertical blank period ends.
7 6 5 4 3 2 1 0
END VERTICAL BLANK
Bits 7–0 END VERTICAL BLANK

Value = least significant 8 bits of the scan line counter value at which vertical blank-
ing ends. To obtain this value, add the desired width of the vertical blanking pulse in
scan lines to [(value in the Start Vertical Blank register)-1], also in scan lines. The 8
least significant bits of this sum are programmed into this field. This allows a maxi-
mum vertical blanking pulse of 255 scan line units.

CRTC Mode Control Register (CRT_MD) (CR17)

This register is a multifunction control register, with each bit defining a different specification.
7 6 5 4 3 2 1 0
BYTE ADW WRD VT 4BK 2BK
RST MODE 16K =0 MODE X2 HGC CGA
Bit 0 2BK CGA - Select Bank 2 Mode for CGA Emulation

0 = Row scan counter bit 0 is substituted for memory address bit 13 during active
display time
1 = Memory address bit 13 appears on the memory address output bit 13 signal of
the CRT controller
This bit allows memory mapping compatibility with the IBM CGA graphics mode.
Bit 1 4BK HGC - Select Bank 4 Mode for HGA Emulation

0 = Row scan counter bit 1 is substituted for memory address bit 14 during active
display time
1 = Memory address bit 14 appears on the memory address output bit 14 signal of
the CRT controller
The combination of this bit and bit 0 of this register allows compatibility with Hercu-
les HGC graphics memory mapping.
Bit 2 VT X2 - Select Vertical Total Double Mode

0 = Horizontal retrace clock selected
1 = Horizontal retrace clock divided by two selected
This bit selects horizontal retrace clock or horizontal retrace clock divided by two as
the clock that controls the vertical timing counter. If the vertical retrace counter is
clocked with the horizontal retrace clock divided by 2, then the vertical resolution is
double.
Bit 3 CNT BY2 - Select Word Mode

0 = Memory address counter is clocked with the character clock input, and byte mode
addressing for the video memory is selected
1 = Memory address counter is clocked by the character clock input divided by 2, and
word mode addressing for the video memory is selected
Bit 4 Reserved = 0

Bit 5 ADW 16K - Address Wrap

0 = When word mode is selected by bit 6 of this register, memory address counter bit
13 appears on the memory address output bit 0 signal of the CRT controller and
the video memory address wraps around at 16 KBytes
1 = When word mode is selected by bit 6 of this register, memory address counter bit
15 appears on the memory address output bit 0 signal of the CRT controller
This bit is useful in implementing IBM CGA mode.
Bit 6 BYTE MODE - Select Byte Addressing Mode

0 = Word mode shifts all memory address counter bits down one bit, and the most
significant bit of the counter appears on the least significant bit of the memory
address output
1 = Byte address mode
Bit 7 RST - Hardware Reset

0 = Vertical and horizontal retrace pulses always inactive
1 = Vertical and horizontal retrace pulses enabled
This bit does not reset any other registers or outputs.
Line Compare Register (LCM) (CR18)

This register is used to implement a split screen function. When the scan line counter value is equal
to the content of this register, the memory address counter is cleared to 0. The linear address counter
then sequentially addresses the display buffer starting at address 0. Each subsequent row address is
determined by the addition of the Offset (CR13) register content. Bit 8 is bit 4 of CR7. Bit 9 is bit 6 of
CR9. Bit 10 is bit 6 of CR5E.
7 6 5 4 3 2 1 0
LINE COMPARE POSITION
Bit 7–0 LINE COMPARE POSITION

11-bit Value = number of scan lines at which the screen is split into screen A and
screen B. This register contains the least significant 8 bits of this value.

CPU Latch Data Register (GCCL) (CR22)
Read Only Address: 3?5H, Index 22H

This register is used to read the CPU latch in the Graphics Controller.
7 6 5 4 3 2 1 0
GRAPHICS CONTROLLER CPU LATCH - N
Bits 7–0 GRAPHICS CONTROLLER CPU LATCH - N

Bits 1-0 of GR4 select the latch number N (3-0) of the CPU Latch.
Attribute Index Register (ATC_F/I) (CR24)
Read Only Address: 3?5H, Index 24H, 26H

This register is used to read the value of the Attribute Controller Index register and its associated
internal address flip-flop (AFF). It can be read at either index 24H or 26H.
7 6 5 4 3 2 1 0
AFF =0 ENV ATTRIBUTE CONTROLLER INDEX
Bits 4–0 ATTRIBUTE CONTROLLER INDEX

This value is the Attribute Controller Index Data at I/O port 3C0H.
Bit 5 ENV- Enable Video Display

This is the setting of bit 5 of 3C0H, indicating video display enabled status
(1 = enabled).
Bit 6 Reserved = 0
Bit 7 AFF
Inverted Internal Address flip-flop

16.4 GRAPHICS CONTROLLER REGISTERS
The graphics controller registers are located at a two byte I/O address space. These registers are
accessed by first writing an index to the Graphics Address register (at 3CEH) and then accessing the
Data register (at 3CFH).
Graphics Controller Index Register (GRC_ADR)
Read/Write Address: 3CEH

This register is loaded with a binary index value that determines which graphics controller register will
be accessed. This value is referred to as the “Index Number” of the GR register (GR0–6).
7 6 5 4 3 2 1 0
=0 =0 =0 =0 GR CONT ADDRESS
Bits 3–0 GR CONT ADDRESS - Graphics Controller Register Index

Graphics Controller Data Register (GRC_DATA)
Read/Write Address: 3CFH

This register is the data port for the graphics controller register indexed by the Graphics Controller
Index register.
7 6 5 4 3 2 1 0
GRAPHICS CONTROLLER DATA
Bit 7–0 GRAPHICS CONTROLLER DATA

Data to the Graphics Controller register indexed by the graphics controller address.

Set/Reset Data Register (SET/RST_DT) (GR0)
Read/Write Address: 3CFH, Index 00H

This register represents the value written to all 8 bits of the respective memory plane when the CPU
executes a memory write in write modes 0 and 3.
7 6 5 4 3 2 1 0
=0 =0 =0 =0 SET/RESET DATA
Bits 3–0 SET/RESET DATA

These bits become the color value for CPU memory write operations. In write mode
0, the set/reset data can be enabled on the corresponding bit of the Enable Set/Reset
Data register. In write mode 3, there is no effect on the Enable Set/Reset Data register.
Enable Set/Reset Data Register (EN_S/R_DT) (GR1)

These bits enable the set/reset data, and affect write mode 0.
7 6 5 4 3 2 1 0
=0 =0 =0 =0 ENB SET/RST DATA
Bits 3–0 ENB SET/RST DATA

When each bit is a logical 1, the respective memory plane is written with the value of
the Set/Reset Data register. A logical 0 disables the set/reset data in a plane, and that
plane is written with the value of CPU write data.

Color Compare Register (COLOR-CMP) (GR2)

These bits represent a 4-bit color value to be compared. In read mode 1, the CPU executes a memory
read, the read data is compared with this value and returns the results. This register works in
conjunction with the Color Don’t Care register.
7 6 5 4 3 2 1 0
=0 =0 =0 =0 COLOR COMPARE DATA
Bits 3–0 COLOR COMPARE DATA

This value becomes the reference color used to compare each pixel. Each of the 8-bit
positions of the read data are compared across four planes and a logical 1 is returned
in each bit position for which the colors match.
Raster Operation/Rotate Count Register (WT_ROP/RTC) (GR3)

This register selects a raster operation function and indicates the number of bits the CPU data will be
rotated (right) on the video memory write operation.
7 6 5 4 3 2 1 0
RST-OP
=0 =0 =0 1 0 ROTATE-COUNT
Bits 2–0 ROTATE-COUNT

These bits define a binary encoded value of the number of positions to right-rotate
data during a CPU memory write. To write non-rotated data, the CPU must preset a
count of 0.

Bits 4–3 RST-OP - Select Raster Operation

The data written to memory can operate logically with the data already in the proces-
sor latches. This function is not available in write mode 1. The logical functions are
defined as follows:
00 = No operation
01 = Logical AND with latched data
10 = Logical OR with latched data
11 = Logical XOR with latched data
The logical function specified by this register is applied to data being written to mem-
ory while in modes 0, 2 and 3.
Read Plane Select Register (RD_PL_SL) (GR4)

7 6 5 4 3 2 1 0
RD-PL-SL
=0 =0 =0 =0 =0 =0 1 0
The contents of this register represent the memory plane from which the CPU reads data in read mode
0. This register has no effect on the color compare read mode (read mode 1). In odd/even mode, bit 0
is ignored. Four memory planes are selected as follows:
Bits 1–0 RD-PL-SL - Read Plane Select

The memory plane is selected as follows:
00 = Plane 0
01 = Plane 1
10 = Plane 2
11 = Plane 3

Graphics Controller Mode Register (GRP_MODE) (GR5)

7 6 5 4 3 2 1 0
SHF-MODE O/E RD WRT-MD
=0 256 O/E MAP CMP =0 1 0
This register controls the mode of the Graphics Controller as follows:
Bit 1–0 WRT-MD - Select Write Mode

These bits select the CPU write mode into video memory. The function of each mode
is defined as follows:
00 = Write Mode 0. Each of four video memory planes is written with the CPU data
rotated by the number of counts in the rotate register. If the Set/Reset register is
enabled for any of four planes, the corresponding plane is written with the data
stored in the set/reset register. Raster operations and bit mask registers are
effective
01 = Write Mode 1. Each of four video memory planes is written with the data in the
processor latches. These latches are loaded during previous CPU read opera-
tions. Raster operation, rotate count, set/reset data, enable set/reset data and bit
mask registers are not effective
10 = Write Mode 2. Memory planes 0-3 are filled with 8 bits of the value of CPU
write data bits 0-3, respectively. For example, if write data bit 0 is a 1, eight 1’s
are written to memory plane 0. The data on the CPU data bus is treated as the
color value. The Bit Mask register is effective as the Mask register. A logical 1 in
the Bit Mask register sets the corresponding pixel in the addressed byte to the
color specified on the data bus. A logical 0 in the Bit Mask register sets the
corresponding pixel in the addressed byte to the corresponding pixel in the
processor latches. The Set/Reset, Enable Set/Reset and Rotate Count registers
are ignored
11 = Write Mode 3. Each of four video memory planes is written with 8 bits of the
color value contained in the set/reset register for that plane. The Enable Set/
Reset register is not effective. Rotated CPU write data is ANDed with the bit mask
register to form an 8-bit value that performs the same function as the Bit Mask
register in write modes 0 and 2. This write mode can be used to fill an area with
a single color and pattern
Bit 2 Reserved = 0
Bit 3 RD CMP - Enable Read Compare

0 = The CPU reads data from the video memory planes. The plane is selected by the
Read Plane Select register. This is called read mode 0
1 = The CPU reads the results of the logical comparison between the data in four
video memory planes selected by the contents of the Color Don’t Care register
and the contents of the Color Compare register. The result is a 1 for a match and
0 for a mismatch on each pixel. This is called read mode 1

Bit 4 O/E MAP - Select Odd/Even Addressing

0 = Standard addressing.
1 = Odd/even addressing mode selected. Even CPU addresses access plane 0 and 2,
while odd CPU addresses access plane 1 and 3. This option is useful for
emulating the CGA compatible mode. The value of this bit should be the inverted
value programmed in bit 2 of the Sequencer Memory Mode register (SR4). This
bit affects reading of display memory by the CPU
Bit 5 SHF-MODE - Select Odd/Even Shift Mode

0 = Normal shift mode
1 = The video shift registers in the graphics section are directed to format the serial
data stream with even-numbered bits from both planes on the even-numbered
planes and odd-numbered bits from both planes on the odd planes
Bit 6 SHF-MODE - Select 256 Color Shift Mode

0 = Bit 5 in this register controls operation of the video shift registers
1 = The shift registers are loaded in a manner that supports the 256 color mode
Bit 7 Reserved = 0
Memory Map Mode Control Register (MISC_GM) (GR6)

This register controls the video memory addressing.
7 6 5 4 3 2 1 0
MEM-MAP CHN TXT
=0 =0 =0 =0 1 0 O/E /GR
Bit 0 TXT/GR - Select Text/Graphics Mode

0 = Text mode display addressing selected
1 = Graphics mode display addressing selected. When set to graphics mode, the
character generator address latches are disabled
Bit 1 CHN O/E - Chain Odd/Even Planes

0 = A0 address bit unchanged
1 = CPU address bit A0 is replaced by a higher order address bit. The content of A0
determines which memory plane is to be addressed. A0 = 0 selects planes 0
and 2, and A0 = 1 selects planes 1 and 3. This mode can be used to double the
address space into video memory

Bits 3–2 MEM-MAP - Memory Map Mode

These bits control the address mapping of video memory into the CPU address
space. The bit functions are defined below.
00 = A0000H to BFFFFH (128 KBytes)
01 = A0000H to AFFFFH (64 KBytes)
10 = B0000H to B7FFFH (32 KBytes)
11 = B8000H to BFFFFH (32 KBytes)
Color Don’t Care Register (CMP_DNTC) (GR7)

This register is effective in read mode 1, and controls whether the corresponding bit of the Color
Compare Register is to be ignored or used for color comparison.
7 6 5 4 3 2 1 0
=0 =0 =0 =0 COMPARE PLANE SEL
Bits 3–0 COMPARE PLANE SEL - Compare Plane Select

0 = The corresponding color plane becomes a don’t care plane when the CPU read
from the video memory is performed in read mode 1
1 = The corresponding color plane is used for color comparison with the data in the
Color Compare register
Bit Mask Register (BIT_MASK) (GR8)

Any bit programmed to 0 in this register will cause the corresponding bit in each of four memory planes
to be immune to change. The data written into memory in this case is the data which was read in the
previous cycle, and was stored in the processor latches. Any bit programmed to 1 allows unimpeded
writes to the corresponding bits in the plane.
7 6 5 4 3 2 1 0
BIT MASK
Bits 7–0 BIT MASK

A logical 0 means the corresponding bit of each plane in memory is set to the corre-
sponding bit in the processor latches. A logical 1 means the corresponding bit of
each plane in memory is set as specified by other conditions.

16.5 ATTRIBUTE CONTROLLER REGISTERS
The attribute controller registers are located at the same byte I/O address for writing address and data.
An internal address flip-flop (AFF) controls the selection of either the attribute index or data registers.
To initialize the address flip-flop (AFF), an I/O read is issued at address 3BAH or 3DAH. This presets the
address flip-flop to select the index register. After the index register has been loaded by an I/O write
to address 3C0H, AFF toggles and the next I/O write loads the data register. Every I/O write to address
3C0H toggles this address flip-flop. However, it does not toggle for I/O reads at address 3C0H or 3C1H.
The Attribute Controller Index register is read at 3C0H, and the Attribute Controller Data register is read
at address 3C1H.
Attribute Controller Index Register (ATR_AD)

This register is loaded with a binary index value that determines which attribute controller register will
be accessed. This value is referred to as the “Index Number” of the AR register (AR0–14).
7 6 5 4 3 2 1 0
ENB
R R PLT ATTRIBUTE ADDRESS
Bits 4–0 ATTRIBUTE ADDRESS

A binary value that points to the attribute controller register where data is to be
written.
Bit 5 ENB PLT - Enable Video Display

0 = Video display access to the palette registers disabled. The Attribute Controller
register can be accessed by the CPU
1 = Display video using the palette registers enabled (normal display operation). The
palette registers (AR0–ARF) cannot be accessed by the CPU
This bit is effective only in 8-bit PA mode (CR67_4 = 0).
Bits 7–6 Reserved

Attribute Controller Data Register (ATR_DATA)
Read/Write Address: R: 3C1H/W: 3COH

This register is the data port for the attribute controller register indexed by the Attribute Controller
Index register.
7 6 5 4 3 2 1 0
ATTRIBUTE DATA
Bits 7–0 ATTRIBUTE DATA

Data to the attribute controller register indexed by the attribute controller address.
Palette Registers (PLT_REG) (AR00-0F)
Read/Write Address: 3C1H/3C0H, Index 00H-0FH

These are 16, 6-bit registers pointed to by the index and color code. They allow a dynamic mapping
between the text attribute or graphics color input and the display color on the CRT screen.
7 6 5 4 3 2 1 0
SECONDARY PRIMARY
=0 =0 SR SG SB R G B
Bits 5–0 PALETTE COLOR

The six bit display color, bits 5-0 are output as SR, SG/I, SB/V, R, G and B,
respectively.

Attribute Mode Control Register (ATR_MODE) (AR10)
Read/Write Address: 3C1H/3C0H, Index 10H

The contents of this register controls the attribute mode of the display function.
7 6 5 4 3 2 1 0
SEL 256 TOP ENB ENB MONO TX /GR
V54 CLR PAN =0 BLNK LGC ATRB
Bit 0 TX/GR - Select Graphics Mode

0 = Selects text attribute control mode
1 = Selects graphics control mode
Bit 1 MONO ATRB - Select Monochrome Attributes

0 = Selects color display text attributes
1 = Selects monochrome display text attributes
Bit 2 ENB LGC - Enable Line Graphics

0 = The ninth dot of a text character (bit 0 of SR1 = 0) is the same as the background
1 = Special line graphics character codes enabled
When this bit is set to 1, it forces the ninth dot of a line graphics character to be identi-
cal to the eighth dot of the character. The line graphics character codes are C0H
through DFH. For other characters, the ninth dot is the same as the background.
Bit 3 ENB BLNK - Enable Blinking

0 = Selects the background intensity for the text attribute input
1 = Selects blink attribute in text modes
This bit must also be set to 1 for blinking graphics modes. The blinking counter is op-
erated by the vertical retrace counter (VRTC) input. It divides the VRTC input by 32.
The blinking rates are ON for 16 VRTC clocks and OFF for 16 VRTC clocks. In the
graphics mode, when blink is activated, the most significant color bit (bit 3) for each
dot is inverted alternately, thus allowing two different colors to be displayed for 16
VRTC clocks each.
When the cursor is displayed in the text mode, it is blinked at a rate of ON for 8 VRTC
clocks and OFF for 8 VRTC clocks (period by 16 frames). The displayed characters are
independently blinked at the rate of 32 frames as above.
Bit 4 Reserved = 0
Bit 5 TOP PAN - Top Panning Enable

0 = Line compare has no effect on the output of the pixel panning register
1 = Forces the output of the pixel panning register to 0 after matching line compare
until VSYNC occurs in the CRT controller. At the top of screen the output of the
Pixel Panning register returns to its programmed value. This bit allows a top
portion of a split screen to be panned.

Bit 6 256 CLR - Select 256 Color Mode

0 = 4 bits of video (translated to 6 bits by the palette) are output every internal
dot-clock cycle
1 = Two 4-bit sets of video data are assembled to generate 8-bit video data at half the
frequency of the internal dot-clock
Bit 7 SEL V54 - Select V[5:4]

0 = In VGA, mode, bits 5-4 of video output are generated by the attribute palette
registers. Bits 7-6 of video output are always generated by bits 3-2 of AR14
1 = Bits 5-4 of video output are generated by bits 1-0 of AR14
Border Color Register (BDR_CLR) (AR11)

7 6 5 4 3 2 1 0
BORDER COLOR
Bits 7–0 Border Color. This 8-bit register determines the border color displayed on the CRT
screen. The border is an area around the screen display area.
This register is only effective in 8-bit PA modes (CR67_4 = 0). See also CR33_5.
Color Plane Enable Register (DISP_PLN) (AR12)

This register enables the respective video memory color plane 3–0 and selects video color outputs to
be read back in the display status.
7 6 5 4 3 2 1 0
VDT-SEL
=0 =0 1 0 DISPLAY PLANE ENBL
Bits 3–0 DISPLAY PLANE ENBL

A 0 in any of these bits forces the corresponding color plane bit to 0 before accessing
the internal palette. A 1 in any of these bits enables the data on the corresponding
color plane.

Bits 5–4 VDT-SEL - Video Test Select

These bits select two of the eight bit color outputs to be available in the Input Status
1 register. The output color combinations available on the status bits are as follows:
D STS MUX STS 1

Bit 5 Bit 4 Bit 5 Bit 4
0 0 Video 2 Video 0
0 1 Video 5 Video 4
1 0 Video 3 Video 1
1 1 Video 7 Video 6
Horizontal Pixel Panning Register (H_PX_PAN) (AR13)

This register specifies the number of pixels to shift the display data horizontally to the left. Pixel panning
is available in both text and graphics modes. It is not available with Enhanced mode memory mappings
(CR31_3 = 1).
7 6 5 4 3 2 1 0
=0 =0 =0 =0 NUMBER OF PAN SHIFT
Bits 3–0 NUMBER OF PAN SHIFT

This register selects the number of pixels to shift the display data horizontally to the
left. In the 9 pixels/character text mode, the output can be shifted a maximum shift of
8 pixels. In the 8 pixels/character text mode and all graphics modes, except 256 color
mode, a maximum shift of 7 pixels is possible. In the 256 color mode, bit 0 of this reg-
ister must be 0 resulting in only 4 panning positions per display byte. The panning is
controlled as follows:
Number of pixels shifted in

Bits 3–0 9 pixel/char. 8 pixel/char. 256 color mode
0000 1 0 0
0001 2 1 –
0010 3 2 1
0011 4 3 –
0100 5 4 2
0101 6 5 –
0110 7 6 3
0111 8 7 –
1000 0 – –

Pixel Padding Register (PX_PADD) (AR14)

This register specifies the high-order bits of video output when pixel padding is enabled and disabled
in the 256 color mode.
7 6 5 4 3 2 1 0
PIXEL PADDING
=0 =0 =0 =0 V7 V6 V5 V4
Bits 1–0 PIXEL PADDING V5, V4

These bits are enabled with a logical 1 of bit 7 of AR10, and can be used in place of
the V5 and V4 bits from the Palette registers to form the 8-bit digital color value out-
put.
Bits 3–2 PIXEL PADDING V7, V6

In all modes except 256 color mode, these bits are the two high-order bits of the 8-bit
digital color value output.

16.6 RAMDAC REGISTERS
All of the RAMDAC registers described in this section are physically located inside ViRGE.
DAC Mask Register (DAC_AD_MK)

This register is the pixel read mask register to select pixel video output. The CPU can access this register
at any time.
7 6 5 4 3 2 1 0
DAC ADDRESS MASK
Bits 7–0 DAC ADDRESS MASK

The contents of this register are bit-wise logically ANDed with the pixel select video
output (PA[7:0]). This register is initialized to FFH by the BIOS during a video mode
set.
DAC Read Index Register (DAC_RD_AD)
Write Only Address: 3C7H

This register contains the pointer to one of 256 palette data registers and is used when reading the
color palette.
7 6 5 4 3 2 1 0
DAC READ ADDRESS
Bits 7–0 DAC READ ADDRESS

Each time the color code is written to this register, it identifies that a read sequence
will occur. A read sequence consists of three successive byte reads from the RAM-
DAC data register at I/O address 3C9H. The least significant 6 bits of each byte taken
from the RAMDAC data register contain the corresponding color value, and the most
significant 2 bits contain zeros. The order is red byte first, then green, and finally
blue. The sequence of events for a read cycle is:
1. Write the color code to this register (RAMDAC Read Index) at address 3C7H.
2. The contents of the location in the color look-up table pointed to by the color code
are transferred to the RAMDAC data register at address 3C9H.
3. Three bytes are read back from the RAMDAC data register.
4. The contents of this register auto-increment by one.

5. Go to step 2.
The effects of writing to the RAMDAC data register during a three-byte read cycle or
reading from the RAMDAC data register during a 3-byte write cycle (i.e., interrupting
the sequence) are undefined and may change the look-up table contents.
DAC Status Register (DAC_STS)
Read Only Address: 3C7H

7 6 5 4 3 2 1 0
=0 =0 =0 =0 =0 =0 DAC-STS
Bits 1–0 DAC-STS - RAMDAC Cycle Status

The last executing cycle was:
00 = Write Palette cycle
11 = Read Palette cycle
Reads from the RAMDAC Write Index at address 3C8H or the DAC status register at
address 3C7H do not interfere with read or write cycles and may take place at any
time.
DAC Write Index Register (DAC_WR_AD)

7 6 5 4 3 2 1 0
DAC WRITE ADDRESS/GIP READ DATA
Bits 7–0 DAC WRITE ADDRESS/GIP READ DATA

This register contains the pointer to one of 256 palette data registers and is used dur-
ing a palette load. Each time the color code is written to this register, it identifies that
a write sequence will occur. A write sequence consists of three successive byte writes
to the DAC data register at I/O address 3C9H. The least significant 6 bits of each byte
are concatenated to form the value placed in the 18-bit data register. The order is red
byte first, then green, and finally blue. Once the third byte has been written, the value
in the data register is written to the location pointed to by the color code. The se-
quence of events for a write cycle is:
1. Write the color code to this register (DAC Write Index) at address 3C8H.
2. Three bytes are written to the DAC Data register at address 3C9H.

3. The contents of the DAC data register are transferred to the location in the color
look-up table pointed to by the color code.
4. The DAC Write Index register auto-increments by 1.
5. Go to step 2.
If bit 2 of the Extended RAMDAC Control register (CR55) is set to 1 to enable the Gen-
eral I/O Port read function, a read of 3C8H retrieves data from an external input buff-
er. The data is transmitted via GD[7:0] to AD[7:0] for a PCI bus configuration and
directly to SD[7:0] for a VL-Bus configuration.
RAMDAC Data Register (DAC_DATA)

This register is a data port to read or write the contents of the location in the color look-up table pointed
to by the DAC Read Index or the DAC Write Index registers.
7 6 5 4 3 2 1 0
DAC READ/WRITE DATA
Bits 7–0 DAC READ/WRITE DATA

To prevent “snow flicker” on the screen, an application reading data from or writing
data to the DAC Data register should ensure that the BLANK input to the RAMDAC is
asserted. This can be accomplished either by restricting data transfers to retrace inter-
vals, checking bit 3 of the Input Status 1 register (3?AH) to determine when retrace is
occurring, or by using the screen-off bit in the Clocking Mode register of the se-
quencer (bit 5 of SR1).

Section 17: Extended Sequencer Register Descriptions
The following registers are located in the Sequencer Register address space not used by the standard
VGA. SR8 must be programmed with an appropriate value to unlock access to these registers.
In the following register descriptions, ‘U’ stands for undefined or unused and ‘R’ stands for reserved
(write = 0, read = U).
See Appendix A for a table listing each register in this section and its page number.
Unlock Extended Sequencer Register (SR8)

Loading xxxx0110b (e.g., 06H) unlocks accessing of all the S3 extensions (SR9 - SR1C) to the standard
VGA Sequencer register set. (x = don’t care).
7 6 5 4 3 2 1 0
R R R R =0 =1 =1 =0
Extended Sequencer 9 Register (SR9)

7 6 5 4 3 2 1 0
MMIO-
ONLY R R R R R R R
Bits 6-0 Reserved
EXTENDED SEQUENCER REGISTER DESCRIPTIONS 17-1

Bit 7 MMIO-ONLY - Memory-mapped I/O register access only

0 = When MMIO is enabled, both programmed I/O and memory-mapped I/O register
accesses are allowed
1 = When MMIO is enabled, only memory-mapped I/O register accesses are allowed
to extended (non-standard VGA) registers. Both I/O and MMIO accesses can be
made to standard VGA registers.
Extended Sequencer A Register (SRA)
Read/Write Address: 3C5H, Index 0AH

7 6 5 4 3 2 1 0
2 P50 PD-
MCLK SEL NTRI R R R R R
Bits 4-0 Reserved
Bit 5 PD-NTRI - PD[63:0] Not Tri-stated

0 = PD[63:0] tri-stated
1 = PD[63:0] not tri-stated
The default value of 0 reduces power consumption. The pins are enabled for output
only as needed. Note that output pads for PD[63:29] also latch the most recent output
state.
Bit 6 P50 SEL - Pin 50 Function Select

0 = Pin 50 outputs OE1. This setting should never be required.
1 = Pin 50 outputs RAS1. This setting is required for 4-MByte configurations.
Bit 7 2MCLK - 2 MCLK CPU writes to memory

0 = 3 MCLK memory writes
1 = 2 MCLK memory writes
Setting this bit to 1 improves performance for systems using an MCLK less than 57
MHz. For MCLK frequencies between 55 and 57 MHz, bit 7 of SR15 should also be set
to 1 if linear addressing is being used.
17-2 EXTENDED SEQUENCER REGISTER DESCRIPTIONS

Extended Sequencer B Register (SRB)
Read/Write Address: 3C5H, Index 0BH

7 6 5 4 3 2 1 0
VAFC DOT=
ALT COLOR MODE R R VCLKI VCLKI
Bit 0 DOT = VCLKI - Dot clock = VCLKI

0 = Use internal dot clock
1 = Use VCLKI input for all internal dot clock functions
This bit is used for S3 test purposes only.
Bit 1 VAFC VCLKI - Use VCLKI input with VAFC

0 = Pixel data from pass-through feature connector latched by incoming VCLK
1 = Pixel data from VAFC latched by VCLKI input
Bits 3-2 Reserved
Bits 7-4 ALT COLOR MODE - Color Mode for feature connector input
0000 = Mode 0: 8-bit color, 1 pixel/VCLK
0001 = Mode 8: 8-bit color, 2 pixels/VCLK
All other mode values are reserved. Setting mode 0001 (clock doubled mode) also re-
quires that either bit 4 or bit 6 of SR15 be set to 1 and that bit 7 of SR18 be set to 1.
Clock doubling cannot be used with the Streams Processor active.

Extended Sequencer D Register (SRD)
Read/Write Address: 3C5H, Index 0DH

This register provides feature connector control and also provides independent control of the
HSYNC and VSYNC signals, therefore supporting the VESA DPMS (Display Power Management Con-
trol) standard.
7 6 5 4 3 2 1 0
VSY-CTL HSY-CTL R R LPB EN-
1 0 1 0 FEAT FEAT
Bit 0 EN-FEAT - Enable Feature Connector

0 = ENFEAT (pin 151) is high. VCLK, HSYNC and VSYNC are outputs.
1 = ENFEAT (pin 151) is low. The direction of VCLK is controlled by EVCLK and the
direction of BLANK, HSYNC and VSYNC is controlled by ESYNC. In both cases,
assertion (low) specifies an input and a logic high specifies an output.
This bit is set to 1 to drive pin 151 with a logic 0.
Bit 1 LPB FEAT - Select LPB Feature Connector

0 = Selects non-supported VAFC feature connector configuration
1 = Select the LPB feature connector configuration
The LPB must be disabled and feature connector operation enabled for this bit to
have an effect. This bit should always be set to 1 before feature connector operation
is enabled. It must be cleared to 0 for Scenic Highway operation.
Bits 3–2 Reserved
Bits 5–4 HSY-CTL - HSYNC Control

01 = HSYNC = 0
10 = HSYNC = 1
11 = Reserved
Bits 7–6 VSY-CTL - VSYNC Control

01 = VSYNC = 0
10 = VSYNC = 1
11 = Reserved

MCLK Value Low Register (SR10)

Power-On Default: See description below.
The power-on default value for this register in conjunction with the power-on default value for SR11
generate an MCLK value of 45 MHz. All other MCLK values must be specified by programming of
SR10 and SR11. Loading of a new value is enabled by either bit 0 or bit 5 of SR15.
7 6 5 4 3 2 1 0
R PLL R VALUE PLL N-DIVIDER VALUE
Bits 4-0 PLL N-DIVIDER VALUE

These bits contain the binary equivalent of the integer (1-31) divider used to scale the
input to the MCLK PLL. See Section 9 for a detailed explanation.
Bits 6-5 PLL R VALUE

These bits contain the binary equivalent of the integer (1, 2, 4, 8) range value used to
scale the output of the MCLK PLL. See Section 9 for a detailed explanation.
Bit 7 Reserved
MCLK Value High Register (SR11)

generate an MCLK value of 45 MHz. All other MCLK values must be specified by programming of
SR10 and SR11. Loading of a new value is enabled by either bit 0 or bit 5 of SR15.
7 6 5 4 3 2 1 0
R PLL M-DIVIDER VALUE
Bits 6-0 PLL M-DIVIDER VALUE

These bits contain the binary equivalent of the integer (1-127) divider used in the feed-
back loop of the MCLK PLL. See Section 9 for a detailed explanation.
Bit 7 Reserved

DCLK Value Low Register (SR12)

generate a DCLK value of 25.175 MHz. The default value is automatically placed in this register when
bits 3-2 of 3C2H are programmed to 00b. If bits 3-2 of CR2H are programmed to 01b, the appropriate
PLL R and PLL N values for a 28.322 MHz DCLK will automatically be placed in this register. All other
DCLK values must be specified by programming of SR12 and SR13. Loading of a new value is enabled
by either bit 1 or bit 5 of SR15 and by setting bits 3-2 of 3C2H to 11b.
7 6 5 4 3 2 1 0
R PLL R VALUE PLL N-DIVIDER VALUE
Bits 4-0 N-DIVIDER VALUE

These bits contain the binary equivalent of the integer (1-31) divider used to scale the
input to the DCLK PLL. See Section 9 for a detailed explanation.
Bits 6-5 PLL R VALUE

These bits contain the binary equivalent of the integer (1, 2, 4, 8) range value used to
scale the output of the DCLK PLL. See Section 9 for a detailed explanation.
Bit 7 Reserved
DCLK Value High Register (SR13)

generate a DCLK value of 25.175 MHz. The default value is automatically placed in this register
when bits 3-2 of 3C2H are programmed to 00b. If bits 3-2 of CR2H are programmed to 01b, the ap-
propriate PLL M value for a 28.322 MHz DCLK will automatically be placed in this register. All other
DCLK values must be specified by programming of SR12 and SR13. Loading of a new value is en-
abled by either bit 1 or bit 5 of SR15 and by setting bits 3-2 of 3C2H to 11b.
7 6 5 4 3 2 1 0
R PLL M-DIVIDER VALUE
Bits 6-0 PLL M- DIVIDER VALUE

These bits contain the binary equivalent of the integer (1-127) divider used in the feed-
back loop of the DCLK PLL. See Section 9 for a detailed explanation.
Bit 7 Reserved

CLKSYN Control 1 Register (SR14)

7 6 5 4 3 2 1 0
EXT EXT P151 CLR CLK EN MPLL DPLL
DCLK MCLK SEL CNT TEST CNT PD PD
Bit 0 DPLL PD - Power Down DCLK PLL

0 = DCLK PLL powered
1 = DCLK PLL powered down
Bit 1 MPLL PD - Power Down MCLK PLL

0 = MCLK PLL powered
1 = MCLK PLL powered down
Bit 2 EN CNT - Enable Clock Synthesizer Counter

0 = Clock synthesizer counter disabled
1 = Clock synthesizer counter enabled
Bit 3 CLK TEST - Clock Test

0 = Test DCLK
1 = Test MCLK
See Section 8.7 for a description of clock synthesizer testing.
Bit 4 CLR CNT - Clear clock synthesizer counter

0 = No effect
1 = Clear the clock synthesizer counter
Bit 5 P151 SEL - Pin 151 function select

0 = Pin 151 functions normally
1 = Pin 151 is tri-stated
Setting this bit to 1 allows pin 151 to act as an MCLK input. This is enabled by setting
bit 6 of this register to 1.

Bit 6 EXT MCLK - External MCLK Select

0 = MCLK provided by internal PLL
1 = MCLK is input on pin 151
This bit can also be set to 1 at reset via power-on strapping of PD11. An external
MCLK is only used for S3 test purposes.
Bit 7 EXT DCLK - External DCLK Select

0 = DCLK provided by internal PLL
1 = DCLK is input on pin 156.
This bit can also be set to 1 at reset via power-on strapping of PD11. An external
DCLK is only used for S3 test purposes.
CLKSYN Control 2 Register (SR15)

7 6 5 4 3 2 1 0
2 CYC DCLK\ CLK DCLK/ VCLK MCLK DRFQ MFRQ
MWR INV LOAD 2 OUT OUT EN EN
Bit 0 MFRQ EN - Enable new MCLK frequency load

0 = Register bit clear
1 = Load new MCLK frequency
When new MCLK PLL values are programmed, this bit can be set to 1 to load these
values in the PLL. The loading may be delayed a small but variable amount of time.
This bit should be cleared to 0 after loading to prevent repeated loading. Alternately,
use bit 5 of this register to produce an immediate load.
Bit 1 DFRQ EN - Enable new DCLK frequency load

0 = Register bit clear
1 = Load new DCLK frequency
When new DCLK PLL values are programmed, this bit can be set to 1 to load these
values in the PLL. Bits 3-2 of 3C2H must also be set to 11b if they are not already at
this value. The loading may be delayed a small but variable amount of time. This bit
should be programmed to 1 at power-up to allow loading of the VGA DCLK value and
then left at this setting. Use bit 5 of this register to produce an immediate load.
Bit 2 MCLK OUT - Output internally generated MCLK

0 = Pin 147 functions normally
1 = Pin 147 outputs the internally generated MCLK
This is used only for testing.

Bit 3 VCLK OUT - VCLK direction determined by EVCLK

0 = Pin 148 outputs the internally generated VCLK regardless of the state of EVCLK
1 = VCLK direction is determined by the EVCLK signal
This bit is effective only when the LPB feature connector is enabled.
Bit 4 DCLK/2 - Divide DCLK by 2

0 = DCLK unchanged
1 = Divide DCLK by 2
Either this bit or bit 6 of this register must be set to 1 for clock doubled RAMDAC op-
eration (mode 0001).
Bit 5 CLK LOAD - MCLK, DCLK load

0 = Clock loading is controlled by bits 0 and 1 of this register
1 = Load MCLK and DCLK PLL values immediately
To produce an immediate MCLK and DCLK load, program this bit to 1 and then to 0.
Bits 3-2 of 3C2H must also then be programmed to 11b to load the DCLK values if
they are not already programmed to this value. This register must never be left set to
1.
Bit 6 DCLK INV - Invert DCLK

0 = DCLK unchanged
1 = Invert DCLK
Either this bit or bit 4 of this register must be set to 1 for clock doubled RAMDAC op-
eration (mode 0001).
Bit 7 2 CYC MWR - Enable 2 cycle memory write

0 = 3 MCLK memory write
1 = 2 MCLK memory write
Setting this bit to 1 bypasses the VGA logic for linear addressing when bit 7 of SRA is
set to 1. This can allow 2 MCLK operation for MCLK frequencies between 55 and 57
MHz.
CLKSYN Test High Register (SR16)

7 6 5 4 3 2 1 0
CLOCK TEST RESULTS HIGH BYTE
Bits 7-0 CLOCK TEST RESULTS HIGH BYTE
See Section 9.4 for a description of how to use this register.

CLKSYN Test Low Register (SR17)
Read Only Address: 3C5H, Index 17H

7 6 5 4 3 2 1 0
CLOCK TEST RESULTS LOW BYTE
Bits 7-0 CLOCK TEST RESULTS LOW BYTE
See Section 9.4 for a description of how to use this register.
RAMDAC/CLKSYN Control Register (SR18)

7 6 5 4 3 2 1 0
CLKx LUT DAC TST TST TST TST TST
2 WR PD BLUE GRN RED RST EN
Bit 0 TST EN - Enable SignatureTest Counter

0 = RAMDAC signature test counter disabled
1 = RAMDAC signature test counter enabled
Bit 1 TST RST - Reset Signature Test Counter

0 = No effect
1 = Reset the RAMDAC test counter
Bit 2 TST RED - Test Red Data

0 = No effect
1 = Place signature test red data on internal data bus
The signature test data is read via CR6E.
Bit 3 TST GRN - Test Green Data

0 = No effect
1 = Place signature test green data on internal data bus
Bit 4 TST BLUE - Test Blue Data

0 = No effect
1 = Place signature test blue data on internal data bus

Bit 5 DAC PD - RAMDAC power-down

0 = RAMDAC powered
1 = RAMDAC powered-down
When the RAMDAC is powered down, the RAMDAC memory retains its data.
Bit 6 LUT WR - LUT write cycle control

0 = 2 DCLK LUT write cycle (default)
1 = 1 DCLK LUT write cycle
Bit 7 CLKx2 - Enable clock doubled mode

0 = RAMDAC clock doubled mode (0001) disabled
1 = RAMDAC clock doubled mode (0001) enabled
This bit must be set to 1 when mode 0001 is specified in bits 7-4 of CR67 or SRC.
Either bit 4 or bit 6 of SR15 must also be set to 1.
Extended Sequencer 1C Register (SR1C)
Read/Write Address: 3C5H, Index 1CH

The bits in this register are effective only in LPB mode.
7 6 5 4 3 2 1 0
R R R R R R SIGSEL
Bits 1–0 SIGSEL - Signal Select

(For VL)
00 = Pin 151 is ENFEAT; pin 153 is ROMCS
01 = Pin 151 is GPIOSTR; pin 153 is ROMCS
10 = Pin 151 is GOP0; pin 153 is ROMCS
11 = Pin 151 is GOP0; pin 153 is GOP1
(For PCI)
00 = Pin 151 is ENFEAT; pin 153 is ROMEN, pin 190 is STWR
01 = Pin 151 is reserved; pin 153 is ROMEN, pin 190 is STWR
10 = Pin 151 is GOP0; pin 153 is ROMEN, pin 190 is GOP1
11 = Pin 151 is GOP0; pin 153 is ROMEN, pin 190 is GOP1
GOP0 and GOP1 are bits 0-1 of the General Output Port register (CR5C).
When the system powers up with a default value of 00b for bits 1-0, both pin 151 and
pin 153 will be driven high (logic 1) for VL-Bus configurations and pins 151 and 190
will be driven high for PCI bus configurations.
Bits 7–2 Reserved

Section 18: Extended CRTC Register Descriptions
ViRGE has additional registers to extend the functions beyond VGA. These registers are located in CRT
Controller address space at locations not used by the IBM VGA. All of these registers are read/write
protected at power-up by hardware reset. In order to read/write these registers, CR38 and/or CR39 must
be loaded with a changed key pattern (see the register description). The registers will remain unlocked
until the key pattern is reset by altering a significant bit.
In the following register descriptions, ‘R’ stands for reserved (write =0, read = undefined). See Appendix
A for a table listing each register in this section and its page number.
Device ID High Register (CR2D)
Read Only Address: 3?5H, Index 2DH

This register should contain the same value as the upper byte of the PCI Device ID (Index 02H) register.
7 6 5 4 3 2 1 0
CHIP ID HIGH (56H)
Bits 7–0 CHIP ID HIGH
Device ID Low Register (CR2E)
Read Only Address: 3?5H, Index 2EH

7 6 5 4 3 2 1 0
CHIP ID LOW (31H)
Bits 7–0 CHIP ID LOW
EXTENDED CRTC REGISTER DESCRIPTIONS 18-1

Revision Register (CR2F)
Read Only Address: 3?5H, Index 2FH

Power-On Default: See Description
7 6 5 4 3 2 1 0
REVISION LEVEL
Bits 7–0 REVISION LEVEL
This will change with each steppings.
Chip ID/REV Register (CR30)
Read Only Address: 3?5H, Index 30H

Power-On Default: E1H
CR2D, CR2E and CR2F should be used for chip ID information.
7 6 5 4 3 2 1 0
CHIP ID REVISION STATUS
Bits 7–0 CHIP ID AND REVISION STATUS
Memory Configuration Register (CR31)

7 6 5 4 3 2 1 0
HST OLD-DSAD ENH VGA CPUA
R DFF 17 16 MAP 16B R BASE
Bit 0 CPUA BASE - Enable Base Address Offset

0 = Address offset bits 3-0 of CR35 and bits 3-2 of CR51 or the new address offset bits
(5-0 of CR6A) are disabled
1 = Address offset bits 3-0 CR35 and bits 3-2 of CR51 or the new address offset bits (5-
0 of CR6A) are enabled for specifying the 64K page of display memory. Bits 5-0 of
CR6A are used if this field contains a non-zero value. This allows access to up to
4 MBytes of display memory through a 64K window.
Bit 1 Reserved
18-2 EXTENDED CRTC REGISTER DESCRIPTIONS

Bit 2 VGA 16B - Enable VGA 16-bit Memory Bus Width

0 = 8-bit memory bus operation
1 = Enable 16-bit bus VGA memory read/writes
This is useful in VGA text modes when VGA graphics controller functions are typi-
cally not used.
Bit 3 ENH MAP - Use Enhanced Mode Memory Mapping

0 = Force IBM VGA mapping for memory accesses
1 = Force Enhanced Mode mappings
Setting this bit to 1 overrides the settings of bit 6 of CR14 and bit 3 of CR17 and
causes the use of doubleword memory addressing mode. Also, the function of bits 3-
2 of GR6 is overridden with a fixed 64K map at A0000H.
Bits 5–4 OLD-DSAD 17, 16 - Old Display Start Address Bits 17-16
Bits 17-16 of start address (CRC, CRD) and cursor location (CRE, CRF)
Bits 1-0 of the Extended System Control 2 register (CR51) are bits 19-18 of the ad-
dress and enable access to up to 4 MBytes of display memory. If a value is pro-
grammed into bits 3-0 of the Extended System Control 3 register (CR69), this value
becomes the upper 4 bits of the display start base address and bits 5-4 of CR31 and
bits 1-0 of CR51 are ignored.
Bit 6 HST DFF - Enable High Speed Text Display Font Fetch Mode
0 = Normal font access mode
1 = Enable high speed text display
Setting this bit to 1 is only required for DCLK rates greater than 40 MHz. See bit 5 of
CR3A.
Bit 7 Reserved
Backward Compatibility 1 Register (CR32)

7 6 5 4 3 2 1 0
VGA INT
R FXPG R EN R R R R
Bits 3–0 Reserved
Bit 4 INT EN -Interrupt Enable

0 = All interrupt generation disabled
1 = Interrupt generation enabled
Bit 5 Reserved

Bit 6 VGA FXPG - Use Standard VGA Memory Wrapping

0 = Memory accesses extending past a 256K boundary do not wrap
1 = Memory accesses extending past a 256K boundary wrap at the boundary
The standard 256K VGA memory page always ends on a natural 256K boundary and
accesses beyond this boundary will wrap. If the starting address is moved via bits 4-0
of CR69 (or bits 5-4 of CR31 and bits 1-0 of CR51), the 256K page may not end on a
256K boundary and accesses past the boundary will not wrap. This is the case when
this bit is cleared to 0. For standard VGA compatibility when the page base address is
moved, this bit is set to 1 to cause wrapping at a 256K boundary.
Bit 7 Reserved

7 6 5 4 3 2 1 0
LOCK BDR LOCK VCLK= DIS
R PLTW SEL DACW -DCK R VDE R
Bit 0 Reserved
Bit 1 DIS VDE - Disable Vertical Display End Extension Bits Write Protection
0 = VDE protection enabled
1 = Disables the write protect setting of the bit 7 of CR11 on bits 1 and 6 of CR7
Bit 2 Reserved
Bit 3 VCLK = -DCK - VCLK is Inverted DCLK

0 = VCLK is the external VCLK (pass-through feature connector clock input enabled)
or is divided by 2 for 4 bits/pixel modes (see bit 6 of AR10 or bit 4 of CR3A) or is
the internal DCLK (if neither of the first two cases apply)
1 = VCLK is forced to inverted DCLK
Bit 4 LOCK DACW - Lock RAMDAC Writes

0 = Enable writes to RAMDAC registers
1 = Disable writes to RAMDAC registers
Bit 5 BDR SEL - Blank/Border Select

0 = BLANK active time is defined by CR2 and CR3
1 = BLANK is active during entire display inactive period (no border)
Bit 6 LOCK PLTW - Lock Palette/Border Color Registers

0 = Unlock Palette/Border Color registers
1 = Lock Palette/Border Color registers
Bit 7 Reserved


7 6 5 4 3 2 1 0
ENB PCI PCI PCI
R R R SFF R RET ABT SNP
Bit 0 PCI SNP - PCI DAC snoop method

0 = Handling of PCI master aborts and retries during DAC cycles controlled by bits 1
and 2 of this register
1 = PCI master aborts and retries are not handled during DAC cycles
Bit 1 PCI ABT - PCI master aborts during DAC cycles

0 = PCI master aborts handled during DAC cycles
1 = PCI master aborts not handled during DAC cycles
Bit 0 of this register must be cleared to 0 for this bit to be effective.
Bit 2 PCI RET - PCI retries during DAC cycles

0 = PCI retries handled during DAC cycles
1 = PCI retries not handled during DAC cycles
Bit 0 of this register must be cleared to 0 for this bit to be effective.
Bit 3 Reserved
Bit 4 ENB SFF - Enable Start Display FIFO Fetch Register

0 = Start Display FIFO Fetch register (CR3B) disabled
1 = Start Display FIFO Fetch register (CR3B) enabled
Bits 7–5 Reserved

CRT Register Lock Register (CR35)

7 6 5 4 3 2 1 0
LOCK LOCK OLD-CPU-BASE-ADDRESS
R R HTMG VTMG 17 16 15 14
Bits 3–0 OLD-CPU-BASE-ADDRESS

CPU Base Address bits 17-14. These four bits define the CPU address base in 64
KByte units of display memory. These bits are added with CPU address bit 17 (MSB
of video memory addressing) to bit 14 for display buffer accesses.
Bits 3-2 of the Extended System Control 2 register (CR51) are bits 19-18 of the ad-
dress and enable access to up to 4 MBytes of display memory. If a value is pro-
grammed into bits 5-0 of the Extended System Control 4 register (CR6A), this value
becomes the upper 6 bits of the CPU base address and bits 3-0 of CR35 and bits 3-2 of
CR51 are ignored.
Bit 4 LOCK VTMG - Lock Vertical Timing Registers

0 = Vertical timing registers are unlocked
1 = The following vertical timing registers are locked:
CR6
CR7 (bits 7,5,3,2,0)
CR9 (bit 5)
CR10
CR11 (bits 3-0)
CR15
CR16
CR6, CR7 registers are also locked by bit 7 of the Vertical Retrace End register (CR11).
Bit 5 LOCK HTMG - Lock Horizontal Timing Registers

0 = Horizontal timing registers are unlocked
1 = The following horizontal timing registers are locked:
CR00
CR1
CR2
CR3
CR4
CR5
CR17 (bit 2)
All these registers (except bit 2 of CR17) are also locked by bit 7 of the Vertical Re-
trace End register (CR11).
Bit 7-6 Reserved

Configuration 1 Register (CR36)
Read/Write* Address: 3?5H, Index 36H

Power-On Default: Depends on Strapping
* Bits 1-0 are read only. The other bits can be written only after 0A5H is written to CR39.
This register samples the reset state from PD bus pins [7:0]. Other configuration strapping bits are
found in CR37, CR68 and CR6F.
7 6 5 4 3 2 1 0
MEM SIZE VBE MEM MODE SYS BUS
Bits 1-0 SYS BUS - Select System Bus Interfaced

00 = Reserved
01 = VL-Bus
10 = PCI Bus
11 = Reserved
Bit 3-2 MEM MODE - Memory Page Mode Select

00 = 1-cycle EDO mode
01 = Reserved
10 = 2-cycle EDO mode
11 = Reserved
Bit 4 VBE - Video BIOS Access Enable (VL-Bus only)

0 = Disable video BIOS accesses
1 = Enable video BIOS accesses
Bits 7-5 MEM Size - Memory Size

000 = 4 MBytes
100 = 2 MBytes
All other values are reserved.

Read/Write* Address: 3?5H, Index 37H

* These bits can be written only after 0A5H is written to CR39.
This register samples the reset state from PD bus pins [15:8]. Other configuration strapping bits are
found in CR36, CR68 and CR6F.
7 6 5 4 3 2 1 0
R R R RS CS VBS R EV
Bit 0 EV - Enable ViRGE (VL-Bus only)

0 = Disable ViRGE except for video BIOS accesses
1 = Enable ViRGE
Bit 1 Reserved
Bit 2 VBS - Video BIOS Size (VL-Bus only)

0 = 64-KByte video BIOS ROM
1 = 32-KByte video BIOS ROM
Bit 3 CS - Clock Select

0 = Use external DCLK on pin 156 and external MCLK on pin 146 (test purposes only)
1 = Use internal DCLK, MCLK
Bit 4 RS - RAMDAC Write Snooping (VL-Bus only)

0 = Disable LOCA/SRDY for RAMDAC writes
1 = Enable LOCA/SRDY for RAMDAC writes
Bits 7-5 Reserved

Register Lock 1 Register (CR38)
Read/Write Address: 3?5H, Index 38

Loading 01xx10xx (e.g., 48H) into this register unlocks the extended CRTC registers from CR2D through
CR3F for read/writes. (x = don’t care)
7 6 5 4 3 2 1 0
=0 =1 =1 =0
Register Lock 2 Register (CR39)
Read/Write Address: 3?5H, Index 39

Loading 101xxxxx (e.g., A0H) unlocks the extended CRTC registers registers from CR40 through CRFF
for reading/writing (x = don’t care). Loading A5H allows bits 7-2 of CR36, bits 7-0 of CR37 and bits 7-0
of CR68 to be written.
7 6 5 4 3 2 1 0
=1 =0 =1
Miscellaneous 1 Register (CR3A)

7 6 5 4 3 2 1 0
PCIRB HST ENH TOP ENB REF-CNT
DISA R DFW 256 MEM RFC 1 0
Bits 1–0 REF-CNT - Alternate Refresh Count Control

00 = Refresh Count 0
If enabled by setting bit 2 of this register to 1, these bits override the refresh count in
bit 6 of CR11 and specify the number of refresh cycles per horizontal line.
Bit 2 ENB RFC - Enable Alternate Refresh Count Control

0 = Alternate refresh count control (bits 1-0) is disabled
1 = Alternate refresh count control (bits 1-0) is enabled

Bit 3 TOP MEM - Enable Top of Memory Access

0 = Top of memory access disabled
1 = Simultaneous VGA text and Enhanced modes are enabled. CPU and CRTC
accesses are then directed to the top 32- or 64-KByte area of display memory
depending on whether address bit 13 is 0 or 1 respectively.
Bit 4 ENH 256 - Enable 8 Bits/Pixel or Greater Color Enhanced Mode

0 = Attribute controller shift registers configured for 4-bit modes
1 = Attribute controller shift register configured for 8-, 16- and 24-bit color
Enhanced modes
Bit 5 HST DFW - Enable High Speed Text Font Writing

0 = Disable high speed text font writing
1 = Enable high speed text font writing
Setting this bit to 1 is only required for DCLK rates greater than 40 MHz. See bit 6 of
CR31.
Bit 6 Reserved
Bit 7 PCIRB DISA - PCI Read Bursts Disabled

0 = PCI read burst cycles enabled
1 = PCI read burst cycles disabled
Note: Bit 7 of CR66 must be set to 1 before this bit is set to 1.
Start Display FIFO Register (CR3B)

This value must lie in the horizontal blanking period and is typically 5 less than the value pro-
grammed in CR0. This parameter helps to ensure that adequate time is available during horizontal
blanking for activities such as RAM refresh that require control of the display memory. Bit 9 of this
value is bit 6 of CR5D. This register must be enabled by setting bit 4 of CR34 to 1.
7 6 5 4 3 2 1 0
START DISPLAY FIFO FETCH
Bits 7–0 START DISPLAY FIFO FETCH

9-bit Value = the time in character clocks from the active display start until the restart
of fetching of FIFO data after the start of horizontal blanking. This register contains
the low-order 8 bits of this value.

Interlace Retrace Start Register (CR3C)

This value allows determination of the even/odd row active display starting positions when operat-
ing in an interlaced mode. This register is enabled by bit 5 of CR42.
7 6 5 4 3 2 1 0
INTERLACE RETRACE START POSITION
Bits 7–0 INTERLACE RETRACE START POSITION

Value = offset in terms of character clocks for Interlaced mode start/end in even/odd
frames.
System Configuration Register (CR40)

7 6 5 4 3 2 1 0
RDY EN
=0 =0 R CTL R R R ENH
Bit 0 EN ENH - Enable Enhanced Register Access

0 = Enhanced register access disabled
1 = Enhanced register access enabled
Bits 3–1 Reserved
Bits 4 RDY CTL- Ready Control (VL-Bus only)

0 = Minimum 0 wait state delay from SADS asserted to assertion of SRDY. Address
latching occurs during the T1 cycle.
1 = Minimum 1 wait state delay from SADS asserted to assertion of SRDY (Default)
With this setting, bit 3 of CR58 determines when the address is latched.
Bit 5 Reserved = 1 (Default)
Bits 7–6 Reserved = 00b

BIOS Flag Register (CR41)

7 6 5 4 3 2 1 0
BIOS-FLAG-REGISTER-1
Bits 7–0 BIOS-FLAG-REGISTER-1

Used by the video BIOS.
Mode Control Register (CR42)

7 6 5 4 3 2 1 0
INTL
R R MODE R R R R R
Bits 4–0 Reserved
Bit 5 INTL MODE - Interlaced Mode

0 = Noninterlaced
1 = Interlaced
This bit enables the function of CR3C.
Bits 7–6 Reserved

Extended Mode Register (CR43)

7 6 5 4 3 2 1 0
HCTR OLD
X2 R R R R LSW8 R R
Bits 1–0 Reserved
Bit 2 OLD LSW8 - Logical Screen Width Bit 8

This is an extension of the Offset (Screen Width) register (CR13). This is disabled if
bits 5-4 of the Extended System Control 2 register (CR51) are not 00b.
Bits 6–3 Reserved
Bit 7 HCTR X2 - Horizontal Counter Double Mode

0 = Disable horizontal counter double mode
1 = Enable horizontal counter double mode (horizontal CRT parameters are doubled)
Hardware Graphics Cursor Mode Register (CR45)

7 6 5 4 3 2 1 0
HWGC HWGC
R R R 1280 R R R ENB
Bit 0 HWGC ENB - Hardware Graphics Cursor Enable

0 = Hardware graphics cursor disabled in any mode
1 = Hardware graphics cursor enabled in Enhanced mode
Bits 3-1 Reserved
Bit 4 HWGC 1280 - Hardware Cursor Right Storage

0 = Function disabled
1 = For 4 bits/pixel, the last 256 bytes in each 1-KByte line of the hardware cursor start
address become the hardware graphics cursor storage area. For 8 bits/pixel, the
last 512 bytes in each 2-KByte line of the hardware cursor start address become
the hardware graphics cursor storage area. In either case, bits 1-0 of CR4D must
be 11b.
Bits 7–5 Reserved

Hardware Graphics Cursor Origin-X Registers (CR46, CR47)
Read/Write Address: 3?5H, Index 46H, 47H

The high order three bits are written into CR46 and the low order byte is written into CR47.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R R R R R HWGC ORG X (H) HWGC ORG X (L)
Bits 10–0 HWGC ORG X(H) (L) - X-Coordinate of Cursor Left Side
Bits 15–11 Reserved
Hardware Graphics Cursor Origin-Y Registers (CR48, CR49)
Read/Write Address: 3?5H, Index 48H, 49H

The high order three bits are written into CR48 and the low order byte is written into CR49.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R R R R R HWGC ORG Y (H) HWGC ORG Y (L)
Bits 10–0 HWGC ORG Y (H)(L) - Y-Coordinate of Cursor Upper Line

The cursor X, Y position is registered upon writing HWGC ORG Y (H).
Hardware Graphics Cursor Foreground Color Stack Register (CR4A)

7 6 5 4 3 2 1 0
TRUE COLOR FOREGROUND STACK (0-2)
Bits 7–0 TRUE COLOR FOREGROUND STACK (0-2)
Three foreground color registers are stacked at this address. The stack pointer (com-
mon with CR4B) is reset to 0 by reading the Hardware Graphics Cursor Mode register
(CR45). Each write to this register (CR4A) increments the stack pointer by 1, so three
writes provide 24 bits of true color information.

Hardware Graphics Cursor Background Color Stack Register (CR4B)

7 6 5 4 3 2 1 0
TRUE COLOR BACKGROUND STACK (0-2)
Bits 7–0 TRUE COLOR BACKGROUND STACK (0-2)
Three background color registers are stacked at this address. The stack pointer (com-
mon with CR4A) is reset to 0 by reading the Hardware Graphics Cursor Mode register
(CR45). Each write to this register (CR4B) increments the stack pointer by 1, so three
writes provide 24 bits of true color information.
Hardware Graphics Cursor Storage Start Address Registers (CR4C, CR4D)
Read/Write Address: 3?5H, Index 4CH, 4DH

The high order four bits are written into CR4C and the low order byte is written into CR4D.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R R R R HWGC STA(H) HWGC STA(L)
Bits 11–0 HWGC STA(H)(L) - Hardware Graphics Cursor Storage Start Address
Hardware Graphics Cursor Pattern Display Start X-PXL-Position Register (CR4E)

7 6 5 4 3 2 1 0
R R HWGC PAT DISP START X-POS
Bits 5–0 HWGC PAT DISP START X-POS - HWGC Pattern Display Start-X Pixel Position
This value is the offset (in pixels) from the left side of the 64x64 cursor pixel pattern
from which the cursor is displayed. This allows a partial cursor to be displayed at the
left border of the display.
Bits 7–6 Reserved

Hardware Graphics Cursor Pattern Disp Start Y-PXL-Position Register (CR4F)
Read/Write Address: 3?5H, Index 4FH

7 6 5 4 3 2 1 0
R R HWGC PAT DISP START Y-POS
Bits 5–0 HWGC PAT DISP START Y-POS - HWGC Pattern Display Start-Y Pixel Position
This value is the offset (in pixels) from the top of the 64x64 cursor pixel pattern from
which the cursor is displayed. This allows a partial cursor to be displayed at the top
of the display.
Bits 7–6 Reserved
Extended System Control 2 Register (CR51)

7 6 5 4 3 2 1 0
LOG-SCR-W OLD-CBAD OLD-DSAD
R R 9 8 19 18 19 18
Bits 1–0 OLD-DSAD - Old Display Start Address Bits 19-18

These are extension bits of Memory Configuration register (CR31) bits 5-4 (Display
Start Base Address). If the upper 4 display start address bits are programmed into
bits 3-0 of CR69, these bits and bits 5-4 of CR31 are ignored.
Bits 3–2 OLD-CBAD - Old CPU Base Address Bits 19-18

These are extension bits of CRT Register Lock register (CR35) bits 3-0 (CPU Base Ad-
dress). They becomes bits 19-18 of the CPU base address, enabling access to up to 4
MBytes of display memory. If the upper 6 CPU base address bits are programmed
into bits 5-0 of CR6A, these bits and bits 3-0 of CR35 are ignored.
Bits 5–4 LOG-SCR-W - Logical Screen Width Bits 9-8

These are two extension bits of the Offset register (CR13). If the value of these bits is
not 00b, bit 2 of the Extended Mode register (CR43) is disabled.
Bits 7–6 Reserved

Extended BIOS Flag 1 Register (CR52)

7 6 5 4 3 2 1 0
EXT-BIOS-FLAG-REGISTER-1
Bits 7–0 EXT-BIOS-FLAG-REGISTER-1
Reserved for use by the video BIOS.
Extended Memory Control 1 Register (CR53)

Power-On Default: See Bit Descriptions
7 6 5 4 3 2 1 0
SWP MMIO MMIO BIG ENDIAN
R NBL WIN SELECT LIN ADDR R
Bit 0 Reserved
Bits 2-1 BIG ENDIAN LIN ADDR - Big Endian Data Byte swap (linear addressing only)
00 = No swap (Default)
01 = Swap bytes within each word
10 = Swap all bytes in doublewords (bytes reversed)
11 = Reserved
Bits 4-3 MMIO SELECT

00 = Disable MMIO (Default for VL-Bus)
01 = New MMIO (relocatable) enabled (Default for PCI)
10 = Trio64-type MMIO enabled at window selected by bit 5 of this register
11 = Trio64-type MMIO and new MMIO enabled
Refer to the MMIO explanation in Section 15 for more information.
Bit 5 MMIO WIN - Trio64-type MMIO Window

0 = Trio64-type MMIO window enabled at A8000H - AFFFFH. A0000H - A7FFF
available for image transfers (Default)
1 = Trio64-type MMIO window enabled at B8000H - BFFFFH. A0000H - B7FFFH are not
used (no image transfer area)
Bits 4-3 of this register must be programmed to 10b for this bit to be effective.

Bit 6 SWP NBL - Swap Nibbles

0 = No nibble swap (Default)
1 = Swap nibbles in each byte of a linear memory address read or write operation
Bit 7 Reserved

7 6 5 4 3 2 1 0
R R R R R R BIG ENDIAN
Bits 1–0 BIG ENDIAN - Big Endian Data Byte Swap (not linear addressing or image writes)
11 = Swap according to BE[3:0] (VL-Bus) or C/BE[3:0] (PCI)
Byte enable settings for a bit setting of 11b:

0011 = Swap bytes within selected word
1100 = Swap bytes within selected word
All other values = no swap
Bits 7–2 Reserved
Extended RAMDAC Control Register (CR55)

7 6 5 4 3 2 1 0
TOFF MS R ENB
VCLK R R /X11 GIR R R
Bits 1–0 Reserved

Bit 2 ENB GIR - Enable General Input Port Read (VL-Bus)

0 = RAMDAC reads enabled
1 = General Input Port read enabled
When this bit is set to 1 and SR1C_10 = 01b, the GPIOSTR strobe for reading General
Input Port data is generated when 3C8H is read. The data is transmitted directly to
SD[7:0] for VL-Bus configurations. PCI configurations must use the LPB General Input
Port capability.
Bit 3 Reserved
Bit 4 MS/X11 - Hardware Cursor MS/X11 Mode

0 = MS-Windows mode (Default)
1 = X11-Windows mode
This bit select the type of decoding used for the 64x64x2 storage array of the hard-
ware graphics cursor. See the Programming the Hardware Cursor section for a de-
scription of the decoding.
Bits 6–5 Reserved
Bit 7 TOFF VCLK - Tri-State Off VCLK Output

1 = VCLK output is tri-stated off
External Sync Control 1 Register (CR56)

7 6 5 4 3 2 1 0
DIS DIS
R R R R R VSYN HSYN R
Bit 0 Reserved
Bit 1 DIS HSYN - Tri-state off HSYNC

0 = HSYNC output buffer tri-stated on
1 = HSYNC output buffer tri-stated off
Bit 2 DIS VSYN - Tri-state off VSYNC

0 = VSYNC output buffer tri-stated on
1 = VSYNC output buffer tri-stated off
Bits 7–3 Reserved

Linear Address Window Control Register (CR58)

7 6 5 4 3 2 1 0
RAS ENB LAT LAW-SIZE
PRE R R LA DEL R 1 0
Bits 1–0 LAW-SIZE - Linear Address Window Size

00 = 64 KBytes (Default)
01 = 1 MByte
10 = 2 MBytes
11 = 4 MBytes
Bit 2 Reserved
Bit 3 LAT DEL - Address Latch Delay Control (VL-Bus only)

0 = Address latching is delayed one clock (T2 cycle)
1 = Address latching occurs in the T1 cycle
This bit is effective only when one decode wait state is selected by setting bit 4 of
CR40 to 1.
Bit 4 ENB LA - Enable Linear Addressing

0 = Disable linear addressing (Default)
1 = Enable linear addressing
Enabling linear addressing disables access to the A000H-AFFFH region unless bank-
ing is enabled via bit 0 of CR31, the window size is set to 64K via bits 1-0 of this regis-
ter and A000H is specified as the base in CR59-5A.
This bit is ORed with MM850C_4 and is equivalent to it.
Bits 6–5 Reserved
Bit 7 RAS PRE - RAS Pre-charge Time Adjust

0 = RAS pre-charge (high) time is defined by CR68_3 or MM8204_1.
1 = RAS pre-charge (high) time is decreased by 0.5 MCLKs over that specified by
CR68_3 and the corresponding RAS low time (CR68_2) is increased by 0.5
MCLKs. This leaves the total cycle time unchanged.

Linear Address Window Position Registers (CR59-5A)
Read/Write Address: 3?5H, Index 59H-5AH

Power-On Default: 000AH (VL-Bus), 7000H (PCI)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINEAR-ADDRESS-WINDOW-POSITION
CR59 contains the upper byte (15-8) and CR5A contains the lower byte (7-0). These registers specify
system address bits 31-16 of the Linear Address Window Position in 32-bit CPU address space. The
Linear Address Window resides on a 64KB, 1MB, 2MB or 4MB memory boundary (size-aligned
boundary). Some LSBs of this register (illustrated by “xx..xx” in the following table) are ignored
because of the size-aligned boundary scheme.
LAW Linear Address Window

Size Position Register Bit(s)
64KB 31-25 24 23 22 21 20 19 18 17 16
1MB 31-25 24 23 22 21 20 xx xx xx xx
2MB 31-25 24 23 22 21 xx xx xx xx xx
4MB 31-25 24 23 22 xx xx xx xx xx xx
Bits 15–0 LINEAR-ADDRESS-WINDOW-POSITION - LA Window Position Bits 31-16

16-bit Value = the linear address window position in 32-bit CPU address space.
Bits 15-0 are common with bits 31-16 of the base address programmed into the PCI
Base Address 0 register at address 10H-12H. Writes to these bits in either register will
also be written to the other. Writes to CR59 and CR5A should be read-modify- writes
that do not change the upper 6 bits, as these bits are written by the system BIOS to
place ViRGE in a unique address space. Note that system BIOS writes will leave bits 9-
0 in an indeterminate state, so these should be properly initialized before linear ad-
dressing is enabled.
If a 64K window is specified and bit 0 of CR31 is set to 1, bits 5-0 of CR6A specify the
64K page of display memory to be accessed through a 64K window located at the ad-
dress specified in these registers.

General Output Port Register (CR5C)

7 6 5 4 3 2 1 0
GENERAL OUT PORT
Bits 7–0 GENERAL OUT PORT
This register can be used in a variety of ways. See Section 12-4 for a complete de-
scription.
Extended Horizontal Overflow Register (CR5D)

7 6 5 4 3 2 1 0
SFF EHS SHS EHB SHB HDE HT
R 8 6 8 7 8 8 8
Bit 0 HT 8 - Horizontal Total (CR0) Bit 8
Bit 1 HDE 8 - Horizontal Display End (CR1) Bit 8
Bit 2 SHB 8 - Start Horizontal Blank (CR2) Bit 8
Bit 3 EHB 7 - End Horizontal Blank (CR3) Bit 6
Bit 4 SHS 8 - Start Horizontal Sync Position (CR4) Bit 8
Bit 5 EHS 6 - End Horizontal Sync (CR5) Bit 6
Bit 6 SFF 8 - Start FIFO Fetch (CR3B) Bit 8
Bit 7 Reserved

Extended Vertical Overflow Register (CR5E)

7 6 5 4 3 2 1 0
LCM VRS SVB VDE VT
R 10 R 10 R 10 10 10
Bit 0 VT 10 - Vertical Total (CR6) Bit 10
Bit 1 VDE 10 - Vertical Display End (CR12) Bit 10
Bit 2 SVB 10 - Start Vertical Blank (CR15) Bit 10
Bit 3 Reserved
Bit 4 VRS 10 - Vertical Retrace Start (CR10) Bit 10
Bit 5 Reserved
Bit 6 LCM 10 - Line Compare Position (CR18) Bit 10
Bit 7 Reserved

7 6 5 4 3 2 1 0
R BIG ENDIAN R R R R R
Bits 4-0 Reserved
Bits 6-5 BIT ENDIAN - Big Endian Data Byte Swap (image writes only)
11 = Reserved
Bit 7 Reserved

Extended Miscellaneous Control Register (CR65)

7 6 5 4 3 2 1 0
DELAY BLANK DAC
R R 2 1 0 MMIO R R
Bits 1-0 Reserved
Bit 2 DAC MMIO - RAMDAC MMIO Access

0 = MMIO access to the RAMDAC registers disabled
1 = MMIO access to the RAMDAC registers enabled (default)
The BIOS should program this bit to 0 after each reset.
Bits 4-3 DLK BLANK - Delay BLANK by DCLK

000 = No delay of BLANK
001 = Delay BLANK for 1 DCLK
010 = Delay BLANK for 2 DCLKs
Bits 7-5 Reserved
Extended Miscellaneous Control 1 Register (CR66)

7 6 5 4 3 2 1 0
PCI TOFF PCI ENBL
DE PADT R R DISC R RST ENH
Bit 0 ENBL ENH - Enable Enhanced Functions

0 = Enable VGA and VESA planar (4 bits/pixel) modes
1 = Enable all other modes (Enhanced and VESA non-planar)
This bit has the same function as MM850C_0. It enables operation of the S3D Engine.

Bit 1 RST - Reset

0 = No operation
1 = Software reset of S3D Engine and memory controller
Setting this bit has the same effect as setting MM8504_15-14 (Write) to 10b.
Bit 2 Reserved
Bit 3 PCI DISC - PCI Disconnects

0 = No effect
1 = An attempt to write data with the Command FIFO or LPB Output FIFO full or to
read data with the Command FIFO not empty generates a PCI bus disconnect
cycle
Bit 7 of this register must also be set to 1 to enable this feature.
Bits 5-4 Reserved
Bit 6 TOFF PADT - Tri-State Off Pixel Address Bus

1 = PA[15:0] are set to tri-state off
Bit 7 PCI DE - PCI bus disconnect enable

0 = PCI bus disconnect disabled
1 = PCI bus disconnect enabled
Setting this bit to 1 allows PCI burst cycles to be interrupted if AD[1:0] ≠ 00b or if the
address during the burst goes outside the address ranges supported by ViRGE.
Extended Miscellaneous Control 2 Register (CR67)

7 6 5 4 3 2 1 0
COLOR MODE STREAMS VCLK
3 2 1 0 MODE R PHS
Bit 0 VCLK PHS - VCLK Phase With Respect to DCLK

0 = VCLK is 180° out of phase with DCLK (inverted)
1 = VCLK is in phase with DCLK
Bit 1 Reserved

Bits 3–2 STREAMS MODE

00 = Streams Processor disabled
01 = Secondary stream overlaid on VGA mode background
10 = Reserved
11 = Full Streams Processor operation (primary and secondary streams from all
supported sources)
The Streams Processor should only be enabled or disabled during the VSYNC period.
Bits 7–4 COLOR MODE - RAMDAC Color Mode

0001 = Mode 8: 8-bit color, 2 pixels/VCLK
All other mode values are reserved.

This is the third byte (along with CR36 and CR37) of the power-on strapping bits. CR6F contains the
fourth byte. PD[23:16] are sampled on power-on reset and their states are written to bits 7-0 of this
register. A5H must be written to CR39 to provide read/write access to this register.
7 6 5 4 3 2 1 0
RAS - RAS - CAS/OE
R BIOS AREA PCG LOW ADJUST
Bits 1-0 CAS,OE ADJUST

00 = approximately 6.5 ns adjustment (nominal)
01 = approximately 5 ns adjustment (nominal)
10 = approximately 3.5 ns adjustment (nominal)
11 = no adjustment
If MM8204_7 = 0, the trailing edges of CAS/OE active are delayed by the amount indi-
cated by these bits. If MM8204_7 = 1, the entire CAS/OE active pulses are shifted (de-
layed) by the amount indicated by these bits. The timing adjustment shown above is
an approximation. It is affected by both process and signal loading and must be
measured for each design.

Bit 2 RAS-LOW - RAS Low Timing Select

0 = 4.5 MCLKs
1 = 3.5 MCLKs
This parameter specifies the length of the RAS active time for a single row/column ac-
cess. RAS may be held low longer to accommodate additional page mode accesses
to the same row.
Bit 3 RAS-PCG - RAS Precharge Timing Select

0 = 3.5 MCLKs
1 = 2.5 MCLKs
When RAS goes high to end a memory cycle, this parameter specifies the minimum
period it must be held high before beginning another memory access cycle.
Bits 6-4 BIOS AREA
Reserved for use by the video BIOS.
Bit 7 Reserved
Extended System Control 3 Register (CR69)

7 6 5 4 3 2 1 0
R R R R DISPLAY-START-ADDRESS
Bits 3–0 DISPLAY-START-ADDRESS

This field contains the upper 4 bits (19-16) of the display start address, allowing ad-
dressing of up to 4 MBytes of display memory. When a non-zero value is
programmed in this field, bits 5-4 of CR31 and 1-0 of CR51 (the old display start ad-
dress bits) are ignored.
Bits 7–4 Reserved

Extended System Control 4 Register (CR6A)

7 6 5 4 3 2 1 0
R R CPU-BASE-ADDRESS
Bits 5–0 CPU-BASE-ADDRESS

This field contains the upper 6 bits (19-14) of the CPU base address, allowing access-
ing of up to 4 MBytes of display memory via 64K pages. When a non-zero value is
programmed in this field, bits 3-0 of CR35 and 3-2 of CR51 (the old CPU base address
bits) are ignored. Bit 0 of CR31 must be set to 1 to enable this field. If linear address-
ing is enabled and a 64 KByte window is specified, these bits specify the 64K page to
be accessed at the base address specified in CR59 and CR5A. Otherwise, the base ad-
dress is normally at A000H.
Bits 7–6 Reserved
Extended BIOS Flag 3 Register (CR6B)

7 6 5 4 3 2 1 0

This register is reserved for use by the S3 BIOS.
Extended BIOS Flag 4 Register (CR6C)

7 6 5 4 3 2 1 0

This register is reserved for use by the S3 BIOS.

Extended BIOS Flag 5 Register (CR6D)

This register is reserved for use by the BIOS.
7 6 5 4 3 2 1 0
RESERVED
Bits 7–0 Reserved
RAMDAC Signature Test Data Register (CR6E)

This register is reserved for use by the BIOS.
7 6 5 4 3 2 1 0
RAMDAC SIGNATURE TEST DATA
Bits 7–0 RAMDAC SIGNATURE TEST DATA
See Section 8.7 for a description of signature testing.
Configuration 4 Register (CR6F)
See Bit Definitions Address: 3?5H, Index 6FH

This is the fourth byte of power-on strapping bits. PD[28:24] are sampled at reset and the values are
written to bits 4-0 of this register. A5H must be written to CR39 to provide read/write access to this
register. This register will power up with a value of 1FH if any of PD[28:24] are not pulled low.
7 6 5 4 3 2 1 0
R R R WE ADJUST IOEN IOSEL R
Bit 0 Reserved = 0
This bit must be cleared to 0 by pulling down PD24 at reset.

Bit 1 IOSEL - Serial Port I/O Address Select (read/write)

0 = Serial Port register is accessed at I/O address 000E8H
1 = Serial Port register is accessed at I/O address 000E2H
Bit 2 of this register must be cleared to 0 for this bit to have effect.
Bit 2 IOEN - Serial Port Address Type Select (read/write)

0 = Serial Port register is accessed at the I/O port defined in bit 1 of this register or at
its MMIO address (offset FF20H)
1 = Serial Port register is accessed at its MMIO address only (offset FF20H)
Enabling I/O access allows the serial port to be used for I2C communications when
ViRGE is disabled.
Bits 4-3 WE Delay (read/write)

00 = 3 units delay
01 = 2 units delay
10 = 1 unit delay
11 = 0 units delay
If MM8204_8 = 0, both the leading and trailing edges of WE are delayed by the
amount specified in these bits. If MM8204_8 = 1, only the trailing edge is delayed by
the amount specified in these bits.
Bits 7-5 Reserved

Section 19: S3d Engine Register Descriptions
This section describes the S3d Registers for ViRGE. These registers are used to accelerate the display
of 2D and 3D graphics.
In all register bit descriptions, the letter “R” identifies reserved bits (a reserved bit’s read value is
undefined unless noted, and you may write only zero to a reserved bit).
19.1 REGISTER MAPPING AND ADDRESSING
The S3d registers are memory-mapped starting at an offset of 100 A0000H from the base address.
Table 19-1 shows the location of each register organized by drawing command type. All registers with
the same mnemonic for different commands are the same register with multiple addresses. For
example, at "xx" = D4, the three 2D commands use a register called SRC_BASE, with each of the 2D
commands having a unique address for this register. Similarly, the two 3D commands share the Z-BASE
register. The DEST_BASE register is shared by all commands at "xx" = D8. Each shared register is
described only once in a section (2D or 3D) along with all of its addresses.
S3D ENGINE REGISTER DESCRIPTIONS 19-1

Table 19-1. S3d Register Memory Map
Offset From Base Address (Little Endian Addressing)

100 A0xxH 100 A4xxH 100 A8xxH 100 ACxxH 100 B0xxH 100 B4xxH
xx Pattern Registers BitBLT/Rect Fill 2D Line 2D Polygon 3D Line 3D Triangle
D4 SRC_BASE SRC_BASE SRC_BASE Z_BASE Z_BASE
D8 DEST_BASE DEST_BASE DEST_BASE DEST_BASE DEST_BASE
DC CLIP_L_R CLIP_L_R CLIP_L_R CLIP_L_R CLIP_L_R
E0 CLIP_T_B CLIP_T_B CLIP_T_B CLIP_T_B CLIP_T_B
E4 DEST_SRC_STR DEST_SRC_STR DEST_SRC_STR DEST_SRC_STR DEST_SRC_STR
E8 MONO_PAT_0 MONO_PAT_0 Z_STRIDE Z_STRIDE
EC MONO_PAT_1 MONO_PAT_1 TEX_BASE
F0 PAT_BG_CLR PAT_BG_CLR TEX_BDR_CLR
F4 PAT_FG_CLR PAT_FG_CLR PAT_FG_CLR FOG_CLR FOG_CLR
F8 SRC_BG_CLR COLOR0
FC SRC_FG_CLR COLOR1
100 Start CMD_SET CMD_SET CMD_SET CMD_SET CMD_SET
104 (100 to 1BC) RWIDTH_HEIGHT TBV
108 RSRC_XY TBU
10C RDEST_XY TdWdX
110 TdWdY
114 TWS
118 TdDdX
11C TdVdX
120 TdUdX
124 TdDdY
128 TdVdY
12C TdUdY
130 TDS
134 TVS
138 TUS
13C TdGdX_dBdX
140 TdAdX_dRdX
144 3dGdY_dBdY TdGdY_dBdY
148 3dAdY_dRdY TdAdY_dRdY
14C 3GS_BS TGS_BS
150 3AS_RS TAS_RS
154 TdZdX
158 3dZ TdZdY
15C 3ZSTART TZS
160 TdXdY12
164 TXEND12
168 PRdX TdXdY01
16C LXEND0_END1 PRXSTART 3XEND0_END1 TXEND01
170 LdX PLdX 3dX TdXdY02
174 LXSTART PLXSTART 3XSTART TXSTART02
178 LYSTART PYSTART 3YSTART TYSTART
17C LYCNT PYCNT 3YCNT TY_01_Y12
19-2 S3D ENGINE REGISTER DESCRIPTIONS

19.2 COLOR PATTERN REGISTERS
When the ROP chosen for a BitBLT uses a color pattern, the 8x8 pixel pattern data must be stored in
the register address space starting at offset 100 A100H. The amount of register space required is a
function of the color depth as shown in Table 19-2. The value is derived by multiplying 64 pixels (8x8
pattern) by the color depth (bytes/pixel) and dividing by 4 bytes/doubleword (32-bit registers).
Table 19-2 Color Pattern Data Storage Requirements
Color Depth (Bits/Pixel) Storage Requirements (Doublewords) Offset Range (Hex)

8 16 100 A100 - 100 A13C
16 32 100 A100 - 100 A17C
24 48 100 A100 - 100 A1BC
The pattern color data is written starting with the upper left pixel (0,0) to the end of the line (7,0) and
then proceeding across each line to the last pixel (8,8). Pixel 0,0 is written to 100 A100H. The data are
stored fully packed.
For 8 bits/pixel, pixel 0,0 is written to the low order byte 0, pixel 1,0 is written to byte 1, etc. Pixel 4,0
would then be written to the low order byte of 100 A104H and so on. The 8-bit value for each pixel is
an index to the DAC palette registers.
For 16 bits/pixel, pixel 0,0 is written to the low order word of 100 A100H, pixel 1,0 to the high order
word, etc. Either RGB1555 or RGB565 coding can be used.
For 24 bits/pixel, pixel 0,0 is written to the 3 low order bytes of 100 A100H (RGB888 format). The blue
value for pixel 1,0 is written to the high order byte of 100 A100H. The red and green values for pixel
1,0 are written to the low order word of 100 A104H and so on. Thus pixel data crosses doubleword
boundaries.

19.3 2D REGISTERS
This section describes all the registers used with the 2D drawing commands (BitBLT/Rectangle Fill, 2D
Line and 2D Polygon).
Source Base Address Register (SRC_BASE) (MMA4D4, MMA8D4, MMACD4)
Read/Write Offset: A4D4H (BitBLT), A8D4H (2D Line), ACD4H (2D Polygon)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOURCE BASE ADDRESS 0 0 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R R R R R R R R R R SOURCE BASE ADDRESS
Bits 2-0 Reserved = 0
Bits 21-3 SOURCE BASE ADDRESS
Value = base address in video memory of source data for 2D drawing operations
(quadword aligned)
This value is required when the source is video memory (screen). It is different from
the destination base address when the data is located in off-screen memory. This is
the 0,0 pixel address for off-screen data. The stride for off-screen data is programmed
in the Destination/Source Stride register (MMxxE4).
Bits 31-22 Reserved
Destination Base Address Register (DEST_BASE) (MMA4D8, MMA8D8, MMACD8)
Read/Write Offset: A4D8H (BitBLT), A8D8H (2D Line), ACD8H (2D Polygon)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DESTINATION BASE ADDRESS 0 0 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R R R R R R R R R R DESTINATION BASE ADDRESS

Bits 21-3 DESTINATION BASE ADDRESS
Value = base address in video memory of destination data for 2D drawing operations
(quadword aligned)
This is the 0,0 pixel address in video memory for the screen resolution being used. It
will normally be at the start of video memory.
Bits 31-22 Reserved
Left/Right Clipping Register (CLIP_L_R) (MMA4DC, MMA8DC, MMACDC)
Read/Write Offset: A4DCH (BitBLT), A8DCH (2D Line), ACDCH (2D Polygon)
Bit 1 of the Command Set register must be set to 1 for the settings in this register to have effect.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R R R R R RIGHT CLIPPING LIMIT
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R R R R R LEFT CLIPPING LIMIT
Bits 10-0 RIGHT CLIPPING LIMIT
Value = pixel position of the last pixel to be drawn on each line. The first pixel is 0.
Bits 15-11 Reserved
Bits 26-16 LEFT CLIPPING LIMIT
Value = pixel position of the first pixel to be drawn on each line. The first pixel is 0.
Bits 31-27 Reserved

Top/Bottom Clipping Register (CLIP_T_B) (MMA4E0, MMA8E0, MMACE0)
Read/Write Offset: A4E0H (BitBLT), A8E0H (2D Line), ACE0H (2D Polygon)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R R R R R BOTTOM CLIPPING LIMIT
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R R R R R TOP CLIPPING
LIMIT
Bits 10-0 BOTTOM CLIPPING LIMIT
Value = line position of the last line to be drawn. The first line is 0.
Bits 15-11 Reserved
Bits 26-16 TOP CLIPPING LIMIT
Value = line position of the first line to be drawn. The first line is 0.
Bits 31-27 Reserved
Destination/Source Stride Register (DEST_SRC_STR) (MMA4E4, MMA8E4, MMACE4)
Read/Write Offset: A4E4H (BitBLT), A8E4H (2D Line), ACE4H (2D Polygon)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R R R R SOURCE STRIDE 0 0 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R R R R DESTINATION STRIDE 0 0 0
Bits 11-0 SOURCE STRIDE
Value = byte offset of vertically adjacent pixels for the source data. Bits 2-0 must be
000b.
Bits 15-12 Reserved
Bits 27-16 DESTINATION STRIDE
Value = byte offset of vertically adjacent pixels for the destination data. Bits 2-0 must
be 000b.

Bits 31-28 Reserved
Mono Pattern 0 Register (MONO_PAT_0) (MMA4E8, MMACE8)
Read/Write Offset: A4E8H (BitBLT), ACE8H (2D Polygon)

The pattern data in this register is used when bit 8 of the Command Set register is set to 1 to specify
a mono pattern. The first four lines of the pattern are specified in this register.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
L20 L21 L22 L23 L24 L25 L26 L27 L10 L11 L12 L13 L14 L15 L16 L17
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Bits 31-0 MONO PATTERN 0
Value = first (low order) 32 bits of a 64-bit mono pattern
The second (high order) 32 bits are found in the Mono Pattern 1 register. These two
registers define an 8x8 mono pattern. In the above register bit table, LXY means bit Y
of line X, with the leftmost bit of each line (row) being bit 0.
Mono Pattern 1 Register (MONO_PAT_1) (MMA4EC, MMACEC)
Read/Write Offset: A4ECH (BitBLT), ACECH (2D Polygon)

The pattern data in this register is used when bit 8 of the Command Set register is set to 1 to specify
a mono pattern. The second four lines of the pattern are specified in this register.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
L80 L81 L82 L83 L84 L85 L86 L87 L70 L71 L72 L73 L74 L75 76 L77
Bits 31-0 MONO PATTERN 1
Value = second (high order) 32 bits of a 64-bit mono pattern (little endian format)
The first (low order) 32 bits are found in the Mono Pattern 0 register. These two regis-
ters define an 8x8 mono pattern. In the above register bit table, LXY means bit Y of
line X, with the leftmost bit of each line (row) being bit 0.

Mono Pattern Background Color Register (PAT_BG_CLR) (MMA4F0, MMACF0)
Read/Write Offset: A4F0H (BitBLT), ACF0H (2D Polygon)

The pattern color data in this register is used when bit 8 of the Command Set register is set to 1 to
specify a mono pattern and the pattern bit is 0. The color depth specified must match the value se-
lected by bits 4-2 of the Command Set register.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA 2 DATA 1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R R R R R R R R DATA 3
Bits 7-0 DATA 1
Value = DAC CLUT index (8 bits/pixel), lower byte of color data (15/16 bits/pixel), blue
color index (24 bits/pixel
Bits 15-8 DATA 2
Value = Reserved (8 bits/pixel), upper byte of color data (15/16 bits/pixel), green color
index (24 bits/pixel)
Bit 23-16 DATA 3
Value = Reserved (8, 15 or 16 bits/pixel), red color index (24 bits/pixel)
Bits 31-24 Reserved

Mono Pattern Foreground Color Register (PAT_FG_CLR) (MMA4F4, MMA8F4, MMACF4)
Read/Write Offset: A4F4H (BitBLT), A8F4H (2D Line), ACF4H (2D Polygon)
The pattern color data in this register is used when bit 8 of the Command Set register is set to 1 to
specify a mono pattern and the pattern bit is 1. It is also the pattern color used for rectangle fills,
line draws and polygon fills, regardless of any pattern specification. The color depth specified must
match the value selected by bits 4-2 of the Command Set register.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA 2 DATA 1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Bits 7-0 DATA 1
Bits 15-8 DATA 2
Bit 23-16 DATA 3
Bits 31-24 Reserved

Source Background Color Register (SRC_BG_CLR) (MMA4F8)
Read/Write Offset: A4F8H (BitBLT)

For mono image transfers (bit 6 of the Command Set register set to 1), this is the source color when
the image bit is 0. It is not used when color compare is enabled (bit 9 of the Command Set register
set to 1). The color depth specified must match the value selected by bits 4-2 of the Command Set
register.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA 2 DATA 1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Bits 7-0 DATA 1
Bits 15-8 DATA 2
Bit 23-16 DATA 3
Bits 31-24 Reserved

Source Foreground Color Register (SRC_FG_CLR) (MMA4FC)
Read/Write Offset: A4FCH (BitBLT)

For mono image transfers (bit 6 of the Command Set register set to 1), this is the source color when
the image bit is 1. For 8- or 15/16-bits/pixel color image transfers when transparent color is enabled
(bit 9 of the Command Set register set to 1), the image data color is compared with this color. If it
matches, the screen is not updated. If it does not match, the image data color is used to update the
screen. In all cases, the color depth specified must match the value selected by bits 4-2 of the Com-
mand Set register.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA 2 DATA 1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Bits 7-0 DATA 1
color index (24 bits/pixel)
The 24 bits/pixel color is used only for mono image transfers.
Bits 15-8 DATA 2
Value = DAC CLUT index (8 bits/pixel), upper byte of color data (15/16 bits/pixel),
green color index (24 bits/pixel)
The 8 bits/pixel color must be programmed to both the DATA 1 and DATA 2 bytes.
The 24 bits/pixel color is used only for mono image transfers.
Bit 23-16 DATA 3
This color is used only for mono image transfers.
Bits 31-24 Reserved

Command Set Register (CMD_SET) (MMA500, MMA900, MMAD00)
Read/Write Offset: A500H (BitBLT), A900H (2D Line), AD00H (2D Polygon)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R R FDO ITA TP MP IDS MS DE DEST FORMAT HC AE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
23D 2D COMMAND YP XP 256 ROPS R
Bit 0 AE - Autoexecute
0 = Execute command when this register is written to
1 = Execute command when the highest address register in a drawing type set is
written to
The highest address register in a drawing type set is easily seen in Table 20-1, where
it is the bottom register in each column. For example, if this bit is set to 1, a BitBLT is
executed when the RDEST_XY (MMA50C) register is written to. Similarly, execution
of a 2D line command is based on writing to the LYCNT register, etc. This setting al-
lows multiple executions of a given command using different parameters without re-
writing the Command Set register.
To turn off autoexecute without executing a command, write to this register with this
bit cleared to 0 and bits 30-27 programmed to 1111b (NOP).
Bit 1 HC - Hardware Clipping Enable

0 = Hardware clipping disabled
1 = Hardware clipping enabled
The settings in the clipping registers (MMxxDC, MMxxE0) are effective only when this
bit is set to 1.
Bits 4-2 DEST FORMAT - Destination Color Format

000 = 8 bits/pixel palettized
001 = 16 bits/pixel (RGB1555 or RGB565)
010 = 24 bits/pixel, RGB888
Bit 5 DE - Draw Enable

0 = Don’t update screen
1 = Update screen (normal draw)
Parameter values calculated during the execution of the command end up the same
regardless of the setting of this bit. That is, the command is fully executed except for
the possible non-drawing of the new pixel.
Bit 6 MS - Mono Source (Image Transfers)

0 = Source data is the same pixel depth as the destination data
1 = Source data is mono

Bit 7 IDS - Image Data Source

0 = Source data is from video memory (screen)
1 = Source data is from the image transfer port (CPU, system memory)
When this bit is set to 1, source data is provided by CPU writes to the offset range of
100 0000H to 100 7FFFH or the alternate image transfer port range of 100 D000H to
100 EFFFH. Bit 6 of this register specifies whether mono or color data is being trans-
ferred.
Bit 8 MP - Mono Pattern

0 = Pattern data is the same pixel depth as the destination data
1 = Pattern data is mono
This bit is cleared to 0 for a BitBLT using a ROP with a color source. The 8x8 color pat-
tern is found starting at location 100 A100H. For a mono pattern, the pattern informa-
tion is determined from the Mono Pattern 0 and 1 registers. This bit must be set to 1
for a rectangle fill operation.
Bit 9 TP - Transparent
0 = A mono source image transfer uses both the source foreground (image bit = 1)
and source background (image bit = 0) colors to update the screen. A color image
transfer uses the CPU-provided colors.
1 = A mono source image transfer updates the screen only when the source
foreground color is selected (image bit = 1). Otherwise (image bit = 0), the screen
pixel is left unchanged. A color image transfer updates the screen with the
transmitted color only when that color does not match the color in the source
foreground color register. If a color match occurs, the destination pixel is not
updated. This transparent color feature for color image transfers can be used for
8- and 16-bit color modes, but not for 24-bit color.
Note: This bit is effective only when bit 7 of this register is set to 1. A setting of 1 for
the mono source case provides "transparent text" capability. The term "transparent
text" refers to the updating of only the pixels forming the text characters and not the
entire rectangular text block using the background color for non-text areas.
Bits 11-10 ITA - Image Transfer Alignment

00 = Data for each line of an image transfer is byte aligned
01 = Data for each line of an image transfer is word aligned
10 = Data for each line of an image transfer is doubleword aligned
11 = Reserved
All image transfers are doublewords. If the end of a bit map line is reached within a
doubleword transfer, the setting of these bits determines how the start of the next
line is handled. If doubleword aligned, data in the last doubleword beyond the end of
the line is discarded and the next line begins on the next doubleword. If word aligned
and an upper word of data remains after the end of the line is reached, that word will
be used to begin the next line. If byte aligned, the next line with begin on the next
byte in the doubleword after the end of the line. The latter is used only for mono
source data, e.g., text.

Bits 13-12 FDO - First Doubleword Offset (Image Transfers)

00 = Entire first doubleword of an image transfer contains valid data
01 = Start with the second byte of the first doubleword of an image transfer
10 = Start with the third byte of the first doubleword of an image transfer
11 = Start with the fourth byte of the first doubleword of an image transfer
Bits 16-14 Reserved
Bits 24-17 256 ROPS - 256 Raster Operations
Value = binary key selecting one of 256 three operand raster operations as defined in
Appendix A.
The full 256 three-operand ROPs are available for BitBLT and image transfer opera-
tions. The other 2D operations (Rectangle Fill, Line Draw and Polygon Fill) can only
use the subset of the 256 ROPs that does not have a source. When the ROP contains a
pattern, the pattern must be mono and the hardware forces the pattern value to the
pattern foreground color regardless of the values programmed in the Mono Pattern
registers.
Bit 25 XP - X Positive (BitBLT)

0 = A BitBLT is performed from right to left (X negative)
1 = A BitBLT is performed from left to right (X positive)
Bit 26 YP - Y Positive (BitBLT)

0 = A BitBLT is performed from bottom to top (Y negative)
1 = A BitBLT is performed from top to bottom (Y positive)
Bits 30-27 2D COMMAND

0000 = BitBLT
0001 = Reserved
0010 = Rectangle Fill
0011 = Line Draw
0100 = Reserved
0101 = Polygon Fill
0110 = Reserved
0111 = Reserved
1000 = Reserved
1001 = Reserved
1010 = Reserved
1011 = Reserved
1100 = Reserved
1101 = Reserved
1110 = Reserved
1111 = NOP
The NOP option is required to turn off autoexecute without executing a command.
See the definition for bit 0 of this register.
Bit 31 23D - 2D or 3D Select

0 = A 2D command is being executed

Rectangle Width/Height Register (RWIDTH_HEIGHT) (MMA504)
Read/Write Offset: A504H (BitBLT)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R R R R R RECTANGLE HEIGHT
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R R R R R RECTANGLE WIDTH
Bits 10-0 RECTANGLE HEIGHT
Value = height in lines of the rectangle to be drawn or blitted
A value of 1 equals 1 line.
Bits 15-11 Reserved
Bits 26-16 RECTANGLE WIDTH
Value = width in pixels of the rectangle to be drawn or blitted
A value of 0 equals 1 pixel/line.
Bits 31-27 Reserved
Rectangle Source XY Register (RSRC_XY) (MMA508)
Read/Write Offset: A508H (BitBLT)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R R R R R SOURCE Y
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R R R R R SOURCE X
Bits 10-0 SOURCE Y
Value = y coordinate in lines of the upper left hand corner of the source rectangle for
a BitBLT
Bits 15-11 Reserved

Bits 26-16 SOURCE X
Value = x coordinate in pixels of the upper left hand corner of the source rectangle for
a BitBLT
Bits 31-27 Reserved
Note: The starting coordinate is 0,0.
Rectangle Destination XY Register (RDEST_XY) (MMA50C)
Read/Write Offset: A50CH (BitBLT)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R R R R R DESTINATION Y
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R R R R R DESTINATION X
Bits 10-0 DESTINATION Y
Value = y coordinate in lines of the upper left hand corner of the filled rectangle to be
drawn or the destination for a BitBLT
Bits 15-11 Reserved
Bits 26-16 DESTINATION X
Value = x coordinate in pixels of the upper left hand corner of the filled rectangle to
be drawn or the destination for a BitBLT
Bits 31-27 Reserved
Note: The starting coordinate is 0,0.

Line Draw Endpoints Register (LXEND0_END1) (MMA96C)
Read/Write Offset: A96CH (2D Line)

This register specifies the x coordinates of the first and last pixels drawn for a line. This provides
the ability to not draw the last pixel of each line segment when the line is to be extended to form a
polyline.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 END1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 0 0 0 0 END0
Bits 15-0 END1
Value = x coordinate (in pixels) of the last pixel to be drawn for the topmost scanline.
The first coordinate value is 0. Bits 15-11 are sign bits and must be 0’s to indicate a
positive value.
Bits 31-16 END0
Value = x coordinate (in pixels) of the first pixel to be drawn for the bottommost scan-
line. The first coordinate value is 0. Bits 31-27 are sign bits and must be 0’s to indicate
a positive value.
ViRGE line draw always proceeds from bottom to top. If the requested line is drawn
upward with a don’t draw the last pixel instruction, the END0 coordinate will be the
same as the requested start x coordinate and the END1 coordinate will be 1 less (if
drawn from left to right) or 1 more (if drawn from right to left) than the requested end
x coordinate. If the requested line is drawn downward, the END1 coordinate will be
the same as the requested start x coordinate and the END0 coordinate will be 1 more
(if drawn from right to left) or one less (if drawn from left to right) than the requested
end x coordinate. See the programming examples for 2D line draw for a more de-
tailed explanation.

Line Draw X Delta Register (LdX) (MMA970)
Read/Write Offset: A970H (2D Line)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
X DELTA LOW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
X DELTA HIGH
Bits 31-0 X DELTA
Value = - (∆X << 20)/∆Y) with integer division
If the requested line is from coordinates x1,y1 to x2,y2, ∆X is x2 - x1 and ∆Y is y2 - y1.

(∆X = x1 - x2 and ∆Y = y1 - y2 also works.) The field format is S11.20, i.e, bit 31 is the
sign bit (0 = positive), with 11 integer positions and 20 fractional positions.
Line Draw X Start Register (LXSTART) (MMA974)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
X START LOW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
X START HIGH
Bits 31-0 X START
For an X major line, + X DELTA, value = (x1 << 20) + (X DELTA/2)

For an X major line, - X DELTA, value = (x1 << 20) + (X DELTA/2) + ((1 << 20) - 1)
For a Y major line, value = x1 << 20
For an X major line, the absolute x value increases faster than the absolute y value as
the line is drawn. In this case, there may be more than one pixel drawn per scan line.
For a Y major line, the absolute y value increases faster than the absolute x value. In
this case, at most one pixel will be drawn per scan line. If the requested line is drawn
upward, x1 is the requested starting x coordinate. If the requested line is drawn down-
ward, x1 is the requested ending x coordinate. X DELTA is the value programmed in
MMA970. The field format is S11.20, i.e, bit 31 is the sign bit (0 = positive), with 11 in-
teger positions and 20 fractional positions.

Line Draw Y Start Register (LYSTART) (MMA978)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R R R R R Y START
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R R R R R R R R R R R R R R R R
Bits 10-0 Y START
Value = Y coordinate (in scan lines) of first scan line to be drawn
ViRGE draws lines from bottom to top. Therefore this value will be the largest of the
requested starting and ending y coordinates.
Bits 31-11 Reserved
Line Draw Y Count Register (LYCNT) (MMA97C)
Read/Write Offset: A97CH (2D Line)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R R R R R SCAN LINE COUNT
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIR R R R R R R R R R R R R R R R
Bits 10-0 SCAN LINE COUNT
Value = [abs (y2 - y1)] +1
y2 is the requested ending y coordinate and y1 is the requested starting y coordinate.
Bits 30-11 Reserved
Bit 31 DIR - Drawing Direction

0 = Draw line from right to left
1 = Draw line from left to right

Polygon Right X Delta Register (PRDX) (MMAD68)
Read/Write Offset: AD68H (Polygon Fill)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RIGHT EDGE X DELTA LOW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RIGHT EDGE X DELTA HIGH
Bits 31-0 RIGHT EDGE X DELTA

Polygon Right X Start Register (PRXSTART) (MMAD6C)
Read/Write Offset: AD6CH (Polygon Fill)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RIGHT EDGE X START LOW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RIGHT EDGE X START HIGH
Bits 31-0 RIGHT EDGE X START
For an X major line, value = (x1 << 20) - (RIGHT EDGE X DELTA/2) + (1 << 19)
For a Y major line, value = x1 << 20 + (1 << 19)

Polygon Left X Delta Register (PLDX) (MMAD70)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LEFT EDGE X DELTA LOW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LEFT EDGE X DELTA HIGH
Bits 31-0 LEFT EDGE X DELTA

Polygon Left X Start Register (PLXSTART) (MMAD74)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LEFT EDGE X START LOW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LEFT EDGE X START HIGH
Bits 31-0 LEFT EDGE X START
For an X major line, value = (x1 << 20) - (LEFT EDGE X DELTA/2) + (1 << 19)
For a Y major line, value = x1 << 20 + (1 << 19)

Polygon Y Start Register (PYSTART) (MMAD78)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R R R R R Y START
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Bits 10-0 Y START
requested starting and ending y coordinates. This value need only be programmed
once for each polygon.
Bits 31-11 Reserved
Polygon Y Count Register (PYCNT) (MMAD7C)
Read/Write Offset: AD7CH (Polygon Fill)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R R ULE URE R R R R R R R R R R R R
Value = [abs (y2 - y1] +1
The first polygon update proceeds upward to the first vertex. y2 is the requested end-
ing y coordinate for the line leading to that vertex and y1 is the requested starting y
coordinate for that line. Both bit 28 and bit 29 will be set to 1 for the first update. For
the second polygon update, only the X DELTA for the line extending from the first ver-
tex is re-specified and only the update bit (28 or 29) for that edge is set to 1. The
value in this scan line count field is set for the number of scan lines from the first ver-
tex to the second vertex. See the polygon fill programming examples for a more com-
plete explanation of how to program the polygon fill registers at each step to form a
complete polygon.
Bits 27-11 Reserved

Bit 28 URE - Update Right Edge

0 = Do not update right edge
1 = Update right edge
Bit 29 ULE - Update Left Edge

0 = Do not update left edge
1 = Update left edge
Bits 31-30 Reserved

19.4 3D REGISTERS
Z-Buffer Base Address Register (Z_BASE) (MMB0D4, MMB4D4)
Read/Write Offset: B0D4H (3D Line), B4D4H (3D Triangle)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z-BUFFER BASE ADDRESS 0 0 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R R R R R R R R R R Z-BUFFER BASE ADDRESS
Bits 21-3 Z-BUFFER BASE ADDRESS
Value = base address in video memory of the z-buffer used in 3D drawing operations
to store depth information for each pixel. Bits 2-0 must be 000b (quadword aligned).
Bits 31-22 Reserved
Destination Base Address Register (DEST_BASE) (MMB0D8, MMB4D8)
Read/Write Offset: B0D8H (3D Line), B4D8H (3D Triangle)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DESTINATION BASE ADDRESS 0 0 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R R R R R R R R R R DESTINATION BASE ADDRESS
Bits 21-3 DESTINATION BASE ADDRESS
Value = base address in video memory of destination data for 2D drawing operations.
Bits 2-0 must be 000b (quadword aligned).
This is the 0,0 pixel address in video memory for the screen resolution being used. It
will normally be at the start of video memory.
Bits 31-22 Reserved

Left/Right Clipping Register (CLIP_L_R) (MMB0DC, MMB4DC)
Read/Write Offset: B0DCH (3D Line), B4DCH (3D Triangle)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R R R R R RIGHT CLIPPING LIMIT
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R R R R R LEFT CLIPPING LIMIT
Bits 10-0 RIGHT CLIPPING LIMIT
Value = pixel position of the last pixel to be drawn on each line. The first pixel is 0.
Bits 15-11 Reserved
Bits 26-16 LEFT CLIPPING LIMIT
Value = pixel position of the first pixel to be drawn on each line. The first pixel is 0.
Bits 31-27 Reserved
Top/Bottom Clipping Register (CLIP_T_B) (MMB0E0, MMB4E0)
Read/Write Offset: B0E0H (3D Line), B4E0H (3D Triangle)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R R R R R BOTTOM CLIPPING LIMIT
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R R R R R TOP CLIPPING
LIMIT
Bits 10-0 BOTTOM CLIPPING LIMIT
Value = line position of the last line to be drawn. The first line is 0.
Bits 15-11 Reserved
Bits 26-16 TOP CLIPPING LIMIT
Value = line position of the first line to be drawn. The first line is 0.

Bits 31-27 Reserved
Destination/Source Stride Register (DEST_SRC_STR) (MMB0E4, MMB4E4)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R R R R SOURCE STRIDE 0 0 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R R R R DESTINATION STRIDE 0 0 0
Bits 11-0 SOURCE STRIDE (3D Triangle only)
Value = byte offset of vertically adjacent pixels for a flat (not mipmapped) texture
map. Bits 2-0 must be 000b.
Bits 15-12 Reserved
Bits 27-16 DESTINATION STRIDE
Value = byte offset of vertically adjacent pixels for the destination data. Bits 2-0 must
be 000b.
Bits 31-28 Reserved
Z Stride Register (Z_STRIDE) (MMB0E8, MMB4E8)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R R R R Z STRIDE 0 0 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Bits 11-0 Z STRIDE
Value = byte offset of vertically adjacent pixels for the Z-buffer data . Bits 2-0 must be
000b.
Z-buffer data is always 16 bits/pixel. If the destination format is 16 bits/pixel, the Z

stride will be the same as the destination stride. Otherwise, the Z stride will differ
from the destination stride according to the differing pixel depths.

Bits 31-12 Reserved
Texture Base Address Register (TEX_BASE) (MMB4EC)
Read/Write Offset: B4ECH (3D Triangle)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TEXTURE BASE ADDRESS 0 0 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R R R R R R R R R R TEXTURE BASE ADDRESS
Bits 21-3 TEXTURE BASE ADDRESS
Value = base address in video memory of the texture data (flat or mipmapped). Bits 2-
0 must be 000b (quadword aligned).
Bits 31-22 Reserved
Texture Border Color Register (TEX_BDR_CLR) (MMB4F0)
Read/Write Offset: B4F0H (3D Triangle)

This is used as the texel color for lighting when texture wrapping is not enabled (bit 26 of the Com-
mand Set register is cleared to 0) and the texture rectangle is too small to complete the fill. This
must be in the same format at the texture color.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA 2 DATA 1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Bits 7-0 DATA 1

Bits 15-8 DATA 2
Bit 23-16 DATA 3
Bits 31-24 Reserved
Fog Color Register (FOG_CLR) (MMB0F4, MMB4F4)
Read/Write Offset: B0F4H (3D Line), B0F4H (3D Triangle)

This is the fog color blended with the pixel color when bit 17 of the Command Set register is set to
1. This operation is also called depth cueing when the fog factor (source alpha) corresponds to the
distance from the viewer.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GREEN COLOR INDEX BLUE COLOR INDEX
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R R R R R R R R RED COLOR INDEX
Bits 7-0 BLUE COLOR INDEX
Bits 15-8 GREEN COLOR INDEX
Bit 23-16 RED COLOR INDEX
Bits 31-24 Reserved

Color0 Register (COLOR0) (MMB4F8)
Read/Write Offset: B4F8H (3D Triangle)

When using one of the Blend4 modes for texel storage, this register specifies one of the color limits
used in the interpolation of the texel color during the generate phase of pixel coloring.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Bits 31-24 Reserved
Color1 Register (COLOR1) (MMB4FC)
Read/Write Offset: B4FCH (3D Triangle)

When using one of the Blend4 modes for texel storage, this register specifies one of the color limits
used in the interpolation of the texel color during the generate phase of pixel coloring.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Bits 31-24 Reserved

Command Set Register (CMD_SET) (MMB100, MMB500)
Read/Write Offset: B100H (3D Line), B500H (3D Triangle)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TB TEX FLTR MODE MIPMAP LEVEL SIZE TEX CLR FORMAT DEST FORMAT HC AE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
23D 3D COMMAND TWE ZB MODE ZUP ZB COMP ABC FE TB
Bit 0 AE - Autoexecute
0 = Execute command when this register is written to
1 = Execute command when the highest address register in a drawing type set is
written to
The highest address register in a drawing type set is easily seen in Table 20-1, where
it is the bottom register in each column. For example, if this bit is set to 1, a 3D line is
executed when the 3YCNT (MMB17C) register is written to. Similarly, execution of a
3D Triangle command is based on writing to the TY01_Y12 (MMB57C) register. This
setting allows multiple executions of a given command using different parameters
without re-writing the Command Set register.
To turn off autoexecute without executing a command, write to this register with this
bit cleared to 0 and bits 30-27 programmed to 1111b (NOP).
Bit 1 HC - Hardware Clipping Enable

0 = Hardware clipping disabled
1 = Hardware clipping enabled
The settings in the clipping registers (MMxxDC, MMxxE0) are effective only when this
bit is set to 1.
Bits 4-2 DEST FORMAT - Destination Color Format

000 = 8 bits/pixel palettized
001 = 16 bits/pixel (ZRGB1555)
010 = 24 bits/pixel, RGB888
Bits 7-5 TEX CLR FORMAT - Texel Color Format

011 = 8 bits/pixel (Alpha4, Blend4)
100 = 4 bits/pixel (Blend4, low nibble)
101 = 4 bits/pixel (Blend4, high nibble)
110 = 8 bits/pixel (palettized)
111 = YU/YV (16 bits/pixel equivalent)

Bits 11-8 MIPMAP LEVEL SIZE
Value = s, where 2s is the size of one side of the largest mipmap texture rectangle
For example, a value of 4 specifies the largest mipmap as 24 x 24 = 16 x 16 texels. The

largest allowable s value is 9, which specifies a 512 x 512 texel texture.
Bits 14-12 TEX FLTR MODE - Texture Filtering Mode

000 = M1TPP (MIP_NEAREST)
001 = M2TPP (LINEAR_MIP_NEAREST)
010 = M4TPP (MIP_LINEAR)
011 = M8TPP (LINEAR_MIP_LINEAR)
100 = 1TPP (NEAREST)
101 = V2TPP (used for YU/YV video format - bits 7-5 of this register = 111b)
110 = 4TPP (LINEAR)
111 = Reserved
Only modes with no filtering (000b and 100b) can be used with 8 bits/pixel palettized
data. In addition, the texture blending mode must be decal (bits 16-15 of this register
= 10b.)
Bits 16-15 TB - Texture Blending Mode

00 = Complex Reflection
01 = Modulate
10 = Decal
11 = Reserved
Bit 17 FE - Fog Enable

0 = Fog color blending disabled
1 = Fog color blending enabled
Fogging is not available for Gouraud shaded triangles or if source alpha is used for
blending. If the fog factor (source pixel alpha value) corresponds to the distance from
the viewer, this function is also called depth cueing.
Bits 19-18 ABC - Alpha Blending Control

00 = No alpha blending
01 = No alpha blending
10 = Use texture alpha for blending
11 = Use source alpha for blending
Bits 22-20 ZB COMP - Z-buffer Compare Mode

000 = z compare never passes
001 = Pass if Zs > Zzb
010 = Pass if Zs = Zzb
011 = Pass if Zs ≥ Zzb
100 = Pass if Zs < Zzb
101 = Pass if Zs ≠ Zzb
110 = Pass if Zs ≤ Zzb
111 = z compare always passes

Bit 23 ZUP - Z Update Enable

0 = Never update z-buffer
1 = Update z-buffer with new (source) pixel z value if the z compare passes
Bits 25-24 ZB MODE - Z-buffering Mode

00 = Normal Z-buffering
01 = MUX buffering (Z-buffer pass)
10 = MUX buffering (draw buffer pass)
11 = No Z-buffering
Bit 26 TWE - Texture Wrap Enable

0 = Texture wrapping disabled
1 = Texture wrapping enabled
If wrapping is disabled, the texture border color (MMB4F0) may need to be specified.
Bits 30-27 3D COMMAND

0000 = Gouraud Shaded Triangle
0001 = Lit Texture Triangle
0010 = Unlit Texture Triangle
0011 = Reserved
0100 = Reserved
0101 = Lit Texture Triangle with perspective
0110 = Unlit Texture Triangle with perspective
0111 = Reserved
1000 = 3D Line
1001 = Reserved
1010 = Reserved
1011 = Reserved
1100 = Reserved
1101 = Reserved
1110 = Reserved
1111 = NOP
The NOP option is required to turn off autoexecute without executing a command.
See the definition for bit 0 of this register.
Bit 31 23D - 2D or 3D Select


3D Line Draw GB Delta Register (3dGdY_dBdY) (MMB144)
Read/Write Offset: B144H (3D Line)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BLUE DELTA
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GREEN DELTA
Bits 15-0 BLUE DELTA
Value = Delta value for the accumulation of the blue attribute. The format is S8.7.
Bits 31-16 GREEN DELTA
Value = Delta value for the accumulation of the green attribute. The format is S8.7.
3D Line Draw AR Delta Register (3dAdY_dRdY) (MMB148)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RED DELTA
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ALPHA DELTA
Bits 15-0 RED DELTA
Value = Delta value for the accumulation of the red attribute. The format is S8.7.
Bits 31-16 ALPHA DELTA
Value = Delta value for the accumulation of the alpha attribute. The format is S8.7.

3D Line Draw GB Start Register (3GS_BS) (MMB14C)
Read/Write Offset: B14CH (3D Line)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 BLUE START
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 GREEN START
Bits 15-0 BLUE START
Value = Starting value for the accumulation of the blue attribute. The format is S8.7,
where S must be 0.
Bits 31-16 GREEN START
Value = Starting value for the accumulation of the green attribute. The format is S8.7,
where S must be 0.
3D Line Draw AR Start Register (3AS_RS) (MMB150)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 RED START
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 ALPHA START
Bits 15-0 RED START
Value = Starting value for the accumulation of the red attribute. The format is S8.7,
where S must be 0.
Bits 31-16 ALPHA START
Value = Starting value for the accumulation of the alpha attribute. The format is S8.7,
where S must be 0.

3D Line Draw Z Delta Register (3dZ) (MMB158)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z DELTA LOW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Z DELTA HIGH
Bits 31-0 Z DELTA
Value = Delta value for the accumulation of the Z attribute. The format is S16.15.
3D Line Draw Z Start Register (3ZSTART) (MMB15C)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z START LOW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 Z START HIGH
Bits 31-0 Z START
Value = Starting value for the accumulation of the Z attribute. The format is S16.15,
where S must be 0.

3D Line Draw Endpoints Register (3XEND0_END1) (MMB16C)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 END1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 0 0 0 0 END0
Bits 15-0 END1
Value = x coordinate (in pixels) of the last pixel to be drawn for the topmost scanline.
The first coordinate value is 0. Bits 15-11 are sign bits and must be 0’s to indicate a
positive value.
Bits 31-16 END0
Value = x coordinate (in pixels) of the first pixel to be drawn for the bottommost scan-
line. The first coordinate value is 0. Bits 31-27 are sign bits and must be 0’s to indicate
a positive value.
3D Line Draw X Delta Register (3dX) (MMB170)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
X DELTA LOW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
X DELTA HIGH
Bits 31-0 X DELTA
Value = Delta value for the accumulation of the X attribute. The format is S11.20.

3D Line Draw X Start Register (3XSTART) (MMB174)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
X START LOW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 X START HIGH
Bits 31-0 X START
Value = Starting value for the accumulation of the X attribute. The format is S11.20,
where S must be 0.
3D Line Draw Y Start Register (3YSTART) (MMB178)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R R R R R Y START
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Bits 10-0 Y START
requested starting and ending y coordinates.
Bits 31-11 Reserved

3D Line Draw Y Count Register (3YCNT) (MMB17C)
Read/Write Offset: AB1CH (3D Line)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIR R R R R R R R R R R R R R R R
Value = The number of scan lines to be rendered
Bits 30-11 Reserved
Bit 31 DIR - Drawing Direction

0 = Draw line from right to left
1 = Draw line from left to right
Triangle Base V Register (TBV) (MMB504)
Read/Write Offset: B504H (3D Triangle)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BASE V
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R R R R R R R R R R R R BASE V
Bits 19-0 BASE V
Value = Base vertical coordinate value for texels. The format is (4 + s).(16-s), where s
is the number of mipmap levels programmed in MMB500_11-8.
This is the common offset for all V coordinate values for textures.
Bits 31-20 Reserved

Triangle Base U Register (TBU) (MMB508)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BASE U
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R R R R R R R R R R R R BASE U
Bits 19-0 BASE U
Value = Base horizontal coordinate value for texels. The format is (4 + s).(16-s), where
s is the number of mipmap levels programmed in MMB500_11-8.
This is the common offset for all U coordinate values for textures.
Bits 31-20 Reserved
Triangle WX Delta Register (TdWdX) (MMB50C)
Read/Write Offset: B50CH (3D Triangle)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WX DELTA LOW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WX DELTA HIGH
Bits 31-0 WX DELTA
Value = Delta value for the accumulation of the W attribute (homogeneous coordi-
nate) with respect to X. The format is S12.19.
W is the depth coordinate for 3D texture maps.

Triangle WY Delta Register (TdWdY) (MMB510)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WY DELTA LOW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WY DELTA HIGH
Bits 31-0 WY DELTA
Value = Delta value for the accumulation of the W attribute (homogeneous coordi-
nate) with respect to Y. The format is S12.19.
Triangle W Start Register (TWS) (MMB514)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W START LOW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 W START HIGH
Bits 31-0 W START
Value = Starting value for the accumulation of the W attribute (homogeneous coordi-
nate). The format is S12.19, where S must be 0.

Triangle DX Delta Register (TdDdX) (MMB518)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DX DELTA LOW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DX DELTA HIGH
Bits 31-0 DX DELTA
Value = Delta value for the accumulation of the D attribute with respect to X. The for-
mat is S4.27.
Triangle VX Delta Register (TdVdX) (MMB51C)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VX DELTA LOW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VX DELTA HIGH
Bits 31-0 VX DELTA
Value = Delta value for the accumulation of the V attribute with respect to X. The for-
mat is S(4 + s).(27 - s) if perspective is enabled (3D command = 0101b or 0110b),
where s is the number of mipmap levels programmed in MMB500_11-8. The format is
S12.8.11 without perspective enabled. This format is 1 sign bit, 12 integer bits, 8 filter
bits and 11 fractional bits.

Triangle UX Delta Register (TdUdX) (MMB520)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UX DELTA LOW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UX DELTA HIGH
Bits 31-0 UX DELTA
Value = Delta value for the accumulation of the U attribute with respect to X. The for-
Triangle DY Delta Register (TdDdY) (MMB524)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DY DELTA LOW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DY DELTA HIGH
Bits 31-0 DY DELTA
Value = Delta value for the accumulation of the D attribute with respect to Y. The for-
mat is S4.27.

Triangle VY Delta Register (TdVdY) (MMB528)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VY DELTA LOW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VY DELTA HIGH
Bits 31-0 VY DELTA
Value = Delta value for the accumulation of the V attribute with respect to Y. The for-
Triangle UY Delta Register (TdUdY) (MMB52C)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UY DELTA LOW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UY DELTA HIGH
Bits 31-0 UY DELTA
Value = Delta value for the accumulation of the U attribute with respect to Y. The for-

Triangle D Start Register (TDS) (MMB530)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D START
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 D START
Bits 31-0 D START
Value = Starting value for the accumulation of the D attribute. The format is S4.27.
Triangle V Start Register (TVS) (MMB534)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
V START LOW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 V START HIGH
Bits 31-0 V START
Value = Starting value for the accumulation of the V attribute. The format is
S(4 + s).(27 - s) if perspective is enabled (3D command = 0101b or 0110b), where s is
the number of mipmap levels programmed in MMB500_11-8. The format is S12.8.11
without perspective enabled. This format is 1 sign bit, 12 integer bits, 8 filter bits and
11 fractional bits. In either case, the sign bit must be 0.
The V attribute is the vertical coordinate value for a texel.

Triangle U Start Register (TUS) (MMB538)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
U START LOW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 U START HIGH
Bits 31-0 U START
Value = Starting value for the accumulation of the U attribute. The format is
S(4 + s).(27 - s) if perspective is enabled (3D command = 0101b or 0110b), where s is
the number of mipmap levels programmed in MMB500_11-8. The format is S12.8.11
without perspective enabled. This format is 1 sign bit, 12 integer bits, 8 filter bits and
11 fractional bits. In either case, the sign bit must be 0.
The U attribute is the horizontal coordinate value for a texel.
Triangle GBX Delta Register (TdGdX_dBdX) (MMB53C)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BLUE X DELTA
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GREEN X DELTA
Bits 15-0 BLUE X DELTA
Value = Delta value for the accumulation of the blue attribute with respect to X. The
format is S8.7.
Bits 31-16 GREEN X DELTA
Value = Delta value for the accumulation of the green attribute with respect to X. The
format is S8.7.

Triangle ARX Delta Register (TdAdX_dRdX) (MMB540)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RED X DELTA
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ALPHA X DELTA
Bits 15-0 RED X DELTA
Value = Delta value for the accumulation of the red attribute with respect to X. The
format is S8.7.
Bits 31-16 ALPHA X DELTA
Value = Delta value for the accumulation of the alpha attribute with respect to X. The
format is S8.7.
Triangle GBY Delta Register (TdGdY_dBdY) (MMB544)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BLUE Y DELTA
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GREEN Y DELTA
Bits 15-0 BLUE Y DELTA
Value = Delta value for the accumulation of the blue attribute with respect to Y. The
format is S8.7.
Bits 31-16 GREEN Y DELTA
Value = Delta value for the accumulation of the green attribute with respect to Y. The
format is S8.7.

Triangle ARY Delta Register (TdAdY_dRdY) (MMB548)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RED Y DELTA
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ALPHA Y DELTA
Bits 15-0 RED Y DELTA
Value = Delta value for the accumulation of the red attribute with respect to Y. The
format is S8.7.
Bits 31-16 ALPHA Y DELTA
Value = Delta value for the accumulation of the alpha attribute with respect to Y. The
format is S8.7.
Triangle GB Start Register (TGS_BS) (MMB54C)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 BLUE START
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 GREEN START
Bits 15-0 BLUE START
Value = Starting value for the accumulation of the blue attribute. The format is S8.7,
where S must be 0.
Bits 31-16 GREEN START
Value = Starting value for the accumulation of the green attribute. The format is S8.7,
where S must be 0.

Triangle AR Start Register (TAS_RS) (MMB550)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 RED START
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 ALPHA START
Bits 15-0 RED START
Value = Starting value for the accumulation of the red attribute. The format is S8.7,
where S must be 0.
Bits 31-16 ALPHA START
Value = Starting value for the accumulation of the alpha attribute. The format is S8.7,
where S must be 0.
Triangle ZX Delta Register (TdZdX) (MMB554)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ZX DELTA LOW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ZX DELTA HIGH
Bits 31-0 ZX DELTA
Value = Delta value for the accumulation of the Z attribute with respect to X. The for-
mat is S16.15.

Triangle ZY Delta Register (TdZdY) (MMB558)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ZY DELTA LOW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ZY DELTA HIGH
Bits 31-0 ZY DELTA
Value = Delta value for the accumulation of the Z attribute with respect to Y. The for-
mat is S16.15.
Triangle Z Start Register (TZS) (MMB55C)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z START LOW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 Z START HIGH
Bits 31-0 Z START
Value = Starting value for the accumulation of the Z attribute. The format is S16.15,
where S must be 0.
The Z attribute is used in conjunction with z-buffering.

Triangle XY12 Delta Register (TdXdY12) (MMB560)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XY12 DELTA LOW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
XY12 DELTA HIGH
Bits 31-0 XY12 DELTA
Value = Delta value for the accumulation of the X attribute with respect to Y along the
12 side. The format is S11.20.
See 3D Programming in Section 15 for an explanation of this field.
Triangle X12 End Register (TXEND12) (MMB564)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
X12 END LOW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 X12 END HIGH
Bits 31-0 X12 END
Value = X coordinate for the last pixel drawn for side 12. The format is S11.20, where
S must be 0.


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XY01 DELTA LOW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
XY01 DELTA HIGH
Triangle X01 End Register (TXEND01) (MMB56C)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
X01 END LOW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 X01 END HIGH
Bits 31-0 X01 END
Value = X coordinate for the last pixel drawn for side 01. The format is S11.20, where
S must be 0.


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XY02 DELTA LOW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
XY02 DELTA HIGH
Triangle X Start Register (TXS) (MMB574)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
X START LOW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 X START HIGH
Bits 31-0 X START
Value = Starting value for the accumulation of the X attribute. The format is S11.20,
where S must be 0.

Triangle Y Start Register (TYS) (MMB578)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R R R R R Y START
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Bits 10-0 Y START
Value = Starting value for the accumulation of the Y attribute.
Triangle Y Count Register (TY01_Y12) (MMB57C)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R R R R R SCAN LINE COUNT 12
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
L/R R R R R SCAN LINE COUNT 01
Bits 10-0 SCAN LINE COUNT 12
Value = The number of scan lines required to render the 12 side of the triangle.
See 3D Programming in Section 15 for a graphic description of this field. Either this
field or the SCAN LINE COUNT 01 field below must be non-zero for the S3d Engine to
draw a triangle.
Bits 15-11 Reserved
Bits 26-16 SCAN LINE COUNT 01
Value = The number of scan lines required to render the 01 side of the triangle.
See 3D Programming in Section 15 for a graphic description of this field. Either this
field or the SCAN LINE COUNT 12 field above must be non-zero for the S3d Engine to
draw a triangle.
Bits 30-27 Reserved

Bit 31 L/R - Left/Right Drawing Direction

0 = Render the triangle from right to left
1 = Render the triangle from left to right
The triangle must always be rendered in the direction starting with the triangle side
with the largest Y component. See 3D Programming in Section 15 for a graphic de-
scription.

Section 20: Streams Processor Register Descriptions
This section describes the Streams Processor registers.
STREAMS PROCESSOR REGISTER DESCRIPTIONS 20-1

Primary Stream Control (MM8180)
Read/Write Address: 8180H

Power-on Default: 00000000H
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R PSHFC R PSIDF R R R R R R R R
Bits 23-0 Reserved
Bits 26-24 PSIDF - Primary Stream Input Data Format

000 = RGB-8 (CLUT)
001 = Reserved
010 = Reserved
011 = KRGB-16 (1.5.5.5)
100 = Reserved
101 = RGB-16 (5.6.5)
110 = RGB-24 (8.8.8)
111 = XRGB-32 (X.8.8.8)
Bit 27 Reserved
Bits 30-28 PSFC - Primary Stream Horizontal Filter Characteristics

000 = Primary stream
001 = Primary stream for 2X horizontal stretch (replication)
010 = Primary stream 2X horizontal stretch (interpolation)
Other values reserved
Bit 31 Reserved
20-2 STREAMS PROCESSOR REGISTER DESCRIPTIONS

Color/Chroma Key Control (MM8184)
Read/Write Adds: 8184H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
G/U/Cb KEY (LOW) B/V/Cr KEY (LOW)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R R R KC R RGB CC R/Y KEY (LOW)
Bits 7-0 B/V/Cr key value (lower bound for chroma)
Bits 15-8 G/U/Cb key value (lower bound for chroma)
Bits 23-16 R/Y key value (lower bound for chroma)
Bits 26-24 RGB CC - RGB Color Comparison Precision

000 = Compare bit 7 of RGB (compare red bit 7’s, green bit 7’s and blue bit 7’s)
001 = Compare bits 7-6 of RGB
Bit 27 Reserved
Bit 28 KC - Key Control

0 = Extract key data from input stream key bit (if present). (KRGB-16, 1.5.5.5 only)
If the K bit is 0, the pixel from the other stream is used (transparent). If the K bit is
1, the key bit streams pixel is used (opaque)
1 = Enable color or chroma keying for all modes other than KRGB-16
Bits 31-29 Reserved

Secondary Stream Control (MM8190)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R R R R DDA HORIZONTAL ACCUMULATOR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R SFC R SDIF R R R R R R R R
Bits 11-0 DDA Horizontal Accumulator Initial Value
Value = 2 (W0-1) - (W1-1), where W0 is the line width in pixels before scaling and W1
is the line width in pixels after scaling. This is a signed value.
When this field is programmed, the value does not take effect until the next VSYNC.
Bits 23-12 Reserved
Bits 26-24 SDIF - Secondary Stream Input Data Format

000 = Reserved
001 = YCbCr-16 (4.2.2), 16 to 240 input range
010 = YUV-16 (4.2.2), -128 to 127 input range
011 = KRGB-16 (1.5.5.5)
100 = YUV (2.1.1)
101 = RGB-16 (5.6.5)
110 = RGB-24 (8.8.8)
111 = XRGB-32 (X.8.8.8)
Bit 27 Reserved
Bits 30-28 SFC - Secondary Stream Horizontal Filter Characteristics

000 = Secondary stream
001 = Secondary stream, fixed weighted 0-2-4-2-0 (for up to 2X stretch)
010 = Secondary stream, interpolated (for 2X to 4X stretch)
011 = Secondary stream, fixed weighted 1-2-2-2-1 (for 4X or greater stretch)
Other values reserved
Any valid setting can be used for any degree of stretch. The parenthetical comments
are recommendations which may not be optimal for all cases.
Bit 31 Reserved

Chroma Key Upper Bound (MM8194)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
U/Cb KEY (UPPER) V/Cr KEY (UPPER)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R R R R R R R R Y KEY (UPPER)
Bits 7-0 V/Cr key value (upper bound)
Bits 15-8 U/Cb key value (upper bound)
Bits 23-16 Y key value (upper bound)
Bits 31-24 Reserved
Secondary Stream Stretch/Filter Constants (MM8198)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R R R R R K2 HORIZONTAL SCALE FACTOR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R R R R R K1 HORIZONTAL SCALE FACTOR
Bits 10-0 K1 Horizontal Scale Factor
Value = W0-1, where W0 is the width in pixels of the initial output window (before
scaling)
Bits 15-11 Reserved
Bits 26-16 K2 Horizontal Scale Factor
Value = W0-W1, where W0 is the initial (unscaled) window width in pixels and W1 is
the final output window width in pixels. This is a signed value and will always be
negative.
Bits 31-27 Reserved

Blend Control (MM81A0)
Read/Write Address: 81A0H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R R R KP R R R R R KS R R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R R R R R COMP MODE R R R R R R R R
Bits 1-0 Reserved
Bits 4-2 Ks
Value = secondary stream blend coefficient
Bits 9-5 Reserved
Bits 12-10 Kp
Value = primary stream blend coefficient
Bits 23-13 Reserved
Bits 26-24 Compose Mode

000 = Secondary stream opaque overlay on primary stream
001 = Primary stream opaque overlay on secondary stream
010 = Dissolve, [Pp x Kp + Ps x (8 - Kp)]/8, ignore Ks
011 = Fade, [Pp x Kp + Ps x Ks]/8, where Kp + Ks must be ≤ 8
100 = Reserved
101 = Color key on primary stream (secondary stream overlay on primary stream)
110 = Color or chroma key on secondary stream (primary stream overlay on
secondary stream)
111 = Reserved
Bits 31-27 Reserved

Primary Stream Frame Buffer Address 0 (MM81C0)

Power-on Default: Undefined
If a primary stream is enabled, this register specifies the starting address in the frame buffer.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIMARY BUFFER ADDRESS 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R R R R R R R R R R PRIMARY BUFFER ADDRESS 0
Bits 21-0 Value = Primary stream frame buffer starting address 0
This value must be quadword aligned.
Bits 31-22 Reserved
Primary Stream Frame Buffer Address 1 (MM81C4)

If the primary stream is double buffered, this register specifies the starting address in the frame buffer
for the second buffer.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIMARY BUFFER ADDRESS 1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R R R R R R R R R R PRIMARY BUFFER ADDRESS 1
Bits 21-0 Value = Primary stream frame buffer starting address 1
Bits 31-22 Reserved

Primary Stream Stride (MM81C8)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R R R R PRIMARY STREAM STRIDE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Bits 11-0 Primary stream stride
Value = byte offset of vertically adjacent pixels in the primary stream buffer(s)
If double buffering is used, the stride must be the same for both buffers.
Bits 31-12 Reserved
Double Buffer/LPB Support (MM81CC)
Read/Write Address: 81CCH

Power-on Default: xxxxxx00H
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R R R R R R R R R LST LSL LIS R SBS PBS
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Bit 0 PBS - Primary Stream Buffer Select

0 = Primary frame buffer starting address 0 (MM81C0_21-0) used for the primary
stream
1 = Primary frame buffer starting address 1 (MM81C4_21-0) used for the primary
stream

Bits 2-1 SBS - Secondary Stream Buffer Select

secondary stream
secondary stream
secondary stream and LPB frame buffer starting address 0 (MMFF0C_21-0) used
for the LPB input stream OR secondary frame buffer starting address 1
(MM81D4_21-0) used for the secondary stream and LPB frame buffer starting
address 1 (MMFF10_21-0) used for the LPB input stream. Which alternative
applies is determined by LPB starting address register selected by bit 4 of this
register
secondary stream and LPB frame buffer starting address 1 (MMFF10_21-0) used
for the LPB input stream OR secondary frame buffer starting address 1
(MM81D4_21-0) used for the secondary stream and LPB frame buffer starting
address 0 (MMFF0C_21-0) used for the LPB input stream. Which alternative
applies is determined by the LPB starting address register selected by bit 4 of this
register
Bit 3 Reserved
Bit 4 LIS - LPB Input Buffer Select

0 = LPB frame buffer starting address 0 (MMFF0C_21-0) used for the LPB input
1 = LPB frame buffer starting address 1 (MMFF10_21-0) used for the LPB input
This bit selects the starting address for writing LPB data into the frame buffer. When
the value programmed to this bit takes effect is determined by the setting of bit 5 of
this register. This bit can be toggled at the completion of writing all the data for a
frame to the frame buffer via bit 6 of this register
Bit 5 LSL - LPB Input Buffer Select Loading

0 = The value programmed into bit 4 of this register takes effect immediately
1 = The value programmed into bit 4 of this register takes effect at the next end of
frame (completion of writing all the data for a frame into the frame buffer)
Bit 6 LST - LPB Input Buffer Select Toggle

0 = End of frame (completion of writing all the data for a frame into the frame buffer)
has no effect on the setting of bit 4 of this register
Bits 31-7 Reserved

Secondary Stream Frame Buffer Address 0 (MM81D0)
Read/Write Address: 81D0H

If a secondary stream is enabled, this register specifies the starting address in the frame buffer
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SECONDARY BUFFER ADDRESS 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R R R R R R R R R R SECONDARY BUFFER ADDRESS 0
Bits 21-0 Value = Secondary stream frame buffer starting address 0
Bits 31-22 Reserved
Secondary Stream Frame Buffer Address 1 (MM81D4)

If the secondary stream is double buffered, this register specifies the starting address in the frame
buffer for the second buffer.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SECONDARY BUFFER ADDRESS 1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R R R R R R R R R R SECONDARY BUFFER ADDRESS 1
Bits 21-0 Value = Secondary stream frame buffer starting address 1
Bits 31-22 Reserved

Secondary Stream Stride (MM81D8)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R R R R SECONDARY STREAM STRIDE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Bits 11-0 Secondary stream stride
Value = byte offset of vertically adjacent pixels in the secondary stream buffer(s)
If double buffering is used, the stride must be the same for both buffers.
Bits 31-12 Reserved
Opaque Overlay Control (MM81DC)
Read/Write Address: 81DCH

Power-on Default: Undefined except bits 31-30 are 00b.
When an opaque overlay mode is being used (bits 26-24 of MM81A0 = 000b or 001b), the fields in this
register can be programmed to eliminate the fetching of the pixels for the rectangular area under the
top (opaque) window. This reduces the memory bandwidth requirements. The bottom window should
be full-screen when this feature is enabled. None of the fields in this register have an effect unless bit
31 is set to 1. Note that only horizontal coordinates must be specified. The vertical coordinates are
handled automatically by the hardware.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R R R PIXEL STOP FETCH R R R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OOC TSS R PIXEL RESUME FETCH R R R
Bits 2-0 Reserved
Bits 12-3 Pixel Stop Fetch
Value = [Offset in quadwords from the background starting pixel horizontal position
to the first pixel of the line not to be fetched from memory (hidden background)] + 1
quadword
If the primary stream is the background, MM81F0_26-16 define the starting position
for each line in the background window (X0) and MM81F8_26-16 define the first pixel
position for each line in the top window (X1). The latter is the first background pixel
that does not need to be fetched. The value programmed in this field is then [(X1 -

X0) x bytes per pixel/8] +1. If the result is a fraction, it is rounded up the next highest
integer. This gives the required quadword offset (O) for this field. This value is also
used in the calculation for the field value of bits 28-19 of this register.
If the secondary stream is the background, the value is [(X0 - X1) x bytes per pixel/8]
+ 1.
Bits 18-13 Reserved
Bits 28-19 Pixel Resume Fetch
Value = {Offset in quadwords from the background starting pixel horizontal position
to the line position of the resumption of pixel fetching from memory (i.e., visible back-
ground)} - 1 quadword
The value is determined by adding the Pixel Stop Fetch field value (O) above (bits 12-
3) to the width in quadwords of the top window (W). The width of the top window in
pixels (P) is found in MM81F4_26-16 if the primary stream is on top and in
MM81FC_26-16 if the secondary stream is on top. W in quadwords = P x bytes per
pixel/8. If this is a fraction, the result is truncated to the next lowest integer. The value
in this field is then [W + O] - 1.
Bit 29 Reserved
Bit 30 TSS - Top Stream Select

0 = Secondary stream on top
1 = Primary stream on top
Bit 31 OOC - Opaque Overlay Control Enable

0 = Opaque overlay control disabled
1 = Opaque overlay control enabled
K1 Vertical Scale Factor (MM81E0)
Read/Write Address: 81E0H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R R R R R K1 VERTICAL SCALE FACTOR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Bits 10-0 K1 Vertical Scale Factor
Value = [height (in lines) of the initial output window (before scaling)] - 1
Bits 31-11 Reserved

K2 Vertical Scale Factor (MM81E4)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R R R R R K2 VERTICAL SCALE FACTOR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Bits 10-0 K2 Vertical Scale Factor
Value = [height (in lines) of the initial output window (before scaling)] - [height (in
lines) of the final output window (after scaling)]
Bits 31-11 Reserved
DDA Vertical Accumulator Initial Value (MM81E8)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R R R R DDA VERTICAL ACCUMULATOR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Bits 11-0 DDA Vertical Accumulator Initial Value
Value = 2’s complement of [height (in lines) of the output window after scaling] - 1
Bits 31-12 Reserved

Streams FIFO Control (MM81EC)
Read/Write Address: 81ECH

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R R R R R R R R R R PDD MAR TSM EWS R R
Bits 17-0 Reserved
Bit 18 EWS - EDO Memory Wait State Control (LPB Memory Cycles Only)
0 = Standard 2-cycle memory operation
1 = 1-cycle EDO memory operation (requires EDO memory capable of this)
This bit must be set to correspond to the memory type used when enabling LPB op-
eration.
Bit 19 TSM - Tri-state Memory Data Lines

0 = Tri-state PD[63:16] during ROM cycles
1 = Do not tri-state PD[63:16] during ROM cycles
PD[15:0] are driven with the ROM address. This bit should normally be left at its de-
fault value of 0.
Bit 20 MAR - Memory Arbitration

0 = Arbitrate for the memory bus when ROM cycle initiated
1 = ROM cycle immediately uses memory bus
This bit should normally be left at its default value of 0.
Bit 21 PDD - PD Output Delay

0 = Delay output of PD[63:0] for 0.5 MCLKs
1 = No delay of PD[63:0] output
This bit should normally be left at its default value of 0.
Bits 31-22 Reserved

Primary Stream Window Start Coordinates (MM81F0)
Read/Write Address: 81F0H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R R R R R PRIMARY STREAM Y-START
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R R R R R PRIMARY STREAM X-START
Bits 10-0 Primary Stream Y-Start
Value = Screen line number +1 of the first line of the primary stream window
Bits 15-11 Reserved
Bits 26-16 Primary Stream X-Start
Value = Screen pixel number +1 of the first pixel of the primary stream window
Bits 31-27 Reserved
Primary Stream Window Size (MM81F4)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R R R R R PRIMARY STREAM HEIGHT
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R R R R R PRIMARY STREAM WIDTH
Bits 10-0 Primary Stream Height
Value = Number of lines displayed in the primary stream window
Bits 15-11 Reserved
Bits 26-16 Primary Stream Width
Value = Number of pixels -1 displayed in each line in the primary stream window
Bits 31-27 Reserved

Secondary Stream Window Start Coordinates (MM81F8)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R R R R R SECONDARY STREAM Y-START
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R R R R R SECONDARY STREAM X-START
Bits 10-0 Secondary Stream Y-Start
Value = Screen line number +1 of the first line of the secondary stream window
Bits 15-11 Reserved
Bits 26-16 Secondary Stream X-Start
Value = Screen pixel number +1 of the first pixel of the secondary stream window
Bits 31-27 Reserved
Secondary Stream Window Size (MM81FC)
Read/Write Address: 81FCH

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R R R R R SECONDARY STREAM HEIGHT
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R R R R R SECONDARY STREAM WIDTH
Bits 10-0 Secondary Stream Height
Value = Number of lines displayed in the secondary stream window
Bits 15-11 Reserved
Bits 26-16 Secondary Stream Width
Value = Number of pixels -1 displayed in each line in the primary stream window
Bits 31-27 Reserved

Section 21: Memory Port Controller

Register Descriptions
This section describes the Memory Port Controller (MPC) Registers for ViRGE. These registers are used
to adjust memory control signals and control the video data FIFOs.
MEMORY PORT CONTROLLER REGISTER DESCRIPTIONS 21-1

FIFO Control (MM8200)
Read/Write Offset: 8200H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PS THRESHOLD R SS THRESHOLD R P/S BOUNDARY
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R R R R R R R R R R R R R R R
Bits 4-0 P/S BOUNDARY - Primary/Secondary Stream FIFO Boundary

00000 = Primary Stream = 24 slots; Secondary stream = 0 slots
All other values are reserved and must not be programmed. Each slot holds 1 quad-
word.
Bit 5 Reserved
Bits 10-6 SS THRESHOLD - Secondary Stream Threshold
Value = Number of secondary stream FIFO slots
When the secondary stream FIFO empties down to this value, an internal signal is
generated requesting refilling of the secondary stream FIFO. This value must be ≤ the
secondary stream FIFO size specified in bits 4-0 of this register.
Bit 11 Reserved
Bits 16-12 PS THRESHOLD - Primary Stream Threshold
Value = Number of primary stream FIFO slots
When the primary stream FIFO empties down to this value, an internal signal is gener-
ated requesting refilling of the primary stream FIFO. This value must be ≤ the primary
stream FIFO size specified in bits 4-0 of this register.
Bits 31-17 Reserved
21-2 MEMORY PORT CONTROLLER REGISTER DESCRIPTIONS

MIU Control Register (MM8204)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R R R R R DRR LPR WED COA R R R WT RL RP RI
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Bit 0 RI - RAS Inactive

0 = RAS stays low until the start of the next cycle
1 = RAS goes high at the end of the cycle
Bit 1 RP - RAS Pre-charge Control

0 = RAS pre-charge specified by CR68_3 (2.5 or 3.5 MCLKs)
1 = RAS pre-charge = 1.5 MCLKs
Bit 2 RL - RAS Low

0 = RAS low specified by CR68_2 (3.5 or 4.5 MCLKs)
1 = RAS low = 2.5 MCLKs
Bits 6-3 Reserved
Bit 7 COA - CAS/OE Adjust

0 = CAS/OE active trailing edge delay specified by CR68_1-0
1 = CAS/OE active pulse delay specified by CR68_1-0
Bit 8 WED - WE Delay

1 = WE active pulse delay specified by CR6F_4-3
0 = WE active trailing edge delay specified by CR6F_4-3
Bit 9 LPR - Low Priority Request Control

0 = A low priority primary or secondary stream memory request is service when an
S3d Engine request goes inactive
1 = A low priority primary or secondary stream memory request is serviced only after
an S3d Engine request has been inactive for more than 3 MCLKs.
Bit 10 DRR - Delay RAS Rising Edge

0 = No delay of RAS rising edge
1 = Delay RAS rising edge by 1/2 MCLK
Bits 31-11 Reserved

Streams Timeout Register (MM8208)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PS TIMEOUT SS TIMEOUT
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R R R R R R R R R R R R R R R PST
Bits 7-0 SS TIMEOUT - Secondary Stream Timeout
Value = number of MCLKs that the secondary stream is given read access to video
memory before its grant is withdrawn
Bits 15-8 PS TIMEOUT - Primary Stream Timeout
Value = number of MCLKs that the primary stream is given read access to video mem-
ory before its grant is withdrawn
Bit 16 PST - Primary/Secondary Tiebreaker

0 = Primary wins in case of a tie
1 = Secondary wins in case of a tie
This bit is effective when the primary and secondary streams have simultaneous re-
quests for video memory access pending.
Bits 31-17 Reserved

Miscellaneous Timeout Register (MM820C)
Read/Write Offset: 820CH

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
S3D ENGINE TIMEOUT CPU TIMEOUT
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXT TIMEOUT LPB TIMEOUT
Bits 7-0 CPU TIMEOUT
Value = number of MCLKs that the CPU is given access to video memory before its
grant is withdrawn
Bits 15-8 S3D ENGINE TIMEOUT
Value = number of MCLKs that the S3D Engine is given access to video memory be-
fore its grant is withdrawn
Bits 23-16 LPB TIMEOUT
Value = number of MCLKs that the LPB is given write access to video memory before
its grant is withdrawn
Bits 31-24 EXT TIMEOUT
Value = number of MCLKs that another memory master is given access to video mem-
ory before its grant is withdrawn

DMA Read Base Address Register (MM8220)

This register is used when the CPU is doing DMA transfers from video memory as specified by clear-
ing bit 1 of MM8580 to 0 (read) and setting bit 0 of MM8588 to 1 (video DMA enable).
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMA READ BASE ADDRESS 0 0 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R R R R R R R R R DMA READ BASE ADDRESS
Bits 22-3 DMA READ BASE ADDRESS
Value = Starting address in video memory for data to be DMAed to system memory
(quadword aligned)
Bits 31-23 Reserved
DMA Read Stride/Width Register (MM8224)

This register is used when the CPU is doing DMA transfers from video memory as specified by clear-
ing bit 1 of MM8580 to 0 (read) and setting bit 0 of MM8480 to 1 (video DMA enable).
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R R R R DMA READ STRIDE 0 ATC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R R R R DMA READ WIDTH 0 0 0
Bits 1-0 ATC - Address Tiling Control

00 = CPU address lines 14-8 are sequential (linear addressing)
01 = CPU address lines 14-8 are rearranged to 14, 9, 8, 13, 12, 11, 10
10 = CPU address lines 14-8 are rearranged to 10, 9, 8, 14, 13, 12, 11
11 = CPU address lines 14-8 are sequential (linear addressing)
The rearranged settings provide a narrower and deeper memory page size to mini-
mize page breaks when drawing is limited to a small area of the screen. The 10 set-
ting provides the narrowest page size.
Bit 2 Reserved = 0

Bits 11-3 DMA READ STRIDE
Value = Number of quadwords to add to the address at the end of a line to generate
the address for the next line to be transferred
A DMA transfer from video memory to system memory starts at the address speci-
fied in MM8220_22_3 and proceeds for the number of quadwords defined by the
value in bits 27-19 of this register. The stride value is then added to end of line ad-
dress to get the address for the start of the next line to be transferred.
Bits 15-12 Reserved
Bits 27-19 DMA READ WIDTH
Value = [Number of quadwords per line to transfer to system memory] - 1
Bits 31-28 Reserved

Section 22: Miscellaneous Register Descriptions
Subsystem Status Register (MM8504)
Read Only Offset: 8504H

This read-only register provides information on interrupt status, monitor I.D. and the number of bits
per pixel. See the Subsystem Control (MM8504, Write Only) register for details on enabling and clearing
interrupts.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
S3d LPB 3DF CD HD FIFO FIFO 3D VSY
R R ENG S3d FIFO SLOTS FREE INT FIFO DON DON EMP OVF DON INT
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Bit 0 VSY INT - Vertical Sync Interrupt Status

0 = No interrupt
1 = Interrupt generated
Bit 1 3D DON - S3d Engine Done Interrupt Status

0 = No interrupt
Bit 2 FIFO OVF - Command FIFO Overflow Interrupt Status

0 = No interrupt
Bit 3 FIFO EMP - Command FIFO Empty Interrupt Status

0 = No interrupt
MISCELLANEOUS REGISTER DESCRIPTIONS 22-1

Bit 4 HD DON - Host DMA Done Interrupt Status

0 = No interrupt
Bit 5 CD DON - Command DMA Done Interrupt Status

0 = No interrupt
Bit 6 3DF FIF - S3d FIFO Empty Status

0 = No interrupt
Bit 7 LPB INT - LPB Interrupt Status

0 = No interrupt
Bits 12-8 S3d FIFO SLOTS FREE

00000 = 0 slots free
.
.
.
10000 = 16 slots free (S3d Engine FIFO is 16 slots deep)
Bit 13 S3d ENG - S3d Engine Status

0 = S3d Engine busy
1 = S3d Engine idle
Subsystem Control Register (MM8504)
Write Only Offset: 8504H

This register allows each of several interrupt sources to be enabled or disabled. Interrupt status (Subsystem
Status (MM8504, Read Only) can be cleared. This register also controls the software reset of the graphics
engine.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
S3d RST 3DF CDD FIFO ENB 3DD VSY HDD 3DF CDD HDD FIFO FIFO 3DD VSY
1 0 ENB ENB EMP OVF ENB ENB ENB CLR CLR CLR CLE CLO CLR CLR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Bit 0 VSY CLR - Clear Vertical Sync Interrupt Status

0 = No change
1 = Clear
22-2 MISCELLANEOUS REGISTER DESCRIPTIONS

Bit 1 3DD CLR - Clear S3d Engine Done Interrupt Status

0 = No change
1 = Clear
Bit 2 FIFO CLO - Clear Command FIFO Overflow Interrupt Status

0 = No change
1 = Clear
Bit 3 FIFO CLE - Clear Command FIFO Empty Interrupt Status

0 = No change
1 = Clear
Bit 4 HDD CLR - Clear Host DMA Done Interrupt Status

0 = No change
1 = Clear
Bit 5 CDD CLR - Clear Command DMA Done Interrupt Status

0 = No change
1 = Clear
Bit 6 3DF CLR - Clear S3d FIFO Empty Interrupt Status

0 = No change
1 = Clear
Bit 7 HDD ENB - Host DMA Done Interrupt Enable

0 = Disable
1 = Enable interrupt when a host DMA transfer is complete and CR32_4 = 1
Bit 8 VSY ENB - Vertical Sync Interrupt Enable

0 = Disable
1 = Enable interrupt when VSYNC goes active and CR32_4 = 1
Bit 9 3DD ENB- S3d Engine Done Interrupt Enable

0 = Disable
1 = Enable interrupt when the S3d Engine completes its current task and becomes
idle and CR32_4 = 1
Bit 10 FIFO ENB OVF - Command FIFO Overflow Interrupt Enable

0 = Disable
1 = Enable interrupt when the command FIFO overflows and CR32_4 = 1
Bit 11 FIFO ENB EMP - Command FIFO Empty Interrupt Enable

0 = Disable
1 = Enable interrupt when the command FIFO becomes empty and CR32_4 = 1
Bit 12 CDD ENB - Command DMA Done Interrupt Enable

0 = Disable
1 = Enable interrupt when a command DMA transfer is complete and CR32_4 = 1
Bit 13 3DF ENB - S3d FIFO Empty Interrupt Enable

0 = Disable
1 = Enable interrupt when the S3d FIFO becomes empty and CR32_4 = 1

Bits 15–14 S3d RST - S3d Engine Software Reset

00 = No change
01 = S3d Engine enabled
10 = Reset
11 = Reserved
Setting CR66_1 to 1 is equivalent to setting these bits to 10b.
Bits 31-16 Reserved
Advanced Function Control Register (MM850C)
See Bit Descriptions Offset: 850CH

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LA RST ENB
R R R R R R CMD FIFO STATUS R ENB R R DM EHFC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Bit 0 ENB EHFC - Enable Enhanced Functions (Read/Write)

0 = Enable VGA and VESA planar (4 bits/pixel) modes
1 = Enable all other modes (Enhanced and VESA non-planar)
This bit is ORed with bit 0 of CR66 and is equivalent to it.
Bit 1 RST DM - Reset Read DMA (Read/Write)

0 = No effect
1 = Reset read DMA pointers
This bit should be toggled (program a 1 and then a 0) by software immediately after
the completion of each read DMA operation.
Bits 3-2 Reserved
Bit 4 LA ENB- Linear Addressing Enable (Read/Write)

0 = Disable linear addressing
1 = Enable linear addressing
This bit is ORed with bit 4 of CR58 and is equivalent to it.
Bit 5 Reserved
22-4 MISCELLANEOUS REGISTER DESCRIPTIONS

Bits 9-6 COMMAND FIFO STATUS (Read Only)

0000 = 0 slot free
0001 = 1 slot free
0010 = 2 slots free
0011 = 3 slots free
0100 = 4 slots free
0101 = 5 slots free
0110 = 6 slots free
0111 = 7 slots free
1000 = 8 slots free

Section 23: DMA Register Descriptions
This section describes the Direct Memory Access (DMA) registers for ViRGE. These registers are used
to control the two DMA channels when ViRGE operates as a PCI bus master. The video/graphics data
transfer channel handles:
• Compressed video data transfers from system memory to an MPEG-1 decoder via the LPB
• Decompressed video data (software MPEG) transfers to the frame buffer via the LPB
• Frame buffer data transfers to system memory
For the latter case, the video memory read data location and structure are specified in MM8220 and
MM8224. These are described in the Memory Port Controller section.
The command data channel handles transfers of command and drawing parameter data from system
memory to the S3D Engine.
These two channels can operate independently.
DMA REGISTER DESCRIPTIONS 23-1

23.1 VIDEO/GRAPHICS DATA TRANSFER CHANNEL
Video DMA Starting System Memory Address Register (MM8580)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STARTING MEMORY ADDRESS R/W R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STARTING MEMORY ADDRESS
Bit 0 Reserved
Bit 1 R/W - Video/Graphics DMA Read/Write

0 = Video DMA write (system memory to the LPB output FIFO)
1 = Video DMA read (video memory to system memory)
Data written to the LPB output FIFO can be directed to an MPEG decoder (com-
pressed data) or to video memory with optional decimation.
Bits 31-2 STARTING MEMORY ADDRESS
Value = Starting memory address when performing a DMA transfer from video mem-
ory to system memory or from system memory to the LPB output FIFO
23-2 DMA REGISTER DESCRIPTIONS

Video DMA Transfer Length Register (MM8584)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMA TRANSFER LENGTH R R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R R R R R R R R DMA TRANSFER LENGTH
Bits 1-0 Reserved
Bits 23-2 DMA TRANSFER LENGTH
Value = (Number of double words to transfer) - 1.
Bits 31-24 Reserved
Video DMA Transfer Enable Register (MM8588)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R R R R R R R R R R R R R R R VDE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Bit 0 VDE - Video/Graphics DMA Enable

0 = Disable video/graphics DMA
1 = Enable video graphics DMA
This bit is reset to 0 by the DMA controller at the completion of a video/graphics DMA
transfer.
Bits 31-1 Reserved

23.2 COMMAND TRANSFER CHANNEL
Command DMA Base Address Register (MM8590)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BASE ADDRESS R R R R R R R R R R BS R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BASE ADDRESS
Bit 0 Reserved
Bit 1 BS - Command DMA Buffer Size

0 = 4 KByte buffer size
1 = 64 KByte buffer size
Bits 11-2 Reserved
Bits 31-12 BASE ADDRESS
Value = Command DMA buffer base address
Bits 15-12 must be 000b for a 64K buffer size (64K aligned).

Command DMA Write Pointer Register (MM8594)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRITE POINTER R R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R R R R R R R R R R R R R R R WPU
Bits 1-0 Reserved
Bits 15-2 WRITE POINTER
Value = next doubleword address after the last doubleword written to the system
memory buffer
Bit 16 WPU - Write Pointer Updated
Software must set this bit to 1 each time it updates the write pointer.
Bits 31-17 Reserved
Command DMA Read Pointer Register (MM8598)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
READ POINTER R R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Bits 1-0 Reserved
Bits 15-2 READ POINTER
Value = Address of next doubleword in system memory to be read by the DMA
4K buffer: address = base address 31-12 (concat) read pointer 11-2 (concat) 00
64K buffer: address = base address 31-16 (concat) read pointer 15-2 (concat) 00
After this pointer value is initialized, it is is updated automatically by ViRGE.
Bits 31-16 Reserved

Command DMA Enable Register (MM859C)
Read/Write Offset: 859CH

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R R R R R R R R R R R R R R R CDE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Bit 0 CDE - Command DMA Enable

0 = Command DMA Disabled
1 = Command DMA Enabled
Bits 31-1 Reserved


Register Descriptions
This section describes the Local Peripheral Bus (LPB) registers.
LOCAL PERIPHERAL BUS REGISTER DESCRIPTIONS 24-1

LPB Mode Register (MMFF00)
Read/Write Address: FF00H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R R LBA CHS CVS LHS LVS R R CBS SF LR LPB MODE LE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CFL R R R R ILC SNO CS R VFT R R R MBS
Bit 0 LE - LPB Enable

0 = LPB Disabled
1 = LPB Enabled
Once enabled, the LPB is reset either by a system reset or via bit 4 of this register.
Bits 3-1 LPB MODE

000 = Scenic/MX2 Mode. Pins 203 and 204 act as VREQ/VRDY and CREQ/CRDY
respectively.
001 = Video 16 Mode (PCI only). Pins 203 and 204 act as HS and VS respectively and
pins 201-199, 189-185 act as LD[15:8]. ViRGE expects 16-bit Philips digitizer
input.
010 = Video 8 In Mode. Pins 203 and 204 to act as HS and VS respectively and the
ViRGE expects video data in 8-bit units (LD[7:0]).
100 = Pass-through Mode. 32-bit data from the output FIFO is passed directly to the
decimation input to the video FIFO. This allows decimation of CPU-provided
data.
Bit 4 LR- LPB Reset

0 = No effect
1 = Reset LPB
This bit should be set and then reset before switching between LPB modes.
Bit 5 SF - Skip Frames

0 = Write all received frames to memory
1 = Write every other received frame to memory (1, 3, etc.)
24-2 LOCAL PERIPHERAL BUS REGISTER DESCRIPTIONS

Bit 6 CBS - Color Byte Swap

0 = Incoming video is in U01, Y0, V01, Y1 format, byte swapping enabled
1 = Incoming video is in Y0, U01, Y1, V01 format (e.g., SAA7110), no byte swapping
Bits 8-7 Reserved
Bit 9 LVS - LPB Vertical Sync Input Polarity

0 = LPB vertical sync input is active low
1 = LPB vertical sync input is active high
Bit 10 LHS - LPB Horizontal Sync Input Polarity

0 = LPB horizontal sync input is active low
1 = LPB horizontal sync input is active high
Bit 11 CVS - CPU VSYNC (Write Only)
Writing a 1 to this bit causes ViRGE to do whatever functions it is programmed to do

upon receipt of a VSYNC. For example, values programmed in certain registers only
take effect at the next VSYNC.
Bit 12 CHS - CPU HSYNC (Write Only)
Writing a 1 to this bit causes ViRGE to do whatever functions it is programmed to do

upon receipt of an HSYNC.
Bit 13 LBA - Load Base Address (Write Only)
Writing a 1 to this bit immediately loads the base address currently being pointed to.
Bits 15-14 Reserved
Bits 17-16 MBS - Maximum LPB to Scenic/MX2 Compressed Data Burst Size (Scenic/MX2 mode
only)
00 = Burst 1 32-bit word
01 = Burst 2 32-bit words
10 = Burst 3 32-bit words
11 = Burst all 32-bit words (until empty)
With a setting of 11b, software must ensure that no more than eight 32-bit words are
burst to the Scenic/MX2 in a single burst. For example, if the FIFO is full (8 entries),
no more entries should be written until the burst is complete.
Bits 20-18 Reserved
Bits 22-21 VFT - Video FIFO Threshold

00 = 1 FIFO slot
01 = 2 FIFO slots
10 = 4 FIFO slots
11 = 6 FIFO slots
When this many slots are filled in the video FIFO, a request is generated to the mem-
ory manager to begin emptying the FIFO. This is used to maximize the efficiency of
the memory interface.

Bit 23 Reserved
Bit 24 CS - LPB Clock Source

0 = LPB clock driven by SCLK (pin 194)
1 = LPB clock driven by LCLK (pin 148)
This bit allows for the LPB to be used in pass-through mode (MMFF00_3-1 = 100b)
when ViRGE is configured for compatible mode. The LPB is normally driven by LCLK,
but this is not available in compatible mode.
Bit 25 SNO - Sync Non-Overlap

0 = No effect
1 = Don’t add stride after first HSYNC
This bit must be set when the first HSYNC does not occur within the VSYNC active pe-
riod.
Bit 26 ILC - Invert LCLK

0 = Use LCLK as received
1 = Invert the LCLK input
Bit 24 of this register must be set to 1 for this bit to be effective.
Bits 31-27 Reserved

LPB FIFO Status Register (MMFF04)
Read Only Address: FF04H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R R OFAE OFE OFF R R R R R R R OFIFO STATUS
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VF1A VF1E VF1F R R R R R R VF0A VF0E VF0F R R R R
Bits 3-0 LPB Output FIFO Status

0000 = 0 FIFO slots free
0001 = 1 FIFO slot free
Each slot contains 4 bytes
Bits 10-4 Reserved
Bit 11 OFF - LPB Output FIFO Full

0 = Output FIFO not full
1 = Output FIFO full
Bit 12 OFE - LPB Output FIFO Empty

0 = Output FIFO not empty
1 = Output FIFO empty
Bit 13 OFAE - LPB Output FIFO Almost Empty

0 = Output FIFO has something other than 1 slot filled
1 = Output FIFO has one slot filled
Bits 19-14 Reserved
Bit 20 VF0F - LPB Video FIFO 0 Full

0 = Video FIFO 0 not full
1 = Video FIFO 0 full
Bit 21 VF0E - LPB Video FIFO 0 Empty

0 = Video FIFO 0 not empty
1 = Video FIFO 0 empty
Bit 22 VF0A - LPB Video FIFO 0 Almost Empty

0 = Video FIFO 0 has something other than 1 slot filled
1 = Video FIFO 0 has one slot filled

Bits 28-23 Reserved
Bit 29 VF1F - LPB Video FIFO 1 Full

0 = Video FIFO 1 not full
1 = Video FIFO 1 full
Bit 30 VF1E - LPB Video FIFO 1 Empty

0 = Video FIFO 1 not empty
1 = Video FIFO 1 empty
Bit 31 VF1A - LPB Video FIFO 1 Almost Empty

0 = Video FIFO 1 has something other than 1 slot filled
1 = Video FIFO 1 has one slot filled
LPB Interrupt Flags Register (MMFF08)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R R R R R R R R R R R R SPS EFI ELI FEI
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R R R R R R R SPW R R R R SPM EFM ELM FEM
Bit 0 FEI - LPB Output FIFO Empty Interrupt Status

0 = No interrupt
1 = LPB output FIFO empty
Writing a 1 to this bit clears the interrupt.
Bit 1 ELI - End of Line Interrupt Status

0 = No interrupt
1 = HSYNC input on pin 202
Bit 2 EFI - End of Frame Interrupt Status

0 = No interrupt
1 = VSYNC input on pin 203
Bit 3 SPS - Serial Port Start Detect Interrupt Status

0 - No interrupt
1 = Serial port start condition detected
A serial port start condition occurs when SPD (pin 206) is driven low by another de-
vice while SPCLK (pin 205) is not being driven low. Writing a 1 to this bit clears the in-
terrupt.

Bits 15-4 Reserved
Bit 16 FEM - LPB Output FIFO Empty Interrupt Enable Mask

0 = LPB output FIFO empty interrupt disabled
1 = LPB output FIFO empty interrupt enabled
Bit 17 ELM - End of Line Interrupt Enable Mask

0 = End of Line interrupt disabled
1 = End of Line interrupt enabled
Bit 18 EFM - End of Frame Interrupt Enable Mask

0 = End of frame interrupt disabled
1 = End of frame interrupt enabled
Bit 19 SPM - Serial Port Start Detect Interrupt Mask

0 = Serial port start detect interrupt disabled
1 = Serial port start detect interrupt enabled
Bits 23-20 Reserved
Bit 24 SPW - Serial Port Wait

0 = Release SPCLK (pin 205) to float high
1 = Drive SPCLK (pin 205) low upon receipt of a serial port start condition
Setting this bit to 1 enables serial port wait states until the Host is ready to process
the data.
Bit 31-25 Reserved

LPB Frame Buffer Address 0 Register (MMFF0C)
Read/Write Address: FF0CH

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LPB BUFFER ADDRESS 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R R R R R R R R R R LPB BUFFER ADDRESS 0
Bits 21-0 LPB Frame Buffer Address 0
Value = starting address 0 (offset in bytes from the start of the frame buffer) for writ-
ing LPB data to the frame buffer
This value will normally be the same as the secondary stream frame buffer address 0.
The value must start on an 8-byte boundary.
Bits 31-22 Reserved
LPB Frame Buffer Address 1 Register (MMFF10)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LPB BUFFER ADDRESS 1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R R R R R R R R R R LPB BUFFER ADDRESS 1
Bits 21-0 LPB Frame Buffer Address 1
Value = starting address 1 (offset in bytes from the start of the frame buffer) for writ-
ing LPB data to the frame buffer
This value will normally be the same as the secondary stream frame buffer address 1.
Both address 0 and address 1 are defined when double buffering is used. The value
must start on an 8-byte boundary.
Bits 31-22 Reserved

LPB Direct Read/Write Address Register (MMFF14)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LPB DIRECT READ/WRITE ADDRESS
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R R R R R R R R TT LPB READ/WRITE ADDRESS
Bits 20-0 LPB Direct Read/Write Address
Value = address of Scenic/MX2 register to read/write
Bits 23-21 TT - Transaction Type (Scenic/MX2)

000 = Register write
001 = Register read
110 = Compressed video data write from the output FIFO. This value is automatically
generated by hardware when data is written to the output FIFO.
Bits 31-24 Reserved
LPB Direct Read/Write Data Register (MMFF18)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LPB DIRECT READ/WRITE DATA
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPB DIRECT READ/WRITE DATA
Bits 31-0 LPB Direct Read/Write Data
A write to this register triggers a read/write sequence based on the address informa-
tion in MMFF14_23-0.

LPB General Purpose Input/Output Port Register (MMFF1C)
Read/Write - see bit definitions Address: FF1CH

This register is available only for PCI bus configurations.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R R R R R R R R LPB GIP LPB GOP
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Bits 3-0 LPB General Purpose Output Data Port
These bits are driven onto the LPB LD[3:0] lines whenever a write is performed to
CR5C. STWR is asserted (low) at this time for use as an enable strobe for latching the
data into an external buffer.
Bits 7-4 LPB General Purpose Input Data Port (Read only)
Whenever a write is performed to CR5C, STWR is asserted (low). This strobe can be
used to enable a register to drive data onto any or all of the LD[7:4] lines. This data is
then latched into these bits.
Bits 31-8 Reserved

Serial Port Register (MMFF20)
See Bit Definitions Address: FF20H

This register can also be accessed at I/O ports E2H or E8H. See the Serial Communications Port de-
scription in Section 12.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R R R B4M B3M B2M B1M B0M R R R SPE SDR SCR SDW SCW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Bit 0 SCW - Serial Clock Write

0 = Pin 205 is driven low
Pin 205 carries the DDC/I2C clock, depending on the operational mode. When pin 205
is tri-stated, other devices may drive this line. The actual state of the pin is read via
bit 2 of this register.
Bit 1 SDW - Serial Data Write

Pin 206 carries the DDC/I2C data, depending on the operational mode. When pin 206
is tri-stated, other devices may drive this line. The actual state of the pin is read via
bit 3 of this register.
Bit 2 SCR - Serial Clock Read (Read Only)

0 = Pin 205 is low
1 = Pin 205 is tri-stated (no device is driving this line)
Bit 3 SDR - Serial Data Read (Read Only)

0 = Pin 206 is low
Bit 4 SPE - Serial Port Enable

0 = Use of bits 1-0 of this register disabled
1 = Use of bits 1-0 of this register enabled
Bits 5-7 Reserved
Bit 8 B0M - Bit 0 Mirror (Read Only)




0 = Pin 205 is low
Bit 11 B3M -Bit 3 Mirror (Read Only)

0 = Pin 206 is low

0 = Use of bits 1-0 of this register disabled
1 = Use of bits 1-0 of this register enabled
Bits 31-13 Reserved
LPB Video Input Window Size Register (MMFF24)

This register applies only to Video 8 In or Video 16 mode
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R R R R VIDEO INPUT LINE WIDTH
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R R R R R R R VIDEO INPUT WINDOW HEIGHT
Bits 11-0 Video Input Line Width
Value = [# pixels x 2] - 2 for Video 8 mode

Value = # pixels -2 for Video 16 mode
This is the width of the displayed line after the offset specified in MMFF28_11-0. Be-
fore the 2 is subtracted, the number of pixels must be a multiple of 4. For example, in
Video 16 mode, if the line width is 637 pixels, this must be rounded up to 640. The
programmed value is then 640 - 2 = 638.
Bits 15-12 Reserved
Bits 24-16 Video Input Window Height
Value = [height in lines of each video input frame] - 1
This is the number of displayed lines - 1 after the offset specified in MMFF28_24_16.
Bits 31-25 Reserved

LPB Video Data Offsets Register (MMFF28)

This register applies only to Video 8 In or Video 16 mode
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R R R R HORIZONTAL VIDEO DATA OFFSET
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R R R R R R R VERTICAL VIDEO DATA OFFSET
Bits 11-0 Horizontal Video Data Offset
Value = [number of LCLKs between HSYNC and the start of valid pixel data] - 2
Bits 15-12 Reserved
Bits 24-16 Vertical Video Data Offset
Value = number of HSYNCs between VSYNC and the first valid data line
Bits 31-25 Reserved

LPB Horizontal Decimation Control Register (MMFF2C)
Read/Write Address: FF2CH

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VIDEO DATA BYTE MASK
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VIDEO DATA BYTE MASK
Bits 31-0 Video Data Byte Mask
Each 32 bytes of video data input is compared with this mask. If a bit in this mask is 1,
the corresponding byte is discarded. If a bit is a 0, the corresponding byte is passed
to the video memory. In Video 16 mode, each bit masks 2 bytes. In pass-through
mode, each bit masks 4 bytes. Normally, decimation starts with bit 0 after an HSYNC.
If a horizontal video data offset is specified in MMFF28_11-0 (video 8 or 16 modes
only), decimation aligns with the start of data after the offset.
LPB Vertical Decimation Control Register (MMFF30)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VIDEO DATA LINE MASK
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VIDEO DATA LINE MASK
Bits 31-0 Video Data Line Mask
Each 32 lines of video data input is compared with this mask. If a bit in the mask is 0,
the corresponding line is discarded. If a bit is a 1, the corresponding line is passed to
the video memory. If a vertical video data offset is specified in MMFF28_24-16 (video
8 or 16 modes only), decimation does not align with the starting line after the offset
and instead starts from VSYNC.

LPB Line Stride (MMFF34)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R R R R LINE STRIDE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R R R R R R R R R R R R R R R
Bits 11-0 Line Stride
Value = byte offset of vertically adjacent pixels
This offset is added to the line starting address each HSYNC to get the new line start-
ing address. Each line must begin on an 8-byte boundary.
Bits 31-12 Reserved
LPB Output FIFO Register (MMFF40)
Read/Write Address: FF40H, FF44H...,FF5CH

Writes to any of the addresses in this 8 doubleword address range will be transferred to the LPB input
FIFO. This allows efficient use of the MOVSD assembly language instruction. Accesses must be to
doubleword addresses.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUTPUT FIFO DATA
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OUTPUT FIFO DATA
Bits 31-0 Output FIFO Data
Note: Software must never transfer more compressed data than there is room for in
the output FIFO. This information is read from MMFF04_3-0.

Section 25: PCI Register Descriptions
The PCI specification defines a configuration register space. These registers allow device relocation,
device independent system address map construction and automatic configurations. ViRGE provides
a subset of these registers, which are described below.
The configuration register space occupies 256 bytes. When a configuration read or write command is
issued, the AD[7:0] lines contain the address of the register in this space to be accessed. ViRGE supports
or returns 0 for the first 64 bytes of this space.
In the following register descriptions, ’R’ stands for reserved (write = 0, read = undefined).
Vendor ID
Read Only Address: 00H

This read-only register identifies the device manufacturer.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Vendor ID
Bits 15–0 Vendor ID

This is hardwired to 5333H to identify S3 Incorporated.
PCI REGISTER DESCRIPTIONS 25-1

Device ID

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Device ID
Bits 15–0 Device ID
Hardwired to 5631H (initial stepping)
Command

Power-On Default: 0000H (PCI); 0003H (VL)
This register controls which types of PCI cycles ViRGE can generate and respond to.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAC MEM I/O
R R R R R R R R R R SNP R R BME
Bit 0 I/O - Enable Response to I/O Accesses

0 = Response to I/O space accesses is disabled
1 = Response to I/O space accesses enabled
Bit 1 MEM - Enable Response to Memory Accesses

0 = Response to memory space accesses is disabled
1 = Response to memory space accesses enabled
Bit 2 BME - Bus Master Operation Enable

0 = Bus master operation disabled
1 = Bus master operation enabled
Bits 4-3 Reserved
Bit 5 DAC SNP - RAMDAC Register Access Snooping

0 = ViRGE claims and responds to all RAMDAC register access cycles
1 = ViRGE performs RAMDAC register writes but does not claim the PCI cycle.
RAMDAC register read accesses are performed by ViRGE.
25-2 PCI REGISTER DESCRIPTIONS

Status

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R R RMA RTA R DEVSEL R R R R R R R R R
Bits 8–0 Reserved
Bits 10–9 DEVSEL - Device Select Timing

01 = Medium DEVSEL timing. (hardwired)
Bit 11 Reserved
Bit 12 RTA - Received Target Abort

0 = No effect
1 = Bus master transaction terminated with target-abort
This bit is reset by software by writing a 1 to this location.
Bit 13 RMA - Received Master Abort

0 = No effect
1 = Bus master transaction terminated with master-abort
This bit is reset by software by writing a 1 to this location.
Class Code

Power-On Default: 30000xxH
This register is hardwired to 30000xxH to specify that ViRGE is a VGA-compatible display controller.
The xx will change with each revision.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PROGRAMMING INTERFACE REVISION ID
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BASE CLASS CODE SUB-CLASS

Latency Timer
Read/Write Address: 0DH

7 6 5 4 3 2 1 0
BM LATENCY TIMER 0 0 0
These are the 3 lsb’s of the latency timer value, providing 8 clocks granularity.
Bits 7-3 BM LATENCY TIMER - Bus Master Latency Timer
Value = number of PCI clocks ViRGE can keep its bus master grant without having it
removed
These are the 5 msb’s of this value. The three lsb’s are 000b. This value is normally
programmed by the system BIOS based in part on the requested value in bits 15-8 of
3EH.
Base Address 0
Read/Write Address: 12H (high) 10H (low)

Power-On Default: 7000 0000H (PCI), 0000 0000H (VL)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R R R R R R R R R R R R PREF MSI
=0 TYPE =00 =0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BASE ADDRESS 0 R R R R R R R R R R
Bit 0 MSI - Memory Space Indicator

0 = Base registers map into memory space (hardwired)
Bits 2–1 TYPE - Type of Address Relocation

00 = Locate anywhere in 32-bit address space (hardwired)
Bit 3 PREF - Prefetchable

0 = Does not meet the prefetchable requirements (hardwired)

Bits 31–26 BASE ADDRESS 0
Value = upper 6 bits of the base address for accessing ViRGE registers and memory
via memory-mapped I/O
This field provides for address relocation. These bits map to system address bits 31-
26. All other address bits (25-4) return 0 on read to specify that ViRGE requires a 64
MByte address space. Note that writes to CR59_7-2 will also update this field, so if the
linear addressing base address is being changed, the programmer must do a read-
modify-write to ensure that this field is not changed.
BIOS ROM Base Address
Read/Write Address: 32H (high) 30H (low)

Power-On Default: 000C 0000H
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R R R R R R R R R R R R R R R ADE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BIOS ROM BASE ADDRESS
Bit 0 ADE - Address Decode Enable

0 = Accesses to the BIOS ROM address space defined in this register are disabled
1 = Accesses to the BIOS ROM address space defined in this register are enabled
Bits 31–16 BIOS ROM BASE ADDRESS

These are the upper 16 bits of the BIOS ROM address.
Interrupt Line
Read/Write Address: 3CH

This register contains interrupt line routing information written by the POST program during power-on
initialization.
7 6 5 4 3 2 1 0
INTERRUPT LINE
Bits 7–0 INTERRUPT LINE

Interrupt Pin
Read Only Address: 3DH

This register is hardwired to a value of 1 to specify that INTA is the interrupt pin used.
7 6 5 4 3 2 1 0
INTERRUPT PIN
Bits 7–0 INTERRUPT PIN
Latency/Grant
Read Only Address: 3EH

Power-On Default: FF04H
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAXIMUM LATENCY MINIMUM GRANT
Bits 7–0 MINIMUM GRANT
Value = Length of burst period required in units of 250 ns (33 MHz clock)
Bits 15–8 MAXIMUM LATENCY
Value = Maximum latency of PCI access in units of 250 ns (33 MHz clock)

Appendix A: Listing of Raster Operations
ViRGE supports all 256 triadic raster operations The boolean operators used as as follows:
(ROPs) for BitBLTs as defined by Microsoft for
Windows. The coding for these is found on the o = bitwise OR
following pages.
x = bitwise EXCLUSIVE OR
The HEX value in the first column is the ROP
code. This value must be programmed into bits a = bitwise AND
7-0 of D2E8H at the time that a ROPBLT command
is executed. n = bitwise NOT (inverse)
The effect of the ROP is shown in reverse Polish For example, ROP 16H is PSDPSanaxx. The pat-
notation in the second column. This is interpreted t e r n i s f i r s t A N D e d wi t h t he s ou rc e
as follows: [PSD(PaS)naxx]. The result is inverted and then
ANDed with the destination [PS((Da(notPaS))xx.
S = Source bitmap This result is EXCLUSIVE ORed with the source.
Finally, the result of this is EXCLUSIVE ORed with
P = Pattern the pattern.
D = Destination bitmap Programming using ROPBLTs is explained in En-

hanced Programming section.
The source bitmap can be either the CPU or the
current screen, as specified by bit 7 of the Com-
mand Set register. A CPU source can be either
monochrome or color, as specified by bit 6 of the
Command Set register. A screen source is always
color.
The pattern may be either monochrome or color,

as specified by bit 8 of the Command Set register.
The destination bitmap is always the screen. It is

always color (as opposed to monochrome).
LISTING OF RASTER OPERATIONS A-1

HEX In Reverse Polish HEX In Reverse Polish

00 0 2C SPDSoax
01 DPSoon 2D PSDnox
02 DPSona 2E PSDPxox
03 PSon 2F PSDnoan
04 SDPona 30 PSna
05 DPon 31 SDPnaon
06 PDSxnon 32 SDPSoox
07 PDSaon 33 Sn
08 SDPnaa 34 SPDSaox
09 PDSxon 35 SPDSxnox
0A DPna 36 SDPox
0B PSDnaon 37 SDPoan
0C SPna 38 PSDPoax
0D PDSnaon 39 SPDnox
0E PDSonon 3A SPDSxox
0F Pn 3B SPDnoan
10 PDSona 3C PSx
11 DSon 3D SPDSonox
12 SDPxnon 3E SPDSnaox
13 SDPaon 3F PSan
14 DPSxnon 40 PSDnaa
15 DPSaon 41 DPSxon
16 PSDPSanaxx 42 SDxPDxa
17 SSPxDSxaxn 43 SPDSanaxn
18 SPxPDxa 44 SDna
19 SDPSanaxn 45 DPSnaon
1A PDSPaox 46 DSPDaox
1B SDPSxaxn 47 PSDPxaxn
1C PSDPaox 48 SDPxa
1D DSPDxaxn 49 PDSPDaoxxn
1E PDSox 4A DPSDoax
1F PDSoan 4B PDSnox
20 DPSnaa 4C SDPana
21 SDPxon 4D SSPxDSxoxn
22 DSna 4E PDSPxox
23 SPDnaon 4F PDSnoan
24 SPxDSxa 50 PDna
25 PDSPanaxn 51 DSPnaon
26 SDPSaox 52 DPSDaox
27 SDPSxnox 53 SPDSxaxn
28 DPSxa 54 DPSonon
29 PSDPSaoxxn 55 Dn
2A DPSana 56 DPSox
2B SSPxPDxaxn 57 DPSoan
A-2 LISTING OF RASTER OPERATIONS


58 PDSPoax 84 SDPxna
59 DPSnox 85 PDSPnoaxn
5A DPx 86 DSPDSoaxx
5B DPSDonox 87 PDSaxn
5C DPSDxox 88 DSa
5D DPSnoan 89 SDPSnaoxn
5E DPSDnaox 8A DSPnoa
5F DPan 8B DSPDxoxn
60 PDSxa 8C SDPnoa
61 DSPDSaoxxn 8D SDPSxoxn
62 DSPDoax 8E SSDxPDxax
63 SDPnox 8F PDSanan
64 SDPSoax 90 PDSxna
65 DSPnox 91 SDPSnoaxn
66 DSx 92 DPSDPoaxx
67 SDPSonox 93 SPDaxn
68 DSPDSonoxxn 94 PSDPSoaxx
69 PDSxxn 95 DPSaxn
6A DPSax 96 DPSxx
6B PSDPSoaxxn 97 PSDPSonoxx
6C SDPax 98 SDPSonoxn
6D PDSPDoaxxn 99 DSxn
6E SDPSnoax 9A DPSnax
6F PDSxnan 9B SDPSoaxn
70 PDSana 9C SPDnax
71 SSDxPDxaxn 9D DSPDoaxn
72 SDPSxox 9E DSPDSaoxx
73 SDPnoan 9F PDSxan
74 DSPDxox A0 DPa
75 DSPnoan A1 PDSPnaoxn
76 SDPSnaox A2 DPSnoa
77 DSan A3 DPSDxoxn
78 PDSax A4 PDSPonoxn
79 DSPDSoaxxn A5 PDxn
7A DPSDnoax A6 DSPnax
7B SDPxnan A7 PDSPoaxn
7C SPDSnoax A8 DPSoa
7D DPSxnan A9 DPSoxn
7E SPxDSxo AA D
7F DPSaan AB DPSono
80 DPSaa AC SPDSxax
81 SPxDSxon AD DPSDaoxn
82 DPSxna AE DSPnao
83 SPDSnoaxn AF DPno
LISTING OF RASTER OPERATIONS A-3


B0 PDSnoa DC SPDnao
B1 PDSPxoxn DD SDno
B2 SSPxDSxox DE SDPxo
B3 SDPanan DF SDPano
B4 PSDnax E0 PDSoa
B5 DPSDoaxn E1 PDSoxn
B6 DPSDPaoxx E2 DSPDxax
B7 SDPxan E3 PSDPaoxn
B8 PSDPxax E4 SDPSxax
B9 DSPDaoxn E5 PDSPaoxn
BA DPSnao E6 SDPSanax
BB DSno E7 SPxPDxan
BC SPDSanax E8 SSPxDSxax
BD SDxPDxan E9 DSPDSanaxxn
BE DPSxo EA DPSao
BF DPSano EB DPSxno
C0 PSa EC SDPao
C1 SPDSnaoxn ED SDPxno
C2 SPDSonoxn EE DSo
C3 PSxn EF SDPnoo
C4 SPDnoa F0 P
C5 SPDSxoxn F1 PDSono
C6 SDPnax F2 PDSnao
C7 PSDPoaxn F3 PSno
C8 SDPoa F4 PSDnao
C9 SPDoxn F5 PDno
CA DPSDxax F6 PDSxo
CB SPDSaoxn F7 PDSano
CC S F8 PDSao
CD SDPono F9 PDSxno
CE SDPnao FA DPo
CF SPno FB DPSnoo
D0 PSDnoa FC PSo
D1 PSDPxoxn FD PSDnoo
D2 PDSnax FE DPSoo
D3 SPDSoaxn FF 1
D4 SSPxPDxax
D5 DPSanan
D6 PSDPSaoxx
D7 DPSxan
D8 PDSPxax
D9 SDPSaoxn
DA DPSDanax
DB SPxDSxan
A-4 LISTING OF RASTER OPERATIONS

Appendix B: Register Reference
This Appendix contains tables listing all the registers in each of categories corresponding to Sections
16-26 of this data book.
• VGA
• Extended Sequencer
• Extended CRTC
• S3D
• Streams Processor
• Memory Port
• DMA
• LPB
• Miscellaneous
• PCI Configuration Space
Within each table, registers are listed in order of increasing addresses/indices. Name, address, register
bit descriptions with read/write status and the page number of the detailed register description are
provided for each register. All addresses and indices are hexadecimal values.
REGISTER REFERENCE B-1

B.1 VGA REGISTERS
? = B for monochrome, D for color.
Table B-1. VGA Registers
Add Index Register Name Description

ress Bit(s) Bit Description Page
General or External Registers
3C2 Miscellaneous Output 16-1
0 W Color emulation. Address based at 3Dx
1 W Enable CPU access of video memory
3-2 W Video DCLK select. Enable DCLK PLL loading
4 W Reserved
5 W Select the high 64K page of memory
6 W Make HSYNC an active low signal
7 W Make VSYNC an active low signal
3CC Miscellaneous Output 16-1
0 R Color emulation. Address based at 3Dx
1 R Enable CPU access of video memory
3-2 R Video DCLK select. Enable DCLK PLL loading
4 R Reserved
5 R Select the high 64K page of memory
6 R Make HSYNC an active low signal
7 R Make VSYNC an active low signal
3?A Feature Control 16-2
2-0 W Reserved
3 W VSYNC is ORed with the internal display enable signal
7-4 W Reserved
3CA Feature Control 16-2
2-0 R Reserved
3 R VSYNC is ORed with the internal display enable signal
7-4 R Reserved
3C2 Input Status 0 16-3
3-0 R Reserved
4 R The internal SENSE signal is a logical 1
6-5 R Reserved
7 R Vertical retrace interrupt to the CPU is pending
B-2 REGISTER REFERENCE

Table B-1. VGA Registers (continued)

ress Bit(s) R/W Bit Description Page
3?A Input Status 1 16-3
0 R The display in not in active display mode
1 R Reserved
2 R Reserved = 1
3 R Vertical retrace period is active
5-4 R Feedback of two color outputs for test purposes
7-6 R Reserved
3C3 Video Subsystem Enable 16-4
0 R/W Enable VGA display
7-1 R/W Reserved
Sequencer Registers
3C4 Sequencer Index 16-5
4-0 R/W Index to the sequencer register to be accessed
7-5 R/W Reserved
3C5 Sequencer Data 16-5
7-0 R/W Data to or from the sequencer register accessed
3C5 00 Reset (SR0) 16-6
0 R/W Asynchronous reset (not functional for ViRGE
1 R/W Synchronous reset (not functional for ViRGE)
7-2 R/W Reserved
3C5 01 Clocking Mode (SR1) 16-6
0 R/W Character clocks are 8 dots wide
1 R/W Reserved
2 R/W Load the video serializers every second character clock
3 R/W The internal character clock is 1/2 the DCLK frequency
4 R/W Load the video serializers every fourth character clock
5 R/W Screen is turned off
3C5 02 Enable Write Plane (SR2) 16-7
3-0 R/W Enables a CPU write to the corresponding color plane
7-4 R/W Reserved
3C5 03 Character Font Select (SR3) 16-8
4, 1-0 R/W Select Font B
5,3-2 R/W Select Font A
7-6 R/W Reserved
3C5 04 Memory Mode Control (SR4) 16-9
0 R/W Reserved
1 R/W Memory access to 256K allowed (required for VGA)
2 R/W Sequential addressing for CPU video memory accesses


CRT Controller Registers
3?4 CRT Controller Index 16-10
7-0 R/W Index to the CRTC register to be accessed
3?5 CRT Controller Data 16-10
7-0 R/W Data to or from the CRTC register accessed
3?5 00 Horizontal Total (CR0) 16-11
7-0 R/W Number of characters in a line -5
3?5 01 Horizontal Display End (CR1) 16-11
7-0 R/W One less than the total number of displayed characters
3?5 02 Start Horizontal Blank (CR2) 16-12
7-0 R/W Character count where horizontal blanking starts
3?5 03 End Horizontal Blank (CR3) 16-12
4-0 R/W End position of horizontal blanking
6-5 R/W Display enable skew in character clocks
7 R/W Reserved
3?5 04 Start Horizontal Sync Position (CR4) 16-13
7-0 R/W Character count where HSYNC goes active
3?5 05 End Horizontal Sync Position (CR5) 16-13
4-0 R/W Position where HSYNC goes inactive
6-5 R/W Horizontal retrace end delay in character clocks
7 R/W End horizontal blanking bit 5
3?5 06 Vertical Total (CR6) 16-14
7-0 R/W Number of lines - 2
3?5 07 CRTC Overflow (CR7) 16-14
0 R/W Vertical total bit 8
1 R/W Vertical display end bit 8
2 R/W Vertical retrace start bit 8
3 R/W Start vertical blank bit 8
4 R/W Line compare bit 8
5 R/W Vertical total bit 9
6 R/W Vertical display end bit 9
7 R/W Vertical retrace start bit 9
3?5 08 Preset Row Scan (CR8) 16-15
4-0 R/W Line where first character row begins
6-5 R/W Number of bytes to pan horizontally
7 R/W Reserved


3?5 09 Maximum Scan Line (CR9) 16-15
4-0 R/W Character height in scan lines -1
5 R/W Start vertical blank bit 9
6 R/W Line compare bit 9
7 R/W Double scanning (repeat each line) enabled
3?5 0A Cursor Start Scan Line (CRA) 16-16
4-0 R/W Cursor starting line within the character cell
5 R/W Turns off the cursor
7-6 R/W Reserved
3?5 0B Cursor End Scan Line (CRB 16-16
4-0 R/W Cursor ending line within the character cell
6-5 R/W Cursor skew to right in characters
7 R/W Reserved
3?5 OC Start Address High (CRC) 16-17
7-0 R/W Bits 15-8 of the display start address
3?5 OD Start Address Low (CRD) 16-17
7-0 R/W Bits 7-0 of the display start address
3?5 OE Cursor Location Address High (& Hardware Cursor 16-17
Foreground Color in Enhanced Mode) (CRE)
7-0 R/W Bits 15-8 of the cursor location start address
3?5 OF Cursor Location Address Low (& Hardware Cursor 16-17
Background Color in Enhanced Mode) (CRF)
7-0 R/W Bits 7-0 of the cursor location start address
3?5 10 Vertical Retrace Start (CR10 16-18
7-0 R/W Vertical retrace start in scan lines
3?5 11 Vertical Retrace End (CR11) 16-18
3-0 R/W Vertical retrace end in scan lines
4 R/W Clear the vertical retrace interrupt flip-flop
5 R/W Disable vertical interrupts
6 R/W Five RAM refresh cycles per horizontal line
7 R/W Lock writes to CR0-CR7
3?5 12 Vertical Display End (CR12) 16-19
7-0 R/W Number of scan lines of active video
3?5 13 Offset (CR13) 16-20
7-0 R/W Memory start address jump from one scan line to the next


3?5 14 Underline Location (CR14) 16-20
4-0 R/W Horizontal scan line where underline occurs
5 R/W Memory address counter increment is 4 character clocks
6 R/W Memory accessed as doublewords
7 R/W Reserved
3?5 15 Start Vertical Blank (CR15) 16-21
7-0 R/W Horizontal scan line where vertical blanking starts
3?5 16 End Vertical Blank (CR16 16-21
7-0 R/W Horizontal scan line where vertical blanking ends
3?5 17 CRTC Mode Control (CR17) 16-22
0 R/W Enable bank 2 mode for CGA emulation
1 R/W Enable bank 4 mode for CGA emulation
2 R/W Use horizontal retrace clock divided by 2
3 R/W Enable count by 2 mode
4 R/W Reserved
5 R/W Enable CGA mode address wrap
6 R/W Use byte address mode
7 R/W Horizontal and vertical retrace signals enabled
3?5 18 Line Compare (CR18) 16-23
7-0 R/W Line at which memory address counter cleared to 0
3?5 22 CPU Latch Data (CR22) 16-24
7-0 R Value in the CPU latch in the graphics controller
3?5 24,26 Attribute Controller Flag/Index 16-24
5-0 R Value of the attribute controller index data at 3C0H
6 R Reserved
7 R State of inverted internal address flip-flop
Graphics Controller Registers
3CE Graphics Controller Index 16-25
3-0 R/W Index to the graphics controller register to be accessed
7-4 R/W Reserved
3CF Graphics Controller Data 16-25
7-0 R/W Data to or from the graphics controller register accessed
3CF 00 Set/Reset (GR0) 16-26
3-0 R/W Color value for CPU memory writes
7-4 R/W Reserved
3CF 01 Enable Set/Reset (GR1) 16-26
3-0 R/W Enable planes for writing GR0 data
7-4 R/W Reserved


3CF 02 Color Compare (GR2) 16-27
3-0 R/W Reference color for color compare operations
7-4 R/W Reserved
3CF 03 Raster Operation/Rotate Counter (GR3) 16-27
2-0 R/W Number of right rotate positions for a CPU memory write
4-3 R/W Select raster operation (logical function)
7-5 R/W Reserved
3CF 04 Read Plane Select (GR4) 16-28
1-0 R/W Select planes for reading
7-2 R/W Reserved
3CF 05 Graphics Controller Mode (GR5) 16-29
1-0 R/W Select write mode
2 R/W Reserved
3 R/W Enable read compare operation
4 R/W Select odd/even addressing
5 R/W Select odd/even shift mode
6 R/W Select 256 color shift mode
7 R/W Reserved
3CF 06 Memory Map Mode Control (GR6) 16-30
0 R/W Select graphics mode memory addressing
1 R/W Chain odd/even planes
3-2 R/W Select memory mapping
7-4 R/W Reserved
3CF 07 Color Don’t Care (GR7) 16-31
3-0 R/W Select color plane used for color comparison
7-4 R/W Reserved
3CF 08 Bit Mask (GR8) 16-31
7-0 R/W Each bit is a mask for the corresponding memory plane bit
Attribute Registers
3C0 Attribute Controller Index 16-32
4-0 R/W Index to the attribute controller register to be accessed
5 R/W Enable video display
7-6 R/W Reserved
3C1/0 Attribute Controller Data 16-33
7-0 R/W Data to or from the attribute controller register accessed
3C1/0 00–0F Palette Register (AR0–ARF) 16-33
5-0 R/W Color value
7-6 R/W Reserved


3C1/0 10 Attribute Mode Control (AR10 16-34
0 R/W Select graphics mode
1 R/W Select monochrome display
2 R/W Enable line graphics characters
3 R/W Enable blinking
4 R/W Reserved
5 R/W Enable top panning
6 R/W Select 256 color mode
7 R/W Bits 5-4 of video output come from AR14_1-0
3C1/0 11 Border Color (AR11) 16-35
7-0 R/W Border color value
3C1/0 12 Color Plane Enable (AR12) 16-35
3-0 R/W Display plane enable
5-4 R/W Select inputs to bits 5-4 of 3?AH
7-6 R/W Reserved
3C1/0 13 Horizontal Pixel Panning (AR13) 16-36
3-0 R/W Number of pixels to shift the display to the left
7-4 R/W Reserved
3C1/0 14 Pixel Padding (AR14) 16-37
1-0 R/W Bits 5-4 of the video output if AR10_7 = 1
3-2 R/W Bits 7-6 of the video output
7-4 R/W Reserved
RAMDAC Registers
3C6 DAC Mask 16-38
7-0 R/W Pixel read mask
3C7 DAC Read Index 16-38
7-0 W Index to palette register to be read
3C7 DAC Status 16-39
1-0 R Shows whether previous DAC cycle was a read or write
7-2 R Reserved
3C8 – DAC Write Index 16-39
7-0 R/W Index to palette register to be written or General Input Port
read data
3C9 DAC Data 16-40
7-0 R/W Data from register pointed to by DAC Read or Write Index

B.2 EXTENDED SEQUENCER REGISTERS
Table B-2. Extended Sequencer Registers

3C5 08 Unlock Extended Sequencer (SR8) 17-1
7-0 R/W Load xxxx0110b to unlock SR9-SR1C
3C5 09 R/W Extended Sequencer 9 (SR9) 17-1
6-0 R/W Reserved
7 R/W Memory-mapped I/O only (no PIO)
3C5 0A Extended Sequencer A (SRA) 17-2
4-0 R/W Reserved
5 R/W PD[63:0] not tri-stated
6 R/W Pin 50 is RAS1
7 R/W 2 MCLK memory writes
3C5 0B Extended Sequencer B (SRB) 17-3
0 R/W Use VCLKI for internal dot clock functions (test only)
1 R/W Pixel data from VAFC latched by VCLKI
3-2 R/W Reserved
7-4 R/W Specify color mode for feature connector input
3C5 0D Extended Sequencer D (SRD) 17-4
0 R/W Enable feature connector operation
1 R/W Select LPB feature connector
3-2 R/W Reserved
5-4 R/W HSYNC control for Green PC requirements
7-6 R/W VSYNC control for Green PC requirements
3C5 10 MCLK Value Low (SR10) 17-5
4-0 R/W MCLK N-divider value
6-5 R/W MCLK R value
7 R/W Reserved
3C5 11 MCLK Value High (SR11) 17-5
6-0 R/W MCLK M-divider value
7 R/W Reserved
3C5 12 DCLK Value Low (SR12) 17-6
4-0 R/W DCLK N-divider value
6-5 R/W DCLK R value
7 R/W Reserved
3C5 13 DCLK Value High (SR13) 17-6
6-0 R/W DCLK M-divider value
7 R/W Reserved

Table B-2. Extended Sequencer Registers (continued)

3C5 14 CLKSYN Control 1 (SR14) 17-7
0 R/W DCLK PLL powered down (test only)
1 R/W MCLK PLL powered down (test only)
2 R/W Enable clock synthesizer test counter
3 R/W Select MCLK or DCLK for testing
4 R/W Clear clock synthesizer counter
5 R/W Pin 146 tri-stated
6 R/W MCLK is input on pin 146 (test only)
7 R/W DCLK is input on pin 156 (test only)
3C5 15 CLKSYN Control 2 (SR15) 17-8
0 R/W Load new MCLK frequency
1 R/W Load new DCLK frequency
2 R/W MCLK output on pin 147 (test only)
3 R/W VCLK direction determined by EVCLK
4 R/W Divide DCLK by 2
5 R/W Load MCLK and DCLK PLL values immediately
6 R/W Invert DCLK
7 R/W Enable 2 MCLK memory writes
3C5 16 CLKSYN Test High (SR16) 17-9
7-0 R/W High byte of clock synthesizer test data
3C5 17 CLKSYN Test Low (SR17) 17-10
7-0 R/W Low byte of clock synthesizer test data
3C5 18 RAMDAC/CLKSYN Control (SR18) 17-10
0 R/W RAMDAC signature test counter enabled
1 R/W Reset RAMDAC signature test counter
2 R/W Place signature test red data on internal data bus
3 R/W Place signature test green data on internal data bus
4 R/W Place signature test blue data on internal data bus
5 R/W Power-down RAMDAC
6 R/W Select 1 cycle LUT write
7 R/W RAMDAC clock doubled mode enabled
3C5 1C Extended Sequencer 1C (SR1C) 17-11
1-0 R/W Select functions for pins 151 and 190
1 R/W Reserved

B.3 EXTENDED CRTC REGISTERS
Table B-3. Extended CRTC Registers

3?5 2D Device ID High (CR2D) 18-1
7-0 R High byte of device ID (56H)
3?5 2E Device ID Low (CR2E) 18-1
7-0 R Low byte of device ID (31H)
3?5 2F Revision (CR2F) 18-2
7-0 R Revision level (initially 80H, subject to change)
3?5 30 Chip ID/Rev (CR30) 18-2
3-0 R Chip Identification - EH
7-4 R Chip revision status (stepping) - See CR2F
3?5 31 Memory Configuration (CR31) 18-2
0 R/W Enable base address offset (CR6A_6-0)
1 R/W Reserved
2 R/W Enable VGA 16-Bit Memory Bus Width
3 R/W Use Enhanced mode memory mapping
5-4 R/W Old display start address bits 17-16 (see CR69_3-0)
6 R/W Enable high speed text display font fetch mode
7 R/W Reserved
3?5 32 Backward Compatibility 1 (CR32) 18-3
3-0 R/W Reserved
4 R/W Enable interrupt generation
5 R/W Reserved
6 R/W Use standard VGA memory wrapping at 256K boundary
7 R/W Reserved
0 R/W Reserved
1 R/W Disable write protection provided by CR11_7 on CR7_1,6
2 R/W Reserved
3 R/W VCLK is internal DCLK
4 R/W Disable writes to RAMDAC registers (3C6H-3C9H)
5 R/W BLANK signal active during entire non-active video period
6 R/W Disable writes to Palette/Overscan registers (AR0-ARF)
7 R/W Reserved

Table B-3. Extended CRTC Registers (continued)

0 R/W PCI DAC snoop method select
1 R/W Disable PCI master abort handling during DAC snoop
2 R/W Disable PCI retry handling during DAC snoop
3 R/W Reserved
4 R/W Enable Display Start FIFO Fetch register (CR3B)
7-5 R/W Reserved
3?5 35 CRT Register Lock (CR35) 18-6
3-0 R/W Old CPU base address (see CR6A_6-0)
4 R/W Lock Vertical Timing registers
5 R/W Lock Horizontal Timing registers
7-6 R/W Reserved
3?5 36 Configuration 1 (CR36) 18-7
1-0 R Select system bus (PCI or VL-Bus)
3-2 R/W Select memory page mode (fast page, EDO, 1-cycle EDO)
4 R/W Enable BIOS ROM accesses (VL-Bus)
7-5 R/W Define display memory size
0 R/W Enable ViRGE operation (VL-Bus)
1 R/W Reserved
2 R/W Select 32K or 64K BIOS ROM size (VL-Bus)
3 R/W Use internal MCLK, DCLK
4 R/W Define RAMDAC write snooping (VL-Bus)
7-5 R/W Reserved for BIOS use
3?5 38 Register Lock 1 (CR38) 18-9
7-0 R/W Unlock S3 VGA registers (CR30-CR3C)
3?5 39 Register Lock 2 (CR39) 18-9
7-0 R/W Unlock System Control, System Extension and Strapping
registers (CR40-CR4F, CR50-CR6D)
3?5 3A Miscellaneous 1 (CR3A) 18-9
1-0 R/W Select alternate refresh count per horizontal line
2 R/W Enable alternate refresh count (CR3A_1-0)
3 R/W Enable simultaneous VGA text and Enhanced modes
4 R/W Enable 8-, 16- or 24/32-bit color Enhanced modes
5 R/W Enable high speed text font writing
6 R/W Reserved
7 R/W Disable PCI bus read burst cycles


3?5 3B Start Display FIFO Fetch (CR3B) 18-10
7-0 R/W Specify start of display FIFO fetches for screen refreshing
3?5 3C Interlace Retrace Start (CR3C) 18-11
7-0 R/W Specify interlaced mode retrace start position
3?5 40 System Configuration (CR40) 18-11
0 R/W Enable Enhanced mode register access
3-1 R/W Reserved
4 R/W Ready (Wait State) Control (VL-Bus)
5 R/W Reserved = 1
7-6 R/W Reserved
3?5 41 BIOS Flag (CR41) 18-12
7-0 R/W Used by the video BIOS
3?5 42 Mode Control (CR42) 18-12
4-0 R/W Reserved
5 R/W Select Interlaced mode
6 R/W Reserved
3?5 43 Extended Mode (CR43) 18-13
1-0 R/W Reserved
2 R/W Old logical screen width bit 8
6-3 R/W Reserved
7 R/W Enable horizontal counter double mode
3?5 45 Hardware Graphics Cursor Mode (CR45) 18-13
0 R/W Enable hardware graphics cursor
3-1 R/W Reserved
4 R/W Set up space at right of bit map for hardware cursor
7-5 R/W Reserved
3?5 46–47 Hardware Graphics Cursor Origin-X (CR46-CR47) 18-14
10-0 R/W X-coordinate of the hardware cursor left side
15-11 R/W Reserved
3?5 48–49 Hardware Graphics Cursor Origin-Y (CR48-CR49) 18-14
10-0 R/W Y-coordinate of the hardware cursor upper line
15-11 R/W Reserved


3?5 4A Hardware Graphics Cursor Foreground Stack (CR4A) 18-14
7-0 R/W Hardware cursor foreground color (3 registers)
3?5 4B Hardware Graphics Cursor Background Stack (CR4B) 18-15
7-0 R/W Hardware cursor background color (3 registers)
3?5 4C–4D Hardware Graphics Cursor Start Address (CR4C-CR4D) 18-15
12-0 R/W Hardware cursor start address
15-13 R/W Reserved
3?5 4E Hardware Graphics Cursor Pattern Display Start X-Pixel 18-15
Position (CR4E)
5-0 R/W Hardware cursor display start x-coordinate
7-6 R/W Reserved
3?5 4F Hardware Graphics Cursor Pattern Display Start Y-Pixel 18-16
Position (CR4F)
5-0 R/W Hardware cursor display start y-coordinate
7-6 R/W Reserved
3?5 51 Extended System Cont 2 (CR51) 18-16
1-0 R/W Old display start address bits 19-18
3-2 R/W Old CPU base address bits 19-18
5-4 R/W Logical screen width bits 9-8
7-6 R/W Reserved
3?5 52 Extended BIOS Flag 1 (CR52) 18-17
3?5 53 Extended Memory Cont 1 (CR53) 18-17
0 R/W Reserved
2-1 R/W Big endian data byte swap for linear addressing
4-3 R/W MMIO type enable and select
5 R/W MMIO window at B8000H
6 R/W Enable nibble swap
7 R/W Reserved
3?5 54 Extended Memory Cont 2 (CR54) 18-18
1-0 R/W Big endian data swap (not linear addressing or image write)
7-2 R/W Reserved


dress Bit(s) R/W Bit Description Page
3?5 55 Extended DAC Control (CR55) 18-18
1-0 R/W Reserved
2 R/W Enable General Input Port read (VL-Bus)
3 R/W Reserved
4 R/W Enable X-11 windows hardware cursor mode
6-5 R/W Reserved
7 R/W VCLK output pin is tri-stated
3?5 56 External Sync Cont 1 (CR56) 18-19
0 R/W Reserved
1 R/W HSYNC output buffer tri-stated
2 R/W VSYNC output buffer tri-stated
7-3 R/W Reserved
3?5 58 Linear Address Window Control (CR58) 18-20
1-0 R/W Linear addressing window size
2 R/W Reserved
3 R/W Address latch timing control (VL-Bus)
4 R/W Enable linear addressing
3?5 58 Linear Address Window Control (CR58) (continued) 18-20
6-5 R/W Reserved
7 R/W RAS precharge time increased
3?5 59-5A Linear Address Window Position (CR59-5A) 18-21
15-0 R/W Linear addressing window position bits 31-16
3?5 5C General Out Port (CR5C) 18-22
7-0 R/W General Output Port
3?5 5D Extended Horizontal Overflow (CR5D) 18-22
0 R/W Horizontal total bit 8 (CR0)
1 R/W Horizontal display end bit 8 (CR1)
2 R/W Start horizontal blank bit 8 (CR2)
3 R/W End horizontal blank bit 7 (CR3, CR5)
4 R/W Start horizontal sync position bit 8 (CR4)
5 R/W End horizontal sync position bit 6 (CR5)
6 R/W Start FIFO Fetch bit 8 (CR3B)
7 R/W Reserved


3?5 5E Extended Vertical Overflow (CR5E) 18-23
0 R/W Vertical total bit 10 (CR6)
1 R/W Vertical display end bit 10 (CR12)
2 R/W Start vertical blank bit 10 (CR15)
3 R/W Reserved
4 R/W Vertical retrace start bit 10 (CR10)
5 R/W Reserved
6 R/W Line compare position bit 10 (CR18)
7 R/W Reserved
3?5 61 Extended Memory Control 4 (CR61) 18-23
4-0 R/W Reserved
6-5 R/W Big endian data byte swap (image writes)
7 R/W Reserved
3?5 65 Extended Miscellaneous Control (CR65) 18-24
2-0 R/W Reserved
4-3 R/W Delay BLANK by DCLK
7-5 R/W Reserved
3?5 66 Extended Miscellaneous Control 1 (CR66) 18-24
0 R/W Enable all accelerated modes
1 R/W Software reset of S3D Engine
2 R/W Reserved
3 R/W Enable PCI disconnects under certain FIFO conditions
5-4 R/W Reserved
3?5 66 Extended Miscellaneous Control 1 (CR66) (continued) 18-24
6 R/W PA[15:0] are tri-stated off
7 R/W Enable PCI bus disconnect during burst cycles
3?5 67 Extended Miscellaneous Control 2 (CR67) 18-25
0 R/W VCLK is in phase with DCLK
1 R/W Reserved
3-2 R/W Select Streams Processor mode
7-4 R/W Select RAMDAC color mode


1-0 R/W CAS, OE timing adjustment
2 R/W RAS low timing select
3 R/W RAS precharge timing select
6-4 R/W Reserved
7 R/W Reserved
3?5 69 Extended System Control 3 (CR69) 18-27
4-0 R/W Display start address bits 19-16
7-5 R/W Reserved
3?5 6A Extended System Control 4 (CR6A) 18-28
5-0 R/W CPU base address bits 19-14
7-6 R/W Reserved
3?5 6B Extended BIOS Flag 3 (CR6B) 18-28
3?5 6C Extended BIOS Flag 4 (CR6C) 18-28
3?5 6D Extended BIOS Flag 5 (CR6D) 18-29
3?5 6E RAMDAC Signature Test Data (CR6E) 18-29
7-0 R/W RAMDAC signature test data
3?5 6F Configuration 4 (CRF) 18-29
0 R/W Reserved
1 R/W Select I/O address for MMFF20
2 R/W Disable effect of bit 1 of this register
4-3 R/W WE delay
7-5 R/W Reserved

B.4 S3D REGISTERS
This section lists the registers which support the S3D Engine functions. All of these registers are enabled
only if bit 0 of CR40 is set to 1.
Table B-4. Color Pattern Registers

Color Pattern Registers 19-3
A100 31-0 R/W First pattern register
A104 31-0 R/W Second pattern register
.
.
.
A1BC 31-0 R/W Last pattern register
Table B-5. S3D 2D Registers

AxD4 Source Base Address 19-4
2-0 R/W Reserved = 0
21-3 R/W Source base address
31-22 R/W Reserved
AxD8 Destination Base Address 19-4
21-3 R/W Destination base address
31-22 R/W Reserved
AxDC Left/Right Clipping 19-5
10-0 R/W Left clipping limit
15-11 R/W Reserved
26-16 R/W Right clipping limit
31-27 R/W Reserved
AxE0 Top/Bottom Clipping 19-6
10-0 R/W Bottom clipping limit
15-11 R/W Reserved
26-16 R/W Top clipping limit
31-27 R/W Reserved

Table B-5. S3D 2D Registers (continued)

AxE4 Destination/Source Stride 19-6
11-0 R/W Source stride
15-12 R/W Reserved
27-16 R/W Destination stride
31-28 R/W Reserved
AxE8 Mono Pattern 0 19-7
31-0 R/W Mono pattern 0
AxEC Mono Pattern 1 19-7
31-0 R/W Mono pattern 1
AxF0 Mono Pattern Background Color 19-8
7-0 R/W Data 1
15-8 R/W Data 2
23-16 R/W Data 3
31-24 R/W Reserved
AxF4 Mono Pattern Foreground Color 19-9
7-0 R/W Data 1
15-8 R/W Data 2
23-16 R/W Data 3
31-24 R/W Reserved
A4F8 Source Background Color 19-10
7-0 R/W Data 1
15-8 R/W Data 2
23-16 R/W Data 3
31-24 R/W Reserved
A4FC Source Foreground Color 19-11
7-0 R/W Data 1
15-8 R/W Data 2
23-16 R/W Data 3
31-24 R/W Reserved
Ax00 Command Set 19-12
0 R/W Enable autoexecute
1 R/W Enable hardware clipping
4-2 R/W Destination color format
5 R/W Update screen with new pixel
6 R/W Mono source
7 R/W Image source data from CPU
8 R/W Mono pattern
9 R/W Transparent transfers
11-10 R/W Image transfer alignment


Ax00 Command Set (continued) 19-12
13-12 R/W First doubleword offset for image transfers
16-14 R/W Reserved
24-17 R/W Select one of 256 ROPs
25 R/W X positive BitBLT
26 R/W Y positive BitBLT
30-27 R/W 2D command
31 R/W Select 2D or 3D command
A504 Rectangle Width/Height 19-15
10-0 R/W Rectangle height
15-11 R/W Reserved
26-16 R/W Rectangle width
31-27 R/W Reserved
A508 Rectangle Source XY 19-15
10-0 R/W Rectangle source Y
15-11 R/W Reserved
26-16 R/W Rectangle source X
31-27 R/W Reserved
A50C Rectangle Destination XY 19-16
10-0 R/W Rectangle destination Y
15-11 R/W Reserved
26-16 R/W Rectangle destination X
31-27 R/W Reserved
A96C Line Draw Endpoints 19-17
15-0 R/W End 1
31-16 R/W End 2
A970 Line Draw X Delta 19-18
31-0 R/W X delta
A974 Line Draw X Start 19-18
31-0 R/W X start
A978 Line Draw Y Start 19-19
10-0 R/W Y start
31-11 R/W Reserved


A97C Line Draw Y Count 19-19
10-0 R/W Scan line count
30-11 R/W Reserved
31 R/W Drawing direction from left to right
AD68 Polygon Right X Delta 19-20
31-0 R/W Right edge X delta
AD6C Polygon Right X Start 19-20
31-0 R/W Right edge X start
AD70 Polygon Left X Delta 19-21
31-0 R/W Left edge X delta
AD74 polygon left X Start 19-21
31-0 R/W Left edge X start
AD78 Polygon Y Start 19-22
10-0 R/W Top side of the clipping rectangle
31-11 R/W Reserved
AD7C Polygon Y Count 19-22
27-11 R/W Reserved
28 R/W Update right edge
29 R/W Update left edge
31-30 R/W Reserved

Table B-6. S3D 3D Registers

BxD4 Z-Buffer Base Address 19-24
21-3 R/W Z-buffer base address
31-22 R/W Reserved
BxD8 Destination Base Address 19-24
21-3 R/W Destination base address
31-22 R/W Reserved
BxDC Left/Right Clipping 19-25
10-0 R/W Left clipping limit
15-11 R/W Reserved
26-16 R/W Right clipping limit
31-27 R/W Reserved
BxE0 Top/Bottom Clipping 19-25
10-0 R/W Bottom clipping limit
15-11 R/W Reserved
26-16 R/W Top clipping limit
31-27 R/W Reserved
BxE4 Destination/Source Stride 19-26
11-0 R/W Source stride
15-12 R/W Reserved
27-16 R/W Destination stride
31-28 R/W Reserved
BxE8 Z-Stride 19-26
11-0 R/W Z stride
31-12 R/W Reserved
BxEC Texture Base Address 19-27
21-3 R/W Texture base address
31-22 R/W Reserved
B4F0 Texture Border Color 19-27
7-0 R/W Blue color index
15-8 R/W Green color index
23-16 R/W Red color index
31-24 R/W Reserved


BxF4 Fog Color 19-28
31-24 R/W Reserved
B4F8 Color0 19-29
31-24 R/W Reserved
B4FC Color1 19-29
7-0 R/W Data 1
15-8 R/W Data 2
23-16 R/W Data 3
31-24 R/W Reserved
Bx00 Command Set 19-30
0 R/W Enable autoexecute
1 R/W Enable hardware clipping
4-2 R/W Destination color format
7-5 R/W Texel color format
11-8 R/W MIPMAP level size
14-12 R/W Texture filtering mode
16-15 R/W Texture blending mode
17 R/W Enable fogging
19-18 R/W Alpha blending control
22-20 R/W Z-buffer compare mode
23 R/W Update z-buffer
25-24 R/W Z-buffering mode
26 R/W Enable texture wrapping
30-27 R/W 3D command
31 R/W Select 2D or 3D command


B144 3D Line Draw GB Delta 19-33
15-0 R/W Blue delta
31-16 R/W Green delta
B148 3D Line Draw AR Delta 19-33
15-0 R/W Red delta
31-16 R/W Alpha delta
B14C 3D Line Draw GB Start 19-34
15-0 R/W Blue start
31-16 R/W Green start
B150 3D Line Draw AR Start 19-34
15-0 R/W Red start
31-16 R/W Alpha start
B158 3D Line Draw Z Delta 19-35
31-0 R/W Z delta
B15C 3D Line Draw Z Start 19-35
31-0 R/W Z start
B16C 3D Line Draw Endpoints 19-36
15-0 R/W End 1
31-16 R/W End 2
B170 3D Line Draw X Delta 19-36
31-0 R/W X delta
B174 3D Line Draw X Start 19-37
31-0 R/W X start
B178 3d Line Draw Y Start 19-37
10-0 R/W Y start
31-11 R/W Reserved
B17C 3d Line Draw Y Count 19-38
30-11 R/W Reserved
31 R/W Drawing direction is left to right


B504 Triangle Base V 19-38
19-0 R/W Base V
31-20 R/W Reserved
B508 Triangle Base U 19-39
19-0 R/W Base U
31-20 R/W Reserved
B50C Triangle WX Delta 19-39
31-0 R/W WX delta
B510 Triangle WY Delta 19-40
31-0 R/W WY delta
B514 Triangle W Start 19-40
31-0 R/W W start
B518 Triangle DX Delta 19-41
31-0 R/W DX delta
B51C Triangle VX Delta 19-41
31-0 R/W VX delta
B520 Triangle UX Delta 19-42
31-0 R/W UX delta
B524 Triangle DY Delta 19-42
31-0 R/W DY delta
B528 Triangle VY Delta 19-43
31-0 R/W VY delta
B52C Triangle UY Delta 19-43
31-0 R/W UY delta
B530 Triangle D Start 19-44
31-0 R/W D start
B534 Triangle V Start 19-44
31-0 R/W V start
B538 Triangle U Start 19-45
31-0 R/W U start
B53C Triangle GBX Delta 19-45
15-0 R/W Blue X delta
31-16 R/W Green X delta
B540 Triangle ARX Delta 19-46
15-0 R/W Red X delta
31-16 R/W Alpha X delta


B544 Triangle GBY Delta 19-46
15-0 R/W Blue Y delta
31-16 R/W Green Y delta
B548 Triangle ARY Delta 19-47
15-0 R/W Red Y delta
31-16 R/W Alpha Y delta
B54C Triangle GB Start 19-47
15-0 R/W Blue start
31-16 R/W Green start
B550 Triangle AR Start 19-48
15-0 R/W Red start
31-16 R/W Alpha start
B554 Triangle ZX Delta 19-48
31-0 R/W ZX delta
B558 Triangle ZY Delta 19-49
31-0 R/W ZY delta
B55C Triangle Z Start 19-49
31-0 R/W Z start
B560 Triangle XY12 Delta 19-50
31-0 R/W XY12 delta
B564 Triangle X12 End 19-50
31-0 R/W X12 end
31-0 R/W XY01 delta
B56C Triangle X01 End 19-51
31-0 R/W X01 end
31-0 R/W XY02 delta
B574 Triangle X Start 19-52
31-0 R/W X start
B578 Triangle Y Start 19-53
31-0 R/W Y start
B57C Triangle Y Count 19-53
10-0 R/W Scan line count 12
15-11 R/W Reserved
26-16 R/W Scan line count 01
30-27 R/W Reserved
31 R/W Render the triangle from right to left

B.5 STREAMS PROCESSOR REGISTERS
Table B-7. Streams Processor Registers

8180 Primary Stream Control 20-2
23-0 R/W Reserved
26-24 R/W Primary stream input data format
27 R/W Reserved
30-28 R/W Primary stream horizontal filter characteristics
31 R/W Reserved
8184 Color/Chroma Key Control 20-3
7-0 R/W B/V/Cr key value (lower bound for chroma)
15-8 R/W G/U/Cb key value (lower bound for chroma)
23-16 R/W R/Y key value (lower bound for chroma)
26-24 R/W RGB color comparison precision
27 R/W Reserved
28 R/W Color key control (full compare or bit 16 of 1.5.5.5)
31-29 R/W Reserved
8190 Secondary Stream Control 20-4
11-0 R/W DDA horizontal accumulator initial value
23-12 R/W Reserved
26-24 R/W Secondary stream input data format
27 R/W Reserved
30-28 R/W Secondary stream horizontal filter characteristics
31 R/W Reserved
8194 Chroma Key Upper Bound 20-5
7-0 R/W V/Cr key value (upper bound)
15-8 R/W U/Cb key value (upper bound)
23-16 R/W Y key value (upper bound)
31-24 R/W Reserved
8198 Secondary Stream Stretch/Filter Constants 20-5
10-0 R/W K1 horizontal scale factor
15-11 R/W Reserved
26-16 R/W K2 horizontal scale factor
31-27 R/W Reserved

Table B-7. Streams Processor Registers (continued)

81A0 Blend Control 20-6
1-0 R/W Reserved
4-2 R/W Secondary stream blend coefficient
9-5 R/W Reserved
12-10 R/W Primary stream blend coefficient
23-13 R/W Reserved
26-24 R/W Compose mode
31-27 R/W Reserved
81C0 Primary Stream Frame Buffer Address 0 20-7
21-0 R/W Primary stream frame buffer starting address 0
31-22 R/W Reserved
81C4 Primary Stream Frame Buffer Address 1 20-7
21-0 R/W Primary stream frame buffer starting address 1
31-22 R/W Reserved
81C8 Primary Stream Stride 20-8
11-0 R/W Primary stream stride
31-12 R/W Reserved
81CC Double Buffer/LPB Support 20-8
0 R/W Select primary frame buffer address 1
2-1 R/W Select secondary frame buffer address
3 R/W Reserved
4 R/W Select LPB frame buffer start address 1
5 R/W LPB input buffer select loading at end of frame
6 R//w Selected LPB input buffer toggles at end of frame
31-7 R/W Reserved
81D0 Secondary Stream Frame Buffer Address 0 20-10
21-0 R/W Secondary stream frame buffer starting address 0
31-22 R/W Reserved
81D4 Secondary Stream Frame Buffer Address 1 20-10
21-0 R/W Secondary stream frame buffer starting address 1
31-22 R/W Reserved
81D8 Secondary Stream Stride 20-11
11-0 R/W Secondary stream stride
31-12 R/W Reserved


81DC Blend Control 20-11
2-0 R/W Reserved
12-3 R/W Pixel stop fetch position
18-13 R/W Reserved
28-19 R/W Pixel start fetch position
29 R/W Reserved
30 R/W Primary stream on top
31 R/W Enable opaque overlay control
81E0 K1 Vertical Scale Factor 20-12
10-0 R/W K1 vertical scale factor
31-11 R/W Reserved
81E4 K2 Vertical Scale Factor 20-13
10-0 R/W K2 vertical scale factor
31-11 R/W Reserved
81E8 DDA Vertical Accumulator Initial Value 20-13
11-0 R/W DDA vertical accumulator initial value
31-12 R/W Reserved
81EC Streams FIFO Control 20-14
17-0 R/W Reserved
18 R/W Specify memory size for LPB memory cycles
19 R/W Do not tri-state PD[63:16] during ROM cycles
20 R/W Disable memory arbitration for ROM cycles
21 R/W Do not delay PD output
31-22 R/W Reserved
81F0 Primary Stream Window Start Coordinates 20-15
10-0 R/W Primary stream Y start
15-11 R/W Reserved
26-16 R/W Primary stream X start
31-27 R/W Reserved
81F4 Primary Stream Window Size 20-15
10-0 R/W Primary stream height
15-11 R/W Reserved
26-16 R/W Primary stream width
31-27 R/W Reserved
81F8 Secondary Stream Window Start Coordinates 20-16
10-0 R/W Secondary stream Y start
15-11 R/W Reserved
26-16 R/W Secondary stream X start
31-27 R/W Reserved


81FC Secondary Stream Window Size 20-16
10-0 R/W Secondary stream height
15-11 R/W Reserved
26-16 R/W Secondary stream width
31-27 R/W Reserved

B.6 MEMORY PORT CONTROLLER REGISTERS
Table B-8. Memory Port Controller Registers

8200 FIFO Control 21-2
4-0 R/W Primary/secondary stream FIFO boundary
5 R/W Reserved
10-6 R/W Secondary stream threshold
11 R/W Reserved
16-12 R/W Primary stream threshold
31-17 R/W Reserved
8204 MIU Control 21-3
0 R/W RAS inactive at end of cycle or start of next cycle
1 R/W RAS pre-charge = 1.5 MCLKs
2 R/W RAS low time = 2.5 MCLKs
6-3 R/W Reserved
7 R/W CAS/OE timing adjustment
8 R/W WE delay
9 R/W Stream Processor low priority request servicing
10 R/W Delay RAS rising edge by 1/2 MCLK
31-11 R/W Reserved
8208 Streams Timeout 21-3
7-0 R/W Secondary stream timeout
15-8 R/W Primary stream timeout
16 R/W Secondary stream wins memory arbitration in case of a tie
31-17 R/W Reserved
820C Miscellaneous Timeout 21-5
7-0 R/W CPU timeout
15-8 R/W S3D Engine Timeout
23-16 R/W LPB Timeout
31-24 R/W External memory master timeout
8220 DMA Read Base Address 21-6
22-3 R/W DMA read base address
31-23 R/W Reserved

Table B-8. Memory Port Controller Registers (continued)

8224 DMA Read Stride/Width 21-6
1-0 R/W Address tiling control
2 R/W Reserved = 0
11-3 R/W DMA read stride
15-12 R/W Reserved
27-19 R/W DMA read width
31-28 R/W Reserved

B.7 MISCELLANEOUS REGISTERS
Table B-9. Miscellaneous Registers

8504 Subsystem Status 22-1
0 R Vertical sync interrupt generated
1 R S3D Engine interrupt generated
2 R Command FIFO overflow interrupt generated
3 R Command FIFO empty interrupt generated
4 R Host DMA done interrupt generated
5 R Command DMA done interrupt generated
6 R S3D FIFO empty interrupt generated
7 R LPB interrupt generated
12-8 R S3D FIFO slots free
13 R S3D Engine idle
31-14 R Reserved
8504 Subsystem Control 22-2
0 W Vertical sync interrupt cleared
1 W S3D Engine interrupt cleared
2 W Command FIFO overflow interrupt cleared
3 W Command FIFO empty interrupt cleared
4 W Host DMA done interrupt cleared
5 W Command DMA done interrupt cleared
6 W S3D FIFO empty interrupt cleared
7 W Host DMA done interrupt enabled
8 W Vertical sync interrupt enabled
9 W S3D Engine interrupt enabled
10 W Command FIFO overflow interrupt enabled
11 W Command FIFO empty interrupt enabled
12 W Command DMA done interrupt enabled
13 W S3D FIFO empty interrupt enabled
15-14 W S3D Engine software reset select
31-16 W Reserved
850C Advanced Function Control 22-4
0 R/W Enable accelerated modes (enhanced and VESA non-planar)
3-1 R/W Reserved
4 R/W Enable linear addressing
5 R/W Reserved
9-6 R BIU FIFO Status
31-10 R/W Reserved

B.8 DMA REGISTERS
Table B-10. DMA Registers

8580 23-2
0 R/W Reserved
1 R/W Video DMA write
31-2 R/W DMA starting memory address
8584 Video DMA Transfer Length 23-3
1-0 R/W Reserved
23-2 R/W DMA transfer length
31-24 R/W Reserved
8588 Video DMA Transfer Length 23-3
0 R/W Enable video/graphics DMA
31-1 R/W Reserved
8590 Command DMA Base Address 23-4
0 R/W Reserved
1 R/W Specify 4/64 KByte buffer size
11-2 R/W Reserved
31-12 R/W Command DMA buffer base address
8594 Command DMA Write Pointer 23-5
1-0 RW Reserved
15-2 R/W Write pointer
16 R/W Write pointer updated
31-17 R/W Reserved
8598 DMA Read Pointer 23-5
1-0 R/W Reserved
15-2 R/W Read pointer
31-16 R/W Reserved
859C Command DMA Enable 23-6
0 RW Enable Command DMA
31-1 R/W Reserved

B.9 LPB REGISTERS
Table B-11. LPB Registers

FF00 LPB Mode 24-2
0 R/W Enable LPB
3-1 R/W LPB mode
4 R/W Reset LPB
5 R/W Write every other received frame to memory
6 R/W No byte swap for incoming video
8-7 R/W Reserved
9 R/W LPB vertical sync is active high
10 R/W LPB horizontal sync is active high
11 W CPU VSYNC
12 W CPU HSYNC
13 W Load base address currently pointed to
15-14 R/W Reserved
17-16 R/W Maximum compressed data bust size
20-18 R/W Reserved
22-21 R/W Video FIFO threshold
23 R/W Reserved
24 R/W LPB clock driven by LCLK
25 R/W Don’t add stride after first HSYNC
26 R/W Invert the LCLK input
30-27 R/W Reserved
31 R CFLEVEL status

Table B-11. LPB Registers (continued)

FF04 LPB FIFO Status 24-5
3-0 R LPB output FIFO status
10-4 R Reserved
11 R LPB output FIFO full
12 R LPB output FIFO empty
13 R LPB output FIFO almost empty
19-14 R Reserved
20 R LPB video FIFO 0 full
21 R LPB video FIFO 0 empty
22 R LPB video FIFO 0 almost empty
28-23 R Reserved
29 R LPB video FIFO 1 full
30 R LPB video FIFO 1 empty
31 R LPB video FIFO 1 almost empty
FF08 LPB Interrupt Flags 24-6
0 R/W LPB Output FIFO empty
1 R/W HSYNC (end of line) input on pin 202
2 R/W VSYNC (end of frame) input on pin 203
3 R/W Serial port start condition detected
15-4 R/W Reserved
16 R/W Enable LPB output FIFO empty interrupt
17 R/W Enable HSYNC (end of line) input interrupt
18 R/W Enable VSYNC (end of frame) input interrupt
19 R/W Enable serial port start condition detect interrupt
23-20 R/W Reserved
24 R/W Drive SPCLK low on receipt of a serial port start condition
31-25 R/W Reserved
FF0C LPB Frame Buffer Address 0 24-8
21-0 R/W LPB frame buffer address 0
31-22 R/W Reserved
FF10 LPB Frame Buffer Address 1 24-8
21-0 R/W LPB frame buffer address 1
31-22 R/W Reserved


FF14 LPB Direct Read/Write Address 24-9
20-0 R/W Address of MPEG decoder address to read/write
23-21 R/W MPEG decoder transaction type
31-24 R/W Reserved
FF18 LPB Direct Read/Write Data 24-9
31-0 R/W LPB direct read/write data
FF1C LPB General Purpose Input/Output Port 24-10
3-0 R/W General purpose output data port
7-4 R General purpose input data port
31-8 R/W Reserved
FF20 Serial Port 24-11
0 R/W 0 = Serial clock write on pin 205, 1 = pin 205 tri-state
1 R/W 0 = Serial data write on pin 206, 1 = pin 206 tri-state
2 R 0 = Serial clock low on pin 205, 1 = pin 205 tri-state
3 R 0 = Serial data low on pin 206, 1 = pin 206 tri-state
4 R/W Enable serial port function
5-7 R/W Reserved
8 R Bit 0 mirror (data on byte lane 2 at E2H)
31-13 R/W Reserved
FF24 LPB Video Input Window Size 24-12
11-0 R/W Video input line width
15-12 R/W Reserved
24-16 R/W Video input window height
31-25 R/W Reserved
FF28 LPB Video Data Offsets 24-13
11-0 R/W Horizontal video data offset
15-12 R/W Reserved
24-16 R/W Vertical video data offset
31-25 R/W Reserved
FF2C LPB Horizontal Decimation Control 24-14
31-0 R/W Video data byte mask
FF30 LPB Vertical Decimation Control 24-14
7-0 R Video data line mask


FF34 LPB Line Stride 24-15
11-0 R/W Line stride
31-12 R/W Reserved
FF40 LPB Output FIFO 24-15
31-0 R/W Output FIFO data

B.10 PCI CONFIGURATION SPACE REGISTERS
When a PCI configuration read or write command is issued, AD[7:0] contain the address of the register
in the configuration space to be accessed.
Table B-12. PCI Configuration Space Registers

00 Vendor ID 25-1
15-0 R Hardwired to 5333H
02 Device ID 25-2
15-0 R Hardwired to 5631H (initial stepping)
04 Command 25-2
0 R/W Response to I/O space accesses enabled
1 R/W Response to memory space accesses enabled
2 R/W Enable bus master operation
4-3 R/W Reserved
5 R/W Enable DAC snooping
15-6 R/W Reserved
06 Status 25-3
8-0 R/W Reserved
10-9 R/W Hardwired to select medium device select timing
11 R/W Reserved
12 R/W Bus master transaction terminated with target-abort
13 R/W Bus master transaction terminated with master-abort
15-14 R/W Reserved
08 Class Code 25-3
31-0 R Hardwired to indicate VGA-compatible display controller
0D Latency Timer 25-4
7-0 R/W Reserved
10-8 R/W Reserved = 0 (3 LSBs of latency timer)
15-11 R/W Bus master latency timer
10 Base Address 0 25-4
0 R/W Hardwired to indicate base registers map into memory space
2-1 R/W Hardwired to allow mapping anywhere in 32-bit address space
3 R/W Hardwired to indicate does not meet prefetchable requirements
22-4 R/W Reserved
31-23 R/W Base address 0
30 BIOS Base Address 25-5
0 R/W Enable access to BIOS ROM address space
15-1 R/W Reserved
31-16 R/W Upper 16 bits of BIOS ROM address

Table B-12. PCI Configuration Space Registers (continued)

3C Interrupt Line 25-3
7-0 R/W Interrupt line routing information
3D Interrupt Pin 25-6
7-0 R Hardwired to specify use of INTA
3E Latency/Grant 25-6
7-0 R/W Minimum grant
15-8 R/W Maximum latency

Index
2D line draw programming 15-18 bus master DMA

2D polygon fill programming 15-21 programming 15-33
3D color generation 15-26 bus master enable 25-2
3D line draw programming 15-23 byte mode addressing 16-23
3D triangle programming 15-23
C
A
CAS
address latch delay 18-20 adjust timing 7-1, 18-26, 21-3
address tiling 21-6 character clock
alpha blending 15-30 dot clocks per 16-6
select type 19-31 chip ID 13-4, 18-1 - 18-2
alpha4/blend4 15-29 chip wakeup 13-1
autoexecute 15-6 chroma keying 10-8, 20-3, 20-5
2D 19-12 enable 20-3
3D 19-30 clipping 15-6
2D 19-5 - 19-6
B 3D 19-25
enable (2D) 19-12
base address enable (3D) 19-30
command DMA buffer 23-4 clock generator
destination (2D) 19-5 DC specifications 4-1
destination (3D) 19-24 frequency synthesis 9-1
DMA read 21-6 new DCLK PLL load 17-8
source 19-4 new MCLK and DCLK PLL load 17-9
texture 19-27 new MCLK PLL load 17-8
z-buffer 19-24 color compare
BIOS VGA 16-27, 16-31
See video BIOS color keying 10-8, 20-3
BitBLT enable 20-3
destination location 19-16 in KRGB mode 20-3
drawing direction 19-14 color mode select 17-3
programming 15-7 color pattern registers 19-3
rectangle dimensions 19-15 color pattern select 19-13
source location 19-15 color space conversion 10-5
blank/border select 18-4 command
blend4 15-29 2D (specify) 19-14
color limits 19-29 3D (specify) 19-32
blending 10-7, 20-6 command FIFO status 22-5
border color 15-29 command set register
INDEX I-1
2D 19-12 command DMA control 23-5

3D 19-30 control 23-2
complex reflection 15-29, 19-31 programming 15-33
configuration strapping 18-7 read stride 21-7
at reset 5-3 reset read DMA pointers 22-4
unlocking access to registers 18-9 transfers 15-33
DMA 23-3 doubleword mode addressing 16-20, 18-3
CPU base address draw enable 19-12
enable 18-2
specify 18-28 E
cursor
end 16-16 EDO memory 7-1
location address 16-17 1-cycle support 7-6
start 16-16 2-cycle support 7-1
cursor location address 16-17 EDO memory (1-cycle) 18-7
enable
D chroma keying 20-3
clipping (2D) 19-12
DCLK clipping (3D) 19-30
control 9-3 color keying 20-3
halving 16-6, 17-9 Enhanced mode 22-4
invert 17-9 feature connector 17-4
inverted 18-4 fogging 19-31
loading new frequency 9-2, 17-8 - 17-9 hardware graphics cursor 18-13
programming 9-2, 17-6 linear addressing 18-20, 22-4
testing 9-3, 17-7 LPB 24-2
decal 15-29, 19-31 memory mapped I/O 18-17
decimation 11-9, 24-14 PCI bus master operation 25-2
destination base address pixel drawing (2D) 19-12
2D 19-5 texture wrapping 19-32
3D 19-24 ViRGE 18-8
destination color format end horizontal blank 16-12
2D 19-12 end horizontal sync position 16-13
3D 19-30 end vertical blank 16-21
DEVSEL timing 6-1 ENFEAT 17-4
digitizer interface 11-7 Enhanced mode
display active status 16-3 enable 15-3, 22-4
display FIFO fetch enable 8 bpp or greater 18-10
enable 18-5 memory mapping 18-3
specify start position 18-10 programming 15-5
display memory ESYNC 17-4
2 MCLK writes 17-2, 17-9 EVCLK 17-4, 17-9
access control 7-8, 21-3 extended data out (EDO) memory 7-1
address tiling 7-8
chip count limitation 7-1 F
configurations 7-1
refresh 7-1 feature connector
refresh cycle control 7-1, 16-19 AC timing 4-8
size specification 5-1, 18-7 enable 3-8, 17-4
display pitch 16-20 interfaces 12-7
display start address 18-27 LPB 12-7
DMA Trio64-type versus LPB 17-4
Command DMA buffer size 23-4
I-2 INDEX
FIFO status I
command FIFO 22-5
S3d Engine FIFO 22-2 I square C
filtering textures 15-27 See serial port
fogging 15-30 ID, chip 18-1 - 18-2
enable 19-31 image transfer
font selection 16-8 alignment 19-13
frame buffer data source 19-13
See display memory first doubleword select 19-14
mono or color source 19-12
G initialization 5-1
interlaced operation 18-11 - 18-12
General Data bus interrupt
BIOS ROM interface 12-2 command DMA done interrupt clear 22-3
general input port 16-39 command DMA done interrupt enable 22-3
description 12-4 command DMA done interrupt status 22-2
enable 12-4, 18-19 command FIFO empty interrupt clear 22-3
general output port 18-22 command FIFO empty interrupt enable 22-3
description 12-5 command FIFO empty interrupt status 22-1
LPB 24-10 command FIFO overflow interrupt enable 22-
Gouraud shading 19-32 3
green PC command FIFO overflow interrupt status 22-
HSYNC/VSYNC control 12-4, 17-4 1
commandFIFO overflow interrupt clear 22-3
H enable 12-9, 18-3
generation 12-9
hardware graphics cursor host DMA done interrupt clear 22-3
background color 18-15 host DMA done interrupt enable 22-3
enable 18-13 host DMA done interrupt status 22-2
foreground color 18-14 LPB 24-6
pattern display x origin 18-15 S3d Engine done interrupt status 22-1
pattern display y origin 18-16 S3d Engine interrupt clear 22-3
programming 15-31 - 15-32 S3d Engine interrupt enable 22-3
storage start address 18-15 S3d FIFO empty interrupt clear 22-3
Windows/X-Windows modes 15-31, 18-19 S3d FIFO empty interrupt enable 22-3
x origin 18-14 S3d FIFO empty interrupt status 22-2
y origin 18-14 vertical retrace interrupt clear 16-18
high speed text display 18-3 vertical retrace interrupt enable 16-18
high speed text font writing 18-10 vertical retrace interrupt status 16-3
horizontal blank vertical sync interrupt clear 22-2
end 16-12 vertical sync interrupt enable 22-3
start 16-12 vertical sync interrupt status 22-1
horizontal display end 16-11
horizontal sync L
control for power management 17-4
polarity 16-2 latency timer 25-4
horizontal sync position LCLK
end 16-13 invert 24-4
start 16-13 lighting textures 15-29
horizontal total 16-11 line compare 16-23
HSYNC line draw
direction control 3-8 drawing direction 19-19
endpoints 19-17
INDEX I-3
scan line count 19-19 Enhanced/VGA modes 18-3

x delta 19-18 mipmap 15-28
x start 19-18 level size 19-31
y start 19-19 MMIO
line draw programming 15-18, 15-23 See memory mapped I/O
linear addressing modulate 15-29, 19-31
enable 15-3, 18-20, 22-4 mono pattern
explained 15-3 - 15-4 background color 19-8
window position 18-21, 25-5 foreground color 19-9
window size 18-20 registers 19-7
Local Peripheral Bus select 19-13
See LBP MUX buffering 15-26
LPB
burst size 24-3 N
clock source 24-4
color byte swap 24-3 n parameter
decimation 11-9, 24-14 See also PLL n parameter
digitizer interface 11-7 nibble swap 18-18
enable 24-2
frame buffer address 24-8 O
general output port 24-10
input window size 24-12 OE
interrupts 24-6 adjust timing 7-1, 18-26, 21-3
introduction 11-1 control 3-7
line stride 24-15 offset 16-20
mode select 24-2 ordering
output FIFO 24-5, 24-15 reads 15-4
read/write registers 24-9 write 15-4
reset 24-2
Scenic/MX2 interface 11-2 P
skip frames 24-2
sync polarity 24-3 palette registers 16-33
video FIFO 24-3, 24-5 lock access 18-4
LUT write cycle control 17-11 panning 16-15, 16-34, 16-36
pass-through 11-9
M pattern registers
color 19-3
m parameter mono 19-7
See also PLL m parameter PCI Bus
master abort 25-3 BIOS ROM access enable 25-5
maximum scan line 16-15 BIOS ROM base address 25-5
MCLK bus master enable 25-2
external output 17-8 bus master latency timer 25-4
loading new frequency 9-3, 17-8 - 17-9 configuration 6-1
programming 9-3, 17-5 device I.D. 6-1
testing 9-3, 17-7 DEVSEL timing 6-1
mechanical dimensions 2-1 disable read bursts 18-10
memory enable disconnect 18-25
See display memory enable I/O accesses 25-2
memory mapped I/O enable memory accesses 25-2
enable 18-17 interface 6-1
MMIO only select 17-2 linear addressing base address 25-5
memory mapping
I-4 INDEX
master abort handling during DAC cycles accessing 8-3

8-3, 18-5 bus snooping 8-3
maximum latency 25-6 clock doubled operation 8-2, 17-11
minimum grant 25-6 color mode select 18-26
RAMDAC snoop method 18-5 color modes 8-1 - 8-2
received master abort 25-3 DC characteristics 4-1
received target abort 25-3 DC specifications 4-1
retry handling during DAC cycles 8-3, 18-5 disable LOCA/SRDY 18-8
vendor I.D. 6-1 lock writes 18-4
perspective correction 19-32 LUT write cycle control 17-11
pin 50 function select 17-2 PCI bus snooping 18-5
pin descriptions 3-4 - 3-7, 3-10 power down 17-11
pin list sense generation 8-3
alphabetical 3-12 - 3-14 signature analysis 8-3
numerical 3-15 - 3-16, 3-18 RAS
pitch 16-20 delay rising edge 21-3
PLL M parameter 9-1, 17-5 - 17-6 inactive control 21-3
PLL N parameter 9-1, 17-5 - 17-6 low time select 7-1, 18-27, 21-3
PLL R parameter 9-1, 17-5 - 17-6 precharge time select 7-1, 21-3
polygon draw RAS1 function 3-7, 7-1
left edge x delta 19-21 RDYIN 6-2 - 6-4
left edge x start 19-21 read ordering 15-4
right edge x delta 19-20 real mode 15-3
right edge x start 19-20 rectangle fill programming 15-17
scan line count 19-22 refresh, DRAM 7-1, 16-19, 18-9
specify edge to update 19-23 reset
y start 19-22 LPB 24-2
polygon fill programming 15-21 read DMA pointers 22-4
power management S3d Engine 22-4
HSYNC control 12-4, 17-4 system 5-1
VSYNC control 12-4, 17-4 revision status 18-1 - 18-2
programming 15-5 ROP
programming examples list of A-1
2D line draw 15-18 select 19-14
2D polygon fill 15-21 ROPBLT A-1
3D triangle 15-23 row scan count 16-15
BitBLT 15-7
hardware cursor 15-31 S
notational conventions 15-5
rectangle fill 15-17 S3d Engine
protected mode 15-3 enable 22-4
FIFO slots free 22-2
Q idle status 22-2
register mapping 19-1 - 19-2
quadword mode addressing 16-20 software reset 22-4
scaling 10-5
R Scenic Highway 11-1
screen off 16-7
R parameter SENSE
See PLL R parameter status of internal signal 16-3
RAMDAC
AC specifications 4-3
access 16-38 - 16-40
INDEX I-5
serial port 11-7 blend4 15-29

add wait states 24-7 border color 15-29, 19-27
addressing 18-30 complex reflection 15-29, 19-31
register 24-11 decal 15-29, 19-31
signature analysis 8-3 filter mode 19-31
source background color 19-10 - 19-11 filtering 15-27
source base address 19-4 lighting 15-29
SRDY mipmap 15-28
delay assertion 18-11 modulate 15-29, 19-31
generation 6-2 texel color format 19-30
start address 16-17 wrapping 15-29
start horizontal blank 16-12 texture wrapping
start horizontal sync position 16-13 enable 19-32
start vertical blank 16-21 tiling
stepping information 18-1 - 18-2 address 21-6
streams processor timeout counters 21-4 - 21-5
blending 10-7, 20-6 transparency
chroma keying 20-5 See alpha blending
color space conversion 10-5 transparent bit 19-13
color/chroma keying 10-8, 20-3 tri-state off
compose modes 10-6, 20-6 HSYNC 18-19
double buffering 10-3, 20-7 - 20-8 PA[15:0] 18-25
FIFO control 10-8, 21-2 - 21-3 PD lines 17-2
filter characteristics 20-2, 20-4 VCLK 18-19
filter constants 20-5 VSYNC 18-19
input data formats 20-2, 20-4 triangle programming 15-23
introduction 10-1
mode select 18-26 U
opaque overlay 10-7, 20-11
primary stream input 10-2 underline location 16-20
primary stream stride 20-8 unlocking
primary stream window 20-15 configuration strapping registers 18-9
scaling 10-5, 20-12 - 20-13 Enhanced registers 18-11
secondary stream input 10-2 extended sequencer registers 17-1
secondary stream stride 20-11 pseudocode for 13-1
secondary stream window 20-16 S3 VGA registers 18-9
timeout counters 21-4 system control/extension registers 18-9
stride
DMA read 21-7 V
source and destination (2D rendering) 19-6
source and destination (3D) 19-26 VCLK
z-buffer 19-26 direction 17-9
STWR inversion of DCLK 18-4
function select 17-8 phase with respect to DCLK 18-25
super VGA support 14-2 VCLKI 3-8, 17-3
vertical blank
T end 16-21
start 16-21
target abort 25-3 vertical display end 16-19
test load, AC 4-7 vertical retrace
texel color format 19-30 enable interrupt 16-18
texture end 16-18
base address 19-27 start 16-18
I-6 INDEX
vertical sync stride 19-26

active status 16-3 using MUX buffering 15-26
control for power management 17-4
polarity 16-2
vertical total 16-14
VGA compatibility 14-1, 16-1
VGA graphics mode select 16-34
VGA memory bus width 18-3
VGA memory mapping 18-3 - 18-4
video BIOS
access enable (PCI) 12-1, 25-5
base address (PCI) 12-4, 25-5
enable access 12-1
enable accesses 18-7
read functional timing 12-2
ROM interface 12-1
size selection 12-4, 18-8
video display enable 16-32
VL-Bus
address latch delay 6-3 - 6-4, 18-20
cycles 6-2
delay assertion of SRDY 6-2, 6-4, 18-11
interface 6-1
RDYIN 6-3 - 6-4
RDYIN input 6-2
SRDY generation 6-2
write latching delay 6-2
VLKLI 17-3
VSYNC
direction control 3-8
wait state control 18-11

wakeup 13-1
WE
delay 7-5, 18-30
trailing edge delay 21-3
word mode addressing 16-20, 16-22 - 16-23
write ordering 15-4
X-Windows 15-31, 18-19
z-buffering
base address 19-24
buffer update enable 19-32
programming 15-25
select compare mode 19-31
select mode 19-32
INDEX I-7
S3 Incorporated, P.O. Box 58058, Santa Clara, CA 95052-8058 Tel: 408-980-5400, Fax: 408-980-5444
Printed in USA DB019-B

DB019-B ViRGE Integrated 3D Accelerator Aug1996

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ViRGE Integrated 3D Accelerator

The following notational conventions are used in this data book:

When k is used, it refers to decimal 1000.

Additional information may be obtained from:

S3 Incorporated, Literature Department, P.O. Box 58058, Santa Clara, CA 95052-8058.

Telephone: 408-980-5400, Fax: 408-980-5444

Table of Figures . . . . . . . . . . vi Section 7: Display Memory . . . . 7-1

Section 16: VGA Standard Register Appendix A: Listing of Raster

Section 20: Streams Processor

Section 21: Memory Port Controller

Section 22: Miscellaneous

Section 23: DMA Register

Section 24: Local Peripheral Bus

Section 25: PCI Register

# Title Page # Title Page

# Title Page # Title Page

High-Performance Integrated DRAM-based • Support for Indeo, Cinepak, and soft-

Multimedia Support Hooks video as a texture map. These features provide

The S3® ViRGE integrated 3D video/graphics 1.4 S3 Scenic Highway

The S3d Engine provides 2D acceleration for

The S3d Engine incorporates the key Windows

1.5 VIDEO RESOLUTIONS

Table 1-1. Video Resolutions Supported

* 4 bits/pixel modes are not accelerated and use

Section 2: Mechanical Data

2.1 THERMAL SPECIFICATIONS

Parameter Min Typ Max Unit

2.2 MECHANICAL DIMENSIONS

MECHANICAL DATA 2-1

30.60 SQUARE (BASIC)

156 28.0 SQUARE (BASIC)

0.50 (BASIC) 0.22±0.05

COPLANARITY = 0.08 MAX

Figure 2-1. 208-pin PQFP Mechanical Dimensions

2-2 MECHANICAL DATA

3.1 PINOUT DIAGRAMS

Figure 3-1. PCI Bus Pinout

Figure 3-2. VL-Bus Pinout

3.2 PIN DESCRIPTIONS

Table 3-1. Pin Descriptions

Symbol Type Pin Number(s) Description

SD[31:0] B (VL) System Data Bus.

SBE[3:0] I (VL) Data Byte Enables.

SCLK I (VL) CPU System Clock

SINTR (VL) Interrupt Request.

Table 3-1. Pin Descriptions

Symbol Type Pin Number(s) Description

RDYIN I (VL) Local Bus Cycle End Acknowledge. ViRGE holds

SRDY O (VL) Local Bus Cycle End.

LOCA O (VL) Local Bus Access Cycle Indicator. This signal is

SM/IO I (VL) Memory/I/O Cycle Indicator. This signal is high for

SRESET (VL) System Reset.

SADS I (VL) System Address Strobe.

SW/R I (VL) Write/Read Cycle Indicator. This signal is high for

Table 3-1. Pin Descriptions

Symbol Type Pin Number(s) Description

SAUP1 I (VL) Upper Address Decode 1. In conjunction with

Table 3-1. Pin Descriptions

Symbol Type Pin Number(s) Description

Table 3-1. Pin Descriptions