5 4 3 2 1

Table of Contents Rev Date Revision History

Page Sheet Name
X1 11 JAN 2019 Initial revision
01 Title, ToC and Rev History
A 01 APR 2019 Agile release
D 02 Notes D

03 BCC
B 23 JAN 2020 - added inductor in parallel with the antenna
04 MCU - added protection on J19 and J21
- changed MCU to S32K144
05 SBC - BOM optimisation
06 AUTHENTICATION
B1 22 MAY 2020 - JPI CHANGED TO DNP
07 NFC - J20 CHANGED TO POP
08 SWITCH - J6 CHANGED TO CLOSED
- ADDED ALTERNATE PART NUMBER FOR J4&J5
09 OVERCURRENT
C C

RDDRONE-BMS772
B B

6501 W illiam Cannon Drive W est

Austin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,
procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
A A
ICAP Classification: CP: ____ IUO: X PUBI: ____
Designer: Drawing Title:
Ovidiu Leonte
RDDRONE-BMS772
Drawn by: Page Title:
Ovidiu Leonte Title, ToC and Rev History
Approved: Size Document Number Rev
Philippe Perruchoud B SCH45742 - SPF45742 B1

Date: Friday, May 22, 2020 Sheet 1 of 9

5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

DO NOT POPULATE
REF DES
C34,C49,C12,C99,C106,C54,C6,
ASSY_OPT PAGE NAME DEFAULT JUMPER 6501 W illiam Cannon Drive W est
DNP 03 - BCC Austin, TX 78735-8598
C105,C103,C29,C26,C107,C22, This document contains information proprietary to NXP and shall not be used for engineering design,
procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
A C104,C18,C101,C100,JP1,C102 REF DES JUMPER PAGE NAME A
ICAP Classification: CP: ____ IUO: X PUBI: ____
J21 DNP 04 - MCU SJ8,SJ1,SJ2,SJ6,SJ7,SJ10,SJ4, OPEN 03 - BCC Designer: Drawing Title:

R49,C66,R50,J22 DNP 05 - SBC SJ12,SJ3,SJ11,SJ9,SJ5 Ovidiu Leonte

RDDRONE-BMS772
L2 DNP 07 - NFC J6 CLOSED 05 - SBC Drawn by:
Ovidiu Leonte
Page Title:
Notes
HS2,Q3,Q7,R99,Q8,Q4,J5,HS3, DNP 08 - SWITCH SJ15,SJ16 OPEN 07 - NFC
Approved: Size Document Number Rev
HS4,J4,HS1 SJ13,SJ14 CLOSED 08 - SWITCH Philippe Perruchoud B SCH45742 - SPF45742 B1

Date: Friday, May 22, 2020 Sheet 2 of 9

5 4 3 2 1
 5 4 3 2 1

BCC Power Supply

VBAT_IN
Balancing Circuit Battery Cell Controller
BCC

A
D12 VPWR VCOM VCC_3V3_SBC
PMEG3050EP C8
0.1uF
*)
C7

C
R2 6.8
2.2uF C10

C
C1 0.1uF
*)
SPI Interface

3
0.047uF ZD1
D2 BOM note: BCC_MISO
BAS40LT1G fail-safe capacitor BCC_CS

A
D D

NC
BCC_SCLK
Optional/EMC BCC_MOSI

1
Cell voltage measurement
BP-C6P R3 68 CB_6 GPIO0

BP-C6P BP-C6P R5 3.0K R6 2.00k CT_6 C99

220PF
SJ1 C5 C6 DNP

36

35

34

33

32

31

30

29

28

27

26

25
1 2 BP-C6P 0.047uF U1
OPEN
0.1uF
DNP
*)

AN0/GPIO0

RDTX_OUT_P

SI/RDTX_IN_P

CS

VDDIO

SO

SCL

SDA
SCLK/RDTX_IN_N

RDTX_OUT_N

CGND

VCOM
BP-C5P R96 16Ohms CB_6:5_C
SJ2
*)
1 2 BP-C5P C100
OPEN BP-C5P R9 3.0K R10 2.00k CT_5 220PF R19 Optional
DNP
C14 C12 *) R19 10.0K
0.1uF 0.047uF
SJ3 DNP R12 68 CB_5 GPIO1 37
1 2 BP-C6P AN1/GPIO1 24
OPEN
*) C101 GPIO2 38 RESET BCC_RESET
BP-C4P 220PF AN2/GPIO2 23 SPI_EN R23 10.0K VPRE
SJ4 BP-C4P R13 3.0K R14 2.00k CT_4 DNP GPIO3 39 SPI_COM_EN
1 2 BP-C5P AN3/GPIO3 22 CT_REF
OPEN C17 C18
*) 40 CT_REF
CB_4 VSENSE_OUT AN4/GPIO4 CT_1
0.1uF 0.047uF R15 68 21
JP1 41 CT_1
SJ5 DNP
1 1 2 BP-C4P C102 AN5/GPIO5 20 CB_1
2 OPEN
*) 220PF 42 CB_1
3 DNP AN6/GPIO6 19 CB_2:1_C
4 BP-C3P R16 3.0K R17 2.00k CT_3 43 CB_2:1_C
5
*) ISENSE_P ISENSE_P 18 CB_2
6 SJ6 C21 C22 BP-C3P R97 16Ohms CB_4:3_C 44 CB_2
ISENSE_N ISENSE_N CT_2
7 1 2 BP-C6P 0.1uF 0.047uF 17
OPEN DNP C103 45 CT_2
220PF AGND 16 CT_3
C
S7B-XH-A(LF)(SN) SJ7
*) DNP 46 CT_3
C

DNP 1 2 BP-C5P DGND 15 CB_3

OPEN BP-C2P R20 3.0K R21 2.00k CT_2 *) VANA 47 CB_3
0.047uF
0.047uF
0.047uF
0.047uF
0.047uF
0.047uF
0.047uF

R22 68 CB_3 VANA 14 CB_4:3_C

SJ8 C25 C26 C37 48 CB_4:3_C
1 2 BP-C4P 0.047uF C104 GND_REF 13 CB_4
0.1uF CB_4
OPEN DNP BP-C2P 220PF 0.047uF 49
DNP GNDFLAG
C4
C13
C16
C20
C24
C28
C32

SJ9
*)
1 2 BP-C3P
*)

CB_6:5_C
CT_1 CB_2

GNDCP
BP-C1P

VPWR2

VPWR1
OPEN R24 3.0K R25 2.00k R26 68

FAULT
ESD/EMC Filter

VPRE

CB_6

CB_5
CT_6

CT_5

CT_4
VCP
C30 C29 C105
place caps close to 0.1uF 0.047uF 220PF
DNP
JP1 connector
SJ10 DNP MC33772BSP1AE

10

11

12
1 2 BP-C5P VPWR
OPEN
*) *)

CB_6:5_C
BP-C1P R98 16Ohms CB_2:1_C

VPRE
CT_REF

VCP
SJ11 BP-C1M R28 3.0K R29 2.00k

CB_6

CB_5
CT_6

CT_5

CT_4
1 2 BP-C4P C34 C106
C

OPEN C33 0.047uF 220PF C40 C41

D13 0.1uF DNP DNP 0.1uF 0.1uF

C44

C45
SJ12 PMEG3050EP *) *) *) *)
1 2 BP-C3P
OPEN LPF Filter CIN Filter BP-C1M R30 68 CB_1
A

0.47uF

0.01uF
BP-C2P C107 R90 33K
*) *)
BCC_FAULT
220PF
BP-C1P DNP
*) R89
BP-C1M 68K
VCOM VCOM

R71 R68
B B
10.0K 10.0K
Filtering Current Sensor LPF Filter *) LPF Filter *)
RT3
R31 127 R73 3.3K GPIO3 R70 3.3K GPIO2

t
Rsense_P ISENSE_P AFE_temp
C39
0.047uF C43 10K C96 C92
*) 2.2uF 1200pF 1200pF
*)
Rsense_N R32 127 ISENSE_N AFE_temp Q_temp
C47
0.047uF
Temperature sensor Temperature sensor
*) AFE transistor
VCOM VCOM

*) Place close to U1 PIN

R34 C49
Optional for EMC R33
10.0K 1200pF 10.0K

DNP
LPF Filter *) LPF Filter *)
R37 0 R38 3.3K GPIO1 R36 3.3K GPIO0
Depending on the number of cells of the battery, jumpers need to be set.
C54 C55 C51
By default, no jumpers are set. C53 1200pF 1200pF 1200pF
Refer to the table below to set the jumpers to the desired configuration. 1000pF DNP

S2
Rsense_temp
2 J1
1 SM02B-GHS-TB(LF)(SN)
Temperature sensor
sense resistor

S1
A A

Temperature sensor
battery 6501 William Cannon Drive West
Austin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,
procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.

ICAP Classification: CP: ____ IUO: X PUBI: ____

Designer: Drawing Title:
Ovidiu Leonte
RDDRONE-BMS772
Drawn by: Page Title:
Ovidiu Leonte BCC
Approved: Size Document Number Rev
Philippe Perruchoud C SCH45742 - SPF45742 B1

Date: Wednesday, June 03, 2020 Sheet 3 of 9

5 4 3 2 1
 5 4 3 2 1

TP9 TP10

1
J18
SH1
MCU C83 0.1uF

2 J2 D1 VCC_3V3_SBC
SMBUS_SCL R74 120
R75 120 3 1 2 LED_BLUE R59 22 2
SMBUS_SDA I2C/SMBUS VCC_3V3_SBC JTAG_TMS_SW D_DIO

B
4 SH2 3 4
JTAG_TCLK_SW D_CLK

2
5 6 LED_GREEN R58 330 3 1
JTAG_TDO

G
7 8

PESD0402
D9

PESD0402
D10 JTAG_TDI
CON_1X4 9 10 LED_RED R61 330 4
D RST_N D

R
HDR 2X5 155124M173200

1
VCC_3V3_SBC

10uF

0.1uF
0.1uF
0.1uF
C108
VCC_3V3_SBC

C75
C76
C77
U2

2.2K
2.2K
2.2K
2.2K

31
5

6
S32K144HAT0MLFT
19

VDD1
VDD2
VDDA
PTC1/FTM0_CH1/LPSPI2_SOUT/FTM1_CH7/ADC0_SE9 GATE_CTRL_CP
17
PTC2/FTM0_CH2/CAN0_RX/LPUART0_RX/ADC0_SE10/CMP0_IN5 GATE_CTRL_D
16
PTC3/FTM0_CH3/CAN0_TX/LPUART0_TX/ADC0_SE11/CMP0_IN4 OVERCURRENT
R54
R53
R100
R101 46
JTAG_TCLK_SW D_CLK
PTC4/FTM1_CH0/RTC_CLKOUT/EWM_IN/FTM1_QD_PHB/JTAG_TCLK/SWD_CLK/CMP0_IN2 45
PTC5/FTM2_CH0/RTC_CLKOUT/FTM2_QD_PHB/JTAG_TDI JTAG_TDI
38 40
SMBUS_SCL PTA0/FTM2_CH1/LPI2C0_SCLS/FXIO_D2/FTM2_QD_PHA/LPUART0_CTS/TRGMUX_OUT3/ADC0_SE0/CMP0_IN0
PTC6/LPUART1_RX/CAN1_RX/FTM3_CH2/FTM1_QD_PHB/ADC1_SE4 UART_RX
37 39
C SMBUS_SDA PTA1/FTM1_CH1/LPI2C0_SDAS/FXIO_D3/FTM1_QD_PHA/LPUART0_RTS/TRGMUX_OUT0/ADC0_SE1/CMP0_IN1PTC7/LPUART1_TX/CAN1_TX/FTM3_CH3/FTM1_QD_PHA/ADC1_SE5 UART_TX C
36 28
AUTH_NFC_SDA PTA2/FTM3_CH0/LPI2C0_SDA/EWM_OUT/FXIO_D4/LPUART0_RX/ADC1_SE0 PTC8/LPUART1_RX/FTM1_FLT0/LPUART0_CTS GATE_RS
35 27
AUTH_NFC_SCL PTA3/FTM3_CH1/LPI2C0_SCL/EWM_IN/FXIO_D5/LPUART0_TX/ADC1_SE1 PTC9/LPUART1_TX/FTM1_FLT1/LPUART0_RTS BCC_FAULT
48 22
JTAG_TMS_SW D_DIO PTA4/CMP0_OUT/EWM_OUT/JTAG_TMS/SWD_DIO PTC14/FTM1_CH2/LPSPI2_PCS0/TRGMUX_IN9/ADC0_SE12 SBC_W AKE
47 21
RST_N PTA5/TCLK1/RESET PTC15/FTM1_CH3/LPSPI2_SCK/TRGMUX_IN8/ADC0_SE13 AUTH_W AKE
29 20 PTC16
VCC_HARVEST PTA7/FTM0_FLT2/RTC_CLKIN/LPUART1_RTS/ADC0_SE3 PTC16/FTM1_FLT2/CAN2_RX/ADC0_SE14
44
JTAG_TDO PTA10/FTM1_CH4/FXIO_D0/JTAG_TDO/NOETM_TRACE_SWO
43
SBC_LIMP PTA11/FTM1_CH5/FXIO_D1/CMP0_RRT
42 2
NFC_HPD PTA12/FTM1_CH6/CAN1_RX/FTM2_QD_PHB PTD0/FTM0_CH2/LPSPI1_SCK/FTM2_CH0/FXIO_D0/TRGMUX_OUT1 BCC_SCLK
41 1
NFC_ED PTA13/FTM1_CH7/CAN1_TX/FTM2_QD_PHA PTD1/FTM0_CH3/LPSPI1_SIN/FTM2_CH1/FXIO_D1/TRGMUX_OUT2 BCC_MISO
34
PTD2/FTM3_CH4/LPSPI1_SOUT/FXIO_D4/FXIO_D6/TRGMUX_IN5/ADC1_SE2 BCC_MOSI
PTB0 26 33
PTB0/LPUART0_RX/LPSPI0_PCS0/LPTMR0_ALT3/CAN0_RX/ADC0_SE4/ADC1_SE14 PTD3/FTM3_CH5/LPSPI1_PCS0/FXIO_D5/FXIO_D7/TRGMUX_IN4/NMI/ADC1_SE3 BCC_CS
PTB1 25 18
PTB1/LPUART0_TX/LPSPI0_SOUT/TCLK0/CAN0_TX/ADC0_SE5/ADC1_SE15 PTD5/FTM2_CH3/LPTMR0_ALT2/FTM2_FLT1/TRGMUX_IN7 LED_BLUE BCC_RESET
24 11
SBC_SCK PTB2/FTM1_CH0/LPSPI0_SCK/FTM1_QD_PHB/TRGMUX_IN3/ADC0_SE6 PTD15/FTM0_CH0/LPSPI0_SCK LED_RED
23 10
SBC_MISO PTB3/FTM1_CH1/LPSPI0_SIN/FTM1_QD_PHA/TRGMUX_IN2/ADC0_SE7 PTD16/FTM0_CH1/LPSPI0_SIN/CMP0_RRT
15
SBC_MOSI PTB4/FTM0_CH4/LPSPI0_SOUT/TRGMUX_IN1
14 4
SBC_CS PTB5/FTM0_CH5/LPSPI0_PCS1/LPSPI0_PCS0/CLKOUT/TRGMUX_IN0 PTE4/FTM2_QD_PHB/FTM2_CH2/CAN0_RX/FXIO_D6/EWM_OUT SBC_CAN_RX
XTAL 9 3
PTB6/LPI2C0_SDA/XTAL PTE5/TCLK2/FTM2_QD_PHA/FTM2_CH3/CAN0_TX/FXIO_D7/EWM_IN SBC_CAN_TX
EXTAL 8 13 PTE8
LED_GREEN 32 PTB7/LPI2C0_SCL/EXTAL PTE8/FTM0_CH6/CMP0_IN3 12

VSS1
VSS2
PTE9
PTB13/FTM0_CH1/FTM3_FLT1/CAN2_TX/ADC1_SE8/ADC0_SE8 PTE9/FTM0_CH7/LPUART2_CTS
XTAL R87 1M EXTAL

7
30
B R88 B
Y1
0
32MHZ

1 3

VCC_3V3_SBC
C109 C110
2

10pF 10pF
10.0K
10.0K

DNP
C82 0.1uF
J21
PMEG2020EPK
R91
R102

1 C A D22
VCC_3V3_SBC
J19 2
D14 A C PMEG2020EPK 1 SH1 3 PTB1 LPUART0_TX TP15
VCC_3V3_SBC
2 4 PTB0 LPUART0_RX
UART_TX
D15 A C PMEG2020EPK 3 5 PTC16
UART_RX 6501 W illiam Cannon Drive W est
4 6 PTE8
JTAG_TMS_SW D_DIO
JTAG_TCLK_SW D_CLK
5 DCD-LZ 7 PTE9 Austin, TX 78735-8598
6 8 This document contains information proprietary to NXP and shall not be used for engineering design,
RST_N
7 SH2 procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ESD9X5.0ST5G

ESD9X5.0ST5G

ESD9X5.0ST5G

ESD9X5.0ST5G

ESD9X5.0ST5G

ESD9X5.0ST5G

ESD9X5.0ST5G

ESD9X5.0ST5G

ESD9X5.0ST5G

ESD9X5.0ST5G

ESD9X5.0ST5G

ESD9X5.0ST5G

ESD9X5.0ST5G
10.0K

A A
C

C
CON_1X7 HDR_1X8 ICAP Classification: CP: ____ IUO: X PUBI: ____
Designer: Drawing Title:
Ovidiu Leonte
RDDRONE-BMS772
D21

D20

D19

D18

D17

D16

D28

D29

D27

D26

D25

D24

D23
R103

Drawn by: Page Title:

A

A
Ovidiu Leonte MCU
Approved: Size Document Number Rev
Philippe Perruchoud B SCH45742 - SPF45742 B1

Date: W ednesday, June 03, 2020 Sheet 4 of 9

5 4 3 2 1
 5 4 3 2 1

SBC

D D

Q11 TP4
PHPT61003PY
VBAT_IN 3 VCC_3V3_SBC
D8 2 R45
A C 1 5

PMEG3050EP 2.2 C62 C63

0.1uF 10uF R46 R47

4
C60 C61 C58 C59 R48 R77 4.7K 4.7K
0.1uF 10UF 0.1uF 0.1uF 300.0K 100k

J6
BOM note: HDR_1X2

15

6
U3 TP5
fail-safe capacitors 14 5 JUMPER = CLOSED

VEXCTRL

VEXCC
BAT V1

1
2
7 8
SBC_CAN_RX RXD RST RST_N
2
SBC_CAN_TX TXD
LIMP
11
SBC_LIMP
CAN
10
C SBC_SCK SCK J3 C
3 13
SBC_MOSI SDI V2
9 1 SH1
SBC_MISO SDO CAN_HI
20 18 2
SBC_CS SCS CANH

GND1
GND2
GND3
GND4
17 CAN_LO 3
12 CANL 4 SH2

EP
WAKE
4 UJA1169TK/F/3

1
4
16
19

21
CON_1X4
U13B C65 TP6 TP7 R49
S2
DNP NX3008 10uF 60.4
J20
DNP
J22 5 G2 1 SH1
HDR_1X2 2
VCC_3V3_LDO1 3
D2 4 SH2
C66 R50
1
2

R79 3 60.4
4700 PF CON_1X4
300.0K R78 DNP DNP
SW 1 300.0K

2 1 R80 SBC_W AKE

4 3 300.0K
B 6 B
SW SPST C67 D1 U13A
4700PF NX3008
2 G1

R81
S1
100k
1

VBAT_IN U7 VCC_3V3_LDO1
RT9058-33GV TP8 6501 W illiam Cannon Drive W est
1 2 Austin, TX 78735-8598
VCC VOUT This document contains information proprietary to NXP and shall not be used for engineering design,
GND

BOM note: procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
A C73 C88 C74 A
fail-safe capacitor ICAP Classification: CP: ____ IUO: X PUBI: ____
0.1uF 2.2uF 0.1uF
3

Designer: Drawing Title:

Ovidiu Leonte
RDDRONE-BMS772
Drawn by: Page Title:
Ovidiu Leonte SBC
Approved: Size Document Number Rev
Philippe Perruchoud B SCH45742 - SPF45742 B1

Date: W ednesday, June 03, 2020 Sheet 5 of 9

5 4 3 2 1
 5 4 3 2 1

AUTHENTICATION

D D

VCC_3V3_SBC

C68
0.1uF

C
U4 C
6 4
OWI SDA AUTH_NFC_SDA
5 3
AUTH_W AKE WAKEUP SCL AUTH_NFC_SCL
1
7 GND_1 2
GND_2 NC2
A1007

B B

6501 W illiam Cannon Drive W est

Austin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,
procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
A A
ICAP Classification: CP: ____ IUO: X PUBI: ____
Designer: Drawing Title:
Ovidiu Leonte
RDDRONE-BMS772
Drawn by: Page Title:
Ovidiu Leonte AUTHENTICATION
Approved: Size Document Number Rev
Philippe Perruchoud B SCH45742 - SPF45742 B1

Date: W ednesday, June 03, 2020 Sheet 6 of 9

5 4 3 2 1
 5 4 3 2 1

NFC

D D

VCC_3V3_SBC
CLASS 6 Antenna
SJ15
1 2
OPEN

C C
R55
VCC_HARVEST 1M
U5
NTA53321G0FHK
3 16 C118 1800pF
C69 0.1uF VCC_TX LA_TX LA_NTAG C115 2200pF R93 0.75 ohm
9 15
VCC LA
12
VOUT

1
4 L2
nc C72 C116
5 2.2uH
nc1 DNP
11 82pF 680pF
GND1
NFC_HPD 10
HPD

GND_TX
8 14 LB_NTAG C117 2200pF R94 0.75 ohm
NFC_ED

2
ED LB C119 1800pF
AUTH_NFC_SDA 6 13
SDA LB_TX

GND
AUTH_NFC_SCL 7
SCL
The original 82 pF + 680 pF capacitors

2
1
should be replaced by a single 56 pF capacitor
when L2 is used instead of the PCB antenna
TP2 TP3 SJ16
1 2
OPEN
B B
By removing the 0.75 ohm resistors
and connecting the solder jumpers,
users can use L2 instead of PCB antenna.

L2 can be used for extended range operation

6501 W illiam Cannon Drive W est

Austin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,
procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
A A
ICAP Classification: CP: ____ IUO: X PUBI: ____
Designer: Drawing Title:
Ovidiu Leonte
RDDRONE-BMS772
Drawn by: Page Title:
Ovidiu Leonte NFC
Approved: Size Document Number Rev
Philippe Perruchoud B SCH45742 - SPF45742 B1

Date: W ednesday, June 03, 2020 Sheet 7 of 9

5 4 3 2 1
 5 4 3 2 1

Q1 Q2

5
PSMNR70-30YLH
3
2
1
3
2
1
PSMNR70-30YLH

5
SWITCH
DNP DNP
HS1 HS2

4
FK 244 08 D2 PAK FK 244 08 D2 PAK
D D
Q3 Q4

2
PSMNR70-30YLH PSMNR70-30YLH Power Switches Temperature sensor
3 3
2 2 RT2
5 1 1 5

t
Q_temp
10K

4
DNP DNP
VBAT_IN Q5 Q6 VBAT_OUT
PSMNR70-30YLH PSMNR70-30YLH
3 3
TP11 2 2 TP12
5 1 1 5

DNP DNP
HS3 HS4

4
FK 244 08 D2 PAK FK 244 08 D2 PAK
C C
Q7 Q8

2
PSMNR70-30YLH PSMNR70-30YLH
3 3
SILK = POW ER_IN 2 2 SILK = POW ER_OUT
1

1
5 1 1 5
J4 BOM note: J5
CON_1x2 CON_1x2
XT90-S
fail-safe capacitors XT90-S
DNP DNP
2

2
4

4
DNP
DNP
C56 C57 R39
0.1uF 1uF 1M
7

U6 TP14
VCC

8
OUT VSENSE_OUT
6 R40 127
R41 127 1 GATE
IN 5
SOURCE R42
4 1 L1 2 D7
C120 100k
SW 100uH A C 0.01uF
B B
3
GND

RS
BZT52H-B18
AUIR3242STR R95 12
2

R99 10.0K GATE_RS

DNP

GATE_IN

Rsense_P
Rsense_N
1

CAD note:
00 SJ13
00 SJ14
Kelvin contacts
00
00CLOSED
00
00 CLOSED
00 00 6501 W illiam Cannon Drive W est
00 00 Austin, TX 78735-8598
R1 This document contains information proprietary to NXP and shall not be used for engineering design,
2

procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
A A
0.5 mOHM ICAP Classification: CP: ____ IUO: X PUBI: ____
Designer: Drawing Title:
RT1 Ovidiu Leonte
RDDRONE-BMS772
t

TP13 Rsense_temp
Drawn by: Page Title:
10K Ovidiu Leonte SWITCH
Shunt Resistor temperature sensor
Approved: Size Document Number Rev
Philippe Perruchoud B SCH45742 - SPF45742 B1

Date: W ednesday, June 03, 2020 Sheet 8 of 9

5 4 3 2 1
 5 4 3 2 1

OVERCURRENT

D D

VCC_3V3_SBC VCC_3V3_SBC

C84 0.1uF VCC_3V3_SBC

U8
R63 1 5
GATE_CTRL_CP B VCC VCC_3V3_LDO1
2M
2 4
OVERCURRENT A Y
U12 3
R64 1.00k 5 NCX2200GW GND C79 R85
C Rsense_N C
3 VCC 74AUP1G32GW 0.1uF 2M C80 0.1uF
+ 1 R65 10.0K

8
C85 C86 4 U10
- VEE
1000pF 22PF

VCC
2 C97 R76 7 5
TP1 VCC_3V3_SBC SD Q GATE_IN
1000pF 1.00k 1
U11 2 CP
1 5 6 D 3

GND
B VCC RD Q
2 4
GATE_CTRL_D A Y
R62 74AUP1G74

4
180K C87 C98 3
0.01UF GND C81 R84
1000pF
74AUP1G32GW 0.1uF 2M
Rsense_P

B B

6501 W illiam Cannon Drive W est

Austin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,
procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
A A
ICAP Classification: CP: ____ IUO: X PUBI: ____
Designer: Drawing Title:
Ovidiu Leonte
RDDRONE-BMS772
Drawn by: Page Title:
Ovidiu Leonte OVERCURRENT
Approved: Size Document Number Rev
Philippe Perruchoud B SCH45742 - SPF45742 B1

Date: W ednesday, June 03, 2020 Sheet 9 of 9

5 4 3 2 1