Lab Manual, Digital Logic Design

EXPERIMENT # 10

Objective: IMPLEMENTATION OF FULL ADDER WITH 2, 2X4 DECODERS USING

74139 IC

Apparatus: 74139, 7400 IC’s, Bread Board, LEDs and connecting wires
Decoder :
n  2n.
n = No. of input lines.
2n = No. of outputs of a Decoder.
Decoder is a circuit that convert binary information from n-input lines to max of 2 n output
lines e.g. if we have 2 inputs i.e. x,y then there will be 4 output of a Decoder and size of
Decoder will be 2x4.

Block Diagram of 2X4 Decoder.

data input lines

d0

output lines
x
2X4 d1
y DEC O DER d2
d3

Truth Table of 2X4 Decoder

x y E d0 d1 d2 d3
0 0 1 1 0 0 0
0 1 1 0 1 0 0
1 0 1 0 0 1 0
1 1 1 0 0 0 1

Boolean Functions for 2 x 4 Decoder

do = E x′ y′
d1 = E x′y
d2 = E x y′
d3 = E x y

Electronic System Lab, SED, UET Taxila 1

 Lab Manual, Digital Logic Design

Implementation
x y

x' y'
d0 = x' y'
(T o L E D )

d 1 = x' y
(T o L E D )

d 2= x y '
(T o L E D )

d 3= x y
(T o L E D )

Now we implement Half Adder with 2x4 Decoder.

Truth Table of Half Adder

i/p’s o/p’s
x y SHA CHA
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

Truth Table of 2X4 Decoder

i/p’s o/p’s
x y d0 d1 d2 d3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1

By comparing Truth Tables of half Adder and 2 X 4 Decoder.

We can see that SHA = d1 + d2

CHA= d3

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 Lab Manual, Digital Logic Design

Block Diagram of Half Adder with Truth Table of 2X4 Decoder

do
open

x
d1
2X4 S HA
DECODER
d2

y
d3 = C HA

Note:
By connecting an OR gate with output Pin 1 & 2 of 2X4 Decoder. Half Adder can be implemented with 2X4
decoder. Similarly by connecting two Half Adders, we can form a Full Adder by using 2, 2X4 Decoder IC’s.

Truth Table of Full Adder

i/p’s o/p’s
x y z SHA CHA
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Block Diagram of Full Adder with 2, 2X4 Decoders.

Using the concept of implementation of Half Adder with 2X4 Decoder, we can implement Full Adder
with 2, 2 X 4 Decoders.

d o d o
open open

x
d 1
d 1

2X4 S FA =x+y+z
2X4
DECO DER
d 2 S H A =x+y DECO DER d 2

y Z
d 3 d 3 = C FA

= C H A C FA

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 Lab Manual, Digital Logic Design

Pin Configuration of 74LS139

+5 V
1 VCC 16
E
2 15
x E S = x+y

Data i/p
H A

lines

74LS139
y 3 14

Data i/p
lines
4 13
open d 0 z
5 12
d 1 d 0 open
o/p lines

Data o/p
6 11
d d
data

lines
2 1
S H A =x+y 7
d3 d 2 10
8
G ND d 3
9 (C x+y+z )' S FA =x+y+z

C FA

(C x+y )'
P in C o n fig u r a tio n o f 7 4 L S 1 3 9 (2 , 2 X 4 D E C O D E R )

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