15 June 2019

Introduction
• In this chapter we are supposed to learn instruction set of a real
CS 252: Computer Organization and computer; both in the form written by humans (high-level language)
and in the form read by the machine
Architecture II
• We will go step-by-step from a notation that looks like a restricted
programming language, until we see the real language of the real
computer
Lecture 4B
• Computer designers have the common goal:
Principles of Computer Hardware Design and
—To find a language that makes it easy to build the hardware and
Code Generation from HLL the compiler, while maximizing performance and minimizing cost
• C/C++ programming language will be used as HLL, and the MIPS
machine instruction set will also be used
• We will see the restricted programming, at the same time we will
also see the four design principles of computer hardware
By: Dr. E. A. Kalinga, CSE, CoICT, UDSM 1

Operations (ops) of the computer hardware Operations (ops) of the computer hardware
• Every computer must be able to perform fundamental • In C/C++ programming we will have:
arithmetic operations a = b + c + d + e;
• MIPS assembly language notation: • Due to restrictions mentioned above, the equivalent
add a, b, c //a = b + c
assembly language produced by C compiler will be:
Instructs a computer to add two variables b and c and to put their
sum in a add a, b, c // a = b + c
add a, a, d // a = b + c + d
• Restrictions in this is that:
—Each MIPS arithmetic instruction performs only one operation, add a, a, e // a = b + c + d + e
and • Note:
—Each arithmetic instruction must always have exactly three —Three instructions are used to take the sum of four variables
variables; no more, no less
—Each instruction will have exactly three operands, i.e. the two
• Example: suppose we want to place the sum of four numbers being added together and a place to put the sum
variables b, c, d and e into a.

Operations (ops) of the computer hardware Operations (ops) of the computer hardware
• Requiring every instruction to have exactly three operands, Example 1: Compiling two c assignment statement
no more and no less, conforms to the philosophy of into MIPS
keeping the hardware simple This segment of a C program contains the five variables
• i.e. Hardware for a variable number of operands is more a, b, d, and e:
complicated than hardware for a fixed number of operands a = b + c;
• This gives the first out of four (4) principles of hardware d = a – e;
design: The translation from C to MIPS assembly language is performed
by the compiler. Show the MIPS code produced by a C compiler.
Design Principle 1: Simplicity favors regularity Solution:
In assembly language we will have:
add a, b, c // always three operands
sub d, a, e // always three operands

Dr. E. A. Kalinga, CSE, CoICT, UDSM 1

 15 June 2019

Operations (ops) of the computer hardware Operand of the Computer Hardware

Example 2: Compling a complex C assignment into MIPS • In C programming operands are variables (Declared
C program of this kind: location in a memory to carry the type of data and the
f = (g + h) – (i + j); name of that location)
What would a C compiler produce?
• BUT: the operands of arithmetic instructions cannot be any
Solution: variables; they must be from the limited number of special
—Since only one operation is performed per MIPS instruction, the
compiler must break this C statement into several assembly
locations, that is registers (restriction)
instructions • The size of registers in MIPS architecture is 32 bits, and
—To do this, the compiler will create a temporary variables called they are given the name word
‘t0’ and ‘t1’ to store (g + h) and (i + j) respectively
—Then we will have MIPS assembly language as follows:
• MIPS architecture have 32 registers
add t0, g, h // t0 = g + h • In this case we have added another restriction that three
add t1, i, j // t1 = i + j operands of MIPS arithmetic instructions must each be
sub f, t0, t1 // f = (g +h) – (i + j) chosen from one of the 32 32-registers

Operand of the Computer Hardware Operand of the Computer Hardware

• Due to this restriction that three operands of MIPS arithmetic Example: Compiling a c assignment using registers
instruction must each be chosen from one of the 32-bit registers, we
have the second design principle:
f = (g + h) – (i + j);
Solution:
Design Principle 2: Smaller is faster —It is the compiler’s job to associate program variables with
registers. Assume that variable f, g, h, i and j to be associated
with $s0, $s1, $s2, $s3 and $s4 respectively. And $t0 and $t1 to
• In this case, the MIPS conversion will use two character names be temporary registers
following a dollar sign to represent a register, e.g. $s0 —The MIPS assembly language will be:
• From now we will use:
—$s0, $s1,….,$s7 for registers that corresponds to variables in C Add $t0, $s1, $s2 // $t0 = g + h
program
Add $t1, $s3, $s4 // $t1 = i + j
—$t0, $t1,…..,$t7 for temporary registers needed to compile the
Sub $s0, $t0, $t1 // f = (g + h) – (i + j)
program into MIPS instructions

Operand of the Computer Hardware Operand of the Computer Hardware

• But we have more complex data structures e.g. ARRAYS Example: Compiling an Assignment when an Operand is
• Arrays can contain many data elements which may not fit into Memory
registers. The processor will keep small amount of data in register, —Assume that A is an array of 100 words and that the compiler has
other amount of data can be in computer memory associated the variables ‘g’ and ’h’ with the registers ‘$s1’ and
‘$s2’
• Then how can a computer represent and access such large
—Assume that starting address or base address of the array is in
structures?. Arithmetic operations occurs only on registers in MIPS $s3, translate the following C assignment statement
instructions, thus MIPS must include instructions that transfer data
g = h + A[8];
between memory and registers
Solution:
• Thus having data transfer instructions
—We have a single operation in C assignment statement, one of the
• To access a word in memory, the instruction must supply the operand is in memory
memory address —We must first transfer A[8] from memory to a register
• Data transfer instruction in MIPS architecture is load (lw), standing —The address of this array element is the sum of:
for load word, which moves data from memory and load into register The base of the array A found The number to select
+
in $s3 register element. In this case is 8

Dr. E. A. Kalinga, CSE, CoICT, UDSM 2

 15 June 2019

Operand of the Computer Hardware Operand of the Computer Hardware

—The data should be placed in a temporary register $t0 for use in • True Hardware software Interface:
next instruction — The compiler allocates data structure like arrays Memory
and structures to locations in memory . .
—Then we will have MIPS assembly instructions as: — Compiler places the proper starting address into . .
the data transfer instructions . .
— Since 8-bits (1 byte) are useful in many programs,
lw $t0, 8($s3) // temporary register will get the value in A[8] most architectures address individual byte. The the
address of the word (32-bits) matches the address 16
Add $s1, $s2, St0 // g = h + A[8] of one of the 4 bytes within the word
— Words must always start at addresses that are 12
multiples of 4 in MIPS
8
• The constant in a data transfer instruction is called the offset, and — This requirement is called Alignment
Restriction. Which can be either Big-Endian or
the register added to form the address is called the base register Little-Endian (MIPS is in the Big-Endian camp) 4
— To get the proper address in the code, the offset
to be added to the base register must be multiple 0
of 4
i.e. 4 × 8, or 32, so that the load address will select Address Data
A[8] and not A[8/4]

Operand of the Computer Hardware Operand of the Computer Hardware

• The instruction complimentary to load is called store Solution:
(sw), standing for store word, which transfers data from Since we have two operands in memory, we need more MIPS
a register to memory instructions:
i. To transfer data from memory A[8] to the register
Example: Compiling using load and store ii. To add A[8] +h
iii. The result to be transferred to the memory for storage A[12]
Assume variable h is associated with register $s2, and the base
address of the array A is in $s3. What is the MIPS assembly code — Using the proper offset for byte addressing, we will have:
for the C assignment statement below? offset of 8 to be 32 (i.e. 8 × 4) and offset of 12 to be 48
The assembly language will be:
A[12] = h + A[8]; lw $t0, 32($s3) // get A[8] into $t0
add $to, $s2, $t0 // $t0 = h + A[8]
sw $t0, 48($s3) // A[12] = h + A[8]

Operand of the Computer Hardware Operand of the Computer Hardware

Example: Compiling using a variable array index Solution Cont.:
—Assembly language will be:
g = h + A[i];
add $t1, $s4, $s4 // 2i
Assume that A is an array of 100 elements whose base register is
in register $s3. Variable with associations is as follows: g, h and i add $t1, $t1, $t1 // 4i
to $s1, $s2 and $s4 respectively. Write the MIPS assembly code —To get the address of A[i] we add $t1 and base register $s3:
corresponding to the above C segment
add $t1, $t1, $s3 // $t1 carry the address of A[i]
Solution:
—Before we can load A[i] into a temporary register, we need to —Next we can load A[I] into temporary register:
have its address
lw $t0, 0($t1) // $t0 = A[i]
—Before we can add i to the base of array A to form the address,
we must multiply the index i by 4 due to the byte addressing —Finally:
problem add $s1, $s2, $t0 // g = h + A[i]

Dr. E. A. Kalinga, CSE, CoICT, UDSM 3

 15 June 2019

Operand of the Computer Hardware Representing Instructions in the Computers

• Hardware Software Interface: • In computers instructions are represented as a series of high and low
electronic signals (binary digits)
—Many programs have more variables than machine have • Since registers are part of almost all instructions, there must be a
registers. Compiles try to keep the most frequently used conversion to map register names into numbers
variables in registers and places the rest in memory • In MIPS assembly language registers:
$s0 to $s7 maps into registers 16 to 23 respectively
$t0 to $t7 maps into registers 8 to 15 respectively
—It uses load and store instructions to move variables
• Hence $s0 means 16, and $s1 means 17 etc
between register and memory
• Example:Translating a MIPS assembly language into a
—The process of putting less commonly used machine instruction
variables in memory is called Spilling Registers add $t0, $s1, $s2
We will do first as a combination of decimal numbers and then of
binary numbers

Representing Instructions in the Computers Representing Instructions in the Computers

Solution: • Each of these segments of an instruction is called a field
$t0 maps register 8 and is the destination register (rd)
• The first and the last fields (containing 0 and 32 in this
$s1 maps register 17 and is 1st source operand (rs)
case) in combination tell the MIPS computer that this
$s2 maps register 18 and is the 2nd operand (rt) instruction performs addition
—The translation both in decimal and binary will be:
• The last instruction is represented as fields of binary
R-Format: numbers as opposed to decimals
6-bits 5-bits 5-bits 5-bits 5-bits 6-bits

op rs rt rd shamt funct • To distinguish it from assembly language, we call the

In decimal numeric version of instructions machine language and a
0 17 18 8 0 32 sequence of such instructions machine code
In binary(machine language)

000000 10001 10010 01000 00000 100000

MIPS Fields MIPS Fields

R-format • This leads to the third principle of hardware design:
6-bits 5-bits 5-bits 5-bits 5-bits 6-bits
op rs rt rd shamt funct
Design Principle 3: Good design demands good
— op: this is opcode; basic operation of the instruction
compromises
— rs: the first register source operand
• The compromise chosen by the MIPS is:
— rt: the second register source operand —To keep all instructions the same length, thereby
— rd: the register destination operand, it gets the result of the operation —Requiring different kinds of instruction formats for different kinds
— shamt: shift amount, used in shift instructions. In this case it will have 0 value of instructions
— funct: function, selects the specific variant of the operation in the op field. • The format above is called R-type (for registers) or R-format for
Sometimes called function code arithmetic instructions
• A problem occurs when we have an instruction which needs longer • A second type of instruction format is called I-type or
fields than those above: e.g. lw instruction specify two registers and I-format (immediate-type) and is used for data transfer instructions
a constant • The third one is J-Format
• In this case, we have a conflict between the desire to keep all
instructions in the same length and a desire to have a single I-format
6-bits 5-bits 5-bits 16-bits
instruction format
op rs rt address

Dr. E. A. Kalinga, CSE, CoICT, UDSM 4

 15 June 2019

Representing Instructions in the Computers Representing Instructions in the Computers

Example: Translating MIPS assembly language Representation in binary equivalent (machine language code):
into machine language
From the given C program assignment statement find the equivalent MIPS 100011 01001 01000 0000 0100 1011 0000
lw
machine language. Assume that $t1 has the base value of array A and $s2
corresponds to h. add 000000 10010 01000 01000 00000 100000
A[300] = h + A[300];
sw 101011 01001 01000 0000 0100 1011 0000
Solution:
Assembly language will be:
lw $t0, 1200($t1) // $t0 = A[300] • The lw instruction is identified by 35 in the first field (op)
add $to, $s2, $t0 // $t0 = h + A[300] • The sw instruction is identified by 43 in the first field (op)
sw $to, 1200($t1) // store h + A[300] in A[300] • The add instruction is identified with a 0 in the first field
Representation in decimal number will be: (op) and 32 in the last field (funct). Sub instruction will
lw 35 9 8 1200
have 34 in the last field (funct)
add 0 18 8 8 0 32
sw 43 9 8 1200

Stored-Program Concept Stored-Program Concept

• Computers are built on two key principles:
—Instructions are represented as numbers
—Programs can be stored in memory to be read or written just like
numbers
• These principle lead to the stored-program concept;
that: instructions and data of many types can be stored in
Processor
memory as numbers
• e.g. memory can contain the source code for an editor
program, the corresponding compiled machine code, the
text that the compiled program is using, and even the
compiler that generated the machine code
• The switch happens by telling the computer to begin
executing at a given location in memory

Instructions for making decisions Instructions for making decisions

• Decision making is commonly represented in programming Example: Compiling an if statement into a conditional
language using branch
—If statements In the following C code segment: f, g, h, i and j are variables
—Sometimes combined with go to statements and label
if(i==j) go to L1;
• MIPS assembly language include two decision-making f = g + h;
instructions, similar to if statement and go to statement, L1: f = f – i;
these are: Assume that the five variables f through j corresponds to the five
—Branch if equal (beq): beq reg.1, reg.2, L1 registers $s0 through $s4, what is the compiled MIPS code
Meaning: go to statement labeled L1 if values in reg.1 and reg.2 Solution:
are equal
1st: the first statement compares for equality; if true, then
—Branch if not equal (bne): bne reg.1, reg.2, L1 branches to the subtract operation.
Meaning: go to statement labeled L1 if values in reg.1 and reg.2 beq $s3, $s4, L1 // go to L1 if i==j
are not equal
2nd: the second statement performs a single operation
• These instructions are conditional branching add $s0, $s1, $s2 // skipped when i==j

Dr. E. A. Kalinga, CSE, CoICT, UDSM 5

 15 June 2019

Instructions for making decisions Instructions for making decisions

Finally: Example:
—The final statement can be compiled in a single instruction Compiling if-then-else into
—The problem is how to specify its address so that the conditional conditional branches
branch can be skip the add instruction above i=j ij
Using the same variables and i= =j ?
—Instructions are stored in memory in stored-program computers; registers from the example,
hence instruction must have memory addresses compile this C if previous
—Label L1 was forward-referenced by the beq instruction: statement f=g+h f=g-h
L1: sub $s0, $s0, $s3 if(i==j)
Hence the compiled MIPS code will be f=g+h;
else exit
beq $s3, $s4, L1 // go to L1 if i==j
f=g-h;
add $s0, $s1, $s2 // skipped when i==j
• The flowchart is as shown
L1: sub $s0, $s0, $s3

Instructions for making decisions Instructions for making decisions (Loops)

Solution: Example: Compiling a loop with variable array index
• The first C expression compares the equality, seem as if we would want to start
with beq Loop: g=g + A[i];
• BUT the code would be more sufficient if we test for the opposite condition which i=i + j;
will take us to the branch over the code that performs the subsequent then part of If(i != h) go to loop;
it: We will have:
Assume that A is an array of 100 elements and the compiler
bne $s3, $s4, Else // go to Else if (ij) associates the variables g, h, i and j with the registers $s1, $s2, $s3
add $s0, $s1, $s2 // if (i==j), f=g+h and $s4 respectively.Assume base register to be $s5. What is the
MIPS assembly code corresponding to this C loop?
• Now we need to go to the end of if statement (Exit). Unconditional branch
Solution:
instruction (jump) will be used. In this instruction, the machine always follow the
branch —1st get the address of the array A[i] in temporary register
Loop: add $t1, $s3, $s3 //2*i
j Exit // go to exit
add $t1, $t1, $t1 // 4*i
• The next instruction of if (I.e. when i j) will have a label
add St1, St1, $s5 // address of A[i]
Else: sub $s0, $s1, $s2 // skipped if i=j lw $t0, 0($ti) // $to have the value from A[i]
Exit:

Instructions for making decisions (Loops) Instructions for making decisions (Loops)
—The next two instructions add A[i] to g and the j to i Solution:
add $s1, $s1, $t0 // g = g + A[i] —1st step is to load save[i] into a temporary register
add $s3, $s3, $s4 // i = i + j Loop: add $t1, $s3, $s3 // 2*i
—The final instruction will be: add $t1, $t1, $t1 // 4*i
bne $s3, $s4, Loop // go to loop if i  j add $t1, $t1, $s6 // the address of save[i]
lw $t0, 0($t1)
Example: Compiling a while loop —Next performs the loop test, exiting if save[i]  k
while (save[i]==k) bne $t0, $s5, Exit // go to Exit if save[i]  k
i = i + j; add $s3, $s3, $s4 // if save[i] = k, i=i+j
Assume i, j and k maps $s3, $s4 and $s5 respectively. Base —The end of the loop branches back to the while test
register to be $s6. What is the MIPS assembly code
j Loop // go to Loop
Exit:

Dr. E. A. Kalinga, CSE, CoICT, UDSM 6

 15 June 2019

Set on less than (slt) Set on less than (slt)

• Set on less than (slt) compares two registers and sets a Example:
third register to 1 if the first is less than the second; What is the code to test if variable a (corresponding to register $s0)
otherwise, it is set to 0 is less than variable b ( corresponding to register $s1) and then
branch to label less if the condition holds
slt $t0, $s3, $s4
Solution:
How: if $s3 < $s4, $t0 will be set to 1
—1st test for less than
otherwise if $s3 is not less than $s4, $t0 will be set to 0
slt $t0, $s0, $s1 // $t0 gets 1 if $s0 < $s1 (a<b)
• MIPS compiler use the slt, beq, bne and the fixed value of
—Next; if $zero  $t0 then condition holds
0 always available by reading register $zero to create all
bne $t0, $zero, Less // go to less when
relative conditions; i.e. ==, !=, <, <=, > and >=. // condition holds
• $zero register maps to register 0 —This pair of instructions, slt and bne, implements branch on less
than

Constant and Immediate Operands Constant and Immediate Operands

• Many times a program will use a constant in an operation e.g. Example: Translating assembly constants into machine
incrementing an index to point to the next element of an array, language
counting iterations of a loop The add instruction that has one constant operand is called add
• 52% to 69% of arithmetic operations involve constants immediate or “addi”
• Example to add the constant 4 to register $sp, we would use the e.g. addi $sp, $sp, 4 // $sp = $sp + 4
code: Solution:
lw $t0, addrConstant4($zero) //$t0 = constant 4 I-instruction format is:
add $sp, $sp, $t0 // $sp = $sp + 4
6-bits 5-bits 5-bits 16-bits
op rs rt address
• Alternatively; to avoid accesses to memory, a constant is included in
the arithmetic instruction as one operand, i.e a constant is kept Code in decimal
inside the instruction itself
8 29 29 4
• The format used is the same as that of data transfer and branch
instruction, the I-format, where I stands for Immediate Machine language
001000 11101 11101 0000 0000 0000 0100

Constant and Immediate Operands Constant and Immediate Operands

—$sp maps 29 register and addi has 8 in op field • Although constants are frequently short and fit into the 16-bit field,
• Immediate or constants are also popular in comparisons. Since sometimes they are bigger
register $zero is always 0, immediate value can be used in set on • MIPS instruction set includes the instruction load upper immediately
less than “lui”, which is used specifically to set the upper 16 bits of a constant
e.g. slti $t0, $s2, 10 // $t0 = 1 if $s2 < 10 in a register
• This can be followed by bne
bne $t0, $zero, L1 // if $s2 < 10 then go to LI Example: Loading a 32 bit constant
• Immediate addressing gives the fourth design principle: What is the MIPS assembly code to load this 32-bit constant into
register $s0?
0000 0000 0011 1101 0000 1001 0000 0000
Design Principle 4: make the common case fast
Solution:
• That is: Constant operand occur frequently, and by making constants —1st load the upper 16 bits whose decimal value is 61
part of arithmetic instructions, they are much faster than if they were lui $s0, 61
loaded from memory —Then add the lower 16 bits whose decimal value is 2304
addi $s0, $s0, 2304

Dr. E. A. Kalinga, CSE, CoICT, UDSM 7

 15 June 2019

Addressing in Branches and jump Addressing in Branches and jump

• Jump instruction in MIPS is called the “j-type format”. It consists of 6 Example: Showing branch offset in machine language
bits for the operation field and the rest of the bits are for the address What is the MIPS machine code for the following while loop, if we
field
assume that the loop is placed starting at location 80000 in memory
e.g. j 10000
• Conditional branch instructions must specify two operands in addition loop: add $t1, $s3, $s3
to the branch address add $t1, $t1, $t1
e.g. bne $s0, $s1, Exit add $t1, $s3, $s6
• Target address for conditional branching will be the sum of the lw $t0, 0($t1)
address of the next instruction just after conditional branch
instruction and the offset number given to the instruction times the bne $t0, $s5, Exit
4 as a relative word address add $s3, $s3, $s4
• The offset number shown in the conditional branching j loop
address field, can be calculated by only counting the total
Exit:
number of instructions following the branch instruction
J-format 6-bits 26-bits
op address

Addressing in Branches and jump Addressing in Branches and jump

Solution: • Note:
• The assembled instructions and their addresses would look like this: —MIPS instructions use byte addresses, so the addresses of
sequential words differ by four, the number of bytes in word
80000 0 19 19 9 0 32
80004
—The bne instruction on the fifth line adds 8 bytes to the address of
0 9 9 9 0 32 the following instruction (80020), specifying the branch
80008 0 9 22 9 0 32 destination relative to that instruction (8) instead of the current
80012 35 9 8 0 instruction (16) or using the full destination address (80028)
80016 5 8 21 2 —Counting the total number of instructions following the
80020 branch instruction, hence the address field in the “bne”
0 19 20 19 0 32
instruction at location 80016 in the example above should have 2
80024 2 80000 instead of 8.
80028 .....
—The jump instruction on the last line does use the full address
(800000), corresponding to the label Loop
Note: The address for the Exit will be: 80020 + (2  4) =
80028

Decoding machine language Decoding machine language

• Sometimes you may be required to reverse machine language to —Bits 5-0 have the value 32, hence this is an add instruction
create the original assembly language —The rest of the fields will be decoded into decimal, and then find
• The first step is to look at the op field to determine the operation. If the mapping register
it is an arithmetic instruction (i.e. with the 0 at op field) then look at
the funct field —The assembly language is
Example: What is the assembly language corresponding to the add $s0, $a1, $t7
machine instruction • From the above discussion, MIPS addressing modes are:
0000 0000 1010 1111 1000 0000 0010 0000 —Register addressing
Solution:
—Base or displacement addressing
—Since bits 31-26 has the value 000000, then is arithmetic
instruction of R-format —Immediate addressing
—Reformat the binary instruction into R-format field —PC-relative addressing
—Pseudodirect addressing, where the jump address is the 26 bits of
op rs rt rd shamt funct the instruction concatenated with the upper bits of the PC
000000 00101 01111 10000 00000 100000

Dr. E. A. Kalinga, CSE, CoICT, UDSM 8

 15 June 2019

MIPS Register Convention MIPS Instruction formats

Name Register Usage Preserved

number
Name Fields Comment
on call?
Field size 6 bit 5 bits 5 bit 5 bits 5 bits 6 bits All MIPS instructions
$zero 0 The constant value 0 n.a.
32 bits
$v0-$v1 2-3 Values for results and expression evaluation No
R-format op rs rt rd shamt funct Arithmetic instruction
$a0-$a3 4-7 Arguments Yes format
$t0-$t7 8-15 Temporaries No I-format op rs rt Address/immediate Transfer, branch,
$s0-$s7 16-23 Saved Yes immediate format
$t8-$t9 24-25 More temporaries No J-format op Target address Jump instruction
format
$gp 28 Global pointer Yes
$sp 29 Stack pointer Yes
$fp 30 Frame pointer Yes Jump Register (jr) instruction will have R-format
$ra 31 Return address yes

• Register 1, called $at, is reserved for assembler op rs 0 funct

• Registers 26-27, called $k0-$k1, are reserved for operating system

MIPS Instruction Set Covered OP Field Values and Funct Field values of Instructions
Category Instruction Name Format Example Name Format OP Field Funct Field
Add Add R add $s1, $s2, $s3 Value Value
Arithmetic Subtract Sub R sub $s1, $s2, $s3 add R 0 32
Add immediate addi I Addi $s1, $s2, 100 sub R 0 34
Load word lw I Lw $s1, 100($s2) addi I 8 N/A
Data Store word sw I sw $s1, 100($s2) lw I 35 N/A
Transfer sw I 43 N/A
Load upper immediate lui I Lui $s1, 100
Branch on equal beq I beq $s1, $s2, 25 beq I 4 N/A
Conditio- Branch on not equal bne I bne $s1, $s2, 25 bne I 5 N/A
nal branch
Set on less than slt R slt $s1, $s2, $s3 slt R 0 42
Set on less than immediate slti I slti $s1, $s2, 25 j J 2 N/A
Unconditi- Jump j J j 2500 jr R 0 8
onal jump Jump register jr R jr $ra jal J 3 N/A
Jump and link jal J jal 2500

Dr. E. A. Kalinga, CSE, CoICT, UDSM 9