7 August 2020

CS 252: Computer Organization and

Architecture II

Lecture 5 - The Memory System

By: Dr. E. A. Kalinga, CSE, CoICT, UDSM

Organization of Memory Device

• Computer memory is made from arrays of cells (D-
Flip Flop), each of which is capable of storing a
single bit, a one or a zero.
• The array of cells is arranged so that each row
represents a memory location where a binary
number or program instruction would be stored and
the columns represent different bits of those
memory locations.
• Memory is like a matrix where the number of rows
identifies the number of memory locations in the
memory and
• the number of columns identifies the number of bits
in each memory location.

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Organization of Memory Device

• To store to or retrieve data from a memory
device, the processor must place a binary
number called an address on special inputs
to the memory device.
• This address identifies which row of the memory
matrix or array the processor is interested in
communicating with, and enables it.
• Once a valid address is placed on the address
lines, the memory cells from that row are
connected to bi-directional connections on the
memory device that allow data either to be
stored to or read from the latches

Memory Unit
• A memory unit stores binary information in groups of bits
called words.
• Most computer memories use words that are multiples of 8
bits.
• A block diagram of the memory unit is shown below:

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Memory Unit
• The memory unit is specified by the number of
words it contains and the number of bits in each
word.
• The address lines select one particular word.
• Each word in memory is assigned an identification
number called an address.
• Addresses range from:

Interfacing Memory to a Processor

• A processor when communicating with the memory
system, must supply three types of information:
—the address within memory to be accessed
—the type of operation to be performed (read or write), i.e.
the control
—the data to be written (in the case of writes)
• A group of wires called a "bus" provide the pathway
over which this information can be conveyed.
• In the most general case there is a separate
address bus, data bus and control bus.

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Interfacing Memory to a Processor

• The maximum address that can be specified is determined by the width of
the address bus (lines)
• The address lines are controlled entirely by the processor and are used to
specify which memory location the processor wishes to communicate with.
• The maximum amount of data that can be transmitted in a single transfer is
determined by the width of the data bus (lines).
• The data lines are the electrical connections used to send data to or
receive data from memory.
• For example, if the memory of a particular system has 8 latches per memory
location, i.e., 8 columns in the memory matrix or array, then it can store 8-
bit data and has 8 individual wires with which to transfer data.
• The control bus (lines) carries signals such as a read command, a write
command, data ready indicators, etc.
• The control lines consist of the signals that manage the transfer of data.
At a minimum, they specify the timing and direction of the data transfer.
The processor also controls this group of lines.

Basic Processor to Memory Device Interface

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Basic Processor to Memory Device Interface

The Memory Bus

• The memory address register (MAR) and memory
data register (MDR) serve as the interface to the
respective buses and are used by the CPU to
communicate with the memory unit.
• The MAR specifies the address within memory to be
accessed.
• The MDR (also sometimes called the memory
buffer register or MBR) contains data to be written
to memory or receives data that are read from
memory.

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Basic Bus Operation and Timing

• Interaction between the CPU and memory over the
bus is coordinated and synchronized via a clock.
• This clock in many cases runs at a much slower rate
than the clock that drives the CPU due to the relatively
slow speed of the memory system as compared to the
CPU.
• To perform a write to memory, the CPU must:
—supply the memory address (via the MAR)
—supply the data to be written (via the MDR)
—issue a write command by appropriately setting the R/W
control line
—wait for the RDY signal from the memory to determine when
the write completes

Basic Bus Operation and Timing

• To perform a read from memory, the CPU must:
—supply the address from which the data is to be read
—issue a read command by appropriately setting the R/W
control line
—wait for the RDY signal from memory indicating that the
data has been obtained
—transfer the data from the MDR into some other internal
register
• Each of these sets of operations is said to constitute a
"bus transaction" or "bus cycle".
• A bus cycle usually requires a number of clock cycles
as illustrated in the next slides:

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Timing for a Write Operation

Timing for a Read Operation

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Timings
• The double lines used to represent the address and
data bus indicate the presence of multi-bit
information.
• These collapse to a single line when no valid
information is present on the bus.
• Note that control signals can be considered asserted
when they are 0 (active low) or when they are 1
(active high).
• Signals that are active low have a bar over their
specifiers or may have a # appended (such as the
RDY# signal or the Write signal (R/W#)
• r/w# indicates a read command when high but a write
command when low.

RDY Signal
• The access time for the memory can vary as a
function of the type of memory used.
• In the diagram below the data is available in clock
cycle T3. However, if the memory could not have
the data ready at that time, an integral number of
extra clock cycles (called wait states or wait
cycles) would have to be inserted to allow the
memory additional time to acquire the requested
data.
• Thus the RDY signal prevents the CPU from
attempting to use invalid data (i.e. the contents of
the MDR prior to the arrival of the actual requested
data).

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Memory addressing
• A memory system is said to be byte-addressable if
the addresses that are used correspond to individual
byte locations.
• A word-addressable system, on the other hand,
interprets the addresses as indices that indicate which
multi-byte word is to be addressed:
• Assuming a 32-bit word size, the addresses for
adjacent words would differ by 1 on the word-
addressable system but would differ by 4 on the
byte-addressable system.
• To obtain a particular byte on a word-addressable
system it is necessary to read in the word containing
the desired byte. Most systems tend to be byte-
addressable.

Memory Addressing

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Memory Mapping and Memory Blocks

Memory Maps 1
• A memory can be considered to be like a filing
cabinets with a number of folder
• Each folder can contain a single piece of data.
—Example a piece of data can be either code (part of a
program) or data (variables or constants used in the
program).
• Code and data are typically stored in the same
memory, each piece of which is stored in a unique
address or row of memory.
• Some sections of memory are dedicated to a
specific purpose which may place constraints
(restrictions) on how it is implemented.

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Memory Maps 2
• For example,
—the BIOS from which the computer performs its initial
startup sequence is located at a specific address range in
non-volatile memory.
—Video memory may also be located at a specific address
range.
• Both hardware and software designers need to
have a method to describe the arrangement of
memory in a system.
• Since multiple memory devices and different types
of memory may be present in a single system,
—hardware designers need to be able to show what
addresses correspond to which memory devices.

Memory Maps 3

—Software designers also need to have a way to

show how the memory is being used.
—For example,
– which parts of memory will be used for the
operating system,
– which parts will be used to store a program, or
– which parts will be used to store the data for a
program.

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Memory Maps 4

• System designers describe the use of

memory with a memory map.
• A memory map represents a system's memory
with a long, vertical column.
• It is meant to model the memory array where
the rows correspond to the memory locations.
• Within the full range of addresses are smaller
partitions where the individual resources are
present.
• Next figure presents two examples of memory
maps.

Two Examples of Memory Maps

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Memory Maps 5
• The numbers along the left side of the memory map
represent the addresses corresponding to each
memory resource.
• The memory map should represent the full address
range of the processor
• This full address range is referred to as the
processor's memory space, and its size is
represented by the number of memory locations in
the full range,
• i.e., 2m where m equals the number of address lines
coming out of the processor.
• It is up to the designer whether the addresses go in
ascending or descending order on the memory map.

Memory Maps 6
• As an example,
let's calculate the memory space of the processor
represented by the memory map in Figure b above.
The top address for this memory map is
FFFFF16 = 1111 1111 1111 1111 11112.
• Since the processor accesses its highest address
by setting all of its address lines to 1, we know
that this particular processor has 20 address
lines.
• Therefore, its memory space is 220 = 1,048,57610
= 1 Meg.
• This means that all of the memory resources for
this processor must be able to fit into 1 Meg
without overlapping

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Size of Each Partition of Memory

• We can determine the size of a partition in

memory by subtracting the low address from
the high address, then adding one to account
for the fact that the low address itself is a
memory location too.
• For example,
—The range of the BIOS in Figure a above starts at
FF0016 = 65,28010 and goes up to FFFF16 =
65,53510.
—This means that the BIOS fits into
65,535 – 65,280 +1 = 256 memory locations.
—adding one to account for the fact that the low
address itself is a memory location too.

Address decoding
• Take another example the memory range for Program A
in Figure b above.
• The lower address is 2000016 while the upper address is
27FFF16.
• If we convert these addresses to binary, we should see a
relationship.
2000016 = 0010 0000 0000 0000 00002
27FFF16 = 0010 0111 1111 1111 11112
• We can see that upper five bits of these two addresses
are identical while the remaining bits go from all zeros in
the low address to all ones in the high address.
• Converting the high and the low address of any one of
the address ranges in Figure b should reveal the same
phenomenon.

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Address decoding
• Address decoding is a method for using an address to
enable a unique memory device while leaving all other
devices idle.
• All address decoding schemes have one thing in common:
the bits of the full address are divided into two groups,
—one group that is used to identify the memory device and
—one group that identifies the memory location within the
selected memory device.
• In order to determine how to divide the full address into
these two groups of bits, we need to know
—how large the memory device is and
—how large the memory space is.
• Once we know the size of the memory device, then we know
the number of bits that will be required from the full address
to point to a memory location within the memory device.

Address decoding
• The size of the memory space of a device is calculated by
raising 2 to a power equal to the number of address lines
going to that device.
• For example,
—a memory device with 28 address lines going into it has
228 = 256 Meg locations.
—This means that 28 address bits from the full address
must be used to identify a memory location within that
device.
• The division of the full address into two groups is done by
dividing the full address into a group of most significant
bits and least significant bits.
• The block diagram of an m-bit full address in Figure below
shows how this is done.
• Each bit of the full address is represented with an where n
is the bit position.

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Address decoding

• The bits used to enable the memory device

are always the most significant bits while
• The bits used to access a memory location
within the device are always the least
significant bits.

Example
• Example
A processor with a 256 Meg address space is
using the address 35E3C0316 to access a 16 Meg
memory device.
1. How many address lines are used to define when the
16 Meg memory space is enabled?
2. What is the bit pattern of these enable bits that
enables this particular 16 Meg memory device?
3. What is the address within the 16 Meg memory device
that this address is going to transfer data to or from?
4. What is the lowest address in the memory map of the
16 Meg memory device?
5. What is the highest address in the memory map of the
16 Meg memory device?

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Dividing Memory into Blocks

• Main memory stores all of its words in
sequential addresses. The cache, however,
has no sequential order.
• Therefore, it is the addressing scheme of main
memory that is used to define the blocks of
words and the method for locating them.
• The definition of blocks in main memory is
logical only; it has no effect on how the words are
stored.
• The full main memory address defines a specific
memory location within memory.
—For example, a unique twenty-bit address such as
3E9D116=0011 1110 1001 1101 00012 points to exactly one
memory location within a 1 Meg memory space.

Dividing Memory into Blocks

• If we "hide" the last bit of the address, i.e., that bit could be a one
or a zero,
—then the resulting address could refer to one of two
possible locations,
—3E9D116 (0011 1110 1001 1101 00012) or 3E9D016 (0011
1110 1001 1101 00002).
• If we hide the last two bits,
—then the last two bits could be 002, 012, 102, or 112.
—Therefore, the address could be referring to one of the
following four possible sequential locations:
3E9D016 = 0011 1110 1001 1101 00002
3E9D116 = 0011 1110 1001 1101 00012
3E9D216 = 0011 1110 1001 1101 00102
3E9D316 = 0011 1110 1001 1101 00112

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Dividing Memory into Blocks

• This is how a block is defined.
— By removing a small group of bits at the end of an address, the
resulting identifier points to a group of memory locations rather
than a specific address.
— Every additional bit that is removed doubles the size of the group.
• This group of memory locations is what is referred
to as a block.
— The number of words in a block is defined by the number of bits
removed from the end of the address to create the block identifier.
• For example,
— when one bit is removed, a block contains two memory locations.
— When two bits are removed, a block contains four memory
locations.
• In the end, the size of a block, k, is defined by:
k = 2w
where ‘w’ represents the number of bits
"removed“.

1 Meg memory space divided into four word blocks

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Memory Organization into Blocks

• To organize memory into blocks, a memory address is
divided into two logical sets of bits,
—one to represent the block number and
—one to identify the word's position or offset within
the block.
• The memory address for the above example uses
—the most significant 18 bits to identify the block and
—the last two bits to identify a word's position within the
block.
• using the address 101001010110100101102 (A569616).

Example
• How many blocks of 8 words are there in a 1 Gig memory space?
Solution
—Eight words require three bits to uniquely identify their
position within a block.
—Therefore, the last three bits of the address represent the
word's offset into the block.
—Since a 1 Gig (230) address space uses 30 address lines,
there are 30 – 3 = 27 remaining bits in the address.
—These bits are used to identify the block.
—Below is a diagram of the logical organization of the
address.

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Memory Organization – Parallel Structures

• To reduce the amount of time that the CPU has to spend
waiting for instructions and data from memory, a number of
techniques have been developed:
—Some of these involve changing the basic organization of
memory and
—others employ a combination of software and hardware.
• The memory organization may be changed to allow more
than one word to be located and retrieved at the same time.
• The memory is then said to have a parallel structure.
• There are two fundamental parallel memory
architectures:
—Banked memory (or High Order Interleaved) and
—Interleaved memory (or Low Interleaved Memory)

Banked Memory (High Order Interleaved)

• memory is divided into independent blocks, each
with its own MAR and MDR.

• Each block may be accessed in parallel with one or

more of the other blocks.

• For example, while the CPU is fetching an instruction

from bank 0, an I/O device could be performing a
DMA transfer with another memory bank.

• This results in a net increase in the speed of the

computer by reducing the effective memory cycle
time.

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Banked Memory (High Order Interleaved)

Banked Memory (High Order Interleaved)

A 1KB memory were divided into four banks each of which

contained 256 bytes. Here (m - k) = 2 and k = 8.

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Banked Memory (High Order Interleaved)

• For banked memory, the memory address decoder
splits the m-bit address into two parts:
—a (m – k) bits for module number identifying the
appropriate memory bank and
—an ‘k’ bits for offset which identifies the desired location
within the memory bank.
• For example, if the MAR were 10 bits wide, then the
maximum memory size would be 1k bytes.
• Suppose that the memory were divided into eight
banks each of which contained 128 bytes.
—In this case (m – k)=3 (three most significant bits
selecting bank number) and
—k=7 as offset (selecting location within 128 bytes banks)

Drawback for Banked Memory

• If the data requested by the CPU and the I/O device
reside in the same memory bank, then only one
request can be honored at a time. So, we are back to
the problem of having to wait for information from
memory.
• Accessing data from sequential locations would also
require waiting for memory since they would lie within
the same bank.
• One solution to this problem would be to store
sequential locations in different banks, yielding an
interleaved memory organization.

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Interleaved memory (Low Interleaved Memory)

Interleaved memory (Low Interleaved Memory)

• With an interleaved memory organization:
—the memory address decoder uses the low order bits
within the address to select the memory module (m – k)
and
—the high order bits for the offset within the module (k).
• consecutive memory locations are in different memory
modules.
• Using the same address as in the banked memory example,
the address would be split as follows:

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Interleaved memory (Low Interleaved Memory)

Memory Characteristics
• Memory system can be characterized based on:
Location, Capacity, Access method, Performance,
Physical type, Physical characteristics and
Organisation
• Access method
—Sequential [Start at the beginning and read through in
order up to the end]
—Direct [Individual blocks have unique address, Access is
by jumping to vicinity plus sequential search]
—Random [Individual addresses identify locations exactly]
—Associative [Data is located by a comparison; content of
data requested with contents of a portion of the store]

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Associative Memory
• Finding the data item in memory by:
—Reading contents of memory cells and
—Comparing the value stored with the value of the items to
be found
• An alternative way is to:
—Broadcast the value of the search item to all memory
cells simultaneously, and
—To have any memory cells that contains a matching value
respond appropriately.
• This type of memory system which allow
broadcasting is called associative memory or a
content addressable memory

Associative Memory Block Diagram

Argument Register A
Match Register

Input Associative memory

Read m words M
Write n bits per word

Output

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Reading From Associative Memory

• When a word is to be read from associative
memory;
—The content of the word (or part of it) is specified
—The memory locates the word that matches the
specified content and marks it for reading
• The memory is especially suited to do parallel
searches by data association
• Searches can be done on an entire word or on a
specified field within a word

Associative Memory Block Diagram

• The argument register A has n bits, one for each
bit of a word
• The match register M has m bits, one for each word in
memory
• Each word is compared in parallel with the content of
the argument register
• The words that match the bits of the argument
register set a corresponding bit in the match register
• Reading is accomplished by a sequential access to
memory for those words whose corresponding bits in
match register have been set.

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Associative Memory Block Diagram

• Each bit of A is compared with the corresponding bit
of memory word

• The comparison to the corresponding bit is done with

exclusive-NOR gate

• The outputs of all exclusive-NOR gates belonging to

the same word go to the inputs of a common AND
gate to generate the match signal Mi

Associative Memory Block Diagram

A1 A2 A3 A4
BC BC BC BC

M1
BC BC BC BC

M2

To all other words

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Associative Memory
• An associative memory must also be capable of
finding an empty unused location into which a new
value can be stored
• There must also be some way of deleting unwanted
items that are no longer needed
• A special way to accomplish this is to use a tag
register, whose bits indicates whether the
corresponding memory word is active or inactive
• Tag register must have as many bits as there are
words in memory
• For every active word stored in memory, the
corresponding bit in the tag register is set to 1

Associative Memory

• A word is deleted from memory by resetting its tag

bit to 0
• Words are stored in memory by scanning the tag
register until the first 0 bit is encountered
• After a new word is stored in memory it is made
active by setting its tag bit to 1

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Key Register
• In many instances the associative memory is
searched for a match based only on a certain
fields within the word
• To facilitate such a search, the memory includes
a key register (K) that defines which bits in
the word should be matched against the
argument register A
—if bit j within the key register is a 1, then bit j within
each memory word will be compared with bit j of the
argument register
—If bit j of register K is 0, then no comparison is made
for bit j, i.e. bit j of A is considered to automatically
match the corresponding bit of each memory word

Associative Memory with Key Register

Argument Register A

Key Register K
Match Register

Input Associative memory

Read m words M
Write n bits per word

Output

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