Training Tutorial Jaspergold® Apps Property Visualization and Debugging
Training Tutorial Jaspergold® Apps Property Visualization and Debugging
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Publish date: July 24, 2013
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Overview
This tutorial introduces the JasperGold® Apps Visualize™ feature. Property visualization
is useful for debugging properties early in the design cycle when the design under
verification (DUV) is not available. With complex properties written in Property
Specification Language (PSL) or SystemVerilog Assertions (SVA), the property
visualization feature lets you reduce your debugging time by quickly identifying and fixing
incorrect properties.
NOTE: This tutorial uses Verilog® and PSL as target languages. Commands and GUI
results can differ if you use the VHDL or SVA files.
Tutorial Objectives
Tutorial Components
The following graphic illustrates the directory structure for this tutorial.
doc
tutorial_jg_property_visulaization.pdf Tutorial guide
source
<property files>
Conventions
Convention Definition
Italics User interface items such as button, menu option, and dialog
field names.
Menu – Option GUI command sequence.
Figure 2 illustrates a property visualization flow using JasperGold Apps. This tutorial
targets several steps in the flow.
Property
Table
Tabs
Message
pane
Command
line
Message
pane tabs
Footer
See the JasperGold Apps User’s Guide for a detailed description of the console.
You will see that the tool automatically creates a directory called jgproject in your
working directory. It contains information such as log and command files, saved
sessions, and user preferences.
The first operation before starting the verification is to analyze design and property files
and set up the proof environment. You can use the GUI to trigger these commands, type
them directly on the command line, or use the following procedure to source a Tcl script.
1. Click File – Tcl Scripts – Source.
The Tcl File dialog appears.
2. Double-click solution.
3. Click the Tcl file setup.tcl, and then click Open.
JasperGold Apps analyzes the property files and sets up the Visualize environment.
JasperGold Apps lets you add assumptions in the environment before you start to
Visualize properties. Since the signals used in the properties are undriven due to the
absence of the design logic, assumptions let you constrain these signals so that the
generated waveforms do not exhibit illegal behaviors.
1. Click Application – Task – Add Property.
The Add Property dialog appears.
2. Ensure Global is checked so that the assumption affects all tasks in the environment.
3. Type gnt_zero_onehot in the Name field.
4. Type the following expression to specify that the grant signal is always zero or
onehot:
$onehot0(gnt)
5. Click OK.
The global assumption shows in the list of properties in the Property Table. The figure
below shows a view that is available when you select the Task Table tab and then click
on the task v_arbiter_fairness.
JasperGold Apps provides Visualize for properties as a cover trace (reachable), sanity
trace (proven), or violation trace (counterexample found). A sanity trace shows a design
behavior that does not contradict the property, while a violation trace exhibits a failure of
the property.
1. Right-click the assertion property
arbiter.v_arbiter_fairness.a_arbiter_fairness and choose Visualize.
The Visualize dialog appears.
2. In the Visualize dialog, click OK to accept the default values.
The Visualize window appears showing the shortest violation trace based on the
proof environment. The waveform starts with the first cycle after reset. This point is
also defined as the initial state.
Add signals (Signal Browser tab), modify the signal order (drag-and-drop signals where
desired), and create signal groups (right-click on selected signal names and choose
Group from the menu) to obtain a waveform similar to the one shown in Figure 8.
Tip
All debugging features such as Why, trace explanation, and so on, are available
in the Visualize window. For example, doing Why on the property signal brings
up the source code view with context-sensitive information.
You can configure the Visualize trace in many ways. You can specify the minimum length
of the trace or constrain an expression to hold at a specific cycle. Figure 9 shows the
various configurations available and other features in the property visualization flow.
The following steps show how to configure the initial trace to make it more interesting.
The following steps show how to force an expression for all cycles.
1. Select signals req[2] and gnt[2] at cycle one.
3. Modify the expression to force that signal gnt[2] cannot be asserted if signal
req[2] is not asserted. Ensure All Cycles is checked.
4. Click OK.
5. Do the same for signals gnt[0] and req[0].
The following steps show how to force an expression after a specific cycle or at a specific
cycle.
1. Select signal gnt at cycle four.
4. Click OK.
5. Select signal gnt[0] at cycle six.
7. Click OK.
You can further configure the trace to lock known values, freeze all signal values to
concatenate a new behavior to the existing trace, and so on.
You can view the configuration for the current trace directly in the configuration pane.
You can undock this pane from the Visualize window or drag it to a new location in the
window. You can also add, edit, or remove configurations in the configuration pane with
the context menu (right-click).
JasperGold Apps generates a Visualize script for you to check whether a trace can be
computed when the properties change.
1. Click File – Save Visualize Configuration.
The Save Visualize Configuration dialog appears.
2. Enter the name of the Visualize script you want to save.
3. Click OK to accept the default options.
Using QuietTrace
The QuietTrace™ feature decreases the number of signals toggling at the boundary and
in the internal logic that are of no consequence to the behavior being illustrated.
1. In the Visualize window, click the Quiet Trace button.
2. In the Visualize window press F5 or click the Replot button to update the
waveform.
If you compare the QuietTrace to the previous trace (Figure 16), which is also displayed
in the side-by-side view in Figure 18, you can see that sample_transfer_ready and
other signals now have fewer transitions. The trace is less complicated and debugging
the failing condition is easier and faster than before. The Visualize Configuration pane
includes a tree node for Quiet data with figures that show, out of the total number of
soft constraints or preferences that were possible, how many were satisfied and how
many were not satisfied in the final waveform.
JasperGold Apps tries to compute a trace that exhibits the active configuration based on
the environment. Constraints and active configuration can cause the target expression to
become unreachable (no trace of the selected type can be found).
For example, using the last updated trace, add the following configuration:
3. Click OK.
JasperGold Apps shows that no violation trace could be found. Indeed, the last
configuration in combination with the configuration that signal gnt[0] cannot be
asserted without signal req[0] being asserted prevents the violation.
In the Command Line pane of the main window, type the following command to exit this
session:
% exit -force
Command Summary
The following table lists commands you used in this tutorial with their equivalent Tcl
commands and toolbar buttons.
References