Experiment No: 3

Aim: Implementation of CMOS Inverter layout using 0.25 Micron Technology and
Simulating with and without capacitive load and comment on the rise and fall
time.

Software: Microwind

Theory:
CMOS inverter consists of an enhancement type NMOS and PMOS transistor. It is
complementary push-pull in the sense that for high input the NMOS drives the
output mode while NMOs act as load. The CMOS has two important advantages.
i) It has negligible steady state power dissipation.
ii) The VTC exhibits a full output voltage swing between 0V and Vdd and that the
VTC transistor is usually very sharp.

For very low input voltage levels, the output voltage V is equal to the high value of VOH
(output high voltage). In this case, the driver nMOS transistor is in cut-off, and hence, does not
conduct any current. Consequently, the voltage drop across the load device is very small in
magnitude, and the output voltage level is high. As the input voltage V increases, the driver
transistor starts conducting a certain drain current, and the output voltage eventually starts to
decrease. Notice that this drop in the output voltage level does not occur abruptly, such as the
vertical drop assumed for the ideal inverter VTC, but rather gradually and with a finite slope.
We identify two critical voltage points on this curve, where the slope of the Vt(Vin)
characteristic becomes equal to -1, i.e.,

The smaller input voltage value satisfying this condition is called the input low voltage VIL and
the larger input voltage satisfying this condition is called the input high voltage VIH. Both of
these voltages play significant roles in determining the noise margins of the inverter circuit, as
we will discuss in the following sections. The physical justification for selecting these voltage
points will also be examined in the context of noise immunity. As the input voltage is further
increased, the output voltage continues to drop and reaches a value of VOL (output low voltage)
when the input voltage is equal to VOH. The inverter threshold voltage Vt., which is considered
as the transition voltage, is defined as the point where Vin. = Vout., on the VTC. Thus, a total of
five critical voltages, VOL, VOH' VIL' VIH, and Vth, characterize the DC input-output voltage
behavior of the inverter circuit. The functional definitions for the first four of these critical
voltages are given below.
VOH: Maximum output voltage when the output level is logic " 1"
VOL Minimum output voltage when the output level is logic "0"
VIL: Maximum input voltage which can be interpreted as logic "0"
VIH: Minimum input voltage which can be interpreted as logic " 1”

Circuit Diagram :-

Procedure :-
1. First select the Foundry you want to work on (0.25 micron ) and then select NMOS
from the palette in the microwind software and place it on the working space.
2. Similarly, place a PMOS whose current is equivalent to the current of NMOS by
varying the W/L ratio (aspect ratio).
3. Connect the gate of PMOS with the gate of NMOS with the help of polysilicon
material from the palette. Also, connect the drain of PMOS to the drain of NMOS
 by using Metal1 material from the palette.
4. Now connecting Vdd to the to the source of PMOS as well as to the n-well to avoid
the floating effect. Connect ground to the source of the NMOS.
5. Apply input using clock from the palette to the gate connection of the two MOSFET
and place a digital node between the drain connection of the two MOSFET.
Note: Both input and node should lie in the centre, it shouldn’t lie in any of the
regions of NMOS and PMOS.
6. Now, use DRC (Design Rule Checker) to check for errors then run and analyse the
different graphs.
7. To get the correct value of Vth we choose a new PMOS of different W/L ratio and
keep changing the value till we get Vth = Vdd/2 from the graph.
8. Place a capacitor of capacitance 0.001pF at the drain connection and analyse the
changes in the graphs.
Output Graph :-
1) CMOS Inverter

(a) Voltage vs Time

(c) Voltage vs Voltage

(a) Voltage vs Time

(c) Voltage vs Voltage

(a) Voltage vs Time

(c)Voltage vs Voltage
Conclusion :-
1. CMOS Inverter stands for “Complementary MOSFET Inverter” and it consists of two
enhancement type NMOS and PMOS transistor connected at the drain and gate
terminals.
2. It is called as inverter as it inverts/ complements the input and output.
3. The theoretical value of Vth is Vdd/2. which is not seen in the first graph of
CMOS inverter. Hence, we can remove the error of Vth != Vdd/2 by
varying W/L ratio(aspect ratio) of the PMOS till we get Vth = Vdd/2.
4. The rise time signifies the time during transition of CMOS from Min to Max value
and fall time signifies the time from Max to Min value.
5. The Power dissipation of the circuit increases when we connect a capacitor at
the output at drain connection of the two Mosfet.
6. The rise and fall time also increases when a load capacitor is added at the output as
seen
in the Voltage vs Time graph