HDL

Verilog
•Verilog was developed by Gateway Design
Automation as a proprietary language for logic
simulation in 1984.
•Gateway was acquired by Cadence in 1989
•Verilog was made an open standard in 1990 under
the control of Open Verilog International.
•The language became an IEEE standard in 1995
(IEEE STD 1364) and was updated in 2001 and
2005.
Verilog Key Featurers:
 Case sensitive - keywords are lower case
 Semicolons(;) are line terminators
 Concurrent execution
 Comments:
–One line comments start with // ...
–Multi-line comments start with /*and end
with*/
 System tasks and functions start with a dollar
sign, ex $display, $signed
 Verilog Syntax:

Example of And gate

module and2_1( X, A, B ) ;
output X ;
input A, B ;

assign X= A & B ;

endmodule

Logical values
•Logic with multilevel (0,1,X,Z) logic values
–Nand anything with 0 is 1
–Nand two get an X
•True tables define the how outputs are
compute
& 0 1 X Z
0 0 0 0 0
1 0 1 X X
X 0 X X X
Z 0 X X X
 Data types
1) Register :

Example: reg y;
2) Nets:

Example : wire X;
3) Integer: (integer)
–Convenient to counting purposes
–At least 32-bit wide
–Useful for loop
Example : integer i;
4) Real :(real) simulation only
–Can be specified in decimal and scientific
notation

5) vectors :
Know as BUS in hardware
 •Declare by a range following the type
<data type> [left range : right range] <Variable name>

•Single element that is n-bits wide

reg [0:7] A, B; //Two 8-bit reg with MSB as the 0th bit
wire [3:0] Data; //4-bit wide wire MSB as the 4th bit
example input [3:0] I;
•Vector part select (access)
A[5] // bit # 5 of vector A
Data[2:0] // Three LSB of vector Data
6) Array:
Array: range follows the name
<datatype> <array name> [<array indices>]
reg B [15:0]; // array of 16 reg elements
•Array of vectors

<data type> [<vector indices>]<array

name>[<array indices>]
reg [15:0] C [1023:0]; // array of vectors
•Memory access

<var name>[<array indices>] [<vector indices>]

7) Parameters:

Parameters are means of giving names to

constant values
•The values can be overridden when the
design is compiled
•Parameters cannot be used as variables
•Syntax:
parameter <name>=<constant expression>;
parameter n = 10;
 Operators in Verilog
1) Arithmetic Operators
Characte Operation
r performed
+ Add

- Subtract

/ Divide

* Multiply

% Modulus
2) Bitwise Operators
Characte Operation
r performed
~ Invert each bit
& And each bit
| Or each bit
^ Xor each bit
~^ Xnor each bit

3) Reduction Operator
Characte Operation
r performed
& And all bits
~& Nand all bits
| Or all bits
~| Nor all bits
^ Xor all bits
~^ Xnor all bits
 X=1100
Y= &X= 1&(1&(0&0))= 0
Z=^X=1^(1^(0^0))= 0
M=|X= 1|(1|(0|0))= 1
4) Boolean Operator
Characte
Operation performed
r
! Not true
&& Both expressions true
One ore both expressions
||
true
let x = 4'b1010, y =
4'b0000
 1) x | y //bitwise OR, result is 4'b1010
x || y //logical OR, result is 1
2) x&y=0000
x&&y // result 0
3) !x // result 1
4) !y // result 0

5) Relational Operator
Characte Operation
r performed
> Greater than
< Smaller than
Greater than or
>=
equal
 Smaller than or
<=
equal
== Equality
!= Inequality

let a = 4, b = 3, and...
x = 4'b1010, y = 4'b1101, z = 4'b1xxx
a <= b //evaluates to logical zero
a > b //evaluates to logical one
y >= x //evaluates to logical 1
y < z //evaluates to x
6) Shift Operator
Characte Operation
r performed
>> Shift right
 << Shift left

let x = 4'b1100
y = x >> 1; // y is 4'b0110
y = x << 1; // y is 4'b1000
y = x << 2; // y is 4'b0000

7) Other Operators
Characte Operation
r performed
?: Conditions testing
{} Concatenate

x=2’b11 z=2’b01
p=2’b11 q=2’b00
 1) assign Y = (x==z) p:q; // returned value is 0
2) assign big= (x>z) x:z; // result is x ie 11
3) Y={x,z} // result 1101
Assignment:
a = 4'b0011; b = 4'b0100; d = 6; e = 4; f = 2;
then,
a + b //add a and b;
b - a //subtract a from b;
a * b //multiply a and b;
d / e //divide d by e,
e ** f //raises e to the power f.
a = 4'b0011;
// b = 4'b0100;
// d = 6; e = 4; f = 2;
//then,
a + b //evaluates to 4'b0111
b - a // evaluates to 4'b0001
a * b // evaluates to 4'b1100
d / e // evaluates to 4'b0001. Truncates fractional part
e ** f // evaluates to 4'b1111

Replication Operator
Repetitive concatenation of the same number
Operands are number of repetitions, and the
bus or wire
let a = 1'b1, b = 2'b00, c = 2'b10, d = 3'b110
y = { 4{a} } // y = 4'b1111
y = { 4{a}, 2{b} } // y = 8'b11110000
y = { 4{a}, 2{b}, c } // y = 10'b1111000010

Description styles

1) Data flow: Boolean equation

2) Behavioral : TT or functionality
3) Gate level or Structural : circuit diagram
4) Switch level : nmos and pmos
 Data flow description:
 Simplest approach as long as expression is
small
 Boolean expression
 assign
 concurrent execution
 order of the expression in not imp
Half Adder

module HA ( S, Co, A, B ) ;
output S, Co ;
input A, B ;
assign Co = A & B ;
assign S = A ^ B ;
endmodule
 Behavioral Description:
 TT or Functional relationship between input
and output
 Output signal must be declared as reg
 reg S, Co ;
 always block
 conditional statements can be included
 sequential execution inside always block
 syntax of an always@

always @( sensitivity list )

begin

conditional statements(if, if else ,case, loop)

end
 Syntax of if
if (condition)
begin
statements;
end
 Syntax of if else
if (condition)
begin
statements1;
end
else
begin
statements2;
 end
Nested syntax of if else if
if (condition)
begin
statements1;
end
else if (condition2)
begin
statements2;
 end
else
begin
statements3;
end
 Syntax of a case statement
case (vector_signal)
< case1 > :begin < statements1>; end
< case2 > : begin < statements 2>; end
.....
.....
default : begin < statements >; end
endcase
mux 2:1 verilog program

module mux2_1 ( Y , S , I) ;
output Y ;
input S ;
input [1:0] I;
reg Y ;
always@( S , I )
begin
if (s==0)
begin
Y=I[0];
end
else
 begin
Y= I[1];
end
end
endmodule
Mux4:1 Verilog program

module mux4_1( Y, S, I ) ;
output Y ;
input [1:0] S ;
input [3:0] I ;

reg Y ;
always@( S, I )
begin
case( S )
2'b00 : begin Y = I[0]; end
2'b01 : begin Y = I[1]; end
2'b10 : begin Y = I[2]; end
2'b11: begin Y = I[3]; end
endcase
end
endmodule
module HA ( S, Co, A, B ) ;
output S, Co ;
input A, B ;
reg S, Co;
always@ ( A, B )
begin

case ( { B, A } )
2'b00: begin {Co,S}=2'b00; end
2'b01: begin {Co,S}=2'b01; end
2'b10: begin {Co,S}=2'b01; end
2'b11: begin {Co,S}=2'b10; end
endcase
end
endmodule

Delay Flip Flop / D Flip Flop

module dff ( q, qb, d, clk) ;
output q , qb ;
input d, clk ;
reg q , qb ;
always@( posedge clk )
begin
q=d;
qb = ~q ;
end
endmodule
 Gate level Description
 Internal structure of circuit (Gates)
 Instantiation of components
 Concurrent execution

Example : Half Adder

module HA (S, Co, A, B) ;
output S, Co;
input A, B ;
xor x1(S, A, B);
and x2(Co, A, B);
endmodule
Full adder

module fulladder (sum,cout, a, b, cin);

output sum, cout;
input a, b,cin;
wire n1,n2,n3;
xor u1(sum,a,b,cin);
and u2(n1,a,b);
and u3(n2,b,cin);
and u4(n3,a,cin);
or u5(cout,n1,n2,n3);
endmodule
And Or Invert circuit

module AOI(Y,A,B,C,D);
output y;
input A,B,C,D;
wire w1,w2,w3;
and x1(w1,A,B);
and x2(w2,C,D);
or x3(w3,w1,w2);
not x4(Y,w3);
endmodule
Switch level description
module inv ( in, out ) ;
output out ;
input in ;
supply0 a ;
supply1 b ;
nmos ( out, a, in );
pmos ( out, b, in );
endmodule
 1) Data flow method

module mux4_1(Y,S1,S0,I0,I1,I2,I3);
output Y;
input S1,S0,I0,I1,I2,I3;
wire w1,w2,w3,w4;
assign w1=(~S1)&(~S0)&I0;
assign w2=(~S1)&S0&I1;
assign w3=S1&(~S0)&I2;
assign w4=S1&S0&I3;
assign Y=w1 | w2| w3|w4;
endmodule
 2) BEHAVIOURAL DESCRIPTION

module mux4_1(Y,S1,S0,I0,I1,I2,I3);
output Y;
input S1,S0,I0,I1,I2,I3;
reg Y;
always@(S0,S1,I0,I1,I2,I3)
begin
case({S1,S0})
2’B00: begin Y=I0; end
2’B01: begin Y=I1; end
2’B10: begin Y=I2; end
2’B11: begin Y=I3; end
endcase
end
endmodule
Gate level description

module mux4_1(Y,S1,S0,I0,I1,I2,I3);
output Y;
input S1,S0,I0,I1,I2,I3;
wire w1,w2,w3,w4,w5,w6;
or x7(Y, w3,w4,w5,w6);
and x6 (w6,S0,S1,I3);
and x5 (w5,w1,S1,I2);
and x4 (w4,S0,w2,I1);
and x3 (w3,w1,w2,I0);
not x1 (w1,S0);
not x2 (w2,S1);
endmodule

module mux2_1(out,i0,i1,s0);
output out;
input i0,i1,s0;
not x4(w1,s0);
and x1(w2,i0,w1);
and x2(w3,i1,s0);
or x3(out,w2,w3);
endmodule
Logic synthesis
Verilog Signal-Assignment Statement Y = 2 * X + 3 input is of 2 bit
vector

module sign_assn2 (X, Y);

input [1:0] X;
output [3:0] Y;
reg [3:0] Y;
always @ (X)
begin
Y = 2 * X + 3;
end
endmodule