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Solution: Mid-Term Exam

The document contains solutions to 5 questions on a mid-term exam for a computer architecture course. 1. The first question discusses how a new computer design may simulate lower device and logic levels on an older machine, putting them at a higher simulation level. 2. The second question provides the address table, decoding bits, and scheme for a memory with a capacity of 32KB using chips of 8KB and 16KB. 3. The third question proves De Morgan's laws for AND and OR logic forms using truth tables.

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Mai Anh Thư
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65 views3 pages

Solution: Mid-Term Exam

The document contains solutions to 5 questions on a mid-term exam for a computer architecture course. 1. The first question discusses how a new computer design may simulate lower device and logic levels on an older machine, putting them at a higher simulation level. 2. The second question provides the address table, decoding bits, and scheme for a memory with a capacity of 32KB using chips of 8KB and 16KB. 3. The third question proves De Morgan's laws for AND and OR logic forms using truth tables.

Uploaded by

Mai Anh Thư
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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MID-TERM EXAM

Subject: Computer Architecture


1st semester, school year: 2007-2008
--------------------------------------------------

SOLUTION
1. Can you imagine any multilevel computer in which the device level and digital
logic levels were not the lowest levels? Explain.
Solution:

During the detailed design of a new computer, the device and digital logic levels
of the new machine may well be simulated on an old machine, which puts them
around level 5 or 6. At that time, we must have a software for simulating the
device or circuits with the appropriate function. (10 p.)

2. Design the decoder for a memory with the capacity of 32 KB from memory chips:
2 chips of 8 KB, 1 chip of 16 KB.
Note that: You need to present the address table, bits for decoding, and the
scheme.
Solution:

We arrange memory chips by the order (we may have different arrangements): 8
KB (M0), 8 KB (M1), 16 KB (M2).
The address table: (10 p.)

A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

M0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
(8KB) 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1

M1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
(8KB) 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1

M2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
(16KB) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

From the address table above, we use 2 address bits A14 and A13 to decode the
chip selection. The decoder 2->4 (74139) is with 3 inputs A14, A13, A14 is the
MSB (5 p.), its outputs
- 00 is for M0
- 01 is for M1 (10 p.)
- 03 and 04 are ORed for M2
3. In Figure 3-6 (page 144 in the text book) there is De Morgan’s law with
- AND form: A B = A + B
- OR form: A + B = A B
Prove them.
Solution:

The truth table for both of forms is


A B A B AB A+ B AB A+B
0 0 1 1 1 1 1 1
0 1 1 0 1 1 0 0
1 0 0 1 1 1 0 0
1 1 0 0 0 0 0 0
(1) (2) (3) (4)

From the columns (1) and (2) we can see the De Morgan’s law in the form of
AND is true (10 p.).
The same thing for OR form. (10 p.)

4. In Figure 4-2 (page 234 in the text book), prove the functions following:

F0 F1 ENA ENB INVA INC Function


1 1 1 1 0 1 A+B+1
1 1 1 0 0 1 A+1

Prove them with the appropriate values.


Solution:

- Function: A + B + 1
F0 = 1, F1 = 1: addition
ENA = 1: A: 1st input
ENB = 1: B: 2nd input
INVA = 0; no inversion
Æ Result = A + B
INC = 1: increment the result: Result = A + B + 1
(10 p.)
- Function: A + 1
F0 = 1, F1 = 1: addition
ENA = 1: A: 1st input
ENB = 0: B = 0
INVA = 0; inversion
Æ Result = A
INC = 1: increment the result: Result = A + 1
(10 p.)
The appropriate value:
With the format of 8 bit, A = 0000 0000, B = 0000 0001,
Result = A + B + 1 = 0000 0000 + 0000 0001 + 1 = 0000 0010
Result = A + 1 = 0000 0000 + 1 = 0000 0001
(5 p.)

5. Explain the function of the register MPC in the complete block diagram of
microarchitecture in Figure 4-6 (page 242 in the text book)? What does it
contain? What does it point to? Can we have the different mechanism to organize
the diagram without MPC? Explain.
Solution:

The register MPC (Micro Program Counter) contains the address of next
microinstruction in the diagram of microarchitecture (Figure 4-6). After being
translated, the instructions of the program in ISA level will be executed, these
instructions are in form of 36-bit microinstructions in the control store (ROM) in
CPU. The register MPC is used to know what being needed to do next, i.e it
points to the next microinstruction. (10 p.)
Yes, we can. We have 2 cases: (10 p.)
1. We don’t use the control store to store the microprogram. With this case the
program in high level language can be executed directly by the appropriate
hardware.
2. We can use the control store without MPC if the microprogram in it is
arranged in the order of tasks appropriately with the opcode of instructions,
that means the opcode is as the code for the decoder to choose the
microprogram.

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