AOS Week3n4b
AOS Week3n4b
AOS Week3n4b
Interrupt Latency
The interrupt latency is the interval of time measured from the instant an
interrupt is asserted until the corresponding ISR begins to execute.
Synchronous Asynchronous
Device-Status Table
Direct Memory Access Structure
• Involvement of CPU in data transfer is a time-
consuming process. If the CPU needs two
microseconds to respond to each interrupt and
interrupts arrive every four microseconds then less
time is left for process execution.
• DMA is used for high-speed I/O devices able to
transmit information at close to memory speeds.
• Device controller transfers blocks of data from buffer
storage directly to main memory without CPU
intervention.
• Only one interrupt is generated per block, rather than
the one interrupt per byte.
Direct Memory Access Structure
• DMA controller has its own registers for source and
destination addresses
• A device driver sets the DMA controller registers to
use the appropriate source and destination
addresses, transfer length and it is then instructed to
starts I/O operation
• While the DMA controller is performing the data
transfer, the CPU is free to perform other tasks
• As the DMA controller steals memory cycles from the
CPU so it slows down CPU execution during DMA
operation
• DMA interrupts the CPU when the transfer has been
completed
Issue Read Issue Read
command to
CPU --> I/O command to
CPU --> I/O
Issue Read CPU--> DMA
I/O Module I/O Module
Do something Block Command
else to I/O Module Do something
Read Status Read Status else
I/O --> CPU Interpret
of I/O of I/O
Module Module I/O --> CPU
Not
ready Interpret
Read Status
Check Error Check Error
Condition Condition
of DMA
status status
Module
DMA --> CPU
ready
Read word Read word
from I/O I/O --> CPU from I/O I/O --> CPU
Module Module Next Instruction
(c) direct memory access
Write Word Write Word
Into Memory CPU --> Memory Into Memory CPU --> Memory
No No
Done? Done?
yes yes
X X X
Hardware Protection
Dual-Mode Operation
I/O Protection
Memory Protection
CPU Protection
DUAL MODE OPERATION
• Sharing of system resources improved CPU utilization
but increased problems. Many jobs could be affected by
a bug in one program.
• A good OS must ensure that a faulty program cannot
cause other programs to execute incorrectly.
• If a user program fails, the hardware will trap to OS, the
OS dumps the memory of the program for debugging and
terminates it.
• The hardware-supported dual-mode operation protects
the OS, all other programs and their data from any
malfunctioning program.
) User-mode of operation (mode-bit is 1).
) Monitor/supervisor/system mode of operation (mode-bit is 0).
• Whenever an interrupt or trap occurs, the hardware
switches from user-mode to monitor-mode. OS is in the
monitor-mode.
Dual-Mode Operation
• The dual-mode of operation provides us with
the means for protecting the OS from errant
users and errant users from one another.
• The hardware allows privileged instructions
(e.g. system call) to be executed only in
monitor mode.
• When an interrupt or fault occurs hardware
switches to monitor mode.
Interrupt/fault
monitor user
set user mode
I/O Protection
All I/O instructions are defined as privileged
instructions so users cannot issue I/O instructions
from user mode.
Must ensure that a user program could never gain
control of the computer in monitor mode (i.e., a user
program that, as part of its execution, stores a new
address in the interrupt vector).
To do I/O, a user programme executes a system call to
request that the OS perform I/O on its behalf and
returns the control to the users after completion of I/O
operation.
Use of a System Call to Perform I/O
Memory Protection
Must provide memory protection for the interrupt
vector, the interrupt service routines and user
programs from one another.
In order to have memory protection, two registers are
used to determine the range of legal addresses a
program may access:
) Base register – holds the smallest legal physical memory
address.
) Limit register – contains the size of the range
Memory outside the defined range is protected.
A trap is generated if any user’s program attempts to
access unauthorized memory area.
When executing in monitor mode, the operating
system has unrestricted access to both monitor and
user’s memory.
The load instructions for the base and limit registers
are privileged instructions.
Use of a Base and Limit Register
Hardware Address Protection
CPU Protection
A user program may:
) be stuck in an infinite loop
) fail to call system services
) fail to return control to the OS
Timer – interrupts computer after specified period to
ensure operating system maintains control.
) Timer is decremented every clock tick.
) When timer reaches the value 0, an interrupt occurs and
control is automatically transferred to the OS.
Timer is also commonly used to implement time
sharing mechanism.
Time can be used to compute the current time.
Load-timer is a privileged instruction.
Network Structure
Local Area Networks (LAN)
) LANs were introduced in 1970 for economical use of a
number of small computers and sharing of computer
resources.
) LANs cover a small geographical area and are
generally used in an office environment.
) Communication links of LANs have a higher speed
and lower error rate.
) High-quality cables (TP, Fiber Optic etc) are used for
establishment of LANs.
) Common topologies are bus, ring and star.
) Communications speed range from Mbps to Gbps.
) A typical LAN may consist of PCs/Laptops/PDAs,
shared peripheral devices and one or more gateways.
Local Area Network Structure
Network Structure
Wide Area Networks (WAN)
) WANs emerged in the late 1960s to provide efficient communication among sites.
) WANs are physically distributed over a large geographical area.
) Hardware and software resources are shared conveniently and economically by a wide
community of users.
) ARPANet grew from four sites to millions of sites using internet.
) The communication links (telephone lines, leased lines, microwave links, satellite
channels etc) are relatively slow and less reliable.
) Communication processors control the communication links for transferring information
among the various sites.
) The internet WAN provide the ability for hosts at geographically separated sites to
communicate with one another.
) The host computers differ from each other in type, speed, word length, operating system
etc.
) Connections between networks use a telephone-system service to provide
communication:
T1 service provides a transfer rate of 1.544 Mbps
T2 service provides a transfer rate of 6.312 Mbps
T3 service provides a transfer rate of 44.736 Mbps
T4 service provides a transfer rate of 274.176 Mbps
)The router control the path each message takes through the net. Dynamic routing
enhances communication efficiency whereas static routing reduces security risks.
)Modems convert digital data to analog signals and vice versa for communication.
)WANs are slower than LANs (1200 bps to 1 Mbps) and uses PPP for connecting
computers to the internet.