DSPIS

Serial Peripheral Interface –Slave

ver 1.05

master. Transmission is ended when the SS

OVERVIEW line goes high.
The DSPIS is a fully configurable SPI ma The DSPIS is a technology independent
slave device, designated to operate with pas- design that can be implemented in a variety of
sive devices like memories, LCD drivers etc. process technologies.
The DSPIS allows user to configure polarity
and phase of serial clock signal SCK. DSPIS is fully customizable, which means
A serial clock line (SCK) synchronizes shift- it is delivered in the exact configuration to
ing and sampling of the information on the two meet users’ requirements. There is no need to
independent serial data lines. DSPIS data are pay extra for not used features and wasted
simultaneously transmitted and received. silicon. It includes fully automated testbench
The DSPIS system is flexible enough to in- with complete set of tests allowing easy
terface directly with numerous standard prod- package validation at each stage of SoC de-
uct peripherals from several manufacturers. sign flow.
Data rates as high as CLK/4. Clock control
logic allows a selection of clock polarity and a
choice of two fundamentally different clocking APPLICATIONS
protocols to accommodate most available ● Embedded microprocessor boards
synchronous serial peripheral devices.
● Consumer and professional audio/video
The DSPIS allows the SPI Master to com-
municate with passive devices. When trans- ● Home and automotive radio
mission starts (SS Line goes low) the first por- ● Digital multimeters
tion of data is copied to the address register
and then to the ADDRESS bus output, after
transmission of the address the DSPIS gener-
ates the read signal (RD) and copy DATAI bus
contents to the transmitter shift register, and
prepare data to be exchanged with SPI Mas-
ter. During the next data portion transmission
DSPIS simultaneously transmits data out and
in. When the first data portion is received the
DSPIS asserts DATAO bus generates the
write signal (WE), then increments ADDRESS
bus performs a read operation and prepare
another data portion to be exchanged with SPI

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 KEY FEATURES LICENSING
● SPI Slave Comprehensible and clearly defined licensing
○ Slave operation
methods without royalty fees make using of IP
Core easy and simply.
○ Automatic read and write operations
Single Design license allows use IP Core in
○ Automatic address incrementation after any single FPGA bitstream and ASIC implementa-
data portion transfer tion.
○ Configurable address and data length.
Unlimited Designs, One Year licenses allow
○ Configurable SCK phase and polarity. use IP Core in unlimited number of FPGA bit-
○ Supports speeds up ¼ of system clock streams and ASIC implementations.
○ Simple interface allows easy connection to In all cases number of IP Core instantiations
passive devices, and SPI Master within a design, and number of manufactured
chips are unlimited. There is no time restric-
● Fully synthesizable, static synchronous
tion except One Year license where time of
design with no internal tri-states
use is limited to 12 months.
● Single Design license for
DELIVERABLES ○ VHDL, Verilog source code called HDL
♦ Source code: Source
◊ VHDL Source Code or/and
○ Encrypted, or plain text EDIF called Netlist
◊ VERILOG Source Code or/and
◊ Encrypted, or plain text EDIF netlist ● One Year license for
♦ VHDL & VERILOG test bench environ- ○ Encrypted Netlist only
ment
◊ Active-HDL automatic simulation macros ● Unlimited Designs license for
◊ ModelSim automatic simulation macros ○ HDL Source
◊ Tests with reference responses
○ Netlist
♦ Technical documentation
◊ Installation notes ● Upgrade from
◊ HDL core specification
○ HDL Source to Netlist
◊ Datasheet
♦ Synthesis scripts ○ Single Design to Unlimited Designs
♦ Example application
♦ Technical support
◊ IP Core implementation support
◊ 3 months maintenance
● Delivery the IP Core updates, minor
and major versions changes
● Delivery the documentation updates
● Phone & email support

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Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.

 ments. The flexibility of the SPI system on the
SYMBOL DSPIS allows direct interface to almost any
clk existing synchronous serial peripheral.
rst Shift register– is a central element in the SPI
datai(D:0) datao(D:0) system. When an SPI transfer occurs, an 8-bit
address(A:0) character is shifted out on data pin while a
cpha rd
different 8-bit character is simultaneously
cpol we
shifted in a second data pin. Another way to
sck so view this transfer is that an 8-bit shift register
in the master and another 8-bit shift register in
si the slave are connected as a circular 16-bit
ss shift register. When a transfer occurs, this
distributed shift register is shifted eight bit po-
sitions; thus, the characters in the master and
slave are effectively exchanged.
PINS DESCRIPTION
PIN TYPE DESCRIPTION clk cpha
rst SPI Clock Logic cpol
clk input Global clock sck
rst input Global reset
datai(D:0) input Data bus input MSB LSB
so Shift Reg. si
cpha input SCK clock phase
cpol input SCK clock polarity
sck input SPI serial clock
datai Data reg. ss
si input SPI serial data input SPI datao
Controller address
ss input Slave select we
datao(D:0) output Data bus output Adr. reg. rd
addres(A:0) output Address bus output
rd output Read output Data Register holds data read from passive
we output Write enable device and to be sent serially to the SPI Mas-
ter.
so output Slave serial data output
Address Register holds address presented
on Address bus. it’s contents is incremented
BLOCK DIAGRAM every single data portion sent/received serially
SPI Clock logic controls phase and polarity of through the SPI bus.
the SCK clock line, and detects correct sam- SPI Controller - detects begin and end of SPI
ple and shift edge for the Shift register. SPI transfer. Manages data exchange between
clock Logic allow user to select any of four DSPIS and passive device controlled by
combinations of serial clock (SCK) phase and DSPIS, and increment Address Register
polarity using two pins CPHA and CPOL. The (SPAD) after any successful transfer.
clock polarity is specified by the CPOL, which
selects an active high or active low clock and
has no significant effect on the transfer format.
The clock phase CPHA selects one of two
fundamentally different transfer formats. The
clock phase and polarity should be identical
for the master SPI device and the communi-
cating slave device. In some cases, the phase
and polarity are changed between transfers to
allow a master device to communicate with
peripheral slaves having different require-
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are trademarks of their respective owners. http://www.dcd.pl

Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.

 PERFORMANCE
The following table gives a survey about the
Core area and performance in the LATTICE®
devices after Place & Route (all key features
have been included):
Speed
Device LUTs/PFUs Fmax
grade
XP -5 94 / 55 219 MHz
ECP -5 94 / 55 226 MHz
EC -5 94 / 55 222 MHz
XP2 -7 69 / 49 306 MHz
ECP2 -7 90 / 55 324 MHz
ECP2M -7 69 / 49 345 MHz
SC -7 84 / 55 489 MHz
Core performance in LATTICE® devices

Transfer Formats
Software can select any of four combinations of serial clock (SCK) phase and polarity using two
bits in the SPI control register (SPCR). The clock polarity is specified by the CPOL control bit,
which selects an active high or active low clock and has no significant effect on the transfer format.
The clock phase (CPHA) control bit selects one of two fundamentally different transfer formats.
The clock phase and polarity should be identical for the master SPI device and the communicating
slave device. In some cases, the phase and polarity are changed between transfers to allow a
master device to communicate with peripheral slaves having different requirements. The flexibility
of the SPI system on the DSPI allows direct interface to almost any existing synchronous serial
peripheral.
SC K C Y C L E# 1 2 3 4 5 6 7 8

SC K (C PO L=0)

SC K (C PO L=1)

M O SI M SB 6 5 4 3 2 1 LSB

M ISO M SB 6 5 4 3 2 1 LSB

SS

SC K C YC L E# 1 2 3 4 5 6 7 8

SCK (CPO L=0)

SC K (C PO L=1)

M O SI M SB 6 5 4 3 2 1 LSB

M ISO M SB 6 5 4 3 2 1 LSB

SS

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 CONTACTS
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Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.