Dual, Interleaved, Step-Down DC-to-DC Controller With Tracking

Dual, Interleaved, Step-Down
DC-to-DC Controller with Tracking

Data Sheet ADP1823
FEATURES TYPICAL APPLICATION CIRCUIT
IN = 12V
Fixed-frequency operation: 300 kHz, 600 kHz, or
synchronized operation up to 1 MHz 180µF 180µF
1µF
Supply input range: 3.7 V to 20 V EN1
PV IN
Wide power stage input range: 1 V to 24 V TRK1 EN2
Interleaved operation results in smaller, low cost input TRK2
VREG
capacitor
BST2
All-N-channel MOSFET design for low cost 0.47µF
BST1 0.47µF
±0.85% accuracy at 0°C to 70°C IRLR7807Z DH1 DH2 IRLR7807Z

Soft start, thermal overload, current-limit protection ADP1823
10 µA shutdown supply current 1.2V,
6A
2.2µH 2.2µH 1.8V,
8A
Internal linear regulator SW1 SW2
2kΩ 2kΩ
Lossless RDSON current-limit sensing 560µF CSL1 CSL2 560µF
DL1 DL2 2kΩ
Reverse current protection during soft start for handling 2kΩ
IRFR3709Z
IRFR3709Z
precharged outputs PGND2
Independent Power OK (POK) outputs PGND1

FB2
390pF
Voltage tracking for sequencing or DDR termination FB1 COMP2 1kΩ
Available in a 5 mm × 5 mm, 32-lead LFCSP 390pF
2kΩ COMP1
APPLICATIONS FREQ
3900pF 4.53kΩ
Telecommunications and networking systems 4.53kΩ 3900pF

LDOSD
Medical imaging systems GND SYNC
Base station power
05936-001
Set-top boxes
Printers Figure 1.
DDR termination
GENERAL DESCRIPTION
The ADP1823 is a versatile, dual, interleaved, synchronous, component size and cost. For noise sensitive applications, it can
PWM buck controller that generates two independent output also be synchronized to an external clock to achieve switching
rails from an input of 3.7 V to 20 V, with a power input voltage frequencies between 300 kHz and 1 MHz. The ADP1823 includes
that ranges from 1 V to 24 V. Each controller can be configured soft start protection to prevent inrush current from the input
to provide output voltages from 0.6 V to 85% of the input voltage supply during startup, reverse current protection during soft
and is sized to handle large MOSFETs for point-of-load regulators. start for precharged outputs, as well as a unique adjustable
The two channels operate 180° out of phase, reducing stress on lossless current-limit scheme using external MOSFET sensing.
the input capacitor and allowing smaller, low cost components. For applications requiring power supply sequencing, the
The ADP1823 is ideal for a wide range of high power applications, ADP1823 also provides tracking inputs that allow the output
such as DSP and processor core input/output power, and general- voltages to track during startup, shutdown, and faults. This
purpose power in telecommunications, medical imaging, PCs, feature can also be used to implement DDR memory bus
gaming, and industrial applications. termination.
The ADP1823 operates at a pin-selectable, fixed switching The ADP1823 is specified over the −40°C to +125°C junction
frequency of either 300 kHz or 600 kHz, minimizing external temperature range and is available in a 32-lead LFCSP.
Rev. E Document Feedback

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Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
ADP1823 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1 Tracking ....................................................................................... 14
Applications ....................................................................................... 1 MOSFET Drivers ........................................................................ 15
Typical Application Circuit ............................................................. 1 Current Limit .............................................................................. 15
General Description ......................................................................... 1 Applications Information .............................................................. 16
Revision History ............................................................................... 2 Selecting the Input Capacitor ................................................... 16
Specifications..................................................................................... 3 Selecting the MOSFETs ............................................................. 17
Absolute Maximum Ratings............................................................ 5 Setting the Current Limit .......................................................... 18
ESD Caution .................................................................................. 5 Feedback Voltage Divider ......................................................... 18
Functional Block Diagram .............................................................. 6 Compensating the Voltage Mode Buck Regulator ................. 19
Pin Configuration and Function Descriptions ............................. 7 Soft Start ...................................................................................... 22
Typical Performance Characteristics ............................................. 9 Voltage Tracking ......................................................................... 22
Theory of Operation ...................................................................... 13 Coincident Tracking .................................................................. 23
Input Power ................................................................................. 13 Ratiometric Tracking ................................................................. 23
Start-Up Logic ............................................................................. 13 Thermal Considerations............................................................ 24
Internal Linear Regulator .......................................................... 13 PCB Layout Guidelines .................................................................. 25
Oscillator and Synchronization ................................................ 13 LFCSP Considerations ............................................................... 26
Error Amplifier ........................................................................... 14 Application Circuits ....................................................................... 27
Soft Start ...................................................................................... 14 Outline Dimensions ....................................................................... 29
Power OK Indicator ................................................................... 14 Ordering Guide .......................................................................... 29
REVISION HISTORY
4/16—Rev. D to Rev. E Changes to Setting the Current Limit Section............................ 18
Changes to Figure 3 and Table 3 ..................................................... 7 Changes to Compensating the Voltage Mode Buck
Updated Outline Dimensions ....................................................... 29 Regulator Section ........................................................................... 19
Changes to Ordering Guide .......................................................... 29 Inserted Figure 25 ........................................................................... 19
Deleted Table 4................................................................................ 27
10/07—Rev. C to Rev D Changes to Application Circuits Section..................................... 27
Changes to Table 1 ............................................................................ 3 Changes to Figure 34...................................................................... 27
Changes to Equation 33 and Type III Compensator Section ... 21
11/06—Rev. 0 to Rev. A
7/07—Rev. B to Rev C Changes to Features and Applications Sections ............................1
Changes to Figure 34 ...................................................................... 27 Changes to Specifications Section ...................................................3
Changes to Absolute Maximum Ratings Section ..........................5
5/07—Rev. A to Rev. B Replaced Theory of Operation Section ....................................... 13
Changes to Features Section............................................................ 1 Added Feedback Voltage Divider Section ................................... 18
Changes to General Description Section ...................................... 1 Changes to Ratiometric Tracking Section................................... 23
Changes to Power Supply and Logic Thresholds Sections .......... 3 Replaced PCB Layout Guidelines Section ................................... 25
Changes to Absolute Maximum Ratings Section ......................... 5 Added Application Circuits Section ............................................ 29
Changes to Figure 17 ...................................................................... 11 Changes to Ordering Guide .......................................................... 31
Changes to Theory of Operation Section .................................... 13
Changes to Current Limit Section................................................ 15 4/06—Revision 0: Initial Version
Rev. E | Page 2 of 32
Data Sheet ADP1823
SPECIFICATIONS
IN = 12 V, ENx = FREQ = PV = VREG = 5 V, SYNC = GND, TJ = −40°C to +125°C, unless otherwise specified. All limits at temperature
extremes are guaranteed via correlation using standard statistical quality control (SQC). Typical values are at TA = 25°C.
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
POWER SUPPLY
IN Input Voltage PV = VREG (using internal regulator) 5.5 20 V
IN = PV = VREG (not using internal regulator) 3.7 5.5 V
IN Quiescent Current Not switching, IVREG = 0 mA 1.5 3 mA
IN Shutdown Current EN1 = EN2 = GND 10 20 μA
VREG Undervoltage Lockout Threshold VREG rising 2.4 2.7 2.9 V
VREG Undervoltage Lockout Hysteresis 0.125 V
ERROR AMPLIFIER
FB1, FB2 Regulation Voltage TA = 25°C, TRK1, TRK2 > 700 mV 597 600 603 mV
TJ = 0°C to 85°C, TRK1, TRK2 > 700 mV 591 609 mV
TJ = −40°C to +125°C, TRK1, TRK2 > 700 mV 588 612 mV
TJ = 0°C to 70°C, TRK1, TRK2 > 700 mV 595 605 mV
FB1, FB2 Input Bias Current 100 nA
Open-Loop Voltage Gain 70 dB
Gain-Bandwidth Product 20 MHz
COMP1, COMP2 Sink Current 600 μA
COMP1, COMP2 Source Current 120 μA
COMP1, COMP2 Clamp High Voltage 2.4 V
COMP1, COMP2 Clamp Low Voltage 0.75 V
LINEAR REGULATOR
VREG Output Voltage TA = 25°C, IVREG = 20 mA 4.85 5.0 5.15 V
IN = 7 V to 20 V, IVREG = 0 mA to 100 mA, 4.75 5.0 5.25 V
TA = −40°C to +85°C
VREG Load Regulation IVREG = 0 mA to 100 mA, IN = 12 V −40 mV
VREG Line Regulation IN = 7 V to 20 V, IVREG = 20 mA 1 mV
VREG Current Limit VREG = 4 V 220 mA
VREG Short-Circuit Current VREG < 0.5 V 50 140 200 mA
IN to VREG Dropout Voltage IVREG = 100 mA, IN < 5 V 0.7 1.4 V
VREG Minimum Output Capacitance 1 μF
PWM CONTROLLER
PWM Ramp Voltage Peak SYNC = GND 1.3 V
DH1, DH2 Maximum Duty Cycle FREQ = GND (300 kHz) 85 90 %
DH1, DH2 Minimum Duty Cycle FREQ = GND (300 kHz) 1 3 %
SOFT START
SS1, SS2 Pull-Up Resistance SS1, SS2 = GND 90 kΩ
SS1, SS2 Pull-Down Resistance SS1, SS2 = 0.6 V 6 kΩ
SS1, SS2 to FB1, FB2 Offset Voltage SS1, SS2 = 0 mV to 500 mV −45 mV
SS1, SS2 Pull-Up Voltage 0.8 V
TRACKING
TRK1, TRK2 Common-Mode Input Voltage Range 0 600 mV
TRK1, TRK2 to FB1, FB2 Offset Voltage TRK1, TRK2 = 0 mV to 500 mV −5 +5 mV
TRK1, TRK2 Input Bias Current 100 nA
ADP1823 Data Sheet
Parameter Test Conditions/Comments Min Typ Max Unit
OSCILLATOR
Oscillator Frequency SYNC = FREQ = GND (fSW = fOSC) 240 300 370 kHz
SYNC = GND, FREQ = VREG (fSW = fOSC) 480 600 720 kHz
SYNC Synchronization Range 1 FREQ = GND, SYNC = 600 kHz to 1.2 MHz (fSW = fSYNC/2) 300 600 kHz
FREQ = VREG, SYNC = 1.2 MHz to 2 MHz (fSW = fSYNC/2) 600 1000 kHz
SYNC Minimum Input Pulse Width 200 ns
CURRENT SENSE
CSL1, CSL2 Threshold Voltage Relative to PGND −30 0 +30 mV
CSL1, CSL2 Output Current CSL1, CSL2 = PGND 44 50 56 μA
Current Sense Blanking Period 100 ns
GATE DRIVERS
DH1, DH2 Rise Time CDH = 3 nF, VBST − VSW = 5 V 15 ns
DH1, DH2 Fall Time CDH = 3 nF, VBST − VSW = 5 V 10 ns
DL1, DL2 Rise Time CDL = 3 nF 15 ns
DL1, DL2 Fall Time CDL = 3 nF 10 ns
DH to DL, DL to DH Dead Time 40 ns
LOGIC THRESHOLDS
SYNC, FREQ, LDOSD Input High Voltage 2.2 V
SYNC, FREQ, LDOSD Input Low Voltage 0.4 V
SYNC, FREQ Input Leakage Current SYNC, FREQ = 0 V to 5.5 V 1 μA
LDOSD Pull-Down Resistance 100 kΩ
EN1, EN2 Input High Voltage IN = 3.7 V to 20 V 2.0 V
EN1, EN2 Input Low Voltage IN = 3.7 V to 20 V 0.8 V
EN1, EN2 Current Source EN1, EN2 = 0 V to 3.0 V −0.05 −0.6 −1.5 μA
EN1, EN2 Input Impedance to 5 V Zener EN1, EN2 = 5.5 V to 20 V 100 kΩ
THERMAL SHUTDOWN
Thermal Shutdown Threshold 2 145 °C
Thermal Shutdown Hysteresis2 15 °C
POWER GOOD
FB1, UV2 Overvoltage Threshold VFB1, VUV2 rising 750 mV
FB1, UV2 Overvoltage Hysteresis 50 mV
FB1, UV2 Undervoltage Threshold VFB1, VUV2 rising 550 mV
FB1, UV2 Undervoltage Hysteresis 50 mV
POK1, POK2 Propagation Delay 8 μs
POK1, POK2 Off Leakage Current VPOK1, VPOK2 = 5.5 V 1 μA
POK1, POK2 Output Low Voltage IPOK1, IPOK2 = 10 mA 150 500 mV
UV2 Input Bias Current 10 100 nA
1
SYNC input frequency is 2× the single-channel switching frequency. The SYNC frequency is divided by 2, and the separate phases were used to clock the controllers.
2
Guaranteed by design and not subject to production test.
Data Sheet ADP1823
ABSOLUTE MAXIMUM RATINGS

Table 2. Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
Parameter Rating
stress rating only; functional operation of the product at these
IN, EN1, EN2 −0.3 V to +20 V
or any other conditions above those indicated in the operational
BST1, BST2 −0.3 V to +30 V
section of this specification is not implied. Operation beyond
BST1, BST2 to SW1, SW2 −0.3 V to +6 V
the maximum operating conditions for extended periods may
CSL1, CSL2 −1 V to +30 V
affect product reliability.
SW1, SW2 −2 V to +30 V
DH1 SW1 − 0.3 V to BST1 + 0.3 V
DH2 SW2 − 0.3 V to BST2 + 0.3 V ESD CAUTION
DL1, DL2 to PGND −0.3 V to PV + 0.3 V
PGND to GND ±2 V
LDOSD, SYNC, FREQ, COMP1, −0.3 V to +6 V
COMP2, SS1, SS2, FB1, FB2, VREG,
PV, POK1, POK2, TRK1, TRK2
θJA 4-Layer 45°C/W
(JEDEC Standard Board) 1, 2
Operating Ambient Temperature −40°C < TA < +85°C
Range
Operating Junction Temperature −55°C < TJ < +125°C
Range 3
Storage Temperature Range −65°C to +150°C
1
Measured with exposed pad attached to PCB.
2
Junction-to-ambient thermal resistance (θJA) of the package is based on
modeling and calculation using a 4-layer board. The junction-to-ambient
thermal resistance is application and board-layout dependent. In applications
where high maximum power dissipation exists, attention to thermal
dissipation issues in board design is required. For more information, refer
to the AN-772 Application Note, A Design and Manufacturing Guide for the
Lead Frame Chip Scale Package (LFCSP).
3
In applications where high power dissipation and poor package thermal
resistance are present, the maximum ambient temperature may have to be
derated. Maximum ambient temperature (TA_MAX) is dependent on the
maximum operating junction temperature (TJ_MAX_OP = 125oC), the maximum
power dissipation of the device in the application (PD_MAX), and the junction-
to-ambient thermal resistance of the part/package in the application (θJA),
and is given by: TA_MAX = TJ_MAX_OP − (θJA × PD_MAX).
ADP1823 Data Sheet
FUNCTIONAL BLOCK DIAGRAM

IN
ADP1823
VREG LINEAR REG
0.6V 0.75V
0.8V REF 0.55V

UVLO THERMAL
SHUTDOWN
VREG BST1
VREG
LDOSD ILIM2 DH1

CK1
EN1 LOGIC S Q
SW1
EN2 PWM
PV
R Q
FAULT1 FAULT2
CK1 DL1
FREQ RAMP1 VREG

OSCILLATOR ILIM1 + PGND1
PHASE 1 = 0°
PHASE 2 = 180° CK2 50µA –
SYNC
CSL1
RAMP2
RAMP1 +
POK1
COMP1 –
–
FB1 +
TRK1 + 0.75V +
+
0.6V
–
BST2
SS1 +
0.8V
0.55V – DH2
FAULT1 CK2 S Q
SW2
PWM PV
RAMP2 +
Q
R
COMP2 –
DL2
–
FB2 + VREG
TRK2 0.75V +
+
+ ILIM2 + PGND2
0.6V 50µA
–
–
UV2
+ CSL2
SS2
0.8V
POK2
0.55V –
FAULT2
GND
BOTTOM PADDLE
OF LFCSP
05936-002
Figure 2.
Data Sheet ADP1823
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
COMP1
LDOSD
VREG
TRK1
EN2
EN1
SS1
IN
32
31
30
29
28
27
26
25
FB1 1 24 POK1
SYNC 2 23 BST1
FREQ 3 22 DH1
GND 4 ADP1823 21 SW1
TOP VIEW
UV2 5 20 CSL1
(Not to Scale)
FB2 6 19 PGND1
COMP2 7 18 DL1
TRK2 8 17 PV
11
10
12
13
14
15
16
SW2
SS2
POK2
BST2
CSL2
DL2
PGND2
DH2
05936-003
NOTES
1. CONNECT THE EXPOSED PAD TO THE GROUND PLANE.
Figure 3. Pin Configuration
Table 3. Pin Function Descriptions

Pin No. Mnemonic Description
1 FB1 Feedback Voltage Input for Channel 1. Connect a resistor divider from the buck regulator output to GND and
tie the tap to FB1 to set the output voltage.
2 SYNC Frequency Synchronization Input. Accepts external signal between 600 kHz and 1.2 MHz or between 1.2 MHz
and 2 MHz depending on whether FREQ is low or high, respectively. Connect SYNC to ground if not used.
3 FREQ Frequency Select Input. Low for 300 kHz or high for 600 kHz.
4 GND Ground. Connect to a ground plane directly beneath the ADP1823. Tie the bottom of the feedback dividers to
this GND.
5 UV2 Input to the POK2 Undervoltage and Overvoltage Comparators. For the default thresholds, connect UV2
directly to FB2. For some tracking applications, connect UV2 to an extra tap on the FB2 voltage divider string.
6 FB2 Feedback Voltage Input for Channel 2. Connect a resistor divider from the buck regulator output to GND and
tie the tap to FB2 to set the output voltage.
7 COMP2 Error Amplifier Output for Channel 2. Connect an RC network from COMP2 to FB2 to compensate Channel 2.
8 TRK2 Tracking Input for Channel 2. To track a master voltage, drive TRK2 from a voltage divider to the master
voltage. If the tracking function is not used, connect TRK2 to VREG.
9 SS2 Soft Start Control Input. Connect a capacitor from SS2 to GND to set the soft start period.
10 POK2 Open-Drain Power OK Output for Channel 2. Sinks current when UV2 is out of regulation. Connect a pull-up
resistor from POK2 to VREG.
11 BST2 Boost Capacitor Input for Channel 2. Powers the high-side gate driver, DH2. Connect a 0.22 μF to 0.47 μF
ceramic capacitor from BST2 to SW2 and a Schottky diode from PV to BST2.
12 DH2 High-Side (Switch) Gate Driver Output for Channel 2.
13 SW2 Switch Node Connection for Channel 2.
14 CSL2 Current Sense Comparator Inverting Input for Channel 2. Connect a resistor between CSL2 and SW2 to set
the current-limit offset.
15 PGND2 Ground for Channel 2 Gate Driver. Connect to a ground plane directly beneath the ADP1823.
16 DL2 Low-Side (Synchronous Rectifier) Gate Driver Output for Channel 2.
17 PV Positive Input Voltage for Gate Driver DL1 and Gate Driver DL2. Connect PV to VREG and bypass to ground
with a 1 µF capacitor.
18 DL1 Low-Side (Synchronous Rectifier) Gate Driver Output for Channel 1.
19 PGND1 Ground for Channel 1 Gate Driver. Connect to a ground plane directly beneath the ADP1823.
20 CSL1 Current Sense Comparator Inverting Input for Channel 1. Connect a resistor between CSL1 and SW1 to set
the current-limit offset.
21 SW1 Switch Node Connection for Channel 1.
22 DH1 High-Side (Switch) Gate Driver Output for Channel 1.
23 BST1 Boost Capacitor Input for Channel 1. Powers the high-side gate driver, DH1. Connect a 0.22 μF to 0.47 μF
ceramic capacitor from BST1 to SW1 and a Schottky diode from PV to BST1.
ADP1823 Data Sheet
Pin No. Mnemonic Description
24 POK1 Open-Drain Power OK Output for Channel 1. Sinks current when FB1 is out of regulation. Connect a pull-up
resistor from POK1 to VREG.
25 EN1 Enable Input for Channel 1. Drive EN1 high to turn on the Channel 1 controller, and drive it low to turn off
the Channel 1 controller. Enabling starts the internal LDO. Tie to IN for automatic startup.
26 EN2 Enable Input for Channel 2. Drive EN2 high to turn on the Channel 2 controller, and drive it low to turn off
the Channel 2 controller. Enabling starts the internal LDO. Tie to IN for automatic startup.
27 LDOSD LDO Shutdown Input. Only used to shut down the LDO in those applications where IN is tied directly to VREG.
Otherwise, connect LDOSD to GND or leave it open because it has an internal 100 kΩ pull-down resistor.
28 IN Input Supply to the Internal Linear Regulator. Drive IN with 5.5 V to 20 V to power the ADP1823 from the LDO.
For input voltages between 3.7 V and 5.5 V, tie IN to VREG and PV.
29 VREG Output of the Internal Linear Regulator (LDO). The internal circuitry and gate drivers are powered from VREG.
Bypass VREG to the ground plane with a 1 μF ceramic capacitor.
30 SS1 Soft Start Control Input. Connect a capacitor from SS1 to GND to set the soft start period.
31 TRK1 Tracking Input for Channel 1. To track a master voltage, drive TRK1 from a voltage divider to the master voltage.
If the tracking function is not used, connect TRK1 to VREG.
32 COMP1 Error Amplifier Output for Channel 1. Connect an RC network from COMP1 to FB1 to compensate Channel 1.
0 EPAD Exposed Pad. Connect the exposed pad to the ground plane.
Data Sheet ADP1823
TYPICAL PERFORMANCE CHARACTERISTICS

95 92
VIN = 5V
SWITCHING FREQUENCY = 300kHz
VIN = 12V
90
90
88
EFFICIENCY (%)
EFFICIENCY (%)
85 VIN = 20V
86
VIN = 15V
84
80
SWITCHING FREQUENCY = 600kHz
82
75
80
70 78
05936-004
05936-007
0 5 10 15 20 0 5 10 15 20
LOAD CURRENT (A) LOAD CURRENT (A)
Figure 4. Efficiency vs. Load Current, VOUT = 1.8 V, 300 kHz Switching Figure 7. Efficiency vs. Load Current, VIN = 12 V, VOUT = 1.8 V
95 4.980
VOUT = 3.3V
90
VOUT = 1.8V 4.975
VREG VOLTAGE (V)
EFFICIENCY (%)
85
VOUT = 1.2V
4.970
80
4.965
75
70 4.960
05936-005
05936-008
0 5 10 15 20 –40 –15 10 35 60 85
LOAD CURRENT (A) TEMPERATURE (°C)
Figure 5. Efficiency vs. Load Current, VIN = 12 V, 300 kHz Switching Figure 8. VREG Voltage vs. Temperature
94 4.970
SWITCHING FREQUENCY = 300kHz 4.968

92
4.966
90
4.964
EFFICIENCY (%)
88
4.962
VREG (V)
86 SWITCHING FREQUENCY = 600kHz 4.960
4.958
84
4.956
82
4.954
80
4.952
78 4.950
05936-006
05936-009
0 5 10 15 20 5 8 11 14 17 20
LOAD CURRENT (A) INPUT VOLTAGE (V)
Figure 6. Efficiency vs. Load Current, VIN = 5 V, VOUT = 1.8 V Figure 9. VREG vs. Input Voltage, 10 mA Load
ADP1823 Data Sheet
4.960 0.6010
0.6005
4.956
FEEDBACK VOLTAGE (V)

0.6000
4.952
VREG (V)
0.5995
4.948
0.5990
4.944
0.5985
4.940 0.5980
05936-010
05936-013
0 20 40 60 80 100 –40 –15 10 35 60 85
LOAD CURRENT (mA) TEMPERATURE (°C)
Figure 10. VREG vs. Load Current, VIN = 12 V Figure 13. Feedback Voltage vs. Temperature, VIN = 12 V
330
5
320
4
310
VREG OUTPUT (V)
FREQUENCY (Hz)
3 300
290
2
280
1
270
0 260
05936-011
0 50 100 150 200 250
05936-014
–40 –15 10 35 60 85
LOAD CURRENT (mA) TEMPERATURE (°C)
Figure 11. VREG Current-Limit Foldback Figure 14. Switching Frequency vs. Temperature, VIN = 12 V
5
T
4
VREG, AC-COUPLED, 1V/DIV
SUPPLY CURRENT (mA)
SW1 PIN, VOUT = 1.8V, 10V/DIV

2
SW2 PIN, VOUT = 1.2V, 10V/DIV 1

05936-012
200ns/DIV
0
05936-015
2 5 8 11 14 17 20
SUPPLY VOLTAGE (V)
Figure 12. VREG Output During Normal Operation Figure 15. Supply Current vs. Supply Voltage
Data Sheet ADP1823
T T EXTERNAL CLOCK, FREQUENCY = 1MHz
VOUT1, AC-COUPLED,
100mV/DIV
SW PIN, CHANNEL 1
LOAD ON
SW PIN, CHANNEL 2
LOAD OFF LOAD OFF
05936-019
05936-016
100µs/DIV 400ns/DIV
Figure 16. 1.5 A to 15 A Load Transient Response, VIN = 12 V Figure 19. Out-of-Phase Switching, External 1 MHz Clock
T T
SS1, 0.5V/DIV EXTERNAL CLOCK, FREQUENCY = 2MHz
VOUT1, 0.5V/DIV SW PIN, CHANNEL 1
INPUT CURRENT, 0.2A/DIV
SHORT CIRCUIT APPLIED 4ms/DIV SW PIN, CHANNEL 2

05936-017
05936-020
SHORT CIRCUIT REMOVED
200ns/DIV
Figure 17. Output Short-Circuit Response Figure 20. Out-of-Phase Switching, External 2 MHz Clock
T VIN = 12V T
VOUT1, 2V/DIV
SWITCH NODE
CHANNEL 1
EN1, 5V/DIV
SWITCH NODE CHANNEL 2

05936-018
05936-021
400ns/DIV 10ms/DIV
Figure 18. Out-of-Phase Switching, Internal Oscillator Figure 21. Enable Pin Response, VIN = 12 V
ADP1823 Data Sheet
T
VIN, 5V/DIV
EN2 PIN, 5V/DIV
VOUT2, 2V/DIV
VOUT, 2V/DIV
VOUT1, 2V/DIV
SOFT START, 1V/DIV
05936-022
05936-024
4ms/DIV EN1 = 5V 40ms/DIV
Figure 22. Power-On Response, EN Tied to VIN Figure 24. Coincident Voltage Tracking Response
TRACK PIN VOLTAGE, T

200mV/DIV
FEEDBACK PIN
VOLTAGE, 200mV/DIV
05936-023
20ms/DIV
Figure 23. Output Voltage Tracking Response
Data Sheet ADP1823
THEORY OF OPERATION
The ADP1823 is a dual, synchronous, PWM buck controller used. Otherwise, it should be grounded or left open. LDOSD
capable of generating output voltages down to 0.6 V and output has an internal 100 kΩ pull-down resistor.
currents in the tens of amps. The switching of the regulators is Although IN is limited to 20 V, the switching stage can run from
interleaved for reduced current ripple. It is ideal for a wide up to 24 V, and the BST pins can go to 30 V to support the gate
range of applications, such as DSP and processor core input/ drive. Dissipation on the ADP1823 can be limited by running IN
output supplies, general-purpose power in telecommunications, from a low voltage rail while operating the switches from the high
medical imaging, gaming, PCs, set-top boxes, and industrial voltage rail.
controls. The ADP1823 controller operates directly from 3.7 V
to 20 V, and the power stage input voltage range is 1 V to 24 V, START-UP LOGIC
which applies directly to the drain of the high-side external The ADP1823 features independent enable inputs for each
power MOSFET. It includes fully integrated MOSFET gate channel. Drive EN1 or EN2 high to enable their respective
drivers and a linear regulator for internal and gate drive bias. controllers. The LDO starts when either channel is enabled.
The ADP1823 operates at a fixed 300 kHz or 600 kHz switching When both controllers are disabled, the LDO is disabled and
frequency. The ADP1823 can also be synchronized to an external the IN quiescent current drops to about 10 µA. For automatic
clock to switch at up to 1 MHz per channel. The ADP1823 startup, connect EN1 and/or EN2 to IN. The enable pins are
includes soft start to prevent inrush current during startup, as 20 V compliant, but they sink current through an internal
well as a unique adjustable lossless current limit. 100 kΩ resistor when the EN pin voltage exceeds about 5 V.
The ADP1823 offers flexible tracking for startup and shutdown INTERNAL LINEAR REGULATOR
sequencing. It is specified over the −40°C to +125°C temperature The internal linear regulator, VREG, is low dropout, which means
range and is available in a space-saving, 5 mm × 5 mm, it can regulate its output voltage close to the input voltage.
32-lead LFCSP. VREG powers up the internal control and provides bias for
INPUT POWER the gate drivers. It is guaranteed to have more than 100 mA of
output current capability, which is sufficient to handle the gate
The ADP1823 is powered from the IN pin up to 20 V. The drive requirements of typical logic threshold MOSFETs driven
internal low dropout linear regulator, VREG, regulates the IN
at up to 1 MHz. VREG should always be bypassed with a 1 µF
voltage down to 5 V. The control circuits, gate drivers, and
or greater capacitor.
external boost capacitors operate from the LDO output. Tie
the PV pin to VREG and bypass VREG with a 1 µF or greater Because the LDO supplies the gate drive current, the output of
capacitor. VREG is subject to sharp transient currents as the drivers switch
and the boost capacitors recharge during each switching cycle.
The ADP1823 phase shifts the switching of the two step-down The LDO has been optimized to handle these transients without
converters by 180°, thereby reducing the input ripple current. overload faults. Due to the gate drive loading, using the VREG
The phase shift reduces the size and cost of the input capacitors. output for other auxiliary system loads is not recommended.
The input voltage should be bypassed with a capacitor close to
the high-side switch MOSFETs (see the Selecting the Input The LDO includes a current limit well above the expected
Capacitor section). In addition, a minimum 0.1 µF ceramic maximum gate drive load. This current limit also includes a
capacitor should be placed as close as possible to the IN pin. short-circuit foldback to further limit the VREG current in the
event of a fault.
The VREG output is sensed by the undervoltage lockout
(UVLO) circuit to be certain that enough voltage headroom OSCILLATOR AND SYNCHRONIZATION
is available to run the controllers and gate drivers. As VREG The ADP1823 internal oscillator can be set to either 300 kHz or
rises above about 2.7 V, the controllers are enabled. The IN 600 kHz. Drive the FREQ pin low for 300 kHz; drive it high for
voltage is not directly monitored by UVLO. If the IN voltage is 600 kHz. The oscillator generates a start clock for each switching
insufficient to allow VREG to be above the UVLO threshold, phase and generates the internal ramp voltages for the PWM
the controllers are disabled but the LDO continues to operate. modulation.
The LDO is enabled whenever either EN1 or EN2 is high, even The SYNC input is used to synchronize the converter switching
if VREG is below the UVLO threshold. frequency to an external signal. The SYNC input should be
If the desired input voltage is between 3.7 V and 5.5 V, connect driven with twice the desired switching frequency, as the SYNC
IN directly to the VREG pin and the PV pin, and drive LDOSD input is divided by 2, and the resulting phases are used to clock
high to disable the internal regulator. The ADP1823 requires the two channels alternately.
that the voltage at VREG and PV be limited to no more than
5.5 V, which is the only application where the LDOSD pin is
ADP1823 Data Sheet
If FREQ is driven low, the recommended SYNC input frequency SOFT START
is between 600 kHz and 1.2 MHz. If FREQ is driven high, the The ADP1823 employs a programmable soft start that reduces
recommended SYNC frequency is between 1.2 MHz and input current transients and prevents output overshoot. The SS1
2 MHz. The FREQ setting should be carefully observed for and SS2 pins drive auxiliary positive inputs to their respective
these SYNC frequency ranges, because the PWM voltage ramp error amplifiers, thus the voltage at these pins regulates the voltage
scales down from about 1.3 V based on the percentage of at their respective feedback control pins.
frequency overdrive. Driving SYNC faster than recommended
for the FREQ setting results in a small ramp signal, which could Program soft start by connecting capacitors from SS1 and SS2
affect the signal-to-noise ratio and the modulator gain and to GND. When starting up, the capacitor charges from an
stability. internal 90 kΩ resistor to 0.8 V. The regulator output voltage
rises with the voltage at its respective soft start pin, allowing the
When an external clock is detected at the first SYNC edge, the output voltage to rise slowly, reducing inrush current. See the
internal oscillator is reset and clock control shifts to SYNC. Soft Start section in the Applications Information section for
The SYNC edges then trigger subsequent clocking of the PWM more information.
outputs. The DH rising edges appear about 400 ns after the
corresponding SYNC edge, and the frequency is locked to the When a controller is disabled or experiences a current fault, the
external signal. Depending on the start-up conditions of Channel 1 soft start capacitor discharges through an internal 6 kΩ resistor,
and Channel 2, either Channel 1 or Channel 2 can be the first so that at restart or recovery from fault, the output voltage soft
channel synchronized to the rising edge of the SYNC clock. If starts again.
the external SYNC signal disappears during operation, the POWER OK INDICATOR
ADP1823 reverts to its internal oscillator and experiences a
The ADP1823 features open-drain, power OK outputs, POK1
delay of no more than a single cycle of the internal oscillator.
and POK2, which sink current when their respective output
ERROR AMPLIFIER voltages drop, typically 8% below the nominal regulation
The ADP1823 error amplifiers are operational amplifiers. The voltage. The POK pins also go low for overvoltage of typically
ADP1823 senses the output voltages through external resistor 25%. Use this output as a logical power-good signal by connect-
dividers at the FB1 and FB2 pins. The FB pins are the inverting ing pull-up resistors from POK1 and POK2 to VREG.
inputs to the error amplifiers. The error amplifiers compare The POK1 comparator directly monitors FB1, and the threshold
these feedback voltages to the internal 0.6 V reference, and is fixed at 550 mV for undervoltage and 750 mV for overvoltage.
the outputs of the error amplifiers appear at the COMP1 and However, the POK2 undervoltage and overvoltage comparator
COMP2 pins. The COMP pin voltages then directly control input is connected to UV2 rather than FB2. For the default
the duty cycle of each respective switching converter. thresholds at FB2, connect UV2 directly to FB2.
A series/parallel RC network is tied between the FB pins and In a ratiometric tracking configuration, however, Channel 2 can
their respective COMP pins to provide the compensation for be configured to be a fraction of a master voltage, and thus FB2
the buck converter control loops. A detailed design procedure is regulated to a voltage lower than the 0.6 V internal reference.
for compensating the system is provided in the Compensating In this configuration, UV2 can be tied to a different tap on the
the Voltage Mode Buck Regulator section. feedback divider, allowing a POK2 indication at an appropriate
The error amplifier outputs are clamped between a lower limit output voltage threshold. See the Setting the Channel 2
of about 0.7 V and a higher limit of about 2.4 V. When the Undervoltage Threshold for Ratiometric Tracking section.
COMP pins are low, the switching duty cycle goes to 0%, and TRACKING
when the COMP pins are high, the switching duty cycle goes
The ADP1823 features tracking inputs, TRK1 and TRK2, which
to the maximum.
make the output voltages track another master voltage. Voltage
The SS and TRK pins are auxiliary positive inputs to the error tracking is especially useful in core and input/output voltage
amplifiers. Whichever has the lowest voltage, SS, TRK, or the sequencing applications where one output of the ADP1823 can
internal 0.6 V reference controls the FB pin voltage and thus be set to track and not exceed the other, or in other multiple
the output. Therefore, if two or more of these inputs are close output systems where specific sequencing is required.
to each other, a small offset is imposed on the error amplifier.
The internal error amplifiers include three positive inputs, the
For example, if TRK approaches the 0.6 V reference, the FB
internal 0.6 V reference voltage and their respective SS and TRK
sees about 18 mV of negative offset at room temperature. For
pins. The error amplifiers regulate the FB pins to the lowest of
this reason, the soft start pins have a built-in negative offset
the three inputs. To track a supply voltage, tie the TRK pin to a
and they charge to 0.8 V. If the TRK pins are not used, they
resistor divider from the voltage to be tracked. See the Voltage
should be tied high to VREG.
Tracking section.
Data Sheet ADP1823
MOSFET DRIVERS CURRENT LIMIT
The DH1 and DH2 pins drive the high-side switch MOSFETs. The ADP1823 employs a unique, programmable, cycle-by-cycle
These boosted 5 V gate drivers are powered by bootstrap capacitor lossless current-limit circuit that uses a small, ordinary, inexpensive
circuits. This configuration allows the high-side, N-channel resistor to set the threshold. Every switching cycle, the synchro-
MOSFET gate to be driven above the input voltage, allowing nous rectifier turns on for a minimum time and the voltage
full enhancement and a low voltage drop across the MOSFET. drop across the MOSFET RDSON is measured during the off
The bootstrap capacitors are connected from the SW pins to cycle to determine whether the current is too high.
their respective BST pins. The bootstrap Schottky diodes from This measurement is done by an internal current-limit
the PV pin to the BST pins recharge the bootstrap capacitors every comparator and an external current-limit set resistor. The
time the SW nodes go low. Use a bootstrap capacitor value resistor is connected between the switch node (that is, the
greater than 100× the high-side MOSFET input capacitance. drain of the rectifier MOSFET) and the CSL pin. The CSL pin,
In practice, the switch node can run up to 24 V of input voltage, which is the inverting input of the comparator, forces 50 μA
and the boost nodes can operate more than 5 V above this to through the resistor to create an offset voltage drop across it.
allow full gate drive. The IN pin can be run from 3.7 V to 20 V, When the inductor current is flowing in the MOSFET rectifier,
which can provide an advantage, for example, in the case of high its drain is forced below PGND by the voltage drop across its
frequency operation from very high input voltage. Dissipation on RDSON. If the RDSON voltage drop exceeds the preset drop on the
the ADP1823 can be limited by running IN from a lower voltage external resistor, the inverting comparator input is similarly
rail while operating the switches from the high voltage rail. forced below PGND and an overcurrent fault is flagged.
The switching cycle is initiated by the internal clock signal. The The normal transient ringing on the switch node is ignored for
high-side MOSFET is turned on by the DH driver, and the SW 100 ns after the synchronous rectifier turns on; therefore, the
node goes high, pulling up on the inductor. When the internally overcurrent condition must also persist for 100 ns in order for a
generated ramp signal crosses the COMP pin voltage, the switch fault to be flagged.
MOSFET is turned off and the low-side synchronous rectifier
MOSFET is turned on by the DL driver. Active break-before- When an overcurrent event occurs, the overcurrent comparator
make circuitry, as well as a supplemental fixed dead time, are prevents switching cycles until the rectifier current has decayed
used to prevent cross-conduction in the switches. below the threshold. The overcurrent comparator is blanked
for the first 100 ns of the synchronous rectifier cycle to prevent
The DL1 and DL2 pins provide gate drive for the low-side switch node ringing from falsely tripping the current limit. The
MOSFET synchronous rectifiers. Internal circuitry monitors ADP1823 senses the current limit during the off cycle. When
the external MOSFETs to ensure break-before-make switching the current-limit condition occurs, the ADP1823 resets the
to prevent cross-conduction. An active dead time reduction internal clock until the overcurrent condition disappears. The
circuit reduces the break-before-make time of the switching to ADP1823 suppresses the start clock cycles until the overload
limit the losses due to current flowing through the synchronous condition is removed. At the same time, the SS capacitor is
rectifier body diode. discharged through a 6 kΩ resistor. The SS input is an auxiliary
The PV pin provides power to the low-side drivers. It is limited positive input of the error amplifier, so it behaves like another
to 5.5 V maximum input and should have a local decoupling voltage reference. The lowest reference voltage wins.
capacitor. Discharging the SS voltage causes the converter to use a lower
The synchronous rectifiers are turned on for a minimum time voltage reference when switching is allowed again. Therefore,
of about 200 ns on every switching cycle to sense the current. as switching cycles continue around the current limit, the output
This minimum on time and the nonoverlap dead times put a limit looks roughly like a constant current source due to the rectifier
on the maximum high-side switch duty cycle based on the selected limit, and the output voltage droops as the load resistance
switching frequency. Typically, this is about 90% at 300 kHz decreases. In the event of a short circuit, the short-circuit
switching, and at 1 MHz switching, it reduces to about 70% output current is the current limit set by the RCL resistor and
maximum duty cycle. is monitored cycle by cycle. When the overcurrent condition is
Because the two channels are 180° out of phase, if one is operating removed, operation resumes in soft start mode.
around 50% duty cycle, it is common for it to jitter when the In the event of a short circuit, the ADP1823 also offers a
other channel starts switching. The magnitude of the jitter depends technique for implementing a current-limit foldback with the
somewhat on layout, but it is difficult to avoid in practice. use of an additional resistor. See the Setting the Current Limit
When the ADP1823 is disabled, the drivers shut off the external section for more information.
MOSFETs, so that the SW node becomes three-stated or
changes to high impedance.
ADP1823 Data Sheet
APPLICATIONS INFORMATION
SELECTING THE INPUT CAPACITOR Choose the inductor value by
The input current to a buck converter is a pulse waveform. It is VIN − VOUT  VOUT 
L=   (4)
zero when the high-side switch is off and approximately equal ΔI L f SW  VIN 

to the load current when it is on. The input capacitor carries the
input ripple current, allowing the input power source to supply where:
only the dc current. The input capacitor needs sufficient ripple L is the inductor value.
current rating to handle the input ripple and ESR that is low fSW is the switching frequency.
enough to mitigate input voltage ripple. For the usual current VOUT is the output voltage.
ranges for these converters, good practice is to use two parallel VIN is the input voltage.
capacitors placed close to the drains of the high-side switch ∆IL is the inductor ripple current, typically 1/3 of the maximum
MOSFETs, one bulk capacitor of sufficiently high current rating dc load current.
as calculated in Equation 1, along with a 10 μF ceramic capacitor.
Choose the output bulk capacitor to set the desired output voltage
Select an input bulk capacitor based on its ripple current rating. ripple. The impedance of the output capacitor at the switching
If both Channel 1 and Channel 2 maximum output load currents frequency multiplied by the ripple current gives the output
are about the same, the input ripple current is less than half of voltage ripple. The impedance is made up of the capacitive
the higher of the output load currents. In this case, use an input impedance plus the nonideal parasitic characteristics, the
capacitor with a ripple current rating greater than half of the equivalent series resistance (ESR), and the equivalent series
highest load current. inductance (ESL). The output voltage ripple can be
IL approximated with
I RIPPLE > (1)
2  1 
If the Output 1 and Output 2 load currents are significantly ∆VOUT = ∆I L  ESR + + 4 f SW ESL  (5)
 8 f SW C OUT 
 
different (if the smaller is less than 50% of the larger), the
procedure in Equation 1 yields a larger input capacitor than where:
required. In this case, the input capacitor can be chosen as in ∆VOUT is the output ripple voltage.
the case of a single phase converter with only the higher load ∆IL is the inductor ripple current.
current; therefore, first determine the duty cycle of the output ESR is the equivalent series resistance of the output capacitor
with the larger load current. (or the parallel combination of ESR of all output capacitors).
VOUT ESL is the equivalent series inductance of the output capacitor
D= (2)
VIN (or the parallel combination of ESL of all capacitors).
In this case, the input capacitor ripple current is approximately Note that the factors of 8 and 4 in Equation 5 would normally
be 2π for sinusoidal waveforms, but the ripple current waveform in
I RIPPLE ≈ I L D(1 − D) (3) this application is triangular. Parallel combinations of different
where: types of capacitors, for example, a large aluminum electrolytic
in parallel with MLCCs, may give different results.
IL is the maximum inductor or load current for the channel.
D is the duty cycle. Usually, the impedance is dominated by ESR at the switching
frequency, as stated in the maximum ESR rating on the
Use this method to determine the input capacitor ripple current capacitor data sheet, so this equation reduces to
rating for duty cycles between 20% and 80%.
∆VOUT ≅ ∆I L ESR (6)
For duty cycles less than 20% or greater than 80%, use an input
capacitor with a ripple current rating of IRIPPLE > 0.4 IL. Electrolytic capacitors have significant ESL also, on the order of
5 nH to 20 nH, depending on type, size, and geometry, and PCB
Selecting the Output LC Filter
traces contribute some ESR and ESL as well. However, using the
The output LC filter attenuates the switching voltage, making maximum ESR rating from the capacitor data sheet usually
the output an almost dc voltage. The output LC filter characteris- provides some margin such that measuring the ESL is not
tics determine the residual output ripple voltage. usually required.
Choose an inductor value such that the inductor ripple current
is approximately 1/3 of the maximum dc output load current.
Using a larger value inductor results in a physical size larger
than is required, and using a smaller value results in increased
losses in the inductor and MOSFETs.
Data Sheet ADP1823
In the case of output capacitors where the impedance of the Furthermore, the high-side MOSFET transition loss is
ESR and ESL are small at the switching frequency, for instance, approximated by
where the output capacitor is a bank of parallel MLCC VIN I L (t R + t F ) f SW
capacitors, the capacitive impedance dominates and the ripple PT ≅ (10)
equation reduces to 2
where tR and tF are the rise and fall times of the selected
ΔI L
ΔVOUT ≅ (7) MOSFET as stated in the MOSFET data sheet.
8 COUT f SW
The total power dissipation of the high-side MOSFET is
Make sure that the ripple current rating of the output capacitors the sum of the previous losses.
is greater than the maximum inductor ripple current.
PD = PC + PG + PT (11)
During a load step transient on the output, the output capacitor
where PD is the total high-side MOSFET power loss. This
supplies the load until the control loop has a chance to ramp the
dissipation heats the high-side MOSFET.
inductor current. This initial output voltage deviation due to a
change in load is dependent on the output capacitor characteristics. The conduction losses may need an adjustment to account
Again, usually the capacitor ESR dominates this response, and for the MOSFET RDSON variation with temperature. Note that
the ΔVOUT in Equation 6 can be used with the load step current MOSFET RDSON increases with increasing temperature. The
value for ΔIL. MOSFET data sheet should list the thermal resistance of the
package, θJA, along with a normalized curve of the temperature
SELECTING THE MOSFETs
coefficient of RDSON. For the power dissipation estimated,
The choice of MOSFET directly affects the dc-to-dc converter calculate the MOSFET junction temperature rise over the
performance. The MOSFET must have low on resistance (RDSON) ambient temperature of interest.
to reduce I2R losses and low gate charge to reduce switching losses.
TJ = TA + θJA PD (12)
In addition, the MOSFET must have low thermal resistance to
ensure that the power dissipated in the MOSFET does not result Next, calculate the new RDSON from the temperature coefficient
in overheating. curve and the RDSON specification at 25°C. A typical value of the
temperature coefficient (TC) of RDSON is 0.004/°C; therefore, an
The power switch, or high-side MOSFET, carries the load current
alternate method to calculate the MOSFET RDSON at a second
during the PWM on time, carries the transition loss of the
temperature, TJ, is
switching behavior, and requires gate charge drive to switch.
Typically, the smaller the MOSFET RDSON, the higher the gate RDSON at TJ = RDSON at 25°C(1 + TC(TJ − 25°C)) (13)
charge and vice versa. Therefore, it is important to choose a Then the conduction losses can be recalculated and the procedure
high-side MOSFET that balances those two losses. The conduction iterated once or twice until the junction temperature calculations
loss of the high-side MOSFET is determined by are relatively consistent.
VOUT The synchronous rectifier, or low-side MOSFET, carries the
PC ≅ I L 2 RDSON (8)
VIN inductor current when the high-side MOSFET is off. For high
input voltage and low output voltage, the low-side MOSFET
where:
carries the current most of the time, and therefore, to achieve
PC is the conduction power loss. high efficiency it is critical to optimize the low-side MOSFET
RDSON is the MOSFET on resistance. for small on resistance. In cases where the power loss exceeds
The gate charge losses are dissipated by the ADP1823 regulator the MOSFET rating, or lower resistance is required than is
and gate drivers and affect the efficiency of the system. The gate available in a single MOSFET, connect multiple low-side
charge loss is approximated by MOSFETs in parallel. The equation for low-side MOSFET
power loss is
PG ≅ VIN Q G f SW (9)
where:  V 
PLS ≅ I L 2 RDSON 1 − OUT  (14)
 VIN 
PG is the gate charge power.  
QG is the MOSFET total gate charge. where:
fSW is the converter switching frequency.
PLS is the low-side MOSFET on resistance.
Making the conduction losses balance the gate charge losses RDSON is the parallel combination of the resistances of the low-
usually yields the most efficient choice. side MOSFETs.
Check the gate charge losses of the synchronous rectifier(s)
using the PG equation (Equation 9) to make sure they are
reasonable.
ADP1823 Data Sheet
VIN
SETTING THE CURRENT LIMIT
ADP1823
The current-limit comparator measures the voltage across the
M1
low-side MOSFET to determine the load current. DH L VOUT
The current limit is set through the current-limit resistor, RCL. M2

COUT
The current sense pins, CSL1 and CSL2, source 50 μA through DL

RLO RHI
their respective RCL. This current source creates an offset voltage of
05936-035
CSL
RCL multiplied by the 50 μA CSL current. When the drop across
the low-side MOSFET RDSON is equal to or greater than this Figure 25. Short-Circuit Current Foldback Scheme
offset voltage, the ADP1823 flags a current-limit event. Because the buck converters are usually running fairly high
Because the CSL current and the MOSFET RDSON vary over current, PCB layout and component placement may affect the
process and temperature, the minimum current limit should be current-limit setting. An iteration of the RCL or RLO and RHI
set to ensure that the system can handle the maximum desired values may be required for a particular board layout and
load current. To do this, use the peak current in the inductor, MOSFET selection. If alternate MOSFETs are substituted at
which is the desired current-limit level plus the ripple current, some point in production, these resistor values may also need
the maximum RDSON of the MOSFET at its highest expected an iteration.
temperature, and the minimum CSL current.
FEEDBACK VOLTAGE DIVIDER
I LPK R DSON (MAX ) The output regulation voltage is set through the feedback voltage
RCL  (15)
44 μA divider. The output voltage is reduced through the voltage divider
and drives the FB feedback input. The regulation threshold at
where ILPK is the peak inductor current.
FB is 0.6 V. The maximum input bias current into FB is 100 nA.
In addition, the ADP1823 offers a technique for implementing For a 0.15% degradation in regulation voltage and with 100 nA
a current-limit foldback in the event of a short circuit with the bias current, the low-side resistor, RBOT, needs to be less than 9 kΩ,
use of an additional resistor, as shown in Figure 25. Resistor RLO which results in 67 μA of divider current. For RBOT, use 1 kΩ to
is largely responsible for setting the foldback current limit during a 10 kΩ. A larger value resistor can be used but results in a reduction
short circuit, and RHI is mainly responsible for setting up the in output voltage accuracy due to the input bias current at the
normal current limit. RLO is lower than RHI. These current-limit FB pin, whereas lower values cause increased quiescent current
sense resistors can be calculated by consumption. Choose RTOP to set the output voltage by using
I PKFOLDBACK RDSON ( MAX ) the following equation:
RLO  (16)
44 A V  VFB 
RTOP  R BOT  OUT  (18)
VOUT  VFB 
RHI  (17)  
RDSON ( MAX )
I LPK  44 A where:
RLO
RTOP is the high-side voltage divider resistance.
where: RBOT is the low-side voltage divider resistance.
IPKFOLDBACK is the desired short-circuit peak inductor current limit. VOUT is the regulated output voltage.
ILPK is the peak inductor current limit during normal operation VFB is the feedback regulation threshold, 0.6 V.
(also used in Equation 15).
Data Sheet ADP1823
LC FILTER BODE PLOT
COMPENSATING THE VOLTAGE MODE BUCK
REGULATOR GAIN
fLC fESR fCO fSW
0dB
Assuming the LC filter design is complete, the feedback control
FREQUENCY
system can then be compensated. Good compensation is critical
–40dB/dec
to proper operation of the regulator. Calculate the quantities in
Equation 19 through Equation 47 to derive the compensation
values. The goal is to guarantee that the voltage gain of the buck
converter crosses unity at a slope that provides adequate phase
margin for stable operation. Additionally, at frequencies above AFILTER
–20dB/dec
the crossover frequency, fCO, guaranteeing sufficient gain margin
and attenuation of switching noise are important secondary
goals. For initial practical designs, a good choice for the
crossover frequency is one tenth of the switching frequency. PHASE
0°
First calculate
f SW
f CO  (19)
10
This gives sufficient frequency range to design a compensation –90°
that attenuates switching artifacts, while also giving sufficient
ΦFILTER
control loop bandwidth to provide good transient response.
The output LC filter is a resonant network that inflicts two poles
05936-025
upon the response at a frequency fLC, so next calculate –180°
1 Figure 26. LC Filter Bode Plot

f LC  (20)
2π LC To compensate the control loop, the gain of the system must be
Generally, the LC corner frequency is about two orders of brought back up so that it is 0 dB at the desired crossover
magnitude below the switching frequency, and, therefore, about frequency. Some gain is provided by the PWM modulation itself.
one order of magnitude below crossover. To achieve sufficient  V 
phase margin at crossover to guarantee stability, the design A MOD  20 log  IN  (23)
V 
must compensate for the two poles at the LC corner frequency  RAMP 
with two zeros to boost the system phase prior to crossover. The For systems using the internal oscillator, this becomes
two zeros require an additional pole or two above the crossover
 V 
frequency to guarantee adequate gain margin and attenuation of AMOD  20 log  IN  (24)
switching noise at high frequencies.  1.3 V 
 
Depending on component selection, one zero may already be Note that if the converter is being synchronized, the ramp
generated by the equivalent series resistance (ESR) of the output voltage, VRAMP, is lower than 1.3 V by the percentage of
capacitor. Calculate this zero corner frequency, fESR, as frequency increase over the nominal setting of the FREQ pin.
1
f ESR  (21)  2 f FREQ 
2π R ESR COUT VRAMP  1.3 V   (25)
 f 
 SYNC 
Figure 26 shows a typical Bode plot of the LC filter by itself.
The factor of 2 in the numerator takes into account that the
The gain of the LC filter at crossover can be linearly
SYNC frequency is divided by 2 to generate the switching
approximated from Figure 26 as
frequency. For example, if the FREQ pin is set high for the
AFILTER = ALC + AESR 600 kHz range and a 2 MHz SYNC signal is applied, the ramp
voltage is 0.78 V. The gain of the modulator is increased by
f   
AFILTER  40 dB  log  ESR   20 dB log  f CO  (22) 4.4 dB in this example.
 f  f 
 LC   ESR 
If fESR ≈ fCO, add another 3 dB to account for the local difference
between the exact solution and the linear approximation.
ADP1823 Data Sheet
The rest of the system gain is needed to reach 0 dB at crossover. LC FILTER BODE PLOT
PHASE CONTRIBUTION AT CROSSOVER
OF VARIOUS ESR ZERO CORNERS
The total gain of the system, therefore, is given by
GAIN
AT = AMOD + AFILTER + ACOMP (26) fLC fESR1 fESR2 fESR3 fCO fSW
0dB
FREQUENCY
where: –40dB/dec
AMOD is the gain of the PWM modulator.

AFILTER is the gain of the LC filter including the effects of
–20dB/dec
the ESR zero.
ACOMP is the gain of the compensated error amplifier.
Additionally, the phase of the system must be brought back up
to guarantee stability. Note from the Bode plot of the filter that
the LC contributes −180° of phase shift. Additionally, because
the error amplifier is an integrator at low frequency, it contributes
PHASE
an initial −90°. Therefore, before adding compensation or
0°
accounting for the ESR zero, the system is already down −270°.
To avoid loop inversion at crossover, or −180° phase shift, a
good initial practical design is to require a phase margin of 60°,
which is therefore an overall phase loss of −120° from the initial Φ1
–90°
low frequency dc phase. The goal of the compensation is to
boost the phase back up from −270° to −120° at crossover.
Two common compensation schemes are used, which are Φ2
sometimes referred to as Type II or Type III compensation, Φ3
05936-026
–180°
depending on whether the compensation design includes two
or three poles. (Dominant pole compensation, or single pole Figure 27. LC Filter Bode Plot
compensation, is referred to as Type I compensation, but The following equations were used for the calculation of the
unfortunately, it is not very useful for dealing successfully with compensation components as shown in Figure 28 and Figure 29:
switching regulators.)
1
If the zero produced by the ESR of the output capacitor provides f Z1  (27)
2πRZ CI
sufficient phase boost at crossover, Type II compensation is
adequate. If the phase boost produced by the ESR of the output 1
f Z2  (28)
capacitor is not sufficient, another zero is added to the compensa- 2πC FF (RTOP  R FF )
tion network, and thus Type III is used.
1
In Figure 27, the location of the ESR zero corner frequency f P1  (29)
C I C HF
gives significantly different net phase at the crossover frequency. 2πR Z
C I  C HF
Use the following guidelines for selecting between Type II and
1
Type III compensators: f P2  (30)
2πR FF C FF
If fESRZ ≤ fCO/2, use Type II compensation.
where:
If fESRZ > fCO/2, use Type III compensation.
fZ1 is the zero produced in the Type II compensation.
fZ2 is the zero produced in the Type III compensation.
fP1 is the pole produced in the Type II compensation.
fP2 in the pole produced in the Type III compensation.
Data Sheet ADP1823
Type II Compensator Next choose the high frequency pole fP1 to be half of fSW.
–1
S LO 1
G
(dB)
PE f P1  f SW (36)
–1 2
S LO
PE
Because CHF << CI, Equation 29 is simplified to
PHASE fZ fP
1
–180° f P1  (37)
–270° 2πRZ CHF
CHF
Solving for CHF in Equation 36 and Equation 37 yields
RZ CI
1
CHF  (38)
FROM
RTOP πf SW RZ
VOUT
RBOT EA
COMP TO PWM Type III Compensator
VREF VRAMP –1
G S PE
05936-027
LO LO
(dB) PE S –1
0V +1 SL
O PE
Figure 28. Type II Compensation
–90° fZ fP
If the output capacitor ESR zero frequency is sufficiently low PHASE
(≤½ of the crossover frequency), use the ESR to stabilize the –270°
regulator. In this case, use the circuit shown in Figure 28. CHF
Calculate the compensation resistor, RZ, with the following
RFF CFF RZ CI
equation:
RTOPVRAMP f ESR fCO RTOP
FROM
RZ  (31) VOUT
VIN f LC 2 RBOT EA
TO PWM
COMP
where: VREF VRAMP
05936-028
fCO is chosen to be 1/10 of fSW. 0V
VRAMP is 1.3 V. Figure 29. Type III Compensation
Next choose the compensation capacitor to set the compensa- If the output capacitor ESR zero frequency is greater than half
tion zero, fZ1, to the lesser of ¼ of the crossover frequency or ½ of the crossover frequency, use a Type III compensator as
of the LC resonant frequency. shown in Figure 29. Set the poles and zeros as follows:
fCO f 1 1
f Z1   SW  (32) f P1  f P 2  f SW (39)
4 40 2πRZ CI 2
or fCO f 1
f Z1  f Z 2   SW  (40)
f 1 4 40 2 πR Z C I
f Z1  LC  (33)
2 2πRZ C I or
Solving for CI in Equation 32 yields f LC 1
f Z1  f Z 2   (41)
20 2 2RZCI
CI  (34)
πRZ f SW Use the lower zero frequency from Equation 40 or Equation 41.
Solving for CI in Equation 33 yields Calculate the compensator resistor, RZ.
RTOPVRAMP f Z1 fCO
CI 
1
(35) RZ  (42)
πRZ f LC VIN f LC 2
Use the larger value of CI from Equation 34 or Equation 35. Next calculate CI.
Because of the finite output current drive of the error amplifier, 1
CI  (43)
CI needs to be less than 10 nF. If it is larger than 10 nF, choose a 2 πR Z f Z 1
larger RTOP and recalculate RZ and CI until CI is less than 10 nF.
ADP1823 Data Sheet
Because of the finite output current drive of the error amplifier, The soft start period ends when the voltage on the soft start pin
CI needs to be less than 10 nF. If it is larger than 10 nF, choose a reaches 0.6 V. Substituting 0.6 V for VSS and solving for the
larger RTOP and recalculate RZ and CI until CI is less than 10 nF. number of RC time constants
Because CHF << CI, combining Equation 29 and Equation 39 yields  t SS

0.6 V = 0.8 V 1 − e 90 kΩ ( CSS)  (49)
1  
CHF = (44)  
πf SW RZ
tSS = 1.386 RCSS (50)
Next calculate the feedforward capacitor, CFF. Assuming
Because R = 90 kΩ,
RFF << RTOP, then Equation 28 is simplified to
CSS = tSS × 8 µF/s (51)
1
fZ2 = (45)
where tSS is the desired soft start time in seconds.
2πCFF RTOP
Solving CFF in Equation 45 yields VOLTAGE TRACKING
1 The ADP1823 includes a tracking feature that prevents an
CFF = (46) output voltage from exceeding a master voltage. This feature is
2πRTOP f Z 2
especially important when the ADP1823 is powering separate
where fZ2 is obtained from Equation 40 or Equation 41. power supply voltages on a single integrated circuit, such as the
The feedforward resistor, RFF, can be calculated by combining core and input/output voltages of a DSP or microcontroller. In
Equation 30 and Equation 39. these cases, improper sequencing can cause damage to the load.
1 The ADP1823 tracking input is an additional positive input to

RFF = (47) the error amplifier. The feedback voltage is regulated to the lower of
πCFF f SW
the 0.6 V reference or the voltage at TRK; therefore, a lower
Check that the calculated component values are reasonable. For voltage on TRK limits the output voltage. This feature allows
instance, capacitors smaller than about 10 pF should be avoided. implementation of two different types of tracking: coincident
In addition, the ADP1823 error amplifier has finite output tracking, where the output voltage is the same as the master
current drive; therefore, RZ values less than 3 kΩ and CI values voltage until the master voltage reaches regulation, or ratiometric
greater than 10 nF should be avoided. If necessary, recalculate the tracking, where the output voltage is limited to a fraction of the
compensation network with a different starting value of RTOP. If master voltage.
RZ is too small and CI is too big, start with a larger value of RTOP. In all tracking configurations, the master voltage should be
This compensation technique should yield a good working higher than the slave voltage.
solution.
Note that the soft start time setting of the master voltage should
In general, aluminum electrolytic capacitors have high ESR; be longer than the soft start of the slave voltage. This forces the
therefore, a Type II compensation is adequate. However, if several rise time of the master voltage to be imposed on the slave voltage.
aluminum electrolytic capacitors are connected in parallel, If the soft start setting of the slave voltage is longer, the slave
producing a low effective ESR, Type III compensation is needed. In comes up more slowly and the tracking relationship is not seen
addition, ceramic capacitors have very low ESR, on the order of at the output. The slave channel should still have a soft start
a few milliohms; therefore, Type III compensation is needed for capacitor to give a small but reasonable soft start time to protect
ceramic output capacitors. Type III compensation offers better in case of a restart after a current-limit event.
performance than Type II in terms of more low frequency gain VOUT
and more phase margin and less high frequency gain at the
crossover frequency. RTOP
COMP
SOFT START
RBOT
The ADP1823 uses an adjustable soft start to limit the output FB
voltage ramp-up period, thus limiting the input inrush current.
The soft start is set by selecting the capacitor, CSS, from SS1 and TRK MASTER
SS2 to GND. The ADP1823 charges CSS to 0.8 V through an 0.6V
VOLTAGE
ERROR
internal 90 kΩ resistor. The voltage on the soft start capacitor AMPLIFIER SS
RTRKT
while it is charging is
05936-029
DETAIL VIEW OF RTRKB
 t
 ADP1823

VCSS = 0.8 V 1 − e RC SS  (48)
  Figure 30. Voltage Tracking
 
Data Sheet ADP1823
COINCIDENT TRACKING For ratiometric tracking, the simplest configuration is to tie the
The most common application is coincident tracking, used TRK pin of the slave channel to the FB pin of the master channel.
in core vs. input/output voltage sequencing and similar This has the advantage of having the fewest components, but
applications. Coincident tracking limits the slave output voltage the accuracy suffers as the TRK pin voltage becomes equal to
to be the same as the master voltage until it reaches regulation. the internal reference voltage and an offset is imposed on the
Connect the slave TRK input to a resistor divider from the error amplifier of about −18 mV at room temperature.
master voltage that is the same as the divider used on the slave A more accurate solution is to provide a divider from the
FB pin. This technique forces the slave voltage to be the same as master voltage that sets the TRK pin voltage to be something
the master voltage. lower than 0.6 V at regulation, for example, 0.5 V. The slave
For coincident tracking, use RTRKT = RTOP and RTRKB = RBOT, channel can be viewed as having a 0.5 V external reference
where RTOP and RBOT are the values chosen in the Compensating supplied by the master voltage.
the Voltage Mode Buck Regulator section. Once this is complete, the FB divider for the slave voltage is
MASTER VOLTAGE designed as in the Compensating the Voltage Mode Buck
Regulator section, except to substitute the 0.5 V reference for
VOLTAGE
SLAVE VOLTAGE the VFB voltage. The ratio of the slave output voltage to the
master voltage is a function of the two dividers:
 
05936-030
1  RTOP 
TIME
VOUT  R BOT 
Figure 31. Coincident Tracking    (52)
V MASTER  RTRKT 
As the master voltage rises, the slave voltage rises identically. 1 
 RTRKB 
Eventually, the slave voltage reaches its regulation voltage, 
where the internal reference takes over the regulation while the
Another option is to add another tap to the divider for the
TRK input continues to increase and thus removes itself from
master voltage. Split the RBOT resistor of the master voltage into
influencing the output voltage. To ensure that the output voltage
two pieces, with the new tap at 0.5 V when the master voltage is
accuracy is not compromised by the TRK pin being too close in
in regulation. This technique saves one resistor, but be aware
voltage to the 0.6 V reference, make sure that the final value of
that Type III compensation on the master voltage causes the
the master voltage is greater than the slave regulation voltage by
feedforward signal of the master voltage to appear at the TRK
at least 10%, or 60 mV as seen at the FB node. The higher the
input of the slave channel.
final value, the better the performance is. A difference of 60 mV
between TRK and the 0.6 V reference produces about 3 mV of By selecting the resistor values in the divider carefully, Equation 52
offset in the error amplifier, or 0.5%, at room temperature, while shows that the slave voltage output can be made to have a faster
100 mV between them produces only 0.6 mV or 0.1% offset. ramp rate than that of the master voltage by setting the TRK
voltage at the slave larger than 0.6 V and RTRKB greater than
RATIOMETRIC TRACKING RTRKT. Make sure that the master SS period is long enough (that
Ratiometric tracking limits the slave output voltage to a fraction is, sufficiently large SS capacitor) such that the input inrush
of the master voltage. For example, the termination voltage for current does not run into the current limit of the power supply
DDR memories, VTT, is set to half the VDD voltage. during startup.
MASTER VOLTAGE
VOLTAGE
SLAVE VOLTAGE
05936-031
TIME
Figure 32. Ratiometric Tracking
ADP1823 Data Sheet
Setting the Channel 2 Undervoltage Threshold for
RB = RBOT
(VUV 2 − VFB 2 )
(56)
Ratiometric Tracking VFB 2
If FB2 is regulated to a voltage lower than 0.6 V by configuring
THERMAL CONSIDERATIONS
TRK2 for ratiometric tracking, the Channel 2 undervoltage
threshold can be set appropriately by splitting the top resistor The current required to drive the external MOSFETs comprises
in the voltage divider, as shown in Figure 33. RBOT is the same as the vast majority of the power dissipation of the ADP1823. The
calculated for the compensation in Equation 52, and on-chip LDO regulates down to 5 V, and this 5 V supplies the
drivers. The full gate drive current passes through the LDO and
RTOP = RA + RB (53)
is then dissipated in the gate drivers. The power dissipated on
CHANNEL 2
OUTPUT the gate drivers on the ADP1823 is
VOLTAGE
PD = VIN fSW(QDH1 + QDL1 + QDH2 + QDL2) (57)
UV2 RA
where:
550mV VIN is the voltage applied to IN.
POK2
fSW is the switching frequency.
RB Q numbers are the total gate charge specifications from the
selected MOSFET data sheets.
750mV
TO ERROR
FB2 The power dissipation heats the ADP1823. As the switching
AMPLIFIER frequency, the input voltage, and the MOSFET size increase, the
05936-032
RBOT
power dissipation on the ADP1823 increases. Take care not to
exceed the maximum junction temperature. To calculate the
Figure 33. Setting the Channel 2 Undervoltage Threshold
junction temperature from the ambient temperature and power
The current in all the resistors is the same. dissipation
VFB 2 V − VFB 2 V − VUV 2 TJ = TA + PD θJA (58)
= UV 2 = OUT 2 (54)
RBOT RB RA The thermal resistance, θJA, of the package is typically 40°C/W
where: depending on board layout, and the maximum specified junction
temperature is 125°C, which means that at a maximum ambient
VUV2 is 600 mV. temperature of 85°C without airflow, the maximum dissipation
VFB2 is the feedback voltage value set during the ratiometric allowed is about 1 W.
tracking calculations.
VOUT2 is the Channel 2 output voltage. A thermal shutdown protection circuit on the ADP1823 shuts
off the LDO and the controllers if the die temperature exceeds
Solving for RA and RB, approximately 145°C, but this is a gross fault protection only
R A = RBOT
(VOUTA2 − VUV 2 ) (55)
and should not be relied upon for system reliability.
VFB 2
Data Sheet ADP1823
PCB LAYOUT GUIDELINES

In any switching converter, some circuit paths carry high dI/dt, • Avoid long traces or large copper areas at the FB and CSL
which can create spikes and noise. Other circuit paths are pins, which are low signal level inputs that are sensitive to
sensitive to noise. Still others carry high dc current and can capacitive and inductive noise pickup. It is best to position
produce significant IR voltage drops. The key to proper PCB any series resistors and capacitors as close as possible to
layout of a switching converter is to identify these critical paths these pins. Avoid running these traces close and parallel to
and arrange the components and copper area accordingly. high dI/dt traces.
When designing PCB layouts, be sure to keep high current • The switch node is the noisiest place in the switcher circuit
loops small. In addition, keep compensation and feedback with large ac and dc voltage and current. This node should
components away from the switch nodes and their associated be wide to minimize resistive voltage drop. However, to
components. minimize the generation of capacitively coupled noise, the
The following is a list of recommended layout practices for the total area should be small. Place the FETs and inductor all
ADP1823, arranged by decreasing order of importance. close together on a small copper plane to minimize series
resistance and keep the copper area small.
• The current waveform in the top and bottom FETs is a
• Gate drive traces (DH and DL) handle high dI/dt and,
pulse with very high dI/dt; therefore, the path to, through, and
therefore, they tend to produce noise and ringing. They
from each individual FET should be as short as possible
should be as short and direct as possible. If possible, avoid
and the two paths should be commoned as much as
using feedthrough vias in the gate drive traces. If vias are
possible. In designs that use a pair of D-Pak or SO-8 FETs
needed, it is best to use two relatively large ones in parallel
on one side of the PCB, it is best to counter-rotate the two
to reduce the peak current density and the current in each
so that the switch node is on one side of the pair and the
via. If the overall PCB layout is less than optimal, slowing
high-side drain can be bypassed to the low-side source
down the gate drive slightly can be very helpful to reduce
with a suitable ceramic bypass capacitor, placed as close as
noise and ringing. It is occasionally helpful to place small
possible to the FETs to minimize inductance around this
value resistors (such as 5 Ω or 10 Ω) in series with the gate
loop through the FETs and capacitor. The recommended
leads, mainly DH traces to the high-side FET gates. These
bypass ceramic capacitor values range from 1 μF to 22 μF
can be populated with 0 Ω resistors if resistance is not
depending upon the output current. This bypass capacitor is
needed. Note that the added gate resistance increases the
usually connected to a larger value bulk filter capacitor and
switching rise and fall times and that in turn increases the
should be grounded to the PGND plane.
switching power loss in the MOSFET.
• GND, the VREG bypass, the soft start capacitor, and the
• The negative terminal of output filter capacitors should be
bottom end of the output feedback divider resistors should
tied closely to the source of the low-side FET. Doing this
be tied to an (almost isolated) small AGND plane. All of
helps to minimize voltage difference between GND and
these connections should have connections from the pin
PGND at the ADP1823.
to the AGND plane that are as short as possible. No high
• Generally, be sure that all traces are sized according to the
current or high dI/dt signals should be connected to
current to be handled as well as their sensitivity in the
this AGND plane. The AGND area should be connected
circuit. Standard PCB layout guidelines mainly address
through one wide trace to the negative terminal of the
heating effects of current in a copper conductor. These are
output filter capacitors.
completely valid, but they do not fully cover other
• The PGND pin handles high dI/dt gate drive current
concerns, such as stray inductance or dc voltage drop. Any
returning from the source of the low-side MOSFET. The
dc voltage differential in connections between ADP1823
voltage at this pin also establishes the 0 V reference for the
GND and the converter power output ground can cause a
overcurrent limit protection (OCP) function and the CSL
significant output voltage error, because it affects converter
pin. A small PGND plane should connect the PGND pin
output voltage according to the ratio with the 600 mV
and the PVCC bypass capacitor through a wide and direct
feedback reference. For example, a 6 mV offset between
path to the source of the low-side MOSFET. The placement
ground on the ADP1823 and the converter power output
of CIN is critical for controlling ground bounce. The
causes a 1% error in the converter output voltage.
negative terminal of CIN needs to be placed very close to
the source of the low-side MOSFET.
ADP1823 Data Sheet
LFCSP CONSIDERATIONS • The paste mask for the thermal pad needs to be designed
The LFCSP has an exposed die paddle on the bottom that for the maximum coverage to effectively remove the heat
efficiently conducts heat to the PCB. To achieve the optimum from the package. However, due to the presence of thermal
performance from the LFCSP, give special consideration to the vias and the large size of the thermal pad, eliminating voids
layout of the PCB. Use the following layout guidelines for the may not be possible. In addition, if the solder paste
LFCSP: coverage is too large, solder joint defects may occur.
Therefore, it is recommended to use multiple small
• The pad pattern is given in Figure 36. The pad dimension openings over a single big opening in designing the paste
should be followed closely for reliable solder joints while mask. The recommended paste mask pattern is given in
maintaining reasonable clearances to prevent solder Figure 36. This pattern results in about 80% coverage,
bridging. which should not degrade the thermal performance of the
• The thermal pad of the LFCSP provides a low thermal package significantly.
impedance path to the PCB. Therefore, the PCB must be • The recommended paste mask stencil thickness is 0.125 mm.
properly designed to effectively conduct the heat away A laser cut stainless steel stencil with trapezoidal walls
from the package. This is achieved by adding thermal vias should be used.
to the PCB, which provide a thermal path to the inner or • A no-clean, Type 3 solder paste should be used for mounting
bottom layers. See Figure 36 for the recommended via the LFCSP. In addition, a nitrogen purge during the reflow
pattern. Note that the via diameter is small, which prevents process is recommended.
the solder from flowing through the via and leaving voids
• The package manufacturer recommends that the reflow
in the thermal pad solder joint.
temperature should not exceed 220°C and the time above
• Note that the thermal pad is attached to the die substrate; liquid is less than 75 seconds. The preheat ramp should be
therefore, the planes that the thermal pad is connected to 3°C per second or lower. The actual temperature profile
must be electrically isolated or connected to GND. depends on the board density; the assembly house must
• The solder mask opening should be about 120 microns determine what works best.
(4.7 mils) larger than the pad size, resulting in a minimum
60 microns (2.4 mils) clearance between the pad and the
solder mask.
• The paste mask opening is typically designed to match the
pad size used on the peripheral pads of the LFCSP. This
technique should provide a reliable solder joint as long as
the stencil thickness is about 0.125 mm.
Data Sheet ADP1823
APPLICATION CIRCUITS
The ADP1823 controller can be configured to regulate outputs are the polymer aluminum capacitors that are available from
with loads of more than 20 A if the power components, such as other manufacturers, such as United Chemi-Con. Aluminum
the inductor, MOSFETs, and the bulk capacitors, are chosen electrolytic capacitors, such as the Rubycon ZLG low-ESR series,
carefully to meet the power requirement. The maximum load can also be paralleled up at the input or output to meet the
and power dissipation are limited by the powertrain components. ripple current requirement. Because the aluminum electrolytic
Figure 1 shows a typical application circuit that can drive an capacitors have higher ESR and much larger variation in
output load of 8 A. capacitance over the operating temperature range, a larger bulk
Figure 34 shows an application circuit that can drive 20 A loads. input and output capacitance is needed to reduce the effective
Note that two low-side MOSFETs are needed to deliver the 20 A ESR and suppress the current ripple. Figure 34 shows that the
load. The bulk input and output capacitors used in this example polymer aluminum or the aluminum electrolytic capacitors can
are Sanyo OS-CON capacitors, which have low ESR and high be used at the outputs.
current ripple rating. An alternative to the OS-CON capacitors
IN = 5.5V TO 20V
1µF
PV IN EN1
TRK1 EN2
TRK2
CIN2 VREG CIN1
180µF 1µF D2 D1 1µF 180µF
20V BST1 BST2 20V
0.47µF 0.47µF
PGND
M4 DH1 DH2 M1
L2 L1
1.2V, 20A 1µH ADP1823 1µH 1.8V, 20A
SW1 SW2
COUT2 2kΩ 2kΩ COUT1
820µF 1µF 5600pF CSL1 CSL2 10nF 1µF
1200µF
25V M6 M5 DL1 DL2 M2 M3 6.3V
×2 ×3
390Ω 2kΩ 2kΩ 200Ω
PGND1 PGND2
FB1
120nF FB2
1.5nF
2kΩ
1kΩ
COMP1
10kΩ COMP2
47kΩ
4.7nF
6.8nF
FREQ
LDOSD
GND SYNC
AGND
fOSC = 300kHz D1, D2: VISHAY, BAT54

M1, M4: IRLR7807Z M2, M3, M5, M6: IRFR3709Z
05936-033
L1, L2: TOKO, FDA1254-1ROM CIN1, CIN2: SANYO, 20SP180M
COUT1: SANYO, 2R5SEPC820M COUT2: RUBYCON, 6.3ZLG1200M10×16
Figure 34. Application Circuit with 20 A Output Loads
ADP1823 Data Sheet
The ADP1823 can also be configured to drive an output load of package, which reduces cost and saves layout space. An alternative
less than 1 A. Figure 35 shows a typical application circuit that to using the dual-channel SO-8 package is using two single
drives 1.5 A and 3 A loads in all multilayer ceramic capacitor MOSFETs in SOT-23 or TSOP-6 packages, which are low cost
(MLCC) solutions. Notice that the two MOSFETs used in this and small in size.
example are dual-channel MOSFETs in a PowerPAK® SO-8
IN = 3.7V TO 5V
1µF
PV IN EN1
TRK1 EN2
TRK2
VREG
10µF D2 D1 10µF
1µF 1µF
×2 ×2
BST1 BST2
0.22µF 0.22µF
PGND
M3 DH1 DH2 M1
L2 L1
1.0V, 3A 2.2µH ADP1823 2.5µH
1.8V, 1.5A
SW1 SW2
COUT3 COUT2 4.12kΩ 1.4kΩ COUT1
1µF 8.2nF 8.2nF 1µF 10µF
100µF 47µF CSL1 CSL2 100µF
M4 DL1 DL2 M2
84.5Ω 1.33kΩ 2kΩ 84.5Ω
PGND1 PGND2
FB1 FB2
120nF 120nF
2kΩ 1kΩ
COMP1 COMP2
6.65kΩ 6.65kΩ
1.5nF 1.5nF
FREQ IN
LDOSD
GND SYNC
AGND
fOSC = 600kHz
M1 TO M4: DUAL-CHANNEL SO-8 IRF7331 L1: SUMIDA, CDRH5D28-2R5NC
05936-034
L2: TOKO, FDV0602-2R2M COUT1, COUT3: MURATA, GRM31CR60J107M
COUT2: MURATA, GRM31CR60J476M D1, D2: VISHAY BAT54
Figure 35. Application Circuit with All Multilayer Ceramic Capacitors (MLCC)
Data Sheet ADP1823
OUTLINE DIMENSIONS
5.10 0.30
5.00 SQ 0.25
PIN 1 4.90 0.18
INDICATOR PIN 1
25 32 INDICATOR
24 1
0.50
BSC
EXPOSED 3.25
PAD
3.10 SQ
2.95
17 8
16 9
0.50 0.25 MIN
TOP VIEW 0.40 BOTTOM VIEW
0.30 FOR PROPER CONNECTION OF
0.80 THE EXPOSED PAD, REFER TO
0.75 THE PIN CONFIGURATION AND
0.05 MAX FUNCTION DESCRIPTIONS
0.70 SECTION OF THIS DATA SHEET.
0.02 NOM
COPLANARITY
0.08
SEATING 0.20 REF
PLANE
112408-A
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD.
Figure 36. 32-Lead Lead Frame Chip Scale Package [LFCSP]

5 mm × 5 mm Body and 0.75 mm Package Height
(CP-32-7)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1 Temperature Range 2 Package Description Package Option
ADP1823ACPZ-R7 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP] CP-32-7
1
Z = RoHS Compliant Part.
2
Operating junction temperature range is −40°C to +125°C.
ADP1823 Data Sheet
NOTES
Data Sheet ADP1823
NOTES
ADP1823 Data Sheet
NOTES
©2006–2016 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D05936-0-4/16(E)

Dual, Interleaved, Step-Down DC-to-DC Controller With Tracking

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Dual, Interleaved, Step-Down

DC-to-DC Controller with Tracking

±0.85% accuracy at 0°C to 70°C IRLR7807Z DH1 DH2 IRLR7807Z

Independent Power OK (POK) outputs PGND1

Telecommunications and networking systems 4.53kΩ 3900pF

Rev. E Document Feedback

ABSOLUTE MAXIMUM RATINGS

FUNCTIONAL BLOCK DIAGRAM

0.8V REF 0.55V

LDOSD ILIM2 DH1

FREQ RAMP1 VREG

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 3. Pin Configuration

Table 3. Pin Function Descriptions

TYPICAL PERFORMANCE CHARACTERISTICS

SWITCHING FREQUENCY = 300kHz 4.968

86 SWITCHING FREQUENCY = 600kHz 4.960

FEEDBACK VOLTAGE (V)

0 50 100 150 200 250

SW1 PIN, VOUT = 1.8V, 10V/DIV

SW2 PIN, VOUT = 1.2V, 10V/DIV 1

VOUT1, 0.5V/DIV SW PIN, CHANNEL 1

INPUT CURRENT, 0.2A/DIV

SHORT CIRCUIT APPLIED 4ms/DIV SW PIN, CHANNEL 2

SWITCH NODE CHANNEL 2

SOFT START, 1V/DIV

TRACK PIN VOLTAGE, T

Figure 23. Output Voltage Tracking Response

The current limit is set through the current-limit resistor, RCL. M2

The current sense pins, CSL1 and CSL2, source 50 μA through DL

1 Figure 26. LC Filter Bode Plot

AMOD is the gain of the PWM modulator.

sometimes referred to as Type II or Type III compensation, Φ3

where: VREF VRAMP

1 The ADP1823 tracking input is an additional positive input to

DETAIL VIEW OF RTRKB

Figure 32. Ratiometric Tracking

PCB LAYOUT GUIDELINES

fOSC = 300kHz D1, D2: VISHAY, BAT54

Figure 34. Application Circuit with 20 A Output Loads

Figure 36. 32-Lead Lead Frame Chip Scale Package [LFCSP]

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