ECAD & VLSI LAB

Vivado (2018.1)
Introduction:
This lab guides you through the process of using Vivado IDE to create a simple HDL design
targeting the ZedBoard. You will simulate, synthesize, and implement the design with default
settings. Finally, you will generate the bitstream and download it in to the hardware to verify the
design functionality

Objectives:
After completing this lab, you will be able to:

 Create aVivado project sourcing HDL model(s) and targeting a specific FPGA device
located on the ZedBoard
 Use the provided Xilinx Design Constraint (XDC) file to constrainthe pin locations
 Simulate the design using the Vivado simulator
 Synthesize and implement the design
 Generate the bitstream
 Configure the FPGA using the generated bitstream and verify the functionality

Procedure:
This lab is broken into steps that consist of general overview statements providing
information on the detailed instructions that follow. Follow these detailed instructions to
progress through the lab1.

Design Description:
The design consists of some inputs directly connected to the corresponding output LEDs.
Other inputs are logically operated on before the results are output on the remaining LEDs as
shown in Figure 1.

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General Flow:

Step 1: Step 2: Step 3:

Create a Simulate the Synthesize

Vivado design using
project using the Design
Vivado
IDE simulator

Step 4: Step 5: Step 6:

Implement Perform the Verify

Timing functionality
the Design Simulation in Hardware

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PROCEDURE TO WORK WITH VIVADO(18.1 )TOOL

Open Vivado design Suite with following commands.

 cd /home/Xilinx/Vivado/2018.1/bin/

 ./vivado

1. Quick start  Create project.

2. Click Create New Project and click next to open new project wizard.

3. Select Project directory and mention new project name.

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4. Select RTL Project and check Do not specify sources at this time.

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5. Click Boards and select Zynq-7 in Part Selection window or select Part XC7Z020CLG484-
1 from the list of parts available.

6. Now the New Project summary display with project details selected.

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7. Now the Vivado tool opens with Flow Navigator on left and Project Manager on right. Flow
Navigator display the list of process involved from HDL input creation to bit file output
generation. Project manager consist of Source, Workspace and Report Window.

Source Window displays Design Sources (VHDL, Verilog), Constraints (XDC) and Simulation
sources. Workspace Window is used to create and view HDL/XDC files. Report Window consist
of TCL console, Messages, Logs, Reports and Design Rules.

8. Now click Add source and select Add create design sources.

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9. Click create file and select file type and file name as lab1.

10. In the Sources pane, double-click thelab1.v entry to open the file in text mode.

 Notice in the Verilog code that the first line defines the timescale directive for the
simulator. Lines 2-5 are comment lines describing the module name and the purpose of
the module.

 Line 7 defines the beginning (marked with keyword module) and Line 19 defines the end
of the module (marked with keyword endmodule).

 Lines 8-9 defines the input and output ports whereas lines 12-17 defines the actual
functionality.

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11. In the Sources pane, expand the Constraints folder and double-click thelab1.xdc entry to
open the file in text mode.

 Lines 5-20 defines the pin locations of the input switches [7:0] and lines 25-40 defines
the pin locations of the output LEDs [7:0].
12. Simulate the Design using the Vivado Simulator.
 Click Add Sources under the Project Manager tasks of the Flow Navigator pane.

 Select the Add or Create Simulation Sources option and click Next.

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 create the lab1_tb.v testbench file.

 Select the Sources tab and expand the Simulation Sources group. The lab1_tb.v file is
added under the Simulation Sources group, and lab1.v is automatically placed in its
hierarchy as a tut1 instance.

 Double-click on thelab1_tbin the Sources pane to view its contents.

 The testbench defines the simulation step size and the resolution in line 1. The testbench
module definition begins on line 5. Line 15 instantiates the DUT (device/module under
test). Lines 17 through 26 define the same module functionality for the expected value
computation. Lines 28 through 39 define the stimuli generation and compares the
expected output with what the DUP provides. Line 41 ends the testbench.

13. Simulate the design for 200 ns using the Vivado simulator.

 Select Simulation Settings under the Project Manager tasks of the Flow Navigator pane.
A Project Settings form will appear showing the Simulation properties form.

 Select the Simulation tab, and set the Simulation Run Time value to 200 ns and click
OK.

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 Click on Run Simulation > Run Behavioral Simulation under the Project
Manager tasks of the Flow Navigator pane.The testbench and source files will be
compiled and theVivado simulator will be run (assuming no errors). You will see a
simulator output similar to the one shown below.

 You will see four main views: (i) Scopes, where the testbench hierarchy as well as
glbl instances are displayed, (ii) Objects, where top-level signals are displayed, (iii)
the waveform window, and iv)Tcl Console where the simulation activities are
displayed. Notice that since the testbench used is self-checking, the results are
displayed as the simulation is run.

 Click on the Zoom Fit button ( ) to see the entire waveform.

 Notice that the output changes when the input changes. You can also float the
simulation waveform window by clicking on the Float button on the upper right hand
side of the view. This will allow you to have a wider window to view the simulation
waveforms. To reintegrate the floating window back into the GUI, simply click on the
Dock Window button.
 Close the simulator by selecting File >Close Simulation.

 Click OK and then click No to close it without saving the waveform.

14. Perform RTL analysis on the source file.

 Expand the Open Elaborated Designentry under the RTL Analysis tasks of the Flow
Navigator pane and click on Schematic.
 The model (design) will be elaborated and a logic view of the design is displayed.


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 Notice that some of the switch inputs go through gates before being output to LEDs and
the rest go straight through to LEDs as modeled in the file.
14. Synthesize the design with the Vivado synthesis tool and analyze the Project Summary
output.

 Click on Run Synthesis under the Synthesistasks of the Flow Navigator pane.

 The synthesis process will be run on the lab1.v file (and all its hierarchical files if
they exist). When the process is completed a Synthesis Completed dialog box with
three options will be displayed.
 Select the Open Synthesized Design option and click OK as we want to look at the
synthesis output before progressing to the implementation stage.
 Click Yes to close the elaborated design if the dialog box is displayed.

 Select the Project Summary tab and understand the various windows. If you don’t see
the Project Summary tab then selects Layout > Default Layout, or clicks the Project

Summary icon .

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 Click on the Table tab in the Project Summary tab.

 Notice that there are an estimated three LUTs and 16 IOs (8 input and 8 output) that are
used.

 In The Flow Navigator, under Synthesis (expand Synthesized Design if necessary), click
on Schematic to view the synthesized design in a schematic view.

15. Implement the design with the Vivado Implementation Defaults (Vivado
Implementation 2018) settings and analyze the Project Summary output.
 Click on Run Implementation under the Implementation tasks of the Flow Navigator
pane.
 The implementation process will be run on the synthesized design. When the process is
completed anImplementation Completed dialog box with three options will be displayed.

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 SelectOpen implemented designand click OKas we want to look at the implemented

design in a Device view tab.
 Click Yes,if prompted, to close the synthesized design.

 The implemented design will be opened. Click OK to see the device view.

 In the Netlist pane, select one of the nets (e.g. n_0_led_OBUF[1]_inst_i_1) and notice
that the net displayed in the X1Y1 clock region in the Device view tab (you may have to
zoom in to see it).

 If it is not selected, click the Routing Resources icon to show routing resources.

 Close the implemented design view and select the Project Summarytab (you may
have to change to the Default Layout view) and observe the results.
 Select the Post-Implementation tab.

 Notice that the actual resource utilization is three LUTs and 16 IOs. Also, it
indicates that no timing constraints were defined for this design (since the design is
combinatorial).

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 In Vivado, select the Reports tab in the bottom panel (if not visible, click Window in the menu
bar and select Reports), and double-click on the Utilization Report entry under the Place Design
section. The report will be displayed in the auxiliary view pane showing resource utilization.
Note that since the design is combinatorial no registers are used.

16. Run a timing simulation.

 Select Run Simulation > Run Post-Implementation Timing Simulation process under
the Simulation tasks of the Flow Navigator Pane.
 The Vivado simulator will be launched using the implemented design and lab1_tb as the
top-level module.
 Click on the Zoom Fit button to see the waveform window from 0 to 200 ns.
 Close the simulator by selecting File >Close Simulation without saving any changes.
17. Connect the board and power it ON. Generate the bitstream, open a hardware session, and
program the FPGA.
 Make sure that theMicro-USB cable is connected to the JTAG PROG connector
(next to the power supply connector). Connect the power jack.

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 Power ON the switch on the board.

 Click on the Generate Bitstream entry under the Program and Debug tasks of
the Flow Navigator pane.
 The bitstream generation process will be run on the implemented design. When the
process is completed a Bitstream Generation Completed dialog box with three options
will be displayed.

 This process will have generated alab1.bit file under impl_1 directory in the lab1.runs
directory.

 Select theOpen Hardware Session option and click OK.

 The Hardware Session window will open indicating “unconnected” status.

 Click on the Open New Hardware Target link.

 You can also click on the Open Recent Hardware Target link if the board was already
targeted before.

 Click Next to see the Vivado CSE Server Name form.

 Click Next with the localhost port selected.

 The JTAG cable which uses the digilent_plugin should be detected and identified as a
hardware target. It will also show the hardware devices detected in the chain.

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 Click Next twice and Finish.

 The Hardware Session status changes from Unconnected to the server name and the
device is highlighted. Also notice that the Status indicates that it is not programmed.

 Select the device and verify that the lab1.bit is selected as the programming file in the
General tab.

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 Right-click on the device and select Program Device… to program the target FPGA
device.

 Click Program to program the FPGA.

 The DONE light (Blue LED) will light when the device is programmed. You may see
some other LEDs lit depending on switch positions.
 Verify the functionality by flipping switches and observing the output on the LEDs
(Refer to the earlier logic diagram).
 When satisfied, power OFF the board.
 Close the hardware session by selecting File >Close Hardware Session.

 Click OK to close the session.

 Close theVivado program by selecting File > Exit and click OK.

Conclusion:
The Vivado software tool can be used to perform a complete design flow. The project was
created using the supplied source files (HDL model and user constraint file). A behavioral
simulation using the provided testbench was done to verify the model functionality. The model
was then synthesized, implemented, and a bitstream was generated. The timing simulation was
run on the implemented design using the same testbench. The functionality was verified in
hardware using the generated bitstream.

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EXPERIMENT NO:1
HDL CODE TO REALIZE ALL LOGIC GATES
AIM
To develop the source code for logic gates by using VERILOG and obtain the simulation,
synthesis, place and route and implement into FPGA.

SOFTWARE & HARDWARE

1. VIVADO 18.1
2. FPGA-ZYNQ-XC7Z020CLG484-1

LOGIC DIAGRAM

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VERILOG SOURCE CODE

module logicgates(a,b,c);

input a;

input b;

output [6:0]c;

assign c[0] = a&b;

assign c[1] = a|b;

assign c[2] = a^b;

assign c[3] = ~(a&b);

assign c[4] = ~(a|b);

assign c[5] = ~(a^b);

assign c[6] = ~a;

endmodule

Test Bench:

module tb_logicgates;

reg a,b;

wire [6:0]c;

logicgates U1(a,b,c);

initial begin

a=1’b0;b=1’b0;

#5

a=1’b1;b=1’b1;

#10

$stop();

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end

endmodule

SIMULATION RESULT

RESULT
Thus the outputs of all logic gates are verified by synthesizing and simulating the verilog
code.

VIVA QUESTIONS

1. Which gate output will be a LOW for any case when one or more inputs are zero.

2. If a signal passing through a gate is inhibited by sending a low into one of the inputs, and
the output is HIGH the gate is

3. Which logic gate can be used as a single transistor.

4. How many NAND circuits are contained in a 7400 NAND IC?

5. How many truth table entries are necessary for a four-input circuit?

6. Which IC’s can be used for AND ,OR ,INVERTER gates

7. Which IC’s can be used for NAND ,NOR gates.

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EXPERIMENT NO : 2
DESIGN OF 2-TO-4 DECODER
AIM
To develop the source code for decoder by using verilog and obtain the simulation,
synthesis, place and route and implement into FPGA.

SOFTWARE & HARDWARE

1. VIVADO 18.1
2. FPGA-ZYNQ-XC7Z020CLG484-1.

LOGIC DIAGRAM

A1 A0 EN C3 C2 C1 C0
X X 0 0 0 0 0
0 0 1 0 0 0 1
0 1 1 0 0 1 0
1 0 1 0 1 0 0
1 1 1 1 0 0 0

VERILOG SOURCE CODE

module decoder(a,c,en);

input [1:0]a;

input en;

output [3:0]c;

reg [3:0]c;

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always @(a,en)

begin

if(en= =1'b0)

c=4'b0000;

else

case(a)

2'b00: c=4'b0001;

2'b01: c=4'b0010;

2'b10: c=4'b0100;

2'b11: c=4'b1000;

endcase

end

endmodule

Test Bench:

module tb_decoder;

reg [1:0]a;

reg en;

wire [3:0]c;

decoder U1(a,c,en);

initial begin

a=2’b00;

en=1’b0;

#5

a=2’b00;

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en=1’b1;

#5

a=2’b01;

#10

$stop();

end

endmodule

SIMULATION RESULT

RESULT
Thus the output of decoder is verified by synthesizing and simulating the verilog code.
VIVA QUESTIONS
1. What is decoder?

2. For a 2- I/P decoder how many O/P‟s are produced

3. A decoder with „n‟ input produces max. of __ no. of minterms.

4. Draw the 2 to 4 line decoder with only nor gates.

5. Difference b/w de multiplexer and decoder

6. what is an IC number for 3x8decoder..

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EXPERIMENT NO:3
DESIGN OF 8-TO-3 ENCODER (WITH OUT AND WITH PRIORITY)
AIM
To develop the source code for encoder by using VERILOG and obtain the simulation,
synthesis, place and route and implement into FPGA.

SOFTWARE & HARDWARE

1. VIVADO 18.1
2. FPGA-ZYNQ-XC7Z020CLG484-1

LOGIC DIAGRAM
ENCODER WITHOUT PRIORITY

VERILOG SOURCE CODE

module encoder(a,b,en);

input[7:0]a;

input en;

output reg[2:0]b;

always@( en,a )

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begin

if(en= = 1’b0)

b=3’b000;

else

case(a)

8'b00000001: b=3'b 000;

8'b00000010: b=3'b 001;

8'b00000100: b=3'b 010;

8'b00001000: b=3'b 011;

8'b00010000: b=3'b 100;

8'b00100000: b=3'b 101;

8'b01000000: b=3'b 110;

8'b10000000: b=3'b 111;

default:b=3'bXXX;

endcase

end

endmodule

Test Bench:

module tb_encoder;

reg [7:0]a;

reg en;

wire [2:0]b;

encoder U1(a,b,en);

initial begin

en=1’b0;

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a=8’b00000001;

#5

en=1’b1;

a=8’b00000010;

#5

a=8’b00001000;

#10

$stop();

end

endmodule

SIMULATION RESULT

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ENCODER WITH PRIORITY

VERILOG SOURCE CODE

module encoderpp(en,a,b);

input [7:0]a;

input en;

output [2:0]b;

reg [2:0]b;

always@(a,en)

begin

if(en= =1'b0)

b<=3'b000;

else

case(1)

a[7]:b=3’b111;

a[6]:b=3’b110;

a[5]:b=3’b101;

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a[4]:b=3’b100;

a[3]:b=3’b011;

a[2]:b=3’b010;

a[1]:b=3’b001;

a[0]:b=3’b000;

endcase

end

endmodule

Test Bench:

module tb_encoderpp();

reg [7:0]a;

reg en;

wire [2:0]b;

encoderpp u1 (en,a,b);

initial begin

en=1’b0;

a=8’b00000010;

#5

en=1’b1;

a=8,b00001000;

#10

a=8’b00101101;

#10

a=8’b01001011;

#20

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$stop();

end

endmodule

SIMULATION RESULT

RESULT
Thus the output of encoder is verified by synthesizing and simulating the verilog code.

VIVA QUESTIONS
1. What is encoder?

2. Define priority encoder?

3. What is the IC number for encoder and priority encoder?

4. Applications of encoder?

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EXPERIMENT NO : 4

DESIGN OF 8:1 MULTIPLEXER AND 1:8 DEMULTIPLEXER

AIM
To develop the source code for multiplexer and demultiplexer by using verilog and obtain
the simulation, synthesis, place and route and implement into FPGA.

SOFTWARE & HARDWARE

1. VIVADO 18.1
2. FPGA-ZYNQ-XC7Z020CLG484-1

LOGIC DIAGRAM

MULTIPLEXER TRUTH TABLE

EN S2 S1 S0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Z
0 X X X X X X X X X X X 0
1 0 0 0 0 0 0 0 0 0 0 1 1
1 0 0 1 0 0 0 0 0 0 1 0 1
1 0 1 0 0 0 0 0 0 1 0 0 1
1 0 1 1 0 0 0 0 1 0 0 0 1
1 1 0 0 0 0 0 1 0 0 0 0 1
1 1 0 1 0 0 1 0 0 0 0 0 1
1 1 1 0 0 1 0 0 0 0 0 0 1
1 1 1 1 1 0 0 0 0 0 0 0 1

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VERILOG SOURCE CODE

module mux (y,s,en,z);

input [7:0] y;

input [2:0] s;

input en;

output z;

reg z;

always @ (y,s, en)

begin

if(en= =1'b0)

z=1'b0;

else

case(s)

3'b000 : z=y[0];

3'b001 : z=y[1];

3'b010 : z=y[2];

3'b011 : z=y[3];

3'b100 : z=y[4];

3'b101 : z=y[5];

3'b110 : z=y[6];

3'b111 : z=y[7];

endcase

end

endmodule

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Test Bench:

module tb_mux;

reg [7:0]y;

reg [2:0]s;

reg en;

wire [2:0]z;

mux u1(y,s,en,z);

initial begin

en=1’b0;

y=8’b10101000;

s=3’b000;

#10

en=1’b1;

y=8’b11010100;

s=3’b001;

#5

s=3’b010;

#5

$stop();

end

endmodule

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SIMULATION RESULT

DEMULTIPLEXER

TRUTH TABLE

I S2 S1 S0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
0 X X X 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0 0 1
1 0 0 1 0 0 0 0 0 0 1 0
1 0 1 0 0 0 0 0 0 1 0 0
1 0 1 1 0 0 0 0 1 0 0 0
1 1 0 0 0 0 0 1 0 0 0 0
1 1 0 1 0 0 1 0 0 0 0 0
1 1 1 0 0 1 0 0 0 0 0 0
1 1 1 1 1 0 0 0 0 0 0 0

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VERILOG SOURCE CODE

module demux(a,y,s,en);

output reg [7:0]y;

input [2:0]s;

input en,a;

always@(en,s,a)

begin

y=8’b00000000;

if(en = = 1'b0)

y = 8'b00000000;

else

case(s)

3'b 000 : y [0]=a;

3'b 001 : y [1]=a;

3'b 010 : y [2]=a;

3'b 011 : y [3]=a;

3'b 100 : y [4]=a;

3'b 101 : y [5]=a;

3'b 110 : y [6]=a;

3'b 111 : y [7]=a;

endcase

end

endmodule

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Test Bench:

module tb_demux;

reg en,a;

reg [2:0]s;

wire [7:0]y;

demux u1(a,y,s,en);

initial begin

en=1’b0;

a=1’b1;

s=3’b000;

#5

en=1’b1;

a=1’b0;

s=3’b001;

#5

a=1’b1;

s=1’b010;

#10

$stop();

end

endmodule

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SIMULATION RESULT

RESULT
Thus the output of Multiplexer and Demultiplexer is verified by synthesizing and
simulating in verilog code.

VIVA QUESTIONS
1. What is a multiplexer?

2. What is a de-multiplexer?

3. What are the applications of multiplexer and de-multiplexer?

4. Derive the Boolean expression for multiplexer an d de-multiplexer.

5. How do you realize a given function using multiplexer

6. What is the difference between multiplexer & de-multiplexer?

7. In 2n to 1 multiplexer how many selection lines are there?

8. How to get higher order multiplexers?

9. Implement an 8:1 mux using 4:1 muxes?

10. what is an IC number for 8x1 multiplexer and 1x8 demultiplexer

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EXPERIMENT NO: 5
DESIGN OF 4-BIT BINARY TO GRAY CONVERTER
AIM
To develop the source code for binary to gray converter by using verilog and obtained the
simulation, synthesis and implement into FPGA.

SOFTWARE & HARDWARE

1. VIVADO 18.1
2. FPGA-ZYNQ-XC7Z020CLG484-1

CODE CONVERTER (BINARY TO GRAY)

LOGIC DIAGRAM TRUTH TABLE

VERILOG SOURCE CODE

module BtoG(b,g);

input [3:0] b;

output [3:0]g;

assign g[3]=b[3];

assign g[2]=b[2]^b[3];

assign g[1]=b[2]^b[1];

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assign g[0]=b[1]^b[0];

endmodule

Test Bench:

module tb_btog;

reg[3:0]b;

wire[3:0]g;

btog gg(b,g);

initial begin

b=4’b0000;

#5 b=4’b0001;

-----

-----

#5 b=4’b1111;

#20

$stop;

end

endmodule

SIMULATION RESULT

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RESULT
Thus the output of binary to gray converter is verified by synthesizing and simulating
the verilog code.

VIVA QUESTIONS
1. Realize the Boolean expression for binary to gray and gray to binary converter?

2. What are code converter?

3. What is the necessity of code conversions?

4. What is gray code?

5. What is the IC number for binary to gray converter?

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EXPERIMENT NO:6
DESIGN OF 4 BIT COMPARATOR
AIM
To develop the source code for 4 bit comparator by using verilog and obtained the
simulation, synthesis, place and route and implement into FPGA.

SOFTWARE & HARDWARE

1. VIVADO 18.1
2. FPGA-ZYNQ-XC7Z020CLG484-1

LOGIC DIAGRAM

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VERILOG SOURCE CODE

module comparator(a,b,equal,greater,lower);

input [3:0]a;

input [3:0]b;

output reg equal,greater,lower;

always @(a , b)

begin

if(a<b)

begin

equal=0;

greater=0;

lower=1;

end

else if(a>b)

begin

equal=0;

greater=1;

lower=0;

end

else

begin

equal=1;

greater=0;

lower=0;

end

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end

endmodule

Test Bench:

module tb_comparator;

reg [3:0]a,b;

wire equal,greater,lower;

comparator u1(a,b,equal,grater,lower);

initial begin

a=4’b0000;

b=4’b0000;

#5

a=4’b0010;

b=4’b0001;

#5

$stop();

end

endmodule

SIMULATION RESULT

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RESULT
Thus the output of 4 bit comparator is verified by synthesizing and simulating the
VERILOG code.

VIVA QUESTIONS
1.What is Magnitude Comparator?
2. To form a 12 – bit comparator how many 4-bit comparators are connected in cascaded form.

3. The IC 7485 is a package and is a ____ comparator.

4. How many cascaded input are there for a 4-bit comparator.

5 what is an IC number for 4 bit comparator.

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EXPERIMENT NO:7
DESIGN OF FULL ADDER USING THREE MODELLING STYLES
AIM
To develop the source code for full adder using three modeling styles by using verilog
and obtained the simulation, synthesis, place and route and implement into FPGA.

SOFTWARE & HARDWARE

1. VIVADO 18.1
2. FPGA-ZYNQ-XC7Z020CLG484-1

LOGIC DIAGRAM

VERILOG SOURCE CODE

Dataflow Modeling:

module fuladdder(a,b,c,sum,carry);

input a,b,c;

output sum,carry;

assign sum=a^b^c;

assign carry=((a&b)|(b&c)|(c&a));

endmodule

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Behavioral Modeling:

module FuladderBM(a,b,c,sum,carry);

input a,b,c;

output reg sum,carry;

always @(a or b or c)

begin

sum=a^b^c;

carry=((a&b)|(b&c)|(c&a));

end

endmodule

Structural Modeling:

module fastruct(a,b,c,sum,carry);

input a,b,c;

output sum,carry;

wire t1,t2,t3;

xor(t1,a,b);

xor(sum,t1,c);

and(t2,a,b);

and(t3,t1,c);

or(carry,t2,t3);

endmodule

Test Bench:

module tb_fulladder;

reg a,b,c;

wire sum,carry;

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fulladder u1(a,b,c,sum,carry);

initial begin

a=1’b0;

b=1’b0;

c=1’b0;

#5

---

a=1’b1;

b=1’b1;

c=1’b1;

#5

$stop();

end

endmodule

SIMULATION RESULT

RESULT
Thus the outputs of full adder using three modeling styles are verified by synthesizing
and simulating the verilog code.

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EXPERIMENT NO:8
DESIGN OF FLIP FLOPS (SR,JK,D,T)
AIM
To develop the source code for FLIP FLOPS by using VERILOG and obtained the
simulation, synthesis, place and route and implement into FPGA.

SOFTWARE & HARDWARE

1. VIVADO 18.1
2. FPGA-ZYNQ-XC7Z020CLG484-1

LOGIC DIAGRAM
SR FLIPFLOP
CLK S R Q QT+1
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 x
1 1 1 x

VERILOG SOURCE CODE

SR FLIPFLOP

module srff(clk,rst,s,r,q,qb);

input clk,rst,s,r;

output reg q,qb;

always@(posedge clk , rst)

begin

if(rst= =1'b0)

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begin

q=q;

qb=qb;

end

else if(s= =1'b0 && r= =1'b0)

begin

q=q;

qb=qb;

end

else if(s= =1'b0 && r= =1'b1)

begin

q=q;

qb= ~q;

end

else if(s==1'b1 && r==1'b0)

begin

q=1'b1;

qb=~q;

end

else if(s= =1'b1 && r= =1'b1)

begin

q=1'bX;qb=~q;

end

end

endmodule

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Test Bench:

module tb_srff;

reg s,r,clk,rst;

wire q,qb;

srff u1(clk,rst,s,r,q,qb);

initial begin

clk=1’b0;

forever

#5

clk=~clk;

end

initial begin

rst=1’b0;s=1’b0;r=1’b0;

#5 rst=1’b1;s=1’b0;r=1’b1;

#5 s=1’b0;r=1’b1;

#5

$stop();

end

endmodule

SIMULATION RESULT

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JK FLIPFLOP

CLK J K Q QT+1
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0

VERILOG SOURCE CODE

module jkff(clk,rst,j,k,q,qb);

input clk,rst,j,k;

output reg q,qb;

always@(posedge clk ,rst)

begin

if(rst= =1'b0)

begin

q=q;

qb=qb;

end

else if(j= =1'b0 && k= =1'b0)

begin

q=q;

qb=qb;

end

else if(j==1'b0 && k==1'b1)

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begin

q=q;

qb=~q;

end

else if(j==1'b1 && k==1'b0)

begin

q=1'b1;

qb=~q;

end

else if(j==1'b1 && k==1'b1)

begin

q=~q;

qb=~qb;

end

end

endmodule

Test Bench:

module tb_jkff;

reg j,k,clk,rst;

wire q,qb;

jkff u1(clk,rst,j,k,q,qb);

initial begin

clk=1’b0;

forever

#5

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clk=~clk;

end

initial begin

rst=1’b0;j=1’b0;k=1’b0;

#5 rst=1’b1;j=1’b0;k=1’b1;

#5 j=1’b0;k=1’b1;

#5

$stop();

end

endmodule

SIMULATION RESULT

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D FLIPFLOP TRUTH TABLE

CLK D Q QT+1
0 0 0
0 1 0
1 0 1
1 1 1

VERILOG SOURCE CODE

module dff(d,clk,rst,q,qb);

input d,clk,rst;

output reg q,qb;

always@(posedge clk ,rst)

begin

if(rst= =1'b0)

begin

q=1'b0;

qb=~q;

end

else if(d= =1'b0)

begin

q=1'b0;

qb=~q;

end

else

begin

q=1'b1;

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qb=~q;

end

end

endmodule

Test Bench:

module tb_dff;

reg d,clk,rst;

wire q,qb;

dff u1(d,clk,rst,q,qb);

initial begin

clk=1’b0;

forever

#5

clk=~clk;

end

initial begin

rst=1’b0;d=1’b0;

#5 rst=1’b1;d=1’b0;

#5 d=1’b0;

#5

$stop();

end

endmodule

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SIMULATION RESULT

T FLIPFLOP TRUTH TABLE

CLK T Q QT+1
0 0 0
0 1 1
1 0 1
1 1 0

VERILOG SOURCE CODE

module tff(T,clk,rst,q,qb);

input T,clk,rst;

output reg q,qb;

always@(posedge clk , rst)

begin

if(rst= =1'b0)

begin

q=1'b0;

qb=~q;

end

else if(T= =1'b0)

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begin

q=q;

qb=~q;

end

else

begin

q=~q;

qb=~qb;

end

end

endmodule

Test Bench:

module tb_tff;

reg T,clk,rst;

wire q,qb;

tff u1(T,clk,rst,q,qb);

initial begin

clk=1’b0;

forever

#5

clk=~clk;

end

initial begin

rst=1’b0;T=1’b0;

#5 rst=1’b1;T=1’b0;

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#5 T=1’b0;

#5

$stop();

end

endmodule

SIMULATION RESULT

RESULT
Thus the outputs of Flip flops are verified by synthesizing and simulating the verilog
code.

VIVA QUESTIONS
1. what is flip-flop?

2. what is disadvantage of SR flip-flop?

3. what is disadvantage of JK flip-flop?

4. To remove race around condition what we use?

5. what is race around condition?

6. what are the characteristic equation for T flip-flop?

7. D flip-flop is used for?

8. what is full form of T flip-flop?

9. Define a latch?

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EXPERIMENT NO : 9
FINITE STATE MACHINE DESIGN
AIM
To develop the source code for FSM by using VERILOG and obtained the simulation,
synthesis, place and route and implement into FPGA.

SOFTWARE & HARDWARE

1. VIVADO 18.1
2. FPGA-ZYNQ-XC7Z020CLG484-1

LOGIC DIAGRAM

Figure : State Transition Diagram

VERILOG SOURCE CODE

module fsm(x,rst,clk,z);

input x,clk,rst;

output z;

reg [1:0]state;

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parameter a=2’b00 , b=2’b01 , c=2’b10 , d=2’b11;

always@(posedge clk )

begin

if(rst= =1’b0)

state=a;

else

case(state)

a:begin

if(x= =0)

state=a;

else

state=b;

end

b:begin

if(x= =0)

state=c;

else

state=b;

end

c:begin

if(x= =0)

state=a;

else

state=d;

end

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d:begin

if(x= =0)

state=c;

else

state=b;

end

endcase

end

assign z=(state= =)? 1:0;

endmodule

Test Bench:

Module tb_fsm;

Reg clk,rst,x;

Wire z;

fsm hh(x,rst,clk,z);

Initial begin

Clk=1’b0;

Forever

#5 clk=~clk;

End

Initial begin

X=0;rst=0;

#10 x=1;rst=1;

#10 x=1;

#10 x=0;

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#20;

$stop;

endendmodule

SIMULATION RESULT

RESULT
Thus the output of FSM are verified by synthesizing and simulating the verilog code.

VIVA QUESTIONS
1. What is FSM

2. What is the difference between Mealy and Moore FSM?

3. What are various types of state encoding techniques? Explain them.

4. What are Difference between one hot and binary encoding?

5. Design a FSM (Finite State Machine) to detect a sequence 10110?

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