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    Vlsi Design April 2019

    Uploaded by

    Rakesh
    1. The document contains questions from a VLSI Design exam for a third year engineering course. It is divided into two parts - Part A containing short answer questions and Part B containing longer answer questions. 2. Part A asks about equations for MOSFET operation, stick diagrams, constraints in layer choice, ad-hoc testing techniques, RTL synthesis information, and clock skew. 3. Part B contains longer answer questions about MOSFET fabrication processes, transconductance derivation, CMOS gate stick diagrams, driving large capacitors, fault testing categories and techniques, FPGA design processes, and scaling limitations for low power design.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd

    Vlsi Design April 2019

    Uploaded by

    Rakesh
    34 views4 pages
    1. The document contains questions from a VLSI Design exam for a third year engineering course. It is divided into two parts - Part A containing short answer questions and Part B containing longer answer questions. 2. Part A asks about equations for MOSFET operation, stick diagrams, constraints in layer choice, ad-hoc testing techniques, RTL synthesis information, and clock skew. 3. Part B contains longer answer questions about MOSFET fabrication processes, transconductance derivation, CMOS gate stick diagrams, driving large capacitors, fault testing categories and techniques, FPGA design processes, and scaling limitations for low power design.

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    © © All Rights Reserved

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    1. The document contains questions from a VLSI Design exam for a third year engineering course. It is divided into two parts - Part A containing short answer questions and Part B containing longer answer questions. 2. Part A asks about equations for MOSFET operation, stick diagrams, constraints in layer choice, ad-hoc testing techniques, RTL synthesis information, and clock skew. 3. Part B contains longer answer questions about MOSFET fabrication processes, transconductance derivation, CMOS gate stick diagrams, driving large capacitors, fault testing categories and techniques, FPGA design processes, and scaling limitations for low power design.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    34 views4 pages

    Vlsi Design April 2019

    Uploaded by

    Rakesh
    1. The document contains questions from a VLSI Design exam for a third year engineering course. It is divided into two parts - Part A containing short answer questions and Part B containing longer answer questions. 2. Part A asks about equations for MOSFET operation, stick diagrams, constraints in layer choice, ad-hoc testing techniques, RTL synthesis information, and clock skew. 3. Part B contains longer answer questions about MOSFET fabrication processes, transconductance derivation, CMOS gate stick diagrams, driving large capacitors, fault testing categories and techniques, FPGA design processes, and scaling limitations for low power design.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 4

    Code No: R1632043 R16 SET - 1

    III B. Tech II Semester Regular Examinations, April/May - 2019


    VLSI DESIGN
    (Common to Electronics and Communication Engineering, Electronics and Instrumentation
    Engineering, Electronics and Computer Engineering)
    Time: 3 hours Max. Marks: 70
    Note: 1. Question Paper consists of two parts (Part-A and Part-B)
    2. Answer ALL the question in Part-A
    3. Answer any FOUR Questions from Part-B
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    PART –A
    1. a) Write down the equations for Ids of an n-channel enhancement MOSFET operating in [2M]
    Non-saturated region and saturated region.
    b) Define stick diagram and layout diagram. [2M]
    c) Explain about the constraints in choice of layers. [2M]
    d) Mention the common techniques involved in ad-hoc testing. [3M]
    e) What information from the targeted FPGA device is required in RTL synthesis? [3M]
    f) Explain about clock skew. [2M]

    PART -B
    2. a) Explain the nMOS enhancement mode fabrication process for different conditions of [7M]
    Vds.
    b) Derive an expression for transconductance of an n-channel enhancement MOSFET [7M]
    operating in active region.

    3. a) Draw a stick diagram and layout for two input CMOS NAND gate indicating all the [7M]
    regions and layers.
    b) Explain 2 µm Double Metal, Double Poly CMOS / BiCMOS Rules. [7M]

    4. a) Explain the issues involved in driving large capacitor loads in VLSI circuit regions. [7M]
    b) Calculate the gate capacitance value of 5 mm technology minimum size transistor with [7M]
    gate to channel value is 4 x 10-4 pF/mm2.

    5. a) Explain about the following types of faults with suitable example: [7M]
    (i) stuck at faults (ii) Bridge faults (iii) temporary faults
    b) Explain the different categories of DFT techniques. [7M]

    6. a) Write down the step by step approach for FPGA design process on XILINX [7M]
    environment?
    b) Draw and explain the basic architecture of FPGA. [7M]

    7. a) Explain about deep submicron processes with suitable schematic diagrams. [7M]
    b) Explain about the scaling limitation for low voltage, low power design. Give the effect [7M]
    of scaling on various MOSFET parameters with necessary equations.

    ******

    |''|'||||''|'''|||'|
    Code No: R1632043 R16 SET - 2

    III B. Tech II Semester Regular Examinations, April/May - 2019


    VLSI DESIGN
    (Common to Electronics and Communication Engineering, Electronics and Instrumentation
    Engineering, Electronics and Computer Engineering)
    Time: 3 hours Max. Marks: 70
    Note: 1. Question Paper consists of two parts (Part-A and Part-B)
    2. Answer ALL the question in Part-A
    3. Answer any FOUR Questions from Part-B
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    PART –A
    1. a) Explain the terms SSI, LSI, and VLSI with the number of transistors per chip and [2M]
    applications.
    b) Draw the stick diagram for CMOS Inverter. [2M]
    c) What is sheet resistance? Derive the Expression for RS? [2M]
    d) What are the approaches in design for testability? [3M]
    e) Explain synthesis process. [3M]
    f) What are the different types of power consumption? [2M]

    PART -B
    2. a) Explain in detail the p-well process for CMOS fabrication indicating the masks used. [7M]
    b) Compare the relative merits of three different forms of pull-up for an inverter circuit. [7M]
    What is the best choice for realization in nMOS and CMOS technology?

    3. a) What are the λ-based design rules? Give them for each layer. [7M]
    b) Draw a stick diagram for CMOS logic Y= (A+B+C)Ꞌ. [7M]

    4. a) What is inverter delay? How delay is calculated for multiple stages? Explain. [7M]
    b) Two nMOS inverters are cascaded to drive a capacitive load C L=16Cg. Calculate pair [7M]
    delay Vin to Vout in terms of τ.

    5. a) What are the different faults found in combinational circuits? How can they be [7M]
    categorized?
    b) Briefly discuss about Built-In-Self Test technique with a suitable diagram. [7M]

    6. a) Give the steps in FPGA design flow with flow diagram and briefly discuss about each [7M]
    step.
    b) Explain about the principle and operation of FPGAs. What are its applications? [7M]

    7. a) Discuss about the various problems associated with low voltage VLSI circuit design. [7M]
    b) Explain about estimation and optimization of switching activity. [7M]

    *****

    |''|'||||''|'''|||'|
    Code No: R1632043 R16 SET - 3

    III B. Tech II Semester Regular Examinations, April/May - 2019


    VLSI DESIGN
    (Common to Electronics and Communication Engineering, Electronics and Instrumentation
    Engineering, Electronics and Computer Engineering)
    Time: 3 hours Max. Marks: 70
    Note: 1. Question Paper consists of two parts (Part-A and Part-B)
    2. Answer ALL the question in Part-A
    3. Answer any FOUR Questions from Part-B
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    PART –A
    1. a) Define Moore’s law. [2M]
    b) Draw a symbolic layout of a two–input NAND gate. [3M]
    c) Give the scaling factor for Maximum operating frequency (f0) in terms of different [2M]
    scaling models.
    d) What is meant by observability? [3M]
    e) What are FPGAs? [2M]
    f) What is switching activity? [2M]
    PART -B
    2. a) Compare BiCMOS technology with other Technologies. [7M]
    b) Calculate ID and VDS if kn = 100 μA/v2, Vtn = 0.6V and W/L =3 for transistor M1, in [7M]
    the circuit shown below:

    3. a) Explain with suitable examples how to design the layout of a Gate to maximize [7M]
    performance and minimize area.
    b) Design a stick diagram for nMOS logic Y= (A+B+C)Ꞌ. [7M]
    4. a) How does depletion regions around source and drain are affected due to scaling [7M]
    down of device dimensions? Explain.
    b) Derive the expression for propagation delay in the case of cascaded pass transistors. [7M]

    5. a) Define the terms ‘failure’ and ‘fault’. Discuss the different fault models. [7M]
    b) Briefly discuss about On-Chip clock generation and distribution. [7M]
    6. a) Explain the following terms: [8M]
    (i) LUT (ii) CLB (iii) IOB (iv) Switch matrix
    b) List out the various FPGA families. Explain how they are different from each [6M]
    other?
    7. a) Explain about the design limitations imposed on low power, low voltage circuits [7M]
    pertaining to the scaling and inter connect wires.
    b) Briefly discuss about the different techniques for reduction of switching [7M]
    capacitance.
    *****

    |''|'||||''|'''|||'|
    Code No: R1632043 R16 SET - 4

    III B. Tech II Semester Regular Examinations, April/May - 2019


    VLSI DESIGN
    (Common to Electronics and Communication Engineering, Electronics and Instrumentation
    Engineering, Electronics and Computer Engineering)
    Time: 3 hours Max. Marks: 70
    Note: 1. Question Paper consists of two parts (Part-A and Part-B)
    2. Answer ALL the question in Part-A
    3. Answer any FOUR Questions from Part-B
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    PART –A
    1. a) Discuss the microelectronics evolution. [3M]
    b) What is Vias? How to construct it in layout? [2M]
    c) What is the need of scaling in MOS circuits? [2M]
    d) Explain how function of system can be tested. [2M]
    e) List out the commercially available FPGAs. [3M]
    f) What is the need of interconnect? [2M]
    PART -B
    2. a) What are the additional two layers in BiCMOS technology compared to others? [7M]
    With neat sketches explain BiCMOS fabrication process.
    b) Show that the switching speed of an enhancement MOSFET varies inversely as [7M]
    the square of the channel length.

    3. a) Give the design rules for the following cases with neat sketches: [8M]
    (i) Polysilicon – polysilicon (ii) n-type diffusion – n-type diffusion
    (iii) n-type diffusion – p-type diffusion (iv) metal 1 – metal 2.
    b) Design a stick diagram for two input pMOS NAND and NOR gates. [6M]

    4. Describe the following briefly [14M]


    (i) Cascaded inverters as drivers (ii) Super buffers (iii) BiCMOS drivers

    5. a) Explain the terms controllability, observability and fault coverage. [7M]


    b) With suitable diagrams, explain the Scan based test techniques. [7M]

    6. a) List out the different configuration modes in FPGA. Briefly discuss about it. [7M]
    b) How the pass transistors are used to connect wire segments for the purpose of [7M]
    FPGA programming? Explain.

    7. a) What is the different technical parameter issues connected with VLSI low power [7M]
    and low voltage design? Explain.
    b) With schematic diagrams explain about deep submicron processes. [7M]

    *****

    |''|'||||''|'''|||'|

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