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31000 - E LECTRONICS . T UTORIAL

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5 Flip-flops and Latches
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Purpose Acquire practical skills in developing behavioural VHDL of sequential circuits.

Assignment Develop behavioural VHDL models of the digital circuits specified in the exercise. Check
the correctness of the models through a simulation.
Contents
• D flip-flop.
• D flip-flop with asynchronous RESET.
• D flip-flop with asynchronous RESET and ENABLE.
• Register
• R-S flip flop
• D latch

Before starting the exercise answer the following questions and carry out the following tasks:
• Draw a RS latch with NAND gates
• Write the function table of a RS latch
• Modify the RS latch such as it remembers the value if a signal ENABLE is set. (Hint: use AND gates between the
enable and the S/R inputs).
• Modify the RS latch with ENABLE such as to obtain a D latch with enable. (Hint: the S and R inputs should be
complementary. Use a NOT gate.)
• What is the difference between a latch and a flip-flop ?
• How are the edge sensitive signals drawn in schematics ?
• Write down the function table of a J-K flip-flop.
• Draw a D-Type Positive-Edge-Triggered Flip-Flop. Use a D flip-flop with enable (as a circuit) with two outputs Q
and Q̄ and an RS latch with enable at the output.
• What is the difference between the types bit and std logic ?
• Which libraries are opened by default ?

D flip-flop
Table 1 describes the ports of a D flip flop. The input d is remembered at the rising edge of the clock signals clk.
Figure 1 shows the behavioural description of a D flip-flop.

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31000 - Electronics. Tutorial Flip-flops and Latches

Signal Type Direction Function

d std logic Input Data input
clk std logic Input Clock
q std logic Output Data output

Table 1: Description of the signals of a D flip flop.

library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is port (

d: in std_logic;
clk: in std_logic;
q: out std_logic
);
end DFF;

architecture rtl of DFF is

begin

process (clk) begin

if rising_edge(clk) then
q <= d;
end if;
end process;

end rtl;

Figure 1: Behavioural description of a D flip-flop.

• Study the code.

• Make sure that you understand every line of code.
• What does the function rising edge do ?
• What is an attribute in VHDL ?
• Find out which attributes exist .

Figure 2: Simulation of a D flip-flop.

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31000 - Electronics. Tutorial Flip-flops and Latches

• How would you detect the rising edge of a signal in VHDL without using the function rising edge ?
• Is the use of the function rsing edge necessary in the case of the code in Fig. 1 ?
• Simulate the VHDL model by giving the following input signals:

wave /*
force clk 0 0, 1 60 -repeat 120
force d 0 0, 1 100, 0 200
run 400

The results from the simulation are shown in Fig. 2.

D flip-flop with asynchronous RESET

’
Table 2 shows the ports of a D flip-flop with asynchronous RESET.

Signal Type Direction Function

d std logic Input Data input
clk std logic Input Clock signal
rst std logic Input Input for asynchronous RESET
(zero output). Active low level.
q std logic Output Data output

Table 2: Description of the ports of a D flip-flop with asynchronous RESET.

library IEEE;
use IEEE.std_logic_1164.all;

entity DFFAR is port (

d: in std_logic;
clk: in std_logic;
rst: in std_logic;
q: out std_logic);
end DFFAR;

architecture rtl of DFFAR is

begin

process (clk, rst) begin

if rst = ’0’ then
q <= ’0’;
elsif rising_edge(clk) then
q <= d;
end if;
end process;

end rtl;

Figure 3: Behavioural description of a D flip-flop with asyncrhonous RESET.

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31000 - Electronics. Tutorial Flip-flops and Latches

Fig. 3 shows the behavioural model of the D flip-flop. When is the process called ? Notice that the check for an active
RESET signal is done prior to the check for a rising edge of the clock signal. Is the use of the function rising edge
necessary in this code ? Explain.
Simulate the VHDL model by choosing suitable excitations such as to get the result shown in Fig. 4

Figure 4: Simulation of a D flip-flop with asynchronous RESET.

D flip-flop with asynchronous RESET and ENABLE

Table 3 gives the port description of the D flip-flop with asynchronous RESET and ENABLE.

Signal Type Direction Function

d std logic Input Data input
clk std logic Input Clock signal
rst std logic Input Input for asynchronous RESET
(zero output). Active low level.
ena std logic Input Enable. Active high.
q std logic Output Data output

Table 3: Description of the ports of a D flip-flop with asynchronous RESET.

Develop the behavioural model of the flip-flop.

Directions:
1. Use the model of the D flip-flop shown in the previous assignment

2. After the check for a rising edge, add a check for the signal ena. Use a separate
if-then-else construct for the latter.

Simulate the VHDL model using the following inputs:

wave /*
force clk 0 0, 1 60 -repeat 120
force d 1 0
force rst 0 0, 1 30, 0 130, 1 140
force ena 1 0, 0 150, 1 250
run 400
The results of the simulation are shown in Fig. 5.

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31000 - Electronics. Tutorial Flip-flops and Latches

Figure 5: Simulation of a D flip-flop with asynchronous RESET and ENABLE.

Register

Signal Type Direction Function

d std logic vector(7 Input Data input
downto 0)
clk std logic Input Clock signal
rst std logic Input Input for asynchronous RESET
(zero output). Active low level.
ena std logic Input Enable. Active high.
q std logic vector(7 Output Data output
downto 0)

Table 4: Description of the ports of an 8 bit register with asynchronous RESET and ENABLE.

Develop a behavioural VHDL model of the register.

Directions:
1. The register is just a couple of D flip-flops with common RESET and ENABLE
signals.
2. Use the model of the D flip-flop developed in the previous assignment.

Simulate the VHDL model by using the following input signals:

wave /*
force clk 0 0, 1 50 -repeat 100
force d 1111000 0, 000111 500, 10101010 1000
force rst 1 0, 0 850, 1 900
force ena 1 0, 0 200, 1 700
run 1500
The results of the simulations is given in Fig. 6.

R-S flip-flop
The description of the ports of a R-S flip-flop are given in Table 5. The changes in the state of the flip-flop is at the rising
edge of clk.

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31000 - Electronics. Tutorial Flip-flops and Latches

Figure 6: Results from the simulations of the 8-bit register.

Signal Type Direction Function

clk std logic Input Clock signal
R std logic Input See a truth table
S std logic Input See a truth table
Q std logic Output Data output

Table 5: Description of the ports of a R-S flip-flop.

Develop a behavioural VHDL model of the described R-S flip-flop.

1. Use the model of the D flip-flop from the first assignment as a base.
2. After checking for a rising edge of the clock, use an if-then-else operator for
Directions: checking the conditions:

R = ’0’ and S = ’0’

R = ’1’ and S = ’0’
R = ’1’ and S = ’1’

3. In order to preserve the pre condition, it sufficient that the condition R = ’0’ and
S = ’0’ is not checked in the if condition
4. In order to assign an undefined output to the flip-flop, use the value ’X’.

Simulate the VHDL model using the following input signals:

wave /*
force clk 0 0, 1 50 -repeat 100
force r 1 0, 0 100, 1 400
force s 0 0, 1 200, 0 300, 1 400
run 500

The results from the simulation are shown in Fig. 7

D latch
Table 6 shows the description of the ports of a D latch. While ena is high (=’1’) the output q follows the input d. When
ena=’0’ the output q remembers the last value and is not influenced by the input d.
Figure 8 gives the VHDL model of a D latch. Pay attention of the condition in the if operator. It is not fully specified,
i.e. the output q is not given for all values of ena. What are the missing values of ena ?
Simulate the VHDL model of D latch. Choose the input signals such as to get a result like the one in Fig. 9.

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31000 - Electronics. Tutorial Flip-flops and Latches

Figure 7: Results from the simulation of a R-S flip-flop.

Signal Type Direction Function

d std logic Input Data input
ena std logic Input Enable signal
q std logic Output Data output

Table 6: Description of the ports of a D latch.

library IEEE;
use IEEE.std_logic_1164.all;

entity DLATCH is port (

d: in std_logic;
ena: in std_logic;
q: out std_logic);
end DLATCH;

architecture rtl of DLATCH is

begin

process (ena, d) begin

if ena = ’1’ then
q <= d;
end if;
end process;

end rtl;

Figure 8: Behavioural description of a D latch with ENABLE.

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31000 - Electronics. Tutorial Flip-flops and Latches

Figure 9: The result of the simulation of a D latch.

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