MPC565PB/D

MOTOROLA Rev. 2, 5 December 2001

SEMICONDUCTOR
PRODUCT BRIEF
MPC565/MPC566
Product Brief
MPC565/MPC566 RISC MCU with Code
Compression Option
Features

The MPC565 / MPC566 key features are as follows. The information inside boxes are optional features.

• 40 MHz / 56 MHz operation

• 56 MHz operation is available as an option.
— -40° – 125 °C ambient temperature
— 2.6 V ± 0.1 V external bus
• External bus is compatible with external memory devices operating from 2.5 V to 3.4 V.
• Extended voltage range (2.7 – 3.4 V) degrades data drive timing by 1.1 ns on date writes.
— 2.6 ± 0.1 V internal logic
— 5-V I/O (5.0 ± 0.25 V)
• High performance RISC CPU system
— High performance core
• Single issue integer core
• Instruction set compatible with PowerPC instruction set architecture
• Precise exception model
• Floating point
• Code compression supported on the MPC566
— Compression reduces usage of internal or external flash memory
— Compression optimized for automotive (non-cached) applications
— New compression scheme increases compression performance to 40% – 50% compres-
sion
— 4-Kbyte static DECRAM can be used as memory if Compression is not used.
— General-purpose I/O support
• On address (24) and data (32) pins
• 16 GPIO in MIOS14
• Many peripheral pins can be used as GPIO when not used as primary functions
• 2.6-V outputs on external bus pins
• Extensive system development support
— On-chip watchpoints and breakpoints
— Program flow tracking
— Background debug mode (BDM)

Key Feature Details

MPC500 System Interface (USIU, BBC, L2U)

• Periodic interrupt timer, bus monitor, clocks, decrementer and time base
• Clock synthesizer, power management, reset controller
• External bus tolerates 5-V inputs, provides 3.3-V outputs
• Enhanced interrupt controller supports a separate interrupt vector for up to eight external and 40
Internal interrupts

This document contains information on a new product. Specifications and

information herein are subject to change without notice.

© MOTOROLA 2001, All Rights Reserved

 • IEEE 1149.1 JTAG test access port
• Bus supports multiple master designs
• Flexible memory protection units in BBC (IMPU) and L2U (DMPU)
• Flexible chip selects via memory controller
— 24-bit address and 32-bit data buses
— Four- to 16-Mbyte (data) or 4-Gbyte (instruction) region size support
— Four-beat transfer bursts, two-clock minimum bus transactions
— Use with SRAM, EPROM, flash and other peripherals
— Byte selects or write enables
— 32-bit address decodes with bit masks
— Four instruction regions
— Four data regions
• Default attributes available in one global entry
• Attribute support for speculative accesses
• Exception vector table relocation features allow exception table to be relocated to following loca-
tions:
— 0x0000 0100 (normal MPC5xx exception table location)
— 0x0001 0000 (0 + 64 Kbytes; second page of internal flash)
— Second internal flash module
— Internal SRAM
— 0x0FFF_0100 (external memory space; normal MPC5xx exception table location)
• USIU supports dual-mapping of flash to move part of internal flash memory to external bus for de-
velopment

One Mbyte Flash

• Two UC3F modules, 512 Kbytes each
• Page mode read
• Block (64-Kbyte) erasable
• External 4.75- to 5.25-V VPP program, erase, and read power supply

36-Kbyte Static RAM (CALRAM)

• Composed of four- and 32-Kbyte CALRAM modules
• Fast access: one clock
• Keep-alive power
• Soft defect detection (SDD)
• 4-Kbyte calibration (overlay) RAM per module (eight Kbytes total)
• Eight 512-byte overlay regions per module (16 regions total)

IEEE – ISTO Nexus 5001-1999 Debug Port (Class 3)

• Address (24) and data (32) pins can be used as GPIO in single chip mode
• Reduced-port mode (1 MDI, 2 MDo) or full-port mode (2 MDI. 8 MDO)
• Many peripheral pins can be used as GPIO when not used as primary functions
• 5-V outputs with slew rate control

Integrated I/O System

• True 5-V I/O
• Three time processing units (TPU3)
— 16 channels each
— Each TPU3 is a microcoded timer subsystem
— One 6-Kbyte and one 4-Kbyte dual port TPU RAM (DPTRAM), one (6-Kbyte) shared by two
TPU3 modules for TPU microcode and the 4-Kbyte dedicated to the third TPU3 for microcode.

MPC565/MPC566 PRODUCT BRIEF MOTOROLA

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 22-Channel MIOS timer (MIOS14)
• Six modulus counter sub-module (MCSM)
— Four additional MCSM submodules compared to MIOS1
• 10 double action sub-module (DASM).
• 12 dedicated PWM sub-modules (PWMSM)
— Four additional PWM submodules compared to MIOS1 (shared with MIOS GPIO pins)
• Real-time clock sub-module (MRTCSM) provides low power clock/counter
— Requires external 32-KHz crystal
— Uses four pins: two for 32-KHz crystal, two for power/ground.

Two Queued Analog-to-Digital Converter Modules (QADC64E_A, QADC64E_B)

• AMUXes providing a total of 40 analog channels.
• 40 total input channels on the two modules with internal multiplexing (AMUXes)
• Each QADC64E can see all 40 input channels
• 10 bit A/D converter with internal sample/hold
• Typical conversion time is 4 µs (250-Kbyte samples/sec)
• Two conversion command queues of variable length
• Automated queue modes initiated by:
— External edge trigger/level gate
— Software command
— Periodic/interval timer, assignable to both queue 1 and 2
• 64 result registers in each QADC64E module
• Conversions alternate reference (ALTREF) pin. This pin can be connected to a different reference
voltage
• Output data is right or left justified, signed or unsigned

Message Data Link Controller (DLCMD2) Module

• Two pins muxed with QSMCM_B pins. Muxing controlled by QSMCM_B PCS3 pin assignment
register
• SAE J1850 Class B data communications network interface compatible and ISO compatible for
low-speed (< 125 Kbps) serial data communications in automotive applications
• 10.4 Kbps variable pulse width (VPW) bit format
• Digital noise filter, collision detection
• Hardware cyclical redundancy check (CRC) generation and checking
• Block mode receive and transmit supported
• 4X receive mode supported (41.6 Kbps)
• Digital loopback mode
• In-frame response (IFR) types 0, 1, 2, and 3 supported
• Dedicated register for symbol timing adjustments
• Inter-module bus 3 (IMB3) slave interface
• Power-saving IMB3 stop mode with automatic wakeup on network activity
• Power-saving IMB3 CLOCKDIS mode
• Debug mode available through IMB3 FREEZE signal or user controllable SOFT_FRZ bit
• Polling and IMB3 interrupt generation with vector lookup available

Three TouCAN™ Modules (TOUCAN_A, TOUCAN_B, TOUCAN_C)

• 16 message buffers each, programmable I/O modes
• Maskable interrupts
• Programmable loop-back for self test operation
• Independent of the transmission medium (external transceiver is assumed)
• Open network architecture, multimaster concept
• High immunity to EMI
• Short latency time for high-priority messages
• Low power sleep mode, with programmable wake up on bus activity

MPC565/MPC566 PRODUCT BRIEF MOTOROLA

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 • TOUCAN_C pins shared with MIOS14 GPIO pins

Two Queued Serial Modules with One Queued-SPI and two SCI Each (QSMCM_A,
QSMCM_B)
• QSMCM_A matches full MPC555/MPC556 QSMCM functionality
• QSMCM_B has pins muxed with DLCMD2 module
— Two pins are muxed with DLCMD2 (J1850) transmit and receive pins (B_PCS3_J1850_TX
and B_RXD2_J1850_RX)
— QSMCM_B vs J1850 mux control provided by QPAPCS3 bit in QSMCM pin assignment reg-
ister (PQSPAR)
• Queued-SPI
— Provides full-duplex communication port for peripheral expansion or interprocessor communi-
cation
— Up to 32 preprogrammed transfers, reducing overhead
— Synchronous serial interface with baud rate of up to system clock / 4
— Four programmable peripheral-selects pins support up to 16 devices
— Special wrap-around mode allows continuous sampling of a serial peripheral for efficient inter-
facing to serial analog-to-digital (A/D) converters
• SCI
— UART mode provides NRZ format and half- or full-duplex interface
— 16 register receive buffer and 16 register transmit buffer on one SCI
— Advanced error detection, and optional parity generation and detection
— word length programmable as eight or nine bits
— Separate transmitter and receiver enable bits, and double buffering of data
— Wake-up functions allow the CPU to run uninterrupted until either a true idle line is detected,
or a new address byte is received
— External source clock for baud generation
• Available in package
— Plastic ball grid array (PBGA) packaging
• 352/388 ball PBGA
• 27 mm x 27 mm body size
• 1.0 mm ball pitch

MPC565/MPC566 PRODUCT BRIEF MOTOROLA

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 JTAG 512 Kbytes 512 Kbytes
Flash Flash

Burst
Int.
U-BUS
E-BUS
USIU
MPC5xx
READI
Core 4-Kbyte CALRAM_B
+ 4-Kbyte Overlay
FP

L2U
I/F
L-BUS
32K CALRAM_A

28 Kbytes SRAM
(No Overlay)

4-Kbyte Overlay

QADC64E QADC64E UIMB

QSMCM QSMCM DLCMD2
w/AMUX w/AMUX I/F

IMB3

6 Kbytes 4 Kbytes Tou Tou Tou

TPU3 TPU3 TPU3 MIOS14
DPTRAM DPTRAM CAN CAN CAN

Figure 1 MPC565/MPC566 Block Diagram

MPC565/MPC566 PRODUCT BRIEF MOTOROLA

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 0x2F C000
0x00 0000
UC3F_A Flash USIU Control Registers
512 Kbytes
0x07 FFFF 0x2F C800
0x08 0000 C3F_A Control (64 bytes)
UC3F_B Flash
0x2F C840
512 Kbytes C3F_B Control (64 bytes)
0x0F FFFF 0x2F C87F
0x10 0000
Reserved for Flash DPTRAM_AB 0x30 0000
Registers (64 bytes)
(2,016 Kbytes)
DPTRAM_C 0x30 0040
0x2F 7FFF Registers (64 bytes)
0x2F 8000 DLCMD2 (16 bytes) 0x30 0080
DECRAM / BBC
16 Kbytes Reserved (3952 bytes) 0x30 0090
0x2F BFFF
0x2F C000
USIU & Flash Control DPTRAM_C (4 Kbytes) 0x30 1000
0x2F FFFF 16 Kbytes
DPTRAM_AB (6 Kbytes) 0x30 2000
0x30 0000
UIMB I/F & IMB Reserved (2 Kbytes) 0x30 3800
Modules
TPU3_A (1 Kbytes) 0x30 4000
32 Kbytes
0x30 7FFF TPU3_B (1 Kbytes) 0x30 4400
0x30 8000 Reserved for IMB QADC64_A (1 Kbytes) 0x30 4800
0x37 FFFF 480 Kbytes
QADC64_B (1 Kbytes) 0x30 4C00
0x38 0000 CALRAM/
Readi Control QSMCM_A (1 Kbytes) 0x30 5000
0x38 00FF 256 bytes
QSMCM_B (1 Kbytes) 0x30 5400
0x38 0100 Reserved (L-bus Control)
0x38 3FFF ~32 Kbytes 0x30 5800
Reserved (1 Kbytes)
0x38 4000
TPU3_C (1 Kbytes) 0x30 5C00
Reserved (L-bus Mem)
444 Kbytes 0x30 6000
MIOS14 (4 Kbytes)
0x3F 6FFF TOUCAN_A (1 Kbytes) 0x30 7000
0x3F 7000 All 4-Kbytes can be
Overlay Section TOUCAN_B (1 Kbytes) 0x30 7400
0x3F 7FFF CALRAM_B (4 Kbyte)
TOUCAN_C (1 Kbytes) 0x30 7800
0x3F 8000
Reserved (896 bytes) 0x30 7C00
CALRAM_A (32 Kbyte)
UIMB REGISTERS 0x30 7F80
(128 bytes) 0x30 7FFF
0x3F FFFF 4-Kbyte Overlay Section

Figure 2 MPC565 / MPC566 Internal Memory Block

MPC565/MPC566 PRODUCT BRIEF MOTOROLA

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 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
AN53_A_MA1_P AN72_B_MA0_P
A VDD AN64_B_PQB0 VRH VRL AN84 AN80 AN48_A_PQB4
QA1
VDDA VSSA AN76_B_PQA4
QA0
AN67_B_PQB3 AN65_B_PQB1 QVDDL A_TPUCH2 A_TPUCH4 A_TPUCH6 A_TPUCH10 A_TPUCH14 A_TPUCH1 B_TPUCH5 B_TPUCH10 B_TPUCH12 B_TPUCH14 VSS A

AN44_ANW_A_P AN52_A_MA0_P AN73_B_MA1_P

B VSS VDD
QB0
ALTREF AN85 AN81 AN49_A_PQB5
QA0
AN56_A_PQA4 AN58_A_PQA6 AN77_B_PQA5
QA1
AN69_B_PQB5 AN66_B_PQB2 QVDDL ETRIG2 A_TPUCH5 A_TPUCH8 A_TPUCH11 A_T2CLK B_TPUCH3 B_TPUCH6 B_TPUCH7 B_TPUCH13 VSS VDD B

AN45_ANX_A_P AN46_ANY_A_P AN54_A_MA2_P

C VDDRTC VSS VDD
QB1
AN87 AN83
QB2
AN50_A_PQB6
QA2
AN57_A_PQA5 AN79_B_PQA7 AN75_B_PQA3 AN71_B_PQB7 AN70_B_PQB6 QVDDL ETRIG1 B_CNRX0 A_TPUCH9 A_TPUCH12 A_TPUCH15 B_TPUCH4 B_TPUCH11 B_TPUCH8 VSS VDD B_TPUCH15 C

AN47_ANZ_A_P AN74_B_MA2_P
D EXTAL32 VDDSRAM2 VSS VDD VDDH AN86 AN82
QB3
AN51_A_PQB7 AN55_A_PQA3 AN59_A_PQA7 AN78_B_PQA6
QA2
AN68_B_PQB4 QVDDL VDDH A_TPUCH3 A_TPUCH7 A_TPUCH13 A_TPUCH0 B_TPUCH9 NVDDL VSS VDD B_TPUCH2 B_TPUCH0 D

E XTAL32 B_CNTX0 VDDSRAM1 VSS VDD B_TPUCH1 B_T2CLK MPWM17 E

MPWM5_MPIO3
F VSSRTC C_TPUCH14 C_TPUCH15 NVDDL
2B6
MPWM18 MDA11 MDA13 F

G C_TPUCH10 C_TPUCH11 C_TPUCH12 VDDSRAM3 MDA12 MDA27 MDA28 MDA29

G

H C_TPUCH9 C_TPUCH7 C_TPUCH8 C_T2CLK MDA30 MDA31 MPWM0 MPWM1

H
NOTE: This is a top down view of the balls.
MPWM20_MPIO
J C_TPUCH6 C_TPUCH5 C_TPUCH3 C_TPUCH13 MPWM3 MPWM2 MPWM16
32B11 J

MPWM21_MPIO C_CNTX0_MPIO
K C_TPUCH2 C_TPUCH1 C_TPUCH0 C_TPUCH4 MDA15 MDA14
32B12 32B13 K

C_CNRX0_MPIO
L MDI_0 TCK_DSCK MDI_1 MCKI VSS VSS VSS VSS VSS VSS
32B14
MPIO32B15 MPWM19 VF0_MPIO32B0 L

MPWM4_MPIO3 VFLS0_MPIO32B
M TDI_DSDI EVTI_B RSTI_B MSEI_B VSS VSS VSS VSS VSS VSS VF1_MPIO32B1 VF2_MPIO32B2
2B5 3 M

MDO_4_MPIO32 MDO_6_MPIO32 MDO_5_MPIO32 VFLS1_MPIO32B B_PCS0_SS_B_ B_PCS1_QGPIO

N TMS
B10 B8 B9
VSS VSS VSS VSS VSS VSS VDDH
4 QGPIO0 1 N

MDO_7_MPIO32 B_MISO_QGPIO B_PCS3_J1850_ B_MOSI_QGPIO

P B7
JCOMP MCKO MDO_0 VSS VSS VSS VSS VSS VSS B_ECK
4 TX 5 P

B_PCS2_QGPIO
R MDO_1 TDO_DSDO MDO_2 IWP1_VFLS1 VSS VSS VSS VSS VSS VSS B_SCK_QGPIO6
2
B_TXD1_QGPO1 B_TXD2_QGPO2 R

SGPIOC6_FRZ_ A_MISO_QGPIO B_RXD2_J1850_ A_SCK_QGPIO6(

T MDO_3 MSEO_B IWP0_VFLS0
PTR_B
VSS VSS VSS VSS VSS VSS A_TXD1_QGPO1
4 RX C3F_CLK) T

ADDR_SGPIOA1 ADDR_SGPIOA1 A_PCS2_QGPIO A_RXD1_QPI1(C A_MOSI_QGPIO A_PCS3_QGPIO

U 6 7
ADDR_SGPIOA8 NVDDL
2 3F_SUP1) 5 3(C3F_IOUT) U

ADDR_SGPIOA1 ADDR_SGPIOA1 ADDR_SGPIOA1 A_PCS0_SS_B_ A_RXD2_QPI2(C

V 8 9
ADDR_SGPIOA9
0 QGPIO0
A_TXD2_QGPO2
3F_SUP2)
B_RXD1_QGPI1 V

ADDR_SGPIOA2 ADDR_SGPIOA2 ADDR_SGPIOA1 ADDR_SGPIOA1 A_PCS1_QGPIO PULLSEL

W 0 1 1 2
NVDDL VFLASH
1 W

ADDR_SGPIOA2 ADDR_SGPIOA2 ADDR_SGPIOA1 ADDR_SGPIOA1

Y 2 3 3 4
VDDF EXTCLK A_CNTXO KAPWR Y

ADDR_SGPIOA2 ADDR_SGPIOA2 ADDR_SGPIOA1 ADDR_SGPIOA3

AA 4 5 5 0
PORESET_B
_TRST_B
A_CNRXO VSSF XTAL AA

ADDR_SGPIOA2 ADDR_SGPIOA2 ADDR_SGPIOA3 IRQ6_B_MODCK RSTCONF_B_TE

AB 6 7 1
QVDDL HRESET_B
2 XP
EXTAL AB

ADDR_SGPIOA2 DATA_SGPIOD2 DATA_SGPIOD2 DATA_SGPIOD2 DATA_SGPIOD2 DATA_SGPIOD2 SGPIOC7_IRQO IRQ7_B_MODCK

AC 8
NC QVDDL VSS VDD VDDH
9 7
NVDDL
4 2 0
NVDDL
UT_B_LWP0
NVDDL WE_B_AT1 NVDDL CS3_B BI_B_STS_B VDDH VDD VSS QVDDL SRESET_B
3
VSSSYN AC

ADDR_SGPIOA2 DATA_SGPIOD3 DATA_SGPIOD3 DATA_SGPIOD2 DATA_SGPIOD2 DATA_SGPIOD2 DATA_SGPIOD2 DATA_SGPIOD2 DATA_SGPIOD1 IRQ4_B_AT2_SG IRQ2_B_CR_B_S IRQ5_B_SGPIOC
AD 9
QVDDL VSS VDD NC
1 0 8 6 5 3 1 9 PIOC4
TEA_B
GPIOC2
WE_B_AT2 CS1_B TSIZ0 B0EPEE CLKOUT VDD VSS QVDDL
5_MODCK1
XFC AD

IRQ3_B_KR_B_R
DATA_SGPIOD1 DATA_SGPIOD1 DATA_SGPIOD1 DATA_SGPIOD1
AE QVDDL VSS VDD DATA_SGPIOD1 DATA_SGPIOD3 DATA_SGPIOD5 DATA_SGPIOD7 DATA_SGPIOD9
1 3 5 7
ETRY_B_SGPIO BB_B_VF2_IWP3
C3
RD_WR_B OE_B WE_B_AT0 CS0_B BURST_B TS_B BDIP_B NC VDD VSS QVDDL VDDSYN AE

DATA_SGPIOD1 DATA_SGPIOD1 DATA_SGPIOD1 DATA_SGPIOD1 DATA_SGPIOD1 IRQ1_B_RSV_B_ BG_B_VF0_LWP IRQ0_B_SGPIOC

AF VSS VDD DATA_SGPIOD0 DATA_SGPIOD2 DATA_SGPIOD4 DATA_SGPIOD6 DATA_SGPIOD8
0 2 4 6 8 SGPIOC1 1
BR_B_VF1_IWP2
0
WE_B_AT3 CS2_B TSIZ1 TA_B EPEE ENGCLK_BUCLK NC VDD VSS QVDDL AF

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

Figure 3 MPC565 / MPC566 Ball Diagram

MPC565/MPC566 PRODUCT BRIEF MOTOROLA

7
 Ordering Information

Table 1 MPC565 / MPC566

Device Name Order Part Number1 Package Info Temperature Maximum Code
Range Frequency Compression
MPC565 MPC565MZP40 388 PBGA -40 – 125° C 40 MHz No
MPC565 MPC565CZP40 388 PBGA -40 – 85° C 40 MHz No
MPC565 MPC565MZP56 388 PBGA -40 – 125° C 56 MHz No
MPC565 MPC565CZP56 388 PBGA -40 – 85° C 56 MHz No
MPC566 MPC566MZP40 388 PBGA -40 – 125° C 40 MHz Yes
MPC566 MPC566CZP40 388 PBGA -40 – 85° C 40 MHz Yes
MPC566 MPC566MZP56 388 PBGA -40 – 125° C 56 MHz Yes
MPC566 MPC566CZP56 388 PBGA -40 – 85° C 56 MHz Yes
NOTES:
1. Add R2 suffix for parts shipped in tape and reel media.

Table 2 lists the documents that provide a complete description of the MPC565/566 and are required
to design properly with the part. Documentation is available from a local Motorola distributor, a Motorola
semiconductor sales office, a Motorola Literature Distribution Center, or through the Motorola Semicon-
ductor documentation page on the Internet (the source for the latest information).

Table 2 Available Documentation

Document Number Title
MPC565RM/D MPC565/MPC566 Reference Manual
AN1821/D Exception Table Relocation and Multi-Processor
Address Mapping in the Embedded MPC5XX Family
AN2002/D MPC565/566 Nexus Interface Connector Options
AN2109/D MPC555 Interrupts
AN2127/D EMC Guidelines for MPC500-Based Automotive Powertrain Systems

MPC565/MPC566 PRODUCT BRIEF MOTOROLA

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MPC565/MPC566 PRODUCT BRIEF MOTOROLA
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MPC565/MPC566 PRODUCT BRIEF MOTOROLA
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MPC565/MPC566 PRODUCT BRIEF MOTOROLA
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OnCE, DigitalDNA, and the DigitalDNA logo are trademarks of Motorola, Inc.

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty,
representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can
and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must
be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent
rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems
intended for surgical implant into the body, or other applications intended to support life, or for any other application in which the
failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use
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attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or
unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola
and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

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Order Number MPC565PB/D